From e6d87036412b952cb083eff2dc716aee97a771f2 Mon Sep 17 00:00:00 2001 From: Roman Yeryomin Date: Fri, 17 May 2013 20:40:24 +0300 Subject: Move to rsdk 3.2.4. Compiles cleanly. Signed-off-by: Roman Yeryomin --- .../realtek/files/arch/rlx/bsp_rtl8196c/serial.c | 57 ++++++++++++++++++++++ 1 file changed, 57 insertions(+) create mode 100644 target/linux/realtek/files/arch/rlx/bsp_rtl8196c/serial.c (limited to 'target/linux/realtek/files/arch/rlx/bsp_rtl8196c/serial.c') diff --git a/target/linux/realtek/files/arch/rlx/bsp_rtl8196c/serial.c b/target/linux/realtek/files/arch/rlx/bsp_rtl8196c/serial.c new file mode 100644 index 000000000..d2959b4c8 --- /dev/null +++ b/target/linux/realtek/files/arch/rlx/bsp_rtl8196c/serial.c @@ -0,0 +1,57 @@ +/* + * Copyright 2006, Realtek Semiconductor Corp. + * + * arch/rlx/rlxocp/serial.c + * RLXOCP serial port initialization + * + * Tony Wu (tonywu@realtek.com.tw) + * Nov. 07, 2006 + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "bspchip.h" + +void __init bsp_serial_init(void) +{ + struct uart_port s; + + /* clear memory */ + memset(&s, 0, sizeof(s)); + + /* + * UART0 + */ + s.line = 0; + s.type = PORT_16550A; + s.irq = BSP_UART0_IRQ; + s.iotype = UPIO_MEM; + s.regshift = 2; +#if 1 + s.uartclk = BSP_SYS_CLK_RATE; + s.fifosize = 16; + //s.flags = UPF_SKIP_TEST | UPF_LOW_LATENCY; + s.flags = UPF_SKIP_TEST; + s.mapbase = BSP_UART0_MAP_BASE; + //s.membase = ioremap_nocache(s.mapbase, BSP_UART0_MAPSIZE); + s.membase = ioremap_nocache(s.mapbase, 0x20); +#else + s.uartclk = BSP_SYS_CLK_RATE - BSP_BAUDRATE * 24; //??? + s.fifosize = 1; //??? + s.flags = UPF_SKIP_TEST | UPF_LOW_LATENCY | UPF_SPD_CUST; + s.membase = (unsigned char *)BSP_UART0_BASE; + s.custom_divisor = BSP_SYS_CLK_RATE / (BSP_BAUDRATE * 16) - 1; +#endif + + if (early_serial_setup(&s) != 0) { + panic("RTL8196C: bsp_serial_init failed!"); + } +} -- cgit v1.2.3