From 3260740c920ea811e18bc1743c863fce74ac89b7 Mon Sep 17 00:00:00 2001 From: florian Date: Mon, 2 Apr 2007 16:59:59 +0000 Subject: Add preliminary RouterBoard RB1xx support git-svn-id: svn://svn.openwrt.org/openwrt/trunk@6839 3c298f89-4303-0410-b956-a3cf2f4a3e73 --- .../rb1xx-2.6/files/arch/mips/pci/ops-adm5120.c | 63 ++++++++++++++ .../rb1xx-2.6/files/arch/mips/pci/pci-adm5120.c | 96 ++++++++++++++++++++++ 2 files changed, 159 insertions(+) create mode 100644 target/linux/rb1xx-2.6/files/arch/mips/pci/ops-adm5120.c create mode 100644 target/linux/rb1xx-2.6/files/arch/mips/pci/pci-adm5120.c (limited to 'target/linux/rb1xx-2.6/files/arch/mips/pci') diff --git a/target/linux/rb1xx-2.6/files/arch/mips/pci/ops-adm5120.c b/target/linux/rb1xx-2.6/files/arch/mips/pci/ops-adm5120.c new file mode 100644 index 000000000..91dae8999 --- /dev/null +++ b/target/linux/rb1xx-2.6/files/arch/mips/pci/ops-adm5120.c @@ -0,0 +1,63 @@ +/* + * Copyright (C) ADMtek Incorporated. + * Copyright (C) 2005 Jeroen Vreeken (pe1rxq@amsat.org) + * Copyright (C) 2007 Gabor Juhos + * Copyright (C) 2007 OpenWrt.org + */ + +#include +#include +#include +#include +#include + +#include + +volatile u32* pci_config_address_reg = (volatile u32*)KSEG1ADDR(ADM5120_PCICFG_ADDR); +volatile u32* pci_config_data_reg = (volatile u32*)KSEG1ADDR(ADM5120_PCICFG_DATA); + +#define PCI_ENABLE 0x80000000 + +static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, + int size, uint32_t *val) +{ + *pci_config_address_reg = ((bus->number & 0xff) << 0x10) | + ((devfn & 0xff) << 0x08) | (where & 0xfc) | PCI_ENABLE; + switch (size) { + case 1: + *val = ((*pci_config_data_reg)>>((where&3)<<3))&0xff; + break; + case 2: + *val = ((*pci_config_data_reg)>>((where&3)<<3))&0xffff; + break; + default: + *val = (*pci_config_data_reg); + } + return PCIBIOS_SUCCESSFUL; +} + +static int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, + int size, uint32_t val) +{ + *pci_config_address_reg = ((bus->number & 0xff) << 0x10) | + ((devfn & 0xff) << 0x08) | (where & 0xfc) | PCI_ENABLE; + switch (size) { + case 1: + *(volatile u8 *)(((int)pci_config_data_reg) + + (where & 3)) = val; + break; + case 2: + *(volatile u16 *)(((int)pci_config_data_reg) + + (where & 2)) = (val); + break; + default: + *pci_config_data_reg = (val); + } + + return PCIBIOS_SUCCESSFUL; +} + +struct pci_ops adm5120_pci_ops = { + .read = pci_config_read, + .write = pci_config_write, +}; diff --git a/target/linux/rb1xx-2.6/files/arch/mips/pci/pci-adm5120.c b/target/linux/rb1xx-2.6/files/arch/mips/pci/pci-adm5120.c new file mode 100644 index 000000000..78de001c5 --- /dev/null +++ b/target/linux/rb1xx-2.6/files/arch/mips/pci/pci-adm5120.c @@ -0,0 +1,96 @@ +/* + * Copyright (C) ADMtek Incorporated. + * Copyright (C) 2005 Jeroen Vreeken (pe1rxq@amsat.org) + * Copyright (C) 2007 Gabor Juhos + * Copyright (C) 2007 OpenWrt.org + */ + +#include +#include +#include +#include +#include + +#include +#include + +extern struct pci_ops adm5120_pci_ops; + +#define PCI_CMM_IOACC_EN 0x1 +#define PCI_CMM_MEMACC_EN 0x2 +#define PCI_CMM_MASTER_EN 0x4 +#define PCI_CMM_DEF \ + (PCI_CMM_IOACC_EN | PCI_CMM_MEMACC_EN | PCI_CMM_MASTER_EN) + +#define PCI_DEF_CACHE_LINE_SZ 4 + + +struct resource pci_io_resource = { + .name = "ADM5120 PCI I/O", + .start = ADM5120_PCIIO_BASE, + .end = ADM5120_PCICFG_ADDR-1, + .flags = IORESOURCE_IO +}; + +struct resource pci_mem_resource = { + .name = "ADM5120 PCI MEM", + .start = ADM5120_PCIMEM_BASE, + .end = ADM5120_PCIIO_BASE-1, + .flags = IORESOURCE_MEM +}; + +static struct pci_controller adm5120_controller = { + .pci_ops = &adm5120_pci_ops, + .io_resource = &pci_io_resource, + .mem_resource = &pci_mem_resource, +}; + +int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +{ + if (slot < 2 || slot > 4) + return -1; + return slot + 4; +} + +static void adm5120_pci_fixup(struct pci_dev *dev) +{ + if (dev->devfn == 0) { + pci_write_config_word(dev, PCI_COMMAND, PCI_CMM_DEF); + pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, + PCI_DEF_CACHE_LINE_SZ); + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0); + pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0); + } +} + +DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, adm5120_pci_fixup); + + +int pcibios_plat_dev_init(struct pci_dev *dev) +{ + return 0; +} + +static int __init adm5120_pci_setup(void) +{ + int pci_bios; + + pci_bios = adm5120_has_pci(); + + printk("adm5120: system has %sPCI BIOS\n", pci_bios ? "" : "no "); + if (pci_bios == 0) + return 1; + + /* Avoid ISA compat ranges. */ + PCIBIOS_MIN_IO = 0x00000000; + PCIBIOS_MIN_MEM = 0x00000000; + + /* Set I/O resource limits. */ + ioport_resource.end = 0x1fffffff; + iomem_resource.end = 0xffffffff; + + register_pci_controller(&adm5120_controller); + return 0; +} + +subsys_initcall(adm5120_pci_setup); -- cgit v1.2.3