From b887a6d197170b719028f31085876d8deaed35b6 Mon Sep 17 00:00:00 2001 From: juhosg Date: Sun, 30 Aug 2009 19:15:51 +0000 Subject: [ramips] initial support for RT288x/RT305x git-svn-id: svn://svn.openwrt.org/openwrt/trunk@17439 3c298f89-4303-0410-b956-a3cf2f4a3e73 --- .../ramips/files/arch/mips/ralink/rt305x/rt305x.c | 70 ++++++++++++++++++++++ 1 file changed, 70 insertions(+) create mode 100644 target/linux/ramips/files/arch/mips/ralink/rt305x/rt305x.c (limited to 'target/linux/ramips/files/arch/mips/ralink/rt305x/rt305x.c') diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/rt305x.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/rt305x.c new file mode 100644 index 000000000..9d940a2f5 --- /dev/null +++ b/target/linux/ramips/files/arch/mips/ralink/rt305x/rt305x.c @@ -0,0 +1,70 @@ +/* + * Ralink RT305x SoC specific setup + * + * Copyright (C) 2008-2009 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * Parts of this file are based on Ralink's 2.6.21 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include + +#include +#include + +unsigned char rt305x_sys_type[RT305X_SYS_TYPE_LEN]; + +unsigned long rt305x_cpu_freq; +EXPORT_SYMBOL_GPL(rt305x_cpu_freq); + +unsigned long rt305x_sys_freq; +EXPORT_SYMBOL_GPL(rt305x_sys_freq); + +void __iomem * rt305x_intc_base; +void __iomem * rt305x_sysc_base; +void __iomem * rt305x_memc_base; + +void __init rt305x_detect_sys_type(void) +{ + u32 n0; + u32 n1; + u32 id; + + n0 = rt305x_sysc_rr(SYSC_REG_CHIP_NAME0); + n1 = rt305x_sysc_rr(SYSC_REG_CHIP_NAME1); + id = rt305x_sysc_rr(SYSC_REG_CHIP_ID); + + snprintf(rt305x_sys_type, RT305X_SYS_TYPE_LEN, + "Ralink %c%c%c%c%c%c%c%c id:%u rev:%u", + (char) (n0 & 0xff), (char) ((n0 >> 8) & 0xff), + (char) ((n0 >> 16) & 0xff), (char) ((n0 >> 24) & 0xff), + (char) (n1 & 0xff), (char) ((n1 >> 8) & 0xff), + (char) ((n1 >> 16) & 0xff), (char) ((n1 >> 24) & 0xff), + (id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK, + (id & CHIP_ID_REV_MASK)); +} + +void __init rt305x_detect_sys_freq(void) +{ + u32 t; + + t = rt305x_sysc_rr(SYSC_REG_SYSTEM_CONFIG); + t = ((t >> SYSTEM_CONFIG_CPUCLK_SHIFT) & SYSTEM_CONFIG_CPUCLK_MASK); + + switch (t) { + case SYSTEM_CONFIG_CPUCLK_320: + rt305x_cpu_freq = 320000000; + break; + case SYSTEM_CONFIG_CPUCLK_384: + rt305x_cpu_freq = 384000000; + break; + } + + rt305x_sys_freq = rt305x_cpu_freq / 3; +} -- cgit v1.2.3