From b887a6d197170b719028f31085876d8deaed35b6 Mon Sep 17 00:00:00 2001 From: juhosg Date: Sun, 30 Aug 2009 19:15:51 +0000 Subject: [ramips] initial support for RT288x/RT305x git-svn-id: svn://svn.openwrt.org/openwrt/trunk@17439 3c298f89-4303-0410-b956-a3cf2f4a3e73 --- .../asm/mach-ralink/cpu-feature-overrides.h | 56 +++++++++ .../files/arch/mips/include/asm/mach-ralink/gpio.h | 52 ++++++++ .../files/arch/mips/include/asm/mach-ralink/irq.h | 17 +++ .../arch/mips/include/asm/mach-ralink/platform.h | 20 ++++ .../arch/mips/include/asm/mach-ralink/rt288x.h | 89 ++++++++++++++ .../mips/include/asm/mach-ralink/rt288x_regs.h | 121 +++++++++++++++++++ .../arch/mips/include/asm/mach-ralink/rt305x.h | 91 ++++++++++++++ .../mips/include/asm/mach-ralink/rt305x_regs.h | 132 +++++++++++++++++++++ .../files/arch/mips/include/asm/mach-ralink/war.h | 25 ++++ 9 files changed, 603 insertions(+) create mode 100644 target/linux/ramips/files/arch/mips/include/asm/mach-ralink/cpu-feature-overrides.h create mode 100644 target/linux/ramips/files/arch/mips/include/asm/mach-ralink/gpio.h create mode 100644 target/linux/ramips/files/arch/mips/include/asm/mach-ralink/irq.h create mode 100644 target/linux/ramips/files/arch/mips/include/asm/mach-ralink/platform.h create mode 100644 target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x.h create mode 100644 target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x_regs.h create mode 100644 target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x.h create mode 100644 target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h create mode 100644 target/linux/ramips/files/arch/mips/include/asm/mach-ralink/war.h (limited to 'target/linux/ramips/files/arch/mips/include') diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/cpu-feature-overrides.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/cpu-feature-overrides.h new file mode 100644 index 000000000..6c41da851 --- /dev/null +++ b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/cpu-feature-overrides.h @@ -0,0 +1,56 @@ +/* + * Ralink RT288x/RT305x specific CPU feature overrides + * + * Copyright (C) 2008-2009 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This file was derived from: include/asm-mips/cpu-features.h + * Copyright (C) 2003, 2004 Ralf Baechle + * Copyright (C) 2004 Maciej W. Rozycki + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ +#ifndef __ASM_MACH_RALINK_CPU_FEATURE_OVERRIDES_H +#define __ASM_MACH_RALINK_CPU_FEATURE_OVERRIDES_H + +#define cpu_has_tlb 1 +#define cpu_has_4kex 1 +#define cpu_has_3k_cache 0 +#define cpu_has_4k_cache 1 +#define cpu_has_tx39_cache 0 +#define cpu_has_sb1_cache 0 +#define cpu_has_fpu 0 +#define cpu_has_32fpr 0 +#define cpu_has_counter 1 +#define cpu_has_watch 1 +#define cpu_has_divec 1 + +#define cpu_has_prefetch 1 +#define cpu_has_ejtag 1 +#define cpu_has_llsc 1 + +#define cpu_has_mips16 1 +#define cpu_has_mdmx 0 +#define cpu_has_mips3d 0 +#define cpu_has_smartmips 0 + +#define cpu_has_mips32r1 1 +#define cpu_has_mips32r2 1 +#define cpu_has_mips64r1 0 +#define cpu_has_mips64r2 0 + +#define cpu_has_dsp 0 +#define cpu_has_mipsmt 0 + +#define cpu_has_64bits 0 +#define cpu_has_64bit_zero_reg 0 +#define cpu_has_64bit_gp_regs 0 +#define cpu_has_64bit_addresses 0 + +#define cpu_dcache_line_size() 32 +#define cpu_icache_line_size() 32 + +#endif /* __ASM_MACH_RALINK_CPU_FEATURE_OVERRIDES_H */ diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/gpio.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/gpio.h new file mode 100644 index 000000000..e8a0836a3 --- /dev/null +++ b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/gpio.h @@ -0,0 +1,52 @@ +/* + * Ralink RT288x GPIO API definitions + * + * Copyright (C) 2008-2009 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#ifndef __ASM_MACH_RT288X_GPIO_H +#define __ASM_MACH_RT288X_GPIO_H + +#define ARCH_NR_GPIOS 64 +#include + +#include + +extern void __rt288x_gpio_set_value(unsigned gpio, int value); +extern int __rt288x_gpio_get_value(unsigned gpio); + +static inline int gpio_to_irq(unsigned gpio) +{ + return RT288X_GPIO_IRQ(gpio); +} + +static inline int irq_to_gpio(unsigned irq) +{ + return irq - RT288X_GPIO_IRQ_BASE; +} + +static inline int gpio_get_value(unsigned gpio) +{ + if (gpio < RT288X_GPIO_COUNT) + return __rt288x_gpio_get_value(gpio); + + return __gpio_get_value(gpio); +} + +static inline void gpio_set_value(unsigned gpio, int value) +{ + if (gpio < RT288X_GPIO_COUNT) + __rt288x_gpio_set_value(gpio, value); + else + __gpio_set_value(gpio, value); +} + +#define gpio_cansleep __gpio_cansleep + +#endif /* __ASM_MACH_RT288X_GPIO_H */ diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/irq.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/irq.h new file mode 100644 index 000000000..90bfea371 --- /dev/null +++ b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/irq.h @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2008 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ +#ifndef __ASM_MACH_RT288X_IRQ_H +#define __ASM_MACH_RT288X_IRQ_H + +#define MIPS_CPU_IRQ_BASE 0 +#define NR_IRQS 48 + +#include_next + +#endif /* __ASM_MACH_RT288X_IRQ_H */ diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/platform.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/platform.h new file mode 100644 index 000000000..4585d8b56 --- /dev/null +++ b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/platform.h @@ -0,0 +1,20 @@ +/* + * Ralink RT288x SoC specific platform definitions + * + * Copyright (C) 2008 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef __ASM_MACH_RT288X_PLATFORM_H +#define __ASM_MACH_RT288X_PLATFORM_H + +struct physmap_flash_data; + +extern void rt288x_register_flash(unsigned int id, + struct physmap_flash_data *pdata) __init; + +#endif /* __ASM_MACH_RT288X_PLATFORM_H */ diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x.h new file mode 100644 index 000000000..9b218de02 --- /dev/null +++ b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x.h @@ -0,0 +1,89 @@ +/* + * Ralink RT288x SoC specific definitions + * + * Copyright (C) 2008 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * Parts of this file are based on Ralink's 2.6.21 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _RT288X_H_ +#define _RT288X_H_ + +#include +#include + +void rt288x_detect_sys_type(void) __init; + +#define RT288X_SYS_TYPE_LEN 64 +extern unsigned char rt288x_sys_type[RT288X_SYS_TYPE_LEN]; + +void rt288x_detect_sys_freq(void) __init; + +extern unsigned long rt288x_cpu_freq; +extern unsigned long rt288x_sys_freq; + +extern unsigned long rt288x_mach_type; +#define RT288X_MACH_GENERIC 0 + +#define RT288X_CPU_IRQ_BASE 0 +#define RT288X_INTC_IRQ_BASE 8 +#define RT288X_INTC_IRQ_COUNT 32 +#define RT288X_GPIO_IRQ_BASE 40 + +#define RT288X_CPU_IRQ_INTC (RT288X_CPU_IRQ_BASE + 2) +#define RT288X_CPU_IRQ_PCI (RT288X_CPU_IRQ_BASE + 4) +#define RT288X_CPU_IRQ_FE (RT288X_CPU_IRQ_BASE + 5) +#define RT288X_CPU_IRQ_WNIC (RT288X_CPU_IRQ_BASE + 6) +#define RT288X_CPU_IRQ_COUNTER (RT288X_CPU_IRQ_BASE + 7) + +#define RT2880_INTC_IRQ_TIMER0 (RT288X_INTC_IRQ_BASE + 0) +#define RT2880_INTC_IRQ_TIMER1 (RT288X_INTC_IRQ_BASE + 1) +#define RT2880_INTC_IRQ_UART0 (RT288X_INTC_IRQ_BASE + 2) +#define RT2880_INTC_IRQ_PIO (RT288X_INTC_IRQ_BASE + 3) +#define RT2880_INTC_IRQ_PCM (RT288X_INTC_IRQ_BASE + 4) +#define RT2880_INTC_IRQ_UART1 (RT288X_INTC_IRQ_BASE + 8) +#define RT2880_INTC_IRQ_IA (RT288X_INTC_IRQ_BASE + 23) + +#define RT288X_GPIO_IRQ(x) (RT288X_GPIO_IRQ_BASE + (x)) +#define RT288X_GPIO_COUNT 32 + +extern void __iomem *rt288x_sysc_base; +extern void __iomem *rt288x_intc_base; +extern void __iomem *rt288x_memc_base; + +static inline void rt288x_sysc_wr(u32 val, unsigned reg) +{ + __raw_writel(val, rt288x_sysc_base + reg); +} + +static inline u32 rt288x_sysc_rr(unsigned reg) +{ + return __raw_readl(rt288x_sysc_base + reg); +} + +static inline void rt288x_intc_wr(u32 val, unsigned reg) +{ + __raw_writel(val, rt288x_intc_base + reg); +} + +static inline u32 rt288x_intc_rr(unsigned reg) +{ + return __raw_readl(rt288x_intc_base + reg); +} + +static inline void rt288x_memc_wr(u32 val, unsigned reg) +{ + __raw_writel(val, rt288x_memc_base + reg); +} + +static inline u32 rt288x_memc_rr(unsigned reg) +{ + return __raw_readl(rt288x_memc_base + reg); +} + +#endif /* _RT228X_H_ */ diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x_regs.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x_regs.h new file mode 100644 index 000000000..4431a65df --- /dev/null +++ b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x_regs.h @@ -0,0 +1,121 @@ +/* + * Ralink RT288x SoC register definitions + * + * Copyright (C) 2008-2009 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _RT288X_REGS_H_ +#define _RT288X_REGS_H_ + +#include + +#define RT2880_SYSC_BASE 0x00300000 +#define RT2880_TIMER_BASE 0x00300100 +#define RT2880_INTC_BASE 0x00300200 +#define RT2880_MEMC_BASE 0x00300300 +#define RT2880_UART0_BASE 0x00300500 +#define RT2880_PIO_BASE 0x00300600 +#define RT2880_I2C_BASE 0x00300900 +#define RT2880_SPI_BASE 0x00300b00 +#define RT2880_UART1_BASE 0x00300c00 +#define RT2880_FE_BASE 0x00310000 +#define RT2880_ROM_BASE 0x00400000 +#define RT2880_PCI_BASE 0x00500000 +#define RT2880_WMAC_BASE 0x00600000 +#define RT2880_FLASH1_BASE 0x01000000 +#define RT2880_FLASH0_BASE 0x1fc00000 +#define RT2880_SDRAM_BASE 0x08000000 + +#define RT2880_SYSC_SIZE 0x100 +#define RT2880_INTC_SIZE 0x100 +#define RT2880_MEMC_SIZE 0x100 +#define RT2880_UART0_SIZE 0x100 +#define RT2880_UART1_SIZE 0x100 +#define RT2880_FLASH1_SIZE (16 * 1024 * 1024) +#define RT2880_FLASH0_SIZE (4 * 1024 * 1024) + +/* SYSC registers */ +#define SYSC_REG_CHIP_NAME0 0x000 /* Chip Name 0 */ +#define SYSC_REG_CHIP_NAME1 0x004 /* Chip Name 1 */ +#define SYSC_REG_CHIP_ID 0x00c /* Chip Identification */ +#define SYSC_REG_SYSTEM_CONFIG 0x010 /* System Configuration */ +#define SYSC_REG_RESET_CTRL 0x034 /* Reset Control*/ +#define SYSC_REG_RESET_STATUS 0x038 /* Reset Status*/ +#define SYSC_REG_IA_ADDRESS 0x310 /* Illegal Access Address */ +#define SYSC_REG_IA_TYPE 0x314 /* Illegal Access Type */ + +#define CHIP_ID_ID_MASK 0xff +#define CHIP_ID_ID_SHIFT 8 +#define CHIP_ID_REV_MASK 0xff + +#define SYSTEM_CONFIG_CPUCLK_SHIFT 20 +#define SYSTEM_CONFIG_CPUCLK_MASK 0x3 +#define SYSTEM_CONFIG_CPUCLK_250 0x0 +#define SYSTEM_CONFIG_CPUCLK_266 0x1 +#define SYSTEM_CONFIG_CPUCLK_280 0x2 +#define SYSTEM_CONFIG_CPUCLK_300 0x3 + +#define RT2880_RESET_SYSTEM BIT(0) +#define RT2880_RESET_TIMER BIT(1) +#define RT2880_RESET_INTC BIT(2) +#define RT2880_RESET_MEMC BIT(3) +#define RT2880_RESET_CPU BIT(4) +#define RT2880_RESET_UART0 BIT(5) +#define RT2880_RESET_PIO BIT(6) +#define RT2880_RESET_I2C BIT(9) +#define RT2880_RESET_SPI BIT(11) +#define RT2880_RESET_UART1 BIT(12) +#define RT2880_RESET_PCI BIT(16) +#define RT2880_RESET_WMAC BIT(17) +#define RT2880_RESET_FE BIT(18) +#define RT2880_RESET_PCM BIT(19) + +/* TIMER registers */ + +/* INTC register */ +#define INTC_REG_STATUS0 0x00 +#define INTC_REG_STATUS1 0x04 +#define INTC_REG_TYPE 0x20 +#define INTC_REG_RAW_STATUS 0x30 +#define INTC_REG_ENABLE 0x34 +#define INTC_REG_DISABLE 0x38 + +#define RT2880_INTC_INT_TIMER0 BIT(0) +#define RT2880_INTC_INT_TIMER1 BIT(1) +#define RT2880_INTC_INT_UART0 BIT(2) +#define RT2880_INTC_INT_PIO BIT(3) +#define RT2880_INTC_INT_PCM BIT(4) +#define RT2880_INTC_INT_UART1 BIT(8) +#define RT2880_INTC_INT_IA BIT(23) +#define RT2880_INTC_INT_GLOBAL BIT(31) + +/* MEMC registers */ +#define MEMC_REG_SDRAM_CFG0 0x00 +#define MEMC_REG_SDRAM_CFG1 0x04 +#define MEMC_REG_FLASH_CFG0 0x08 +#define MEMC_REG_FLASH_CFG1 0x0c +#define MEMC_REG_IA_ADDR 0x10 +#define MEMC_REG_IA_TYPE 0x14 + +#define FLASH_CFG_WIDTH_SHIFT 26 +#define FLASH_CFG_WIDTH_MASK 0x3 +#define FLASH_CFG_WIDTH_8BIT 0x0 +#define FLASH_CFG_WIDTH_16BIT 0x1 +#define FLASH_CFG_WIDTH_32BIT 0x2 + +/* UART registers */ +#define UART_REG_RX 0 +#define UART_REG_TX 1 +#define UART_REG_IER 2 +#define UART_REG_IIR 3 +#define UART_REG_FCR 4 +#define UART_REG_LCR 5 +#define UART_REG_MCR 6 +#define UART_REG_LSR 7 + +#endif /* _RT288X_REGS_H_ */ diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x.h new file mode 100644 index 000000000..7dcef168a --- /dev/null +++ b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x.h @@ -0,0 +1,91 @@ +/* + * Ralink RT305x SoC specific definitions + * + * Copyright (C) 2009 Gabor Juhos + * + * Parts of this file are based on Ralink's 2.6.21 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _RT305X_H_ +#define _RT305X_H_ + +#include +#include + +void rt305x_detect_sys_type(void) __init; + +#define RT305X_SYS_TYPE_LEN 64 +extern unsigned char rt305x_sys_type[RT305X_SYS_TYPE_LEN]; + +void rt305x_detect_sys_freq(void) __init; + +extern unsigned long rt305x_cpu_freq; +extern unsigned long rt305x_sys_freq; + +#define RT305X_MEM_SIZE_MIN (2 * 1024 * 1024) +#define RT305X_MEM_SIZE_MAX (64 * 1024 * 1024) + +#define RT305X_CPU_IRQ_BASE 0 +#define RT305X_INTC_IRQ_BASE 8 +#define RT305X_INTC_IRQ_COUNT 32 +#define RT305X_GPIO_IRQ_BASE 40 + +#define RT305X_CPU_IRQ_INTC (RT305X_CPU_IRQ_BASE + 2) +#define RT305X_CPU_IRQ_FE (RT305X_CPU_IRQ_BASE + 5) +#define RT305X_CPU_IRQ_WNIC (RT305X_CPU_IRQ_BASE + 6) +#define RT305X_CPU_IRQ_COUNTER (RT305X_CPU_IRQ_BASE + 7) + +#define RT305X_INTC_IRQ_SYSCTL (RT305X_INTC_IRQ_BASE + 0) +#define RT305X_INTC_IRQ_TIMER0 (RT305X_INTC_IRQ_BASE + 1) +#define RT305X_INTC_IRQ_TIMER1 (RT305X_INTC_IRQ_BASE + 2) +#define RT305X_INTC_IRQ_IA (RT305X_INTC_IRQ_BASE + 3) +#define RT305X_INTC_IRQ_PCM (RT305X_INTC_IRQ_BASE + 4) +#define RT305X_INTC_IRQ_UART0 (RT305X_INTC_IRQ_BASE + 5) +#define RT305X_INTC_IRQ_PIO (RT305X_INTC_IRQ_BASE + 6) +#define RT305X_INTC_IRQ_DMA (RT305X_INTC_IRQ_BASE + 7) +#define RT305X_INTC_IRQ_NAND (RT305X_INTC_IRQ_BASE + 8) +#define RT305X_INTC_IRQ_PERFC (RT305X_INTC_IRQ_BASE + 9) +#define RT305X_INTC_IRQ_I2S (RT305X_INTC_IRQ_BASE + 10) +#define RT305X_INTC_IRQ_UART1 (RT305X_INTC_IRQ_BASE + 12) +#define RT305X_INTC_IRQ_ESW (RT305X_INTC_IRQ_BASE + 17) +#define RT305X_INTC_IRQ_OTG (RT305X_INTC_IRQ_BASE + 18) + +extern void __iomem *rt305x_sysc_base; +extern void __iomem *rt305x_intc_base; +extern void __iomem *rt305x_memc_base; + +static inline void rt305x_sysc_wr(u32 val, unsigned reg) +{ + __raw_writel(val, rt305x_sysc_base + reg); +} + +static inline u32 rt305x_sysc_rr(unsigned reg) +{ + return __raw_readl(rt305x_sysc_base + reg); +} + +static inline void rt305x_intc_wr(u32 val, unsigned reg) +{ + __raw_writel(val, rt305x_intc_base + reg); +} + +static inline u32 rt305x_intc_rr(unsigned reg) +{ + return __raw_readl(rt305x_intc_base + reg); +} + +static inline void rt305x_memc_wr(u32 val, unsigned reg) +{ + __raw_writel(val, rt305x_memc_base + reg); +} + +static inline u32 rt305x_memc_rr(unsigned reg) +{ + return __raw_readl(rt305x_memc_base + reg); +} + +#endif /* _RT305X_H_ */ diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h new file mode 100644 index 000000000..7dd9765b8 --- /dev/null +++ b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h @@ -0,0 +1,132 @@ +/* + * Ralink RT305 SoC register definitions + * + * Copyright (C) 2009 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _RT305X_REGS_H_ +#define _RT305X_REGS_H_ + +#include + +#define RT305X_SDRAM_BASE 0x00000000 +#define RT305X_SYSC_BASE 0x10000000 +#define RT305X_TIMER_BASE 0x10000100 +#define RT305X_INTC_BASE 0x10000200 +#define RT305X_MEMC_BASE 0x10000300 +#define RT305X_PCM_BASE 0x10000400 +#define RT305X_UART0_BASE 0x10000500 +#define RT305X_PIO_BASE 0x10000600 +#define RT305X_GDMA_BASE 0x10000700 +#define RT305X_NANDC_BASE 0x10000800 +#define RT305X_I2C_BASE 0x10000900 +#define RT305X_I2S_BASE 0x10000a00 +#define RT305X_SPI_BASE 0x10000b00 +#define RT305X_UART1_BASE 0x10000c00 +#define RT305X_FE_BASE 0x10010000 +#define RT305X_SWITCH_BASE 0x10110000 +#define RT305X_WMAC_BASE 0x00180000 +#define RT305X_OTG_BASE 0x101c0000 +#define RT305X_ROM_BASE 0x00400000 +#define RT305X_FLASH1_BASE 0x1b000000 +#define RT305X_FLASH0_BASE 0x1f000000 + +#define RT305X_SYSC_SIZE 0x100 +#define RT305X_INTC_SIZE 0x100 +#define RT305X_MEMC_SIZE 0x100 +#define RT305X_UART0_SIZE 0x100 +#define RT305X_UART1_SIZE 0x100 +#define RT305X_FLASH1_SIZE (16 * 1024 * 1024) +#define RT305X_FLASH0_SIZE (4 * 1024 * 1024) + +/* SYSC registers */ +#define SYSC_REG_CHIP_NAME0 0x000 /* Chip Name 0 */ +#define SYSC_REG_CHIP_NAME1 0x004 /* Chip Name 1 */ +#define SYSC_REG_CHIP_ID 0x00c /* Chip Identification */ +#define SYSC_REG_SYSTEM_CONFIG 0x010 /* System Configuration */ +#define SYSC_REG_RESET_CTRL 0x034 /* Reset Control*/ +#define SYSC_REG_RESET_STATUS 0x038 /* Reset Status*/ +#define SYSC_REG_IA_ADDRESS 0x310 /* Illegal Access Address */ +#define SYSC_REG_IA_TYPE 0x314 /* Illegal Access Type */ + +#define CHIP_ID_ID_MASK 0xff +#define CHIP_ID_ID_SHIFT 8 +#define CHIP_ID_REV_MASK 0xff + +#define SYSTEM_CONFIG_CPUCLK_SHIFT 18 +#define SYSTEM_CONFIG_CPUCLK_MASK 0x1 +#define SYSTEM_CONFIG_CPUCLK_320 0x0 +#define SYSTEM_CONFIG_CPUCLK_384 0x1 + +#define RT305X_RESET_SYSTEM BIT(0) +#define RT305X_RESET_TIMER BIT(8) +#define RT305X_RESET_INTC BIT(9) +#define RT305X_RESET_MEMC BIT(10) +#define RT305X_RESET_PCM BIT(11) +#define RT305X_RESET_UART0 BIT(12) +#define RT305X_RESET_PIO BIT(13) +#define RT305X_RESET_DMA BIT(14) +#define RT305X_RESET_I2C BIT(16) +#define RT305X_RESET_I2S BIT(17) +#define RT305X_RESET_SPI BIT(18) +#define RT305X_RESET_UART1 BIT(19) +#define RT305X_RESET_WNIC BIT(20) +#define RT305X_RESET_FE BIT(21) +#define RT305X_RESET_OTG BIT(22) +#define RT305X_RESET_ESW BIT(23) + +/* TIMER registers */ + +/* INTC register */ +#define INTC_REG_STATUS0 0x00 +#define INTC_REG_STATUS1 0x04 +#define INTC_REG_TYPE 0x20 +#define INTC_REG_RAW_STATUS 0x30 +#define INTC_REG_ENABLE 0x34 +#define INTC_REG_DISABLE 0x38 + +#define RT305X_INTC_INT_SYSCTL BIT(0) +#define RT305X_INTC_INT_TIMER0 BIT(1) +#define RT305X_INTC_INT_TIMER1 BIT(2) +#define RT305X_INTC_INT_IA BIT(3) +#define RT305X_INTC_INT_PCM BIT(4) +#define RT305X_INTC_INT_UART0 BIT(5) +#define RT305X_INTC_INT_PIO BIT(6) +#define RT305X_INTC_INT_DMA BIT(7) +#define RT305X_INTC_INT_NAND BIT(8) +#define RT305X_INTC_INT_PERFC BIT(9) +#define RT305X_INTC_INT_I2S BIT(10) +#define RT305X_INTC_INT_UART1 BIT(12) +#define RT305X_INTC_INT_ESW BIT(17) +#define RT305X_INTC_INT_OTG BIT(18) +#define RT305X_INTC_INT_GLOBAL BIT(31) + +/* MEMC registers */ +#define MEMC_REG_SDRAM_CFG0 0x00 +#define MEMC_REG_SDRAM_CFG1 0x04 +#define MEMC_REG_FLASH_CFG0 0x08 +#define MEMC_REG_FLASH_CFG1 0x0c +#define MEMC_REG_IA_ADDR 0x10 +#define MEMC_REG_IA_TYPE 0x14 + +#define FLASH_CFG_WIDTH_SHIFT 26 +#define FLASH_CFG_WIDTH_MASK 0x3 +#define FLASH_CFG_WIDTH_8BIT 0x0 +#define FLASH_CFG_WIDTH_16BIT 0x1 +#define FLASH_CFG_WIDTH_32BIT 0x2 + +/* UART registers */ +#define UART_REG_RX 0 +#define UART_REG_TX 1 +#define UART_REG_IER 2 +#define UART_REG_IIR 3 +#define UART_REG_FCR 4 +#define UART_REG_LCR 5 +#define UART_REG_MCR 6 +#define UART_REG_LSR 7 + +#endif /* _RT305X_REGS_H_ */ diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/war.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/war.h new file mode 100644 index 000000000..e27cb2864 --- /dev/null +++ b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MACH_RT288X_WAR_H +#define __ASM_MACH_RT288X_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MACH_RT288X_WAR_H */ -- cgit v1.2.3