From 3ff5d8da9a9bbdf1727661d3c50311af524b4b5d Mon Sep 17 00:00:00 2001 From: juhosg Date: Sat, 21 Apr 2012 12:30:47 +0000 Subject: ramips: rt305x: fix CPU clock detection on RT3352 git-svn-id: svn://svn.openwrt.org/openwrt/trunk@31401 3c298f89-4303-0410-b956-a3cf2f4a3e73 --- .../ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'target/linux/ramips/files/arch/mips/include/asm/mach-ralink') diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h index 9e1aa6642..e12158205 100644 --- a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h +++ b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h @@ -80,6 +80,11 @@ #define RT305X_SYSCFG_SRAM_CS0_MODE_WDT 1 #define RT305X_SYSCFG_SRAM_CS0_MODE_BTCOEX 2 +#define RT3352_SYSCFG0_CPUCLK_SHIFT 8 +#define RT3352_SYSCFG0_CPUCLK_MASK 0x1 +#define RT3352_SYSCFG0_CPUCLK_LOW 0x0 +#define RT3352_SYSCFG0_CPUCLK_HIGH 0x1 + #define RT305X_GPIO_MODE_I2C BIT(0) #define RT305X_GPIO_MODE_SPI BIT(1) #define RT305X_GPIO_MODE_UART0_SHIFT 2 -- cgit v1.2.3