From dfffaea839fd631ec0b3d4f58540316a04c4f2ad Mon Sep 17 00:00:00 2001 From: blogic Date: Thu, 3 Nov 2011 15:15:52 +0000 Subject: lantiq: bump to 3.1 git-svn-id: svn://svn.openwrt.org/openwrt/trunk@28721 3c298f89-4303-0410-b956-a3cf2f4a3e73 --- .../lantiq/patches-2.6.39/990-fix_include.patch | 43 ---------------------- 1 file changed, 43 deletions(-) delete mode 100644 target/linux/lantiq/patches-2.6.39/990-fix_include.patch (limited to 'target/linux/lantiq/patches-2.6.39/990-fix_include.patch') diff --git a/target/linux/lantiq/patches-2.6.39/990-fix_include.patch b/target/linux/lantiq/patches-2.6.39/990-fix_include.patch deleted file mode 100644 index 332ba9371..000000000 --- a/target/linux/lantiq/patches-2.6.39/990-fix_include.patch +++ /dev/null @@ -1,43 +0,0 @@ ---- /dev/null -+++ b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h -@@ -0,0 +1,40 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ * Copyright (C) 2010 John Crispin -+ */ -+ -+#ifndef _LTQ_FALCON_H__ -+#define _LTQ_FALCON_H__ -+ -+#ifdef CONFIG_SOC_FALCON -+ -+#include -+ -+/* Chip IDs */ -+#define SOC_ID_FALCON 0x01B8 -+ -+/* SoC Types */ -+#define SOC_TYPE_FALCON 0x01 -+ -+/* ASC0/1 - serial port */ -+#define LTQ_ASC0_BASE_ADDR 0x1E100C00 -+#define LTQ_ASC1_BASE_ADDR 0x1E100B00 -+#define LTQ_ASC_SIZE 0x100 -+ -+#define LTQ_ASC_TIR(x) (INT_NUM_IM3_IRL0 + (x * 8)) -+#define LTQ_ASC_RIR(x) (INT_NUM_IM3_IRL0 + (x * 8) + 1) -+#define LTQ_ASC_EIR(x) (INT_NUM_IM3_IRL0 + (x * 8) + 2) -+ -+/* ICU - interrupt control unit */ -+#define LTQ_ICU_BASE_ADDR 0x1F880200 -+#define LTQ_ICU_SIZE 0x100 -+ -+/* WDT */ -+#define LTQ_WDT_BASE_ADDR 0x1F8803F0 -+#define LTQ_WDT_SIZE 0x10 -+ -+#endif /* CONFIG_SOC_FALCON */ -+#endif /* _LTQ_XWAY_H__ */ -- cgit v1.2.3