From 0a2b2965cd687a2be744552b09f4f5cf2fde4c0f Mon Sep 17 00:00:00 2001 From: blogic Date: Wed, 3 Nov 2010 19:02:27 +0000 Subject: [ifxmips]: * bump kernel to 2.6.35.8 * merge arcadyn mach files * fixes ar9 * adds hack for tapi drivers git-svn-id: svn://svn.openwrt.org/openwrt/trunk@23836 3c298f89-4303-0410-b956-a3cf2f4a3e73 --- .../010-mips_clocksource_init_war.patch | 33 ---------------------- 1 file changed, 33 deletions(-) delete mode 100644 target/linux/ifxmips/patches-2.6.33/010-mips_clocksource_init_war.patch (limited to 'target/linux/ifxmips/patches-2.6.33/010-mips_clocksource_init_war.patch') diff --git a/target/linux/ifxmips/patches-2.6.33/010-mips_clocksource_init_war.patch b/target/linux/ifxmips/patches-2.6.33/010-mips_clocksource_init_war.patch deleted file mode 100644 index 81eabc6dc..000000000 --- a/target/linux/ifxmips/patches-2.6.33/010-mips_clocksource_init_war.patch +++ /dev/null @@ -1,33 +0,0 @@ ---- a/arch/mips/kernel/cevt-r4k.c -+++ b/arch/mips/kernel/cevt-r4k.c -@@ -22,6 +22,22 @@ - - #ifndef CONFIG_MIPS_MT_SMTC - -+/* -+ * Compare interrupt can be routed and latched outside the core, -+ * so a single execution hazard barrier may not be enough to give -+ * it time to clear as seen in the Cause register. 4 time the -+ * pipeline depth seems reasonably conservative, and empirically -+ * works better in configurations with high CPU/bus clock ratios. -+ */ -+ -+#define compare_change_hazard() \ -+ do { \ -+ irq_disable_hazard(); \ -+ irq_disable_hazard(); \ -+ irq_disable_hazard(); \ -+ irq_disable_hazard(); \ -+ } while (0) -+ - static int mips_next_event(unsigned long delta, - struct clock_event_device *evt) - { -@@ -31,6 +47,7 @@ static int mips_next_event(unsigned long - cnt = read_c0_count(); - cnt += delta; - write_c0_compare(cnt); -+ compare_change_hazard(); - res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0; - return res; - } -- cgit v1.2.3