From 13e93684560de2faa88008652e776d0611f24a40 Mon Sep 17 00:00:00 2001 From: ralph Date: Sat, 24 Apr 2010 21:35:49 +0000 Subject: [ifxmips] add .32 patches git-svn-id: svn://svn.openwrt.org/openwrt/trunk@21150 3c298f89-4303-0410-b956-a3cf2f4a3e73 --- .../010-mips_clocksource_init_war.patch | 35 ++++++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 target/linux/ifxmips/patches-2.6.32/010-mips_clocksource_init_war.patch (limited to 'target/linux/ifxmips/patches-2.6.32/010-mips_clocksource_init_war.patch') diff --git a/target/linux/ifxmips/patches-2.6.32/010-mips_clocksource_init_war.patch b/target/linux/ifxmips/patches-2.6.32/010-mips_clocksource_init_war.patch new file mode 100644 index 000000000..15fd78f4e --- /dev/null +++ b/target/linux/ifxmips/patches-2.6.32/010-mips_clocksource_init_war.patch @@ -0,0 +1,35 @@ +Index: linux-2.6.32.10/arch/mips/kernel/cevt-r4k.c +=================================================================== +--- linux-2.6.32.10.orig/arch/mips/kernel/cevt-r4k.c 2010-04-02 21:11:39.000000000 +0200 ++++ linux-2.6.32.10/arch/mips/kernel/cevt-r4k.c 2010-04-02 21:11:52.000000000 +0200 +@@ -22,6 +22,22 @@ + + #ifndef CONFIG_MIPS_MT_SMTC + ++/* ++ * Compare interrupt can be routed and latched outside the core, ++ * so a single execution hazard barrier may not be enough to give ++ * it time to clear as seen in the Cause register. 4 time the ++ * pipeline depth seems reasonably conservative, and empirically ++ * works better in configurations with high CPU/bus clock ratios. ++ */ ++ ++#define compare_change_hazard() \ ++ do { \ ++ irq_disable_hazard(); \ ++ irq_disable_hazard(); \ ++ irq_disable_hazard(); \ ++ irq_disable_hazard(); \ ++ } while (0) ++ + static int mips_next_event(unsigned long delta, + struct clock_event_device *evt) + { +@@ -31,6 +47,7 @@ + cnt = read_c0_count(); + cnt += delta; + write_c0_compare(cnt); ++ compare_change_hazard(); + res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0; + return res; + } -- cgit v1.2.3