From d5f52f466ee5b18a569603b6b6f1e01974e8346f Mon Sep 17 00:00:00 2001
From: kaloz <kaloz@3c298f89-4303-0410-b956-a3cf2f4a3e73>
Date: Mon, 12 Nov 2012 09:18:00 +0000
Subject: [cns3xxx]: reorder, rename and refresh patches

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@34169 3c298f89-4303-0410-b956-a3cf2f4a3e73
---
 .../linux/cns3xxx/patches-3.3/100-gpio_irq.patch   | 128 +++++++++++++++++++++
 1 file changed, 128 insertions(+)
 create mode 100644 target/linux/cns3xxx/patches-3.3/100-gpio_irq.patch

(limited to 'target/linux/cns3xxx/patches-3.3/100-gpio_irq.patch')

diff --git a/target/linux/cns3xxx/patches-3.3/100-gpio_irq.patch b/target/linux/cns3xxx/patches-3.3/100-gpio_irq.patch
new file mode 100644
index 000000000..a487d52e4
--- /dev/null
+++ b/target/linux/cns3xxx/patches-3.3/100-gpio_irq.patch
@@ -0,0 +1,128 @@
+--- a/arch/arm/mach-cns3xxx/Makefile
++++ b/arch/arm/mach-cns3xxx/Makefile
+@@ -1,4 +1,4 @@
+-obj-$(CONFIG_ARCH_CNS3XXX)		+= core.o pm.o devices.o
++obj-$(CONFIG_ARCH_CNS3XXX)		+= core.o gpio.o pm.o devices.o
+ obj-$(CONFIG_PCI)			+= pcie.o
+ obj-$(CONFIG_MACH_CNS3420VB)		+= cns3420vb.o
+ obj-$(CONFIG_SMP)			+= platsmp.o headsmp.o cns3xxx_fiq.o
+--- a/arch/arm/mach-cns3xxx/cns3420vb.c
++++ b/arch/arm/mach-cns3xxx/cns3420vb.c
+@@ -198,6 +198,10 @@ static void __init cns3420_init(void)
+ 
+ 	cns3xxx_ahci_init();
+ 	cns3xxx_sdhci_init();
++	cns3xxx_gpio_init( 0, 32, CNS3XXX_GPIOA_BASE_VIRT, IRQ_CNS3XXX_GPIOA,
++		NR_IRQS_CNS3XXX);
++	cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT, IRQ_CNS3XXX_GPIOB,
++		NR_IRQS_CNS3XXX + 32);
+ 
+ 	pm_power_off = cns3xxx_power_off;
+ }
+--- a/arch/arm/mach-cns3xxx/core.c
++++ b/arch/arm/mach-cns3xxx/core.c
+@@ -21,7 +21,6 @@
+ #include <asm/hardware/gic.h>
+ #include <asm/smp_twd.h>
+ #include <asm/hardware/cache-l2x0.h>
+-#include <asm/gpio.h>
+ #include <mach/cns3xxx.h>
+ #include "core.h"
+ 
+@@ -83,73 +82,12 @@ static struct map_desc cns3xxx_io_desc[]
+ 	},
+ };
+ 
+-static inline void gpio_line_config(u8 line, u32 direction)
+-{
+-	u32 reg;
+-	if (direction) {
+-		if (line < 32) {
+-			reg = __raw_readl(CNS3XXX_GPIOA_BASE_VIRT + CNS3XXX_GPIO_DIR);
+-			reg |= (1 << line);
+-			__raw_writel(reg, CNS3XXX_GPIOA_BASE_VIRT + CNS3XXX_GPIO_DIR);
+-		} else {
+-			reg = __raw_readl(CNS3XXX_GPIOB_BASE_VIRT + CNS3XXX_GPIO_DIR);
+-			reg |= (1 << (line - 32));
+-			__raw_writel(reg, CNS3XXX_GPIOB_BASE_VIRT + CNS3XXX_GPIO_DIR);
+-		}
+-	} else {
+-		if (line < 32) {
+-			reg = __raw_readl(CNS3XXX_GPIOA_BASE_VIRT + CNS3XXX_GPIO_DIR);
+-			reg &= ~(1 << line);
+-			__raw_writel(reg, CNS3XXX_GPIOA_BASE_VIRT + CNS3XXX_GPIO_DIR);
+-		} else {
+-			reg = __raw_readl(CNS3XXX_GPIOB_BASE_VIRT + CNS3XXX_GPIO_DIR);
+-			reg &= ~(1 << (line - 32));
+-			__raw_writel(reg, CNS3XXX_GPIOB_BASE_VIRT + CNS3XXX_GPIO_DIR);
+-		}
+-	}
+-}
+-
+-static int cns3xxx_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
+-{
+-	gpio_line_config(gpio, CNS3XXX_GPIO_IN);
+-	return 0;
+-}
+-
+-static int cns3xxx_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int level)
+-{
+-	gpio_line_set(gpio, level);
+-	gpio_line_config(gpio, CNS3XXX_GPIO_OUT);
+-	return 0;
+-}
+-
+-static int cns3xxx_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
+-{
+-	return gpio_get_value(gpio);
+-}
+-
+-static void cns3xxx_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
+-{
+-	gpio_set_value(gpio, value);
+-}
+-
+-static struct gpio_chip cns3xxx_gpio_chip = {
+-	.label			= "CNS3XXX_GPIO_CHIP",
+-	.direction_input	= cns3xxx_gpio_direction_input,
+-	.direction_output	= cns3xxx_gpio_direction_output,
+-	.get			= cns3xxx_gpio_get_value,
+-	.set			= cns3xxx_gpio_set_value,
+-	.base			= 0,
+-	.ngpio			= 64,
+-};
+-
+ void __init cns3xxx_common_init(void)
+ {
+ #ifdef CONFIG_LOCAL_TIMERS
+ 	twd_base = (void __iomem *) CNS3XXX_TC11MP_TWD_BASE_VIRT;
+ #endif
+ 	iotable_init(cns3xxx_io_desc, ARRAY_SIZE(cns3xxx_io_desc));
+-
+-	gpiochip_add(&cns3xxx_gpio_chip);
+ }
+ 
+ /* used by entry-macro.S */
+--- a/arch/arm/Kconfig
++++ b/arch/arm/Kconfig
+@@ -366,7 +366,8 @@ config ARCH_CLPS711X
+ config ARCH_CNS3XXX
+ 	bool "Cavium Networks CNS3XXX family"
+ 	select CPU_V6K
+-	select ARCH_WANT_OPTIONAL_GPIOLIB
++	select ARCH_REQUIRE_GPIOLIB
++	select GENERIC_IRQ_CHIP
+ 	select GENERIC_CLOCKEVENTS
+ 	select ARM_GIC
+ 	select CLKDEV_LOOKUP
+--- a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
++++ b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
+@@ -627,7 +627,7 @@ int cns3xxx_cpu_clock(void);
+ 
+ #if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_CNS3XXX)
+ #undef NR_IRQS
+-#define NR_IRQS				NR_IRQS_CNS3XXX
++#define NR_IRQS				(NR_IRQS_CNS3XXX + 64)
+ #endif
+ 
+ #endif	/* __MACH_BOARD_CNS3XXX_H */
-- 
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