From 8bd259b28182af357371fd6048fa7198ad4b7a25 Mon Sep 17 00:00:00 2001
From: florian <florian@3c298f89-4303-0410-b956-a3cf2f4a3e73>
Date: Fri, 6 Mar 2009 01:15:00 +0000
Subject: [brcm63xx] prepare for SPI controller driver

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@14755 3c298f89-4303-0410-b956-a3cf2f4a3e73
---
 .../include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h    | 114 +++++++++++++++++++++
 1 file changed, 114 insertions(+)

(limited to 'target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h')

diff --git a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h b/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h
index 6fa8825b4..be9da2eee 100644
--- a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h
+++ b/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h
@@ -289,6 +289,120 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
 	return 0;
 }
 
+/*
+ * SPI register layout is not compatible
+ * accross CPU versions but it is software
+ * compatible
+ */
+
+enum bcm63xx_regs_spi {
+	SPI_CMD,
+	SPI_INT_STATUS,
+	SPI_INT_MASK_ST,
+	SPI_INT_MASK,
+	SPI_ST,
+	SPI_CLK_CFG,
+	SPI_FILL_BYTE,
+	SPI_MSG_TAIL,
+	SPI_RX_TAIL,
+	SPI_MSG_CTL,
+	SPI_MSG_DATA,
+	SPI_RX_DATA,
+};
+
+extern const unsigned long *bcm63xx_regs_spi;
+
+static inline unsigned long bcm63xx_spireg(enum bcm63xx_regs_spi reg)
+{
+#ifdef BCMCPU_RUNTIME_DETECT
+        return bcm63xx_regs_spi[reg];
+#else
+#ifdef CONFIG_BCM63XX_CPU_6338
+switch (reg) {
+	case SPI_CMD:
+		return SPI_BCM_6338_SPI_CMD;
+	case SPI_INT_STATUS:
+		return SPI_BCM_6338_SPI_INT_STATUS;
+	case SPI_INT_MASK_ST:
+		return SPI_BCM_6338_SPI_MASK_INT_ST;
+	case SPI_INT_MASK:
+		return SPI_BCM_6338_SPI_INT_MASK;
+	case SPI_ST:
+		return SPI_BCM_6338_SPI_ST;
+	case SPI_CLK_CFG:
+		return SPI_BCM_6338_SPI_CLK_CFG;
+	case SPI_FILL_BYTE:
+		return SPI_BCM_6338_SPI_FILL_BYTE;
+	case SPI_MSG_TAIL:
+		return SPI_BCM_6338_SPI_MSG_TAIL;
+	case SPI_RX_TAIL:
+		return SPI_BCM_6338_SPI_RX_TAIL;
+	case SPI_MSG_CTL:
+		return SPI_BCM_6338_SPI_MSG_CTL;
+	case SPI_MSG_DATA:
+		return SPI_BCM_6338_SPI_MSG_DATA;
+	case SPI_RX_DATA:
+		return SPI_BCM_6338_SPI_RX_DATA;
+}
+#endif
+#ifdef CONFIG_BCM63XX_CPU_6348
+switch (reg) {
+	case SPI_CMD:
+		return SPI_BCM_6348_SPI_CMD;
+	case SPI_INT_MASK_ST:
+		return SPI_BCM_6348_SPI_MASK_INT_ST;
+	case SPI_INT_STATUS:
+		return SPI_BCM_6348_SPI_INT_STATUS;
+	case SPI_ST:
+		return SPI_BCM_6348_SPI_ST;
+	case SPI_CLK_CFG:
+		return SPI_BCM_6348_SPI_CLK_CFG;
+	case SPI_FILL_BYTE:
+		return SPI_BCM_6348_SPI_FILL_BYTE;
+	case SPI_MSG_TAIL:
+		return SPI_BCM_6348_SPI_MSG_TAIL;
+	case SPI_RX_TAIL:
+		return SPI_BCM_6348_SPI_RX_TAIL;
+	case SPI_MSG_CTL:
+		return SPI_BCM_6348_SPI_MSG_CTL;
+	case SPI_MSG_DATA:
+		return SPI_BCM_6348_SPI_MSG_DATA;
+	case SPI_BCM_6348_SPI_RX_DATA:
+		return SPI_BCM_6348_SPI_RX_DATA;
+}
+#endif
+#ifdef CONFIG_BCM63XX_CPU_6358
+switch (reg) {
+	case SPI_CMD:
+		return SPI_BCM_6358_SPI_CMD;
+	case SPI_INT_STATUS:
+		return SPI_BCM_6358_SPI_INT_STATUS;
+	case SPI_INT_MASK_ST:
+		return SPI_BCM_6358_SPI_MASK_INT_ST;
+	case SPI_INT_MASK:
+		return SPI_BCM_6358_SPI_INT_MASK;
+	case SPI_ST:
+		return SPI_BCM_6358_SPI_STATUS;
+	case SPI_CLK_CFG:
+		return SPI_BCM_6358_SPI_CLK_CFG;
+	case SPI_FILL_BYTE:
+		return SPI_BCM_6358_SPI_FILL_BYTE;
+	case SPI_MSG_TAIL:
+		return SPI_BCM_6358_SPI_MSG_TAIL;
+	case SPI_RX_TAIL:
+		return SPI_BCM_6358_SPI_RX_TAIL;
+	case SPI_MSG_CTL:
+		return SPI_BCM_6358_MSG_CTL;
+	case SPI_MSG_DATA:
+		return SPI_BCM_6358_SPI_MSG_DATA;
+	case SPI_RX_DATA:
+		return SPI_BCM_6358_SPI_RX_FIFO;
+}
+#endif
+#endif
+	return 0;
+}
+
 /*
  * IRQ number changes across CPU too
  */
-- 
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