From b97f8ef70b5ac2844b8dd6afbb247e80b2bf7787 Mon Sep 17 00:00:00 2001 From: nbd Date: Thu, 22 Mar 2007 20:23:17 +0000 Subject: add brcm47xx-2.6 fixes from #1496 git-svn-id: svn://svn.openwrt.org/openwrt/trunk@6639 3c298f89-4303-0410-b956-a3cf2f4a3e73 --- .../drivers/ssb/driver_chipcommon/chipcommon.c | 29 ++++++++++++++++++++++ 1 file changed, 29 insertions(+) (limited to 'target/linux/brcm47xx-2.6/files/drivers/ssb/driver_chipcommon') diff --git a/target/linux/brcm47xx-2.6/files/drivers/ssb/driver_chipcommon/chipcommon.c b/target/linux/brcm47xx-2.6/files/drivers/ssb/driver_chipcommon/chipcommon.c index 6d3412b58..a17910947 100644 --- a/target/linux/brcm47xx-2.6/files/drivers/ssb/driver_chipcommon/chipcommon.c +++ b/target/linux/brcm47xx-2.6/files/drivers/ssb/driver_chipcommon/chipcommon.c @@ -266,6 +266,35 @@ void ssb_chipco_resume(struct ssb_chipcommon *cc) chipco_powercontrol_init(cc); } +void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc, u32 chip_id, u32 *rate, + u32 *plltype, u32 *n, u32 *m) +{ + *rate = 0; + *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N); + *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT); + switch (*plltype) { + case SSB_PLLTYPE_2: + case SSB_PLLTYPE_4: + case SSB_PLLTYPE_6: + case SSB_PLLTYPE_7: + *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_MIPS); + break; + case SSB_PLLTYPE_5: + *rate = 200000000; + break; + case SSB_PLLTYPE_3: + /* 5350 uses m2 to control mips */ + *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_M2); + break; + default: + *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_SB); + break; + } + + if (*rate == 0 && chip_id == 0x5365) + *rate = 200000000; +} + void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc, u32 *plltype, u32 *n, u32 *m) { -- cgit v1.2.3