From c4105c81c08ae5ec786cc81dc005f2aa58afa751 Mon Sep 17 00:00:00 2001 From: kaloz Date: Sun, 20 May 2007 19:32:31 +0000 Subject: convert aruba to the new structure git-svn-id: svn://svn.openwrt.org/openwrt/trunk@7284 3c298f89-4303-0410-b956-a3cf2f4a3e73 --- .../files/drivers/char/watchdog/wdt_merlot.c | 110 ++ .../aruba-2.6/files/drivers/net/ar2313/Makefile | 5 + .../aruba-2.6/files/drivers/net/ar2313/ar2313.c | 1649 ++++++++++++++++++++ .../aruba-2.6/files/drivers/net/ar2313/ar2313.h | 190 +++ .../files/drivers/net/ar2313/ar2313_msg.h | 17 + .../linux/aruba-2.6/files/drivers/net/ar2313/dma.h | 135 ++ .../aruba-2.6/files/drivers/net/ar2313/platform.h | 128 ++ .../aruba-2.6/files/drivers/net/rc32434_eth.c | 1273 +++++++++++++++ .../aruba-2.6/files/drivers/net/rc32434_eth.h | 187 +++ 9 files changed, 3694 insertions(+) create mode 100644 target/linux/aruba-2.6/files/drivers/char/watchdog/wdt_merlot.c create mode 100644 target/linux/aruba-2.6/files/drivers/net/ar2313/Makefile create mode 100644 target/linux/aruba-2.6/files/drivers/net/ar2313/ar2313.c create mode 100644 target/linux/aruba-2.6/files/drivers/net/ar2313/ar2313.h create mode 100644 target/linux/aruba-2.6/files/drivers/net/ar2313/ar2313_msg.h create mode 100644 target/linux/aruba-2.6/files/drivers/net/ar2313/dma.h create mode 100644 target/linux/aruba-2.6/files/drivers/net/ar2313/platform.h create mode 100644 target/linux/aruba-2.6/files/drivers/net/rc32434_eth.c create mode 100644 target/linux/aruba-2.6/files/drivers/net/rc32434_eth.h (limited to 'target/linux/aruba-2.6/files/drivers') diff --git a/target/linux/aruba-2.6/files/drivers/char/watchdog/wdt_merlot.c b/target/linux/aruba-2.6/files/drivers/char/watchdog/wdt_merlot.c new file mode 100644 index 000000000..de966c869 --- /dev/null +++ b/target/linux/aruba-2.6/files/drivers/char/watchdog/wdt_merlot.c @@ -0,0 +1,110 @@ +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +extern unsigned long mips_machtype; + +static unsigned long wdt_is_open; +static struct timer_list wdt_timer; + +static void wdt_merlot_refresh(void) +{ + volatile __u32 *wdt; + switch (mips_machtype) { + case MACH_ARUBA_AP70: + wdt = (__u32 *) 0xb8030034; + *wdt = 0x10000000; + break; + default: + wdt = (__u32 *) 0xbc00300c; + *wdt = 0x40000000; + break; + } +} + +static void wdt_merlot_timer_fn(unsigned long data) +{ + wdt_merlot_refresh(); + if (!test_bit(1, &wdt_is_open)) + mod_timer(&wdt_timer, jiffies + HZ); +} + +static int wdt_merlot_setup_timer(void) +{ + + init_timer(&wdt_timer); + wdt_timer.function = wdt_merlot_timer_fn; + wdt_timer.data = 0; + wdt_timer.expires = jiffies + HZ; + add_timer(&wdt_timer); + return 0; +} + +static int wdt_open(struct inode *inode, struct file *file) +{ + if (test_and_set_bit(0, &wdt_is_open)) + return -EBUSY; + set_bit(1, &wdt_is_open); + return nonseekable_open(inode, file); +} + +static ssize_t wdt_write(struct file *file, const char __user * buf, size_t count, loff_t * ppos) +{ + if (count) /* something was written */ + wdt_merlot_refresh(); + return count; +} + +static int wdt_release(struct inode *inode, struct file *file) +{ + clear_bit(0, &wdt_is_open); + return 0; +} + +static struct file_operations wdt_fops = { + .owner = THIS_MODULE, + .llseek = no_llseek, + .write = wdt_write, + .open = wdt_open, + .release = wdt_release, +}; + +static struct miscdevice wdt_miscdev = { + .minor = WATCHDOG_MINOR, + .name = "watchdog", + .fops = &wdt_fops, +}; + +static void __exit wdt_exit(void) +{ + misc_deregister(&wdt_miscdev); +} + +static int __init wdt_init(void) +{ + int ret; + ret = misc_register(&wdt_miscdev); + if (ret) { + printk(KERN_ERR + "wdt: cannot register miscdev on minor=%d (err=%d)\n", + WATCHDOG_MINOR, ret); + misc_deregister(&wdt_miscdev); + goto out; + } + printk("wdt: registered with refresh\n"); + wdt_merlot_refresh(); + wdt_merlot_setup_timer(); + out: + return ret; +} + +module_init(wdt_init); +module_exit(wdt_exit); diff --git a/target/linux/aruba-2.6/files/drivers/net/ar2313/Makefile b/target/linux/aruba-2.6/files/drivers/net/ar2313/Makefile new file mode 100644 index 000000000..15db8aa3b --- /dev/null +++ b/target/linux/aruba-2.6/files/drivers/net/ar2313/Makefile @@ -0,0 +1,5 @@ +# +# Makefile for the AR2313 ethernet driver +# + +obj-$(CONFIG_AR2313) += ar2313.o diff --git a/target/linux/aruba-2.6/files/drivers/net/ar2313/ar2313.c b/target/linux/aruba-2.6/files/drivers/net/ar2313/ar2313.c new file mode 100644 index 000000000..72095f83e --- /dev/null +++ b/target/linux/aruba-2.6/files/drivers/net/ar2313/ar2313.c @@ -0,0 +1,1649 @@ +/* + * ar2313.c: Linux driver for the Atheros AR2313 Ethernet device. + * + * Copyright 2004 by Sameer Dekate, . + * Copyright (C) 2006 Imre Kaloz + * + * Thanks to Atheros for providing hardware and documentation + * enabling me to write this driver. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * Additional credits: + * This code is taken from John Taylor's Sibyte driver and then + * modified for the AR2313. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include +#include + +extern char *getenv(char *e); + + +#undef INDEX_DEBUG +#define DEBUG 0 +#define DEBUG_TX 0 +#define DEBUG_RX 0 +#define DEBUG_INT 0 +#define DEBUG_MC 0 +#define DEBUG_ERR 1 + +#ifndef __exit +#define __exit +#endif + +#ifndef min +#define min(a,b) (((a)<(b))?(a):(b)) +#endif + +#ifndef SMP_CACHE_BYTES +#define SMP_CACHE_BYTES L1_CACHE_BYTES +#endif + +#ifndef SET_MODULE_OWNER +#define SET_MODULE_OWNER(dev) {do{} while(0);} +#define AR2313_MOD_INC_USE_COUNT MOD_INC_USE_COUNT +#define AR2313_MOD_DEC_USE_COUNT MOD_DEC_USE_COUNT +#else +#define AR2313_MOD_INC_USE_COUNT {do{} while(0);} +#define AR2313_MOD_DEC_USE_COUNT {do{} while(0);} +#endif + +#define PHYSADDR(a) ((_ACAST32_ (a)) & 0x1fffffff) + +static char ethaddr[18] = "00:00:00:00:00:00"; +static char ifname[5] = "bond"; + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,52) +module_param_string(ethaddr, ethaddr, 18, 0); +module_param_string(ifname, ifname, 5, 0); +#else +MODULE_PARM(ethaddr, "c18"); +MODULE_PARM(ifname, "c5"); +#endif + +#define AR2313_MBOX_SET_BIT 0x8 + +#define BOARD_IDX_STATIC 0 +#define BOARD_IDX_OVERFLOW -1 + +/* margot includes */ +#include + +#include "ar2313_msg.h" +#include "platform.h" +#include "dma.h" +#include "ar2313.h" + +/* + * New interrupt handler strategy: + * + * An old interrupt handler worked using the traditional method of + * replacing an skbuff with a new one when a packet arrives. However + * the rx rings do not need to contain a static number of buffer + * descriptors, thus it makes sense to move the memory allocation out + * of the main interrupt handler and do it in a bottom half handler + * and only allocate new buffers when the number of buffers in the + * ring is below a certain threshold. In order to avoid starving the + * NIC under heavy load it is however necessary to force allocation + * when hitting a minimum threshold. The strategy for alloction is as + * follows: + * + * RX_LOW_BUF_THRES - allocate buffers in the bottom half + * RX_PANIC_LOW_THRES - we are very low on buffers, allocate + * the buffers in the interrupt handler + * RX_RING_THRES - maximum number of buffers in the rx ring + * + * One advantagous side effect of this allocation approach is that the + * entire rx processing can be done without holding any spin lock + * since the rx rings and registers are totally independent of the tx + * ring and its registers. This of course includes the kmalloc's of + * new skb's. Thus start_xmit can run in parallel with rx processing + * and the memory allocation on SMP systems. + * + * Note that running the skb reallocation in a bottom half opens up + * another can of races which needs to be handled properly. In + * particular it can happen that the interrupt handler tries to run + * the reallocation while the bottom half is either running on another + * CPU or was interrupted on the same CPU. To get around this the + * driver uses bitops to prevent the reallocation routines from being + * reentered. + * + * TX handling can also be done without holding any spin lock, wheee + * this is fun! since tx_csm is only written to by the interrupt + * handler. + */ + +/* + * Threshold values for RX buffer allocation - the low water marks for + * when to start refilling the rings are set to 75% of the ring + * sizes. It seems to make sense to refill the rings entirely from the + * intrrupt handler once it gets below the panic threshold, that way + * we don't risk that the refilling is moved to another CPU when the + * one running the interrupt handler just got the slab code hot in its + * cache. + */ +#define RX_RING_SIZE AR2313_DESCR_ENTRIES +#define RX_PANIC_THRES (RX_RING_SIZE/4) +#define RX_LOW_THRES ((3*RX_RING_SIZE)/4) +#define CRC_LEN 4 +#define RX_OFFSET 2 + +#define AR2313_BUFSIZE (AR2313_MTU + ETH_HLEN + CRC_LEN + RX_OFFSET) + +#ifdef MODULE +MODULE_AUTHOR("Sameer Dekate"); +MODULE_DESCRIPTION("AR2313 Ethernet driver"); +#endif + +#if DEBUG +static char version[] __initdata = + "ar2313.c: v0.02 2006/06/19 sdekate@arubanetworks.com\n"; +#endif /* DEBUG */ + +#define virt_to_phys(x) ((u32)(x) & 0x1fffffff) + +// prototypes +static short armiiread(short phy, short reg); +static void armiiwrite(short phy, short reg, short data); +#ifdef TX_TIMEOUT +static void ar2313_tx_timeout(struct net_device *dev); +#endif +static void ar2313_halt(struct net_device *dev); +static void rx_tasklet_func(unsigned long data); +static void ar2313_multicast_list(struct net_device *dev); + +static struct net_device *root_dev; +static int probed __initdata = 0; +static unsigned long ar_eth_base; +static unsigned long ar_dma_base; +static unsigned long ar_int_base; +static unsigned long ar_int_mac_mask; +static unsigned long ar_int_phy_mask; + +#ifndef ERR +#define ERR(fmt, args...) printk("%s: " fmt, __func__, ##args) +#endif + +static int parse_mac_addr(struct net_device *dev, char* macstr){ + int i, j; + unsigned char result, value; + + for (i=0; i<6; i++) { + result = 0; + if (i != 5 && *(macstr+2) != ':') { + ERR("invalid mac address format: %d %c\n", + i, *(macstr+2)); + return -EINVAL; + } + for (j=0; j<2; j++) { + if (isxdigit(*macstr) && (value = isdigit(*macstr) ? *macstr-'0' : + toupper(*macstr)-'A'+10) < 16) + { + result = result*16 + value; + macstr++; + } + else { + ERR("invalid mac address " + "character: %c\n", *macstr); + return -EINVAL; + } + } + + macstr++; + dev->dev_addr[i] = result; + } + + return 0; +} + + +int __init ar2313_probe(void) +{ + struct net_device *dev; + struct ar2313_private *sp; + int version_disp; + char name[64] ; + + if (probed) + return -ENODEV; + probed++; + + version_disp = 0; + sprintf(name, "%s%%d", ifname) ; + dev = alloc_etherdev(sizeof(struct ar2313_private)); + + if (dev == NULL) { + printk(KERN_ERR "ar2313: Unable to allocate net_device structure!\n"); + return -ENOMEM; + } + + SET_MODULE_OWNER(dev); + + sp = dev->priv; + + sp->link = 0; + switch (mips_machtype) { + case MACH_ARUBA_AP60: + ar_eth_base = 0xb8100000; + ar_dma_base = ar_eth_base + 0x1000; + ar_int_base = 0x1C003020; + ar_int_mac_mask = RESET_ENET0|RESET_ENET1; + ar_int_phy_mask = RESET_EPHY0|RESET_EPHY1; + sp->mac = 1; + sp->phy = 1; + dev->irq = 4; + break; + + case MACH_ARUBA_AP40: + ar_eth_base = 0xb0500000; + ar_dma_base = ar_eth_base + 0x1000; + ar_int_base = 0x11000004; + ar_int_mac_mask = 0x800; + ar_int_phy_mask = 0x400; + sp->mac = 0; + sp->phy = 1; + dev->irq = 4; + break; + + case MACH_ARUBA_AP65: + ar_eth_base = 0xb8100000; + ar_dma_base = ar_eth_base + 0x1000; + ar_int_base = 0x1C003020; + ar_int_mac_mask = RESET_ENET0|RESET_ENET1; + ar_int_phy_mask = RESET_EPHY0|RESET_EPHY1; + sp->mac = 0; +#if 0 + // commented out, for now + + if (mips_machtype == MACH_ARUBA_SAMSUNG) { + sp->phy = 0x1f; + } else { + sp->phy = 1; + } +#else + sp->phy = 1; +#endif + dev->irq = 3; + break; + + default: + printk("%s: unsupported mips_machtype=0x%lx\n", + __FUNCTION__, mips_machtype) ; + return -ENODEV; + } + + spin_lock_init(&sp->lock); + + /* initialize func pointers */ + dev->open = &ar2313_open; + dev->stop = &ar2313_close; + dev->hard_start_xmit = &ar2313_start_xmit; + + dev->get_stats = &ar2313_get_stats; + dev->set_multicast_list = &ar2313_multicast_list; +#ifdef TX_TIMEOUT + dev->tx_timeout = ar2313_tx_timeout; + dev->watchdog_timeo = AR2313_TX_TIMEOUT; +#endif + dev->do_ioctl = &ar2313_ioctl; + + // SAMEER: do we need this? + dev->features |= NETIF_F_SG | NETIF_F_HIGHDMA; + + tasklet_init(&sp->rx_tasklet, rx_tasklet_func, (unsigned long) dev); + tasklet_disable(&sp->rx_tasklet); + + /* display version info if adapter is found */ + if (!version_disp) { + /* set display flag to TRUE so that */ + /* we only display this string ONCE */ + version_disp = 1; +#if DEBUG + printk(version); +#endif /* DEBUG */ + } + + request_region(PHYSADDR(ETHERNET_BASE), ETHERNET_SIZE*ETHERNET_MACS, + "AR2313ENET"); + + sp->eth_regs = ioremap_nocache(PHYSADDR(ETHERNET_BASE + ETHERNET_SIZE*sp->mac), + sizeof(*sp->eth_regs)); + if (!sp->eth_regs) { + printk("Can't remap eth registers\n"); + return(-ENXIO); + } + + sp->dma_regs = ioremap_nocache(PHYSADDR(DMA_BASE + DMA_SIZE*sp->mac), + sizeof(*sp->dma_regs)); + dev->base_addr = (unsigned int) sp->dma_regs; + if (!sp->dma_regs) { + printk("Can't remap DMA registers\n"); + return(-ENXIO); + } + + sp->int_regs = ioremap_nocache(PHYSADDR(INTERRUPT_BASE), + sizeof(*sp->int_regs)); + if (!sp->int_regs) { + printk("Can't remap INTERRUPT registers\n"); + return(-ENXIO); + } + + strncpy(sp->name, "Atheros AR2313", sizeof (sp->name) - 1); + sp->name [sizeof (sp->name) - 1] = '\0'; + + { + char mac[32]; + extern char *getenv(char *e); + unsigned char def_mac[6] = {0, 0x0b, 0x86, 0xba, 0xdb, 0xad}; + memset(mac, 0, 32); + memcpy(mac, getenv("ethaddr"), 17); + if (parse_mac_addr(dev, mac)){ + printk("%s: MAC address not found, using default\n", __func__); + memcpy(dev->dev_addr, def_mac, 6); + } + } + + sp->board_idx = BOARD_IDX_STATIC; + + if (ar2313_init(dev)) { + /* + * ar2313_init() calls ar2313_init_cleanup() on error. + */ + kfree(dev); + return -ENODEV; + } + + if (register_netdev(dev)){ + printk("%s: register_netdev failed\n", __func__); + return -1; + } + + printk("%s: %s: %02x:%02x:%02x:%02x:%02x:%02x, irq %d\n", + dev->name, sp->name, + dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2], + dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5], + dev->irq); + + /* start link poll timer */ + ar2313_setup_timer(dev); + + /* + * Register the device + */ + root_dev = dev; + + return 0; +} + +#if 0 +static void ar2313_dump_regs(struct net_device *dev) +{ + unsigned int *ptr, i; + struct ar2313_private *sp = (struct ar2313_private *)dev->priv; + + ptr = (unsigned int *)sp->eth_regs; + for(i=0; i< (sizeof(ETHERNET_STRUCT)/ sizeof(unsigned int)); i++, ptr++) { + printk("ENET: %08x = %08x\n", (int)ptr, *ptr); + } + + ptr = (unsigned int *)sp->dma_regs; + for(i=0; i< (sizeof(DMA)/ sizeof(unsigned int)); i++, ptr++) { + printk("DMA: %08x = %08x\n", (int)ptr, *ptr); + } + + ptr = (unsigned int *)sp->int_regs; + for(i=0; i< (sizeof(INTERRUPT)/ sizeof(unsigned int)); i++, ptr++){ + printk("INT: %08x = %08x\n", (int)ptr, *ptr); + } + + for (i = 0; i < AR2313_DESCR_ENTRIES; i++) { + ar2313_descr_t *td = &sp->tx_ring[i]; + printk("Tx desc %2d: %08x %08x %08x %08x\n", i, + td->status, td->devcs, td->addr, td->descr); + } +} +#endif + +#ifdef TX_TIMEOUT +static void +ar2313_tx_timeout(struct net_device *dev) +{ + struct ar2313_private *sp = (struct ar2313_private *)dev->priv; + unsigned long flags; + +#if DEBUG_TX + printk("Tx timeout\n"); +#endif + spin_lock_irqsave(&sp->lock, flags); + ar2313_restart(dev); + spin_unlock_irqrestore(&sp->lock, flags); +} +#endif + +#if DEBUG_MC +static void +printMcList(struct net_device *dev) +{ + struct dev_mc_list *list = dev->mc_list; + int num=0, i; + while(list){ + printk("%d MC ADDR ", num); + for(i=0;idmi_addrlen;i++) { + printk(":%02x", list->dmi_addr[i]); + } + list = list->next; + printk("\n"); + } +} +#endif + +/* + * Set or clear the multicast filter for this adaptor. + * THIS IS ABSOLUTE CRAP, disabled + */ +static void +ar2313_multicast_list(struct net_device *dev) +{ + /* + * Always listen to broadcasts and + * treat IFF bits independently + */ + struct ar2313_private *sp = (struct ar2313_private *)dev->priv; + unsigned int recognise; + + recognise = sp->eth_regs->mac_control; + + if (dev->flags & IFF_PROMISC) { /* set promiscuous mode */ + recognise |= MAC_CONTROL_PR; + } else { + recognise &= ~MAC_CONTROL_PR; + } + + if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 15)) { +#if DEBUG_MC + printMcList(dev); + printk("%s: all MULTICAST mc_count %d\n", __FUNCTION__, dev->mc_count); +#endif + recognise |= MAC_CONTROL_PM;/* all multicast */ + } else if (dev->mc_count > 0) { +#if DEBUG_MC + printMcList(dev); + printk("%s: mc_count %d\n", __FUNCTION__, dev->mc_count); +#endif + recognise |= MAC_CONTROL_PM; /* for the time being */ + } +#if DEBUG_MC + printk("%s: setting %08x to %08x\n", __FUNCTION__, (int)sp->eth_regs, recognise); +#endif + + sp->eth_regs->mac_control = recognise; +} + +static void rx_tasklet_cleanup(struct net_device *dev) +{ + struct ar2313_private *sp = dev->priv; + + /* + * Tasklet may be scheduled. Need to get it removed from the list + * since we're about to free the struct. + */ + + sp->unloading = 1; + tasklet_enable(&sp->rx_tasklet); + tasklet_kill(&sp->rx_tasklet); +} + +static void __exit ar2313_module_cleanup(void) +{ + rx_tasklet_cleanup(root_dev); + ar2313_init_cleanup(root_dev); + unregister_netdev(root_dev); + kfree(root_dev); + release_region(PHYSADDR(ETHERNET_BASE), ETHERNET_SIZE*ETHERNET_MACS); +} + + +/* + * Restart the AR2313 ethernet controller. + */ +static int ar2313_restart(struct net_device *dev) +{ + /* disable interrupts */ + disable_irq(dev->irq); + + /* stop mac */ + ar2313_halt(dev); + + /* initialize */ + ar2313_init(dev); + + /* enable interrupts */ + enable_irq(dev->irq); + + return 0; +} + +extern unsigned long mips_machtype; + +int __init ar2313_module_init(void) +{ + int status=-1; + switch (mips_machtype){ + case MACH_ARUBA_AP60: + case MACH_ARUBA_AP65: + case MACH_ARUBA_AP40: + root_dev = NULL; + status = ar2313_probe(); + break; + } + return status; +} + + +module_init(ar2313_module_init); +module_exit(ar2313_module_cleanup); + + +static void ar2313_free_descriptors(struct net_device *dev) +{ + struct ar2313_private *sp = dev->priv; + if (sp->rx_ring != NULL) { + kfree((void*)KSEG0ADDR(sp->rx_ring)); + sp->rx_ring = NULL; + sp->tx_ring = NULL; + } +} + + +static int ar2313_allocate_descriptors(struct net_device *dev) +{ + struct ar2313_private *sp = dev->priv; + int size; + int j; + ar2313_descr_t *space; + + if(sp->rx_ring != NULL){ + printk("%s: already done.\n", __FUNCTION__); + return 0; + } + + size = (sizeof(ar2313_descr_t) * (AR2313_DESCR_ENTRIES * AR2313_QUEUES)); + space = kmalloc(size, GFP_KERNEL); + if (space == NULL) + return 1; + + /* invalidate caches */ + dma_cache_inv((unsigned int)space, size); + + /* now convert pointer to KSEG1 */ + space = (ar2313_descr_t *)KSEG1ADDR(space); + + memset((void *)space, 0, size); + + sp->rx_ring = space; + space += AR2313_DESCR_ENTRIES; + + sp->tx_ring = space; + space += AR2313_DESCR_ENTRIES; + + /* Initialize the transmit Descriptors */ + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) { + ar2313_descr_t *td = &sp->tx_ring[j]; + td->status = 0; + td->devcs = DMA_TX1_CHAINED; + td->addr = 0; + td->descr = K1_TO_PHYS(&sp->tx_ring[(j+1) & (AR2313_DESCR_ENTRIES-1)]); + } + + return 0; +} + + +/* + * Generic cleanup handling data allocated during init. Used when the + * module is unloaded or if an error occurs during initialization + */ +static void ar2313_init_cleanup(struct net_device *dev) +{ + struct ar2313_private *sp = dev->priv; + struct sk_buff *skb; + int j; + + ar2313_free_descriptors(dev); + + if (sp->eth_regs) iounmap((void*)sp->eth_regs); + if (sp->dma_regs) iounmap((void*)sp->dma_regs); + + if (sp->rx_skb) { + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) { + skb = sp->rx_skb[j]; + if (skb) { + sp->rx_skb[j] = NULL; + dev_kfree_skb(skb); + } + } + kfree(sp->rx_skb); + sp->rx_skb = NULL; + } + + if (sp->tx_skb) { + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) { + skb = sp->tx_skb[j]; + if (skb) { + sp->tx_skb[j] = NULL; + dev_kfree_skb(skb); + } + } + kfree(sp->tx_skb); + sp->tx_skb = NULL; + } +} + +static int ar2313_setup_timer(struct net_device *dev) +{ + struct ar2313_private *sp = dev->priv; + + init_timer(&sp->link_timer); + + sp->link_timer.function = ar2313_link_timer_fn; + sp->link_timer.data = (int) dev; + sp->link_timer.expires = jiffies + HZ; + + add_timer(&sp->link_timer); + return 0; + +} + +static void ar2313_link_timer_fn(unsigned long data) +{ + struct net_device *dev = (struct net_device *) data; + struct ar2313_private *sp = dev->priv; + + // see if the link status changed + // This was needed to make sure we set the PHY to the + // autonegotiated value of half or full duplex. + ar2313_check_link(dev); + + // Loop faster when we don't have link. + // This was needed to speed up the AP bootstrap time. + if(sp->link == 0) { + mod_timer(&sp->link_timer, jiffies + HZ/2); + } else { + mod_timer(&sp->link_timer, jiffies + LINK_TIMER); + } +} + +static void ar2313_check_link(struct net_device *dev) +{ + struct ar2313_private *sp = dev->priv; + u16 phyData; + + phyData = armiiread(sp->phy, MII_BMSR); + if (sp->phyData != phyData) { + if (phyData & BMSR_LSTATUS) { + /* link is present, ready link partner ability to deterine duplexity */ + int duplex = 0; + u16 reg; + + sp->link = 1; + reg = armiiread(sp->phy, MII_BMCR); + if (reg & BMCR_ANENABLE) { + /* auto neg enabled */ + reg = armiiread(sp->phy, MII_LPA); + duplex = (reg & (LPA_100FULL|LPA_10FULL))? 1:0; + } else { + /* no auto neg, just read duplex config */ + duplex = (reg & BMCR_FULLDPLX)? 1:0; + } + + printk(KERN_INFO "%s: Configuring MAC for %s duplex\n", dev->name, + (duplex)? "full":"half"); + + if (duplex) { + /* full duplex */ + sp->eth_regs->mac_control = ((sp->eth_regs->mac_control | MAC_CONTROL_F) & + ~MAC_CONTROL_DRO); + } else { + /* half duplex */ + sp->eth_regs->mac_control = ((sp->eth_regs->mac_control | MAC_CONTROL_DRO) & + ~MAC_CONTROL_F); + } + } else { + /* no link */ + sp->link = 0; + } + sp->phyData = phyData; + } +} + +static int +ar2313_reset_reg(struct net_device *dev) +{ + struct ar2313_private *sp = (struct ar2313_private *)dev->priv; + unsigned int ethsal, ethsah; + unsigned int flags; + + *sp->int_regs |= ar_int_mac_mask; + mdelay(10); + *sp->int_regs &= ~ar_int_mac_mask; + mdelay(10); + *sp->int_regs |= ar_int_phy_mask; + mdelay(10); + *sp->int_regs &= ~ar_int_phy_mask; + mdelay(10); + + sp->dma_regs->bus_mode = (DMA_BUS_MODE_SWR); + mdelay(10); + sp->dma_regs->bus_mode = ((32 << DMA_BUS_MODE_PBL_SHIFT) | DMA_BUS_MODE_BLE); + + /* enable interrupts */ + sp->dma_regs->intr_ena = (DMA_STATUS_AIS | + DMA_STATUS_NIS | + DMA_STATUS_RI | + DMA_STATUS_TI | + DMA_STATUS_FBE); + sp->dma_regs->xmt_base = K1_TO_PHYS(sp->tx_ring); + sp->dma_regs->rcv_base = K1_TO_PHYS(sp->rx_ring); + sp->dma_regs->control = (DMA_CONTROL_SR | DMA_CONTROL_ST | DMA_CONTROL_SF); + + sp->eth_regs->flow_control = (FLOW_CONTROL_FCE); + sp->eth_regs->vlan_tag = (0x8100); + + /* Enable Ethernet Interface */ + flags = (MAC_CONTROL_TE | /* transmit enable */ + MAC_CONTROL_PM | /* pass mcast */ + MAC_CONTROL_F | /* full duplex */ + MAC_CONTROL_HBD); /* heart beat disabled */ + + if (dev->flags & IFF_PROMISC) { /* set promiscuous mode */ + flags |= MAC_CONTROL_PR; + } + sp->eth_regs->mac_control = flags; + + /* Set all Ethernet station address registers to their initial values */ + ethsah = ((((u_int)(dev->dev_addr[5]) << 8) & (u_int)0x0000FF00) | + (((u_int)(dev->dev_addr[4]) << 0) & (u_int)0x000000FF)); + + ethsal = ((((u_int)(dev->dev_addr[3]) << 24) & (u_int)0xFF000000) | + (((u_int)(dev->dev_addr[2]) << 16) & (u_int)0x00FF0000) | + (((u_int)(dev->dev_addr[1]) << 8) & (u_int)0x0000FF00) | + (((u_int)(dev->dev_addr[0]) << 0) & (u_int)0x000000FF) ); + + sp->eth_regs->mac_addr[0] = ethsah; + sp->eth_regs->mac_addr[1] = ethsal; + + mdelay(10); + + return(0); +} + + +static int ar2313_init(struct net_device *dev) +{ + struct ar2313_private *sp = dev->priv; + int ecode=0; + + /* + * Allocate descriptors + */ + if (ar2313_allocate_descriptors(dev)) { + printk("%s: %s: ar2313_allocate_descriptors failed\n", + dev->name, __FUNCTION__); + ecode = -EAGAIN; + goto init_error; + } + + /* + * Get the memory for the skb rings. + */ + if(sp->rx_skb == NULL) { + sp->rx_skb = kmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES, GFP_KERNEL); + if (!(sp->rx_skb)) { + printk("%s: %s: rx_skb kmalloc failed\n", + dev->name, __FUNCTION__); + ecode = -EAGAIN; + goto init_error; + } + } + memset(sp->rx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES); + + if(sp->tx_skb == NULL) { + sp->tx_skb = kmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES, GFP_KERNEL); + if (!(sp->tx_skb)) { + printk("%s: %s: tx_skb kmalloc failed\n", + dev->name, __FUNCTION__); + ecode = -EAGAIN; + goto init_error; + } + } + memset(sp->tx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES); + + /* + * Set tx_csm before we start receiving interrupts, otherwise + * the interrupt handler might think it is supposed to process + * tx ints before we are up and running, which may cause a null + * pointer access in the int handler. + */ + sp->rx_skbprd = 0; + sp->cur_rx = 0; + sp->tx_prd = 0; + sp->tx_csm = 0; + + /* + * Zero the stats before starting the interface + */ + memset(&sp->stats, 0, sizeof(sp->stats)); + + /* + * We load the ring here as there seem to be no way to tell the + * firmware to wipe the ring without re-initializing it. + */ + ar2313_load_rx_ring(dev, RX_RING_SIZE); + + /* + * Init hardware + */ + ar2313_reset_reg(dev); + + /* + * Get the IRQ + */ + ecode = request_irq(dev->irq, &ar2313_interrupt, SA_SHIRQ | SA_INTERRUPT, dev->name, dev); + if (ecode) { + printk(KERN_WARNING "%s: %s: Requested IRQ %d is busy\n", + dev->name, __FUNCTION__, dev->irq); + goto init_error; + } + +#if 0 + // commented out, for now + + if(mips_machtype == MACH_ARUBA_SAMSUNG) { + int i; + /* configure Marvell 88E6060 */ + /* reset chip */ + armiiwrite(0x1f, 0xa, 0xa130); + do { + udelay(1000); + i = armiiread(sp->phy, 0xa); + } while (i & 0x8000); + + /* configure MAC address */ + armiiwrite(sp->phy, 0x1, dev->dev_addr[0] << 8 | dev->dev_addr[1]); + armiiwrite(sp->phy, 0x2, dev->dev_addr[2] << 8 | dev->dev_addr[3]); + armiiwrite(sp->phy, 0x3, dev->dev_addr[4] << 8 | dev->dev_addr[5]); + + /* set ports to forwarding */ + armiiwrite(0x18, 0x4, 0x3); + armiiwrite(0x1c, 0x4, 0x3); + armiiwrite(0x1d, 0x4, 0x3); + } +#endif + + tasklet_enable(&sp->rx_tasklet); + + return 0; + + init_error: + ar2313_init_cleanup(dev); + return ecode; +} + +/* + * Load the rx ring. + * + * Loading rings is safe without holding the spin lock since this is + * done only before the device is enabled, thus no interrupts are + * generated and by the interrupt handler/tasklet handler. + */ +static void ar2313_load_rx_ring(struct net_device *dev, int nr_bufs) +{ + + struct ar2313_private *sp = ((struct net_device *)dev)->priv; + short i, idx; + + idx = sp->rx_skbprd; + + for (i = 0; i < nr_bufs; i++) { + struct sk_buff *skb; + ar2313_descr_t *rd; + + if (sp->rx_skb[idx]) { +#if DEBUG_RX + printk(KERN_INFO "ar2313 rx refill full\n"); +#endif /* DEBUG */ + break; + } + + // partha: create additional room for the second GRE fragment + skb = alloc_skb(AR2313_BUFSIZE+128, GFP_ATOMIC); + if (!skb) { + printk("\n\n\n\n %s: No memory in system\n\n\n\n", __FUNCTION__); + break; + } + // partha: create additional room in the front for tx pkt capture + skb_reserve(skb, 32); + + /* + * Make sure IP header starts on a fresh cache line. + */ + skb->dev = dev; + skb_reserve(skb, RX_OFFSET); + sp->rx_skb[idx] = skb; + + rd = (ar2313_descr_t *) &sp->rx_ring[idx]; + + /* initialize dma descriptor */ + rd->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) | + DMA_RX1_CHAINED); + rd->addr = virt_to_phys(skb->data); + rd->descr = virt_to_phys(&sp->rx_ring[(idx+1) & (AR2313_DESCR_ENTRIES-1)]); + rd->status = DMA_RX_OWN; + + idx = DSC_NEXT(idx); + } + + if (!i) { +#if DEBUG_ERR + printk(KERN_INFO "Out of memory when allocating standard receive buffers\n"); +#endif /* DEBUG */ + } else { + sp->rx_skbprd = idx; + } + + return; +} + +#define AR2313_MAX_PKTS_PER_CALL 64 + +static int ar2313_rx_int(struct net_device *dev) +{ + struct ar2313_private *sp = dev->priv; + struct sk_buff *skb, *skb_new; + ar2313_descr_t *rxdesc; + unsigned int status; + u32 idx; + int pkts = 0; + int rval; + + idx = sp->cur_rx; + + /* process at most the entire ring and then wait for another interrupt */ + while(1) { + + rxdesc = &sp->rx_ring[idx]; + status = rxdesc->status; + if (status & DMA_RX_OWN) { + /* SiByte owns descriptor or descr not yet filled in */ + rval = 0; + break; + } + + if (++pkts > AR2313_MAX_PKTS_PER_CALL) { + rval = 1; + break; + } + +#if DEBUG_RX + printk("index %d\n", idx); + printk("RX status %08x\n", rxdesc->status); + printk("RX devcs %08x\n", rxdesc->devcs ); + printk("RX addr %08x\n", rxdesc->addr ); + printk("RX descr %08x\n", rxdesc->descr ); +#endif + + if ((status & (DMA_RX_ERROR|DMA_RX_ERR_LENGTH)) && + (!(status & DMA_RX_LONG))){ +#if DEBUG_RX + printk("%s: rx ERROR %08x\n", __FUNCTION__, status); +#endif + sp->stats.rx_errors++; + sp->stats.rx_dropped++; + + /* add statistics counters */ + if (status & DMA_RX_ERR_CRC) sp->stats.rx_crc_errors++; + if (status & DMA_RX_ERR_COL) sp->stats.rx_over_errors++; + if (status & DMA_RX_ERR_LENGTH) + sp->stats.rx_length_errors++; + if (status & DMA_RX_ERR_RUNT) sp->stats.rx_over_errors++; + if (status & DMA_RX_ERR_DESC) sp->stats.rx_over_errors++; + + } else { + /* alloc new buffer. */ + skb_new = dev_alloc_skb(AR2313_BUFSIZE + RX_OFFSET + 128); + if (skb_new != NULL) { + + skb = sp->rx_skb[idx]; + /* set skb */ + skb_put(skb, ((status >> DMA_RX_LEN_SHIFT) & 0x3fff) - CRC_LEN); + +#ifdef CONFIG_MERLOT + if ((dev->am_pkt_handler == NULL) || + (dev->am_pkt_handler(skb, dev) == 0)) { +#endif + sp->stats.rx_bytes += skb->len; + skb->protocol = eth_type_trans(skb, dev); + /* pass the packet to upper layers */ + +#ifdef CONFIG_MERLOT + if (dev->asap_netif_rx) + dev->asap_netif_rx(skb); + else +#endif + netif_rx(skb); +#ifdef CONFIG_MERLOT + } +#endif + skb_new->dev = dev; + /* 16 bit align */ + skb_reserve(skb_new, RX_OFFSET+32); + /* reset descriptor's curr_addr */ + rxdesc->addr = virt_to_phys(skb_new->data); + + sp->stats.rx_packets++; + sp->rx_skb[idx] = skb_new; + + } else { + sp->stats.rx_dropped++; + } + } + + rxdesc->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) | + DMA_RX1_CHAINED); + rxdesc->status = DMA_RX_OWN; + + idx = DSC_NEXT(idx); + } + + sp->cur_rx = idx; + + return rval; +} + + +static void ar2313_tx_int(struct net_device *dev) +{ + struct ar2313_private *sp = dev->priv; + u32 idx; + struct sk_buff *skb; + ar2313_descr_t *txdesc; + unsigned int status=0; + + idx = sp->tx_csm; + + while (idx != sp->tx_prd) { + + txdesc = &sp->tx_ring[idx]; + +#if DEBUG_TX + printk("%s: TXINT: csm=%d idx=%d prd=%d status=%x devcs=%x addr=%08x descr=%x\n", + dev->name, sp->tx_csm, idx, sp->tx_prd, + txdesc->status, txdesc->devcs, txdesc->addr, txdesc->descr); +#endif /* DEBUG */ + + if ((status = txdesc->status) & DMA_TX_OWN) { + /* ar2313 dma still owns descr */ + break; + } + /* done with this descriptor */ + txdesc->status = 0; + + if (status & DMA_TX_ERROR){ + sp->stats.tx_errors++; + sp->stats.tx_dropped++; + if(status & DMA_TX_ERR_UNDER) + sp->stats.tx_fifo_errors++; + if(status & DMA_TX_ERR_HB) + sp->stats.tx_heartbeat_errors++; + if(status & (DMA_TX_ERR_LOSS | + DMA_TX_ERR_LINK)) + sp->stats.tx_carrier_errors++; + if (status & (DMA_TX_ERR_LATE| + DMA_TX_ERR_COL | + DMA_TX_ERR_JABBER | + DMA_TX_ERR_DEFER)) + sp->stats.tx_aborted_errors++; + } else { + /* transmit OK */ + sp->stats.tx_packets++; + } + + skb = sp->tx_skb[idx]; + sp->tx_skb[idx] = NULL; + idx = DSC_NEXT(idx); + sp->stats.tx_bytes += skb->len; + dev_kfree_skb_irq(skb); + } + + sp->tx_csm = idx; + + return; +} + + +static void +rx_tasklet_func(unsigned long data) +{ + struct net_device *dev = (struct net_device *) data; + struct ar2313_private *sp = dev->priv; + + if (sp->unloading) { + return; + } + + if (ar2313_rx_int(dev)) { + tasklet_hi_schedule(&sp->rx_tasklet); + } + else { + unsigned long flags; + spin_lock_irqsave(&sp->lock, flags); + sp->dma_regs->intr_ena |= DMA_STATUS_RI; + spin_unlock_irqrestore(&sp->lock, flags); + } +} + +static void +rx_schedule(struct net_device *dev) +{ + struct ar2313_private *sp = dev->priv; + + sp->dma_regs->intr_ena &= ~DMA_STATUS_RI; + + tasklet_hi_schedule(&sp->rx_tasklet); +} + +static irqreturn_t ar2313_interrupt(int irq, void *dev_id) +{ + struct net_device *dev = (struct net_device *)dev_id; + struct ar2313_private *sp = dev->priv; + unsigned int status, enabled; + + /* clear interrupt */ + /* + * Don't clear RI bit if currently disabled. + */ + status = sp->dma_regs->status; + enabled = sp->dma_regs->intr_ena; + sp->dma_regs->status = status & enabled; + + if (status & DMA_STATUS_NIS) { + /* normal status */ + /* + * Don't schedule rx processing if interrupt + * is already disabled. + */ + if (status & enabled & DMA_STATUS_RI) { + /* receive interrupt */ + rx_schedule(dev); + } + if (status & DMA_STATUS_TI) { + /* transmit interrupt */ + ar2313_tx_int(dev); + } + } + + if (status & DMA_STATUS_AIS) { +#if DEBUG_INT + printk("%s: AIS set %08x & %x\n", __FUNCTION__, + status, (DMA_STATUS_FBE | DMA_STATUS_TPS)); +#endif + /* abnormal status */ + if (status & (DMA_STATUS_FBE | DMA_STATUS_TPS)) { + ar2313_restart(dev); + } + } + return IRQ_HANDLED; +} + + +static int ar2313_open(struct net_device *dev) +{ + struct ar2313_private *sp; + + sp = dev->priv; + + dev->mtu = 1500; + netif_start_queue(dev); + + sp->eth_regs->mac_control |= MAC_CONTROL_RE; + + AR2313_MOD_INC_USE_COUNT; + + return 0; +} + +static void ar2313_halt(struct net_device *dev) +{ + struct ar2313_private *sp = dev->priv; + int j; + + tasklet_disable(&sp->rx_tasklet); + + /* kill the MAC */ + sp->eth_regs->mac_control &= ~(MAC_CONTROL_RE | /* disable Receives */ + MAC_CONTROL_TE); /* disable Transmits */ + /* stop dma */ + sp->dma_regs->control = 0; + sp->dma_regs->bus_mode = DMA_BUS_MODE_SWR; + + /* place phy and MAC in reset */ + *sp->int_regs |= (ar_int_mac_mask | ar_int_phy_mask); + + /* free buffers on tx ring */ + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) { + struct sk_buff *skb; + ar2313_descr_t *txdesc; + + txdesc = &sp->tx_ring[j]; + txdesc->descr = 0; + + skb = sp->tx_skb[j]; + if (skb) { + dev_kfree_skb(skb); + sp->tx_skb[j] = NULL; + } + } +} + +/* + * close should do nothing. Here's why. It's called when + * 'ifconfig bond0 down' is run. If it calls free_irq then + * the irq is gone forever ! When bond0 is made 'up' again, + * the ar2313_open () does not call request_irq (). Worse, + * the call to ar2313_halt() generates a WDOG reset due to + * the write to 'sp->int_regs' and the box reboots. + * Commenting this out is good since it allows the + * system to resume when bond0 is made up again. + */ +static int ar2313_close(struct net_device *dev) +{ +#if 0 + /* + * Disable interrupts + */ + disable_irq(dev->irq); + + /* + * Without (or before) releasing irq and stopping hardware, this + * is an absolute non-sense, by the way. It will be reset instantly + * by the first irq. + */ + netif_stop_queue(dev); + + /* stop the MAC and DMA engines */ + ar2313_halt(dev); + + /* release the interrupt */ + free_irq(dev->irq, dev); + +#endif + AR2313_MOD_DEC_USE_COUNT; + return 0; +} + +static int ar2313_start_xmit(struct sk_buff *skb, struct net_device *dev) +{ + struct ar2313_private *sp = dev->priv; + ar2313_descr_t *td; + u32 idx; + + idx = sp->tx_prd; + td = &sp->tx_ring[idx]; + + if (td->status & DMA_TX_OWN) { +#if DEBUG_TX + printk("%s: No space left to Tx\n", __FUNCTION__); +#endif + /* free skbuf and lie to the caller that we sent it out */ + sp->stats.tx_dropped++; + dev_kfree_skb(skb); + + /* restart transmitter in case locked */ + sp->dma_regs->xmt_poll = 0; + return 0; + } + + /* Setup the transmit descriptor. */ + td->devcs = ((skb->len << DMA_TX1_BSIZE_SHIFT) | + (DMA_TX1_LS|DMA_TX1_IC|DMA_TX1_CHAINED)); + td->addr = virt_to_phys(skb->data); + td->status = DMA_TX_OWN; + + /* kick transmitter last */ + sp->dma_regs->xmt_poll = 0; + +#if DEBUG_TX + printk("index %d\n", idx); + printk("TX status %08x\n", td->status); + printk("TX devcs %08x\n", td->devcs ); + printk("TX addr %08x\n", td->addr ); + printk("TX descr %08x\n", td->descr ); +#endif + + sp->tx_skb[idx] = skb; + idx = DSC_NEXT(idx); + sp->tx_prd = idx; + + //dev->trans_start = jiffies; + + return 0; +} + +static int netdev_get_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd) +{ + struct ar2313_private *np = dev->priv; + u32 tmp; + + ecmd->supported = + (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | + SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | + SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII); + + ecmd->port = PORT_TP; + /* only supports internal transceiver */ + ecmd->transceiver = XCVR_INTERNAL; + /* not sure what this is for */ + ecmd->phy_address = 1; + + ecmd->advertising = ADVERTISED_MII; + tmp = armiiread(np->phy, MII_ADVERTISE); + if (tmp & ADVERTISE_10HALF) + ecmd->advertising |= ADVERTISED_10baseT_Half; + if (tmp & ADVERTISE_10FULL) + ecmd->advertising |= ADVERTISED_10baseT_Full; + if (tmp & ADVERTISE_100HALF) + ecmd->advertising |= ADVERTISED_100baseT_Half; + if (tmp & ADVERTISE_100FULL) + ecmd->advertising |= ADVERTISED_100baseT_Full; + + tmp = armiiread(np->phy, MII_BMCR); + if (tmp & BMCR_ANENABLE) { + ecmd->advertising |= ADVERTISED_Autoneg; + ecmd->autoneg = AUTONEG_ENABLE; + } else { + ecmd->autoneg = AUTONEG_DISABLE; + } + + if (ecmd->autoneg == AUTONEG_ENABLE) { + tmp = armiiread(np->phy, MII_LPA); + if (tmp & (LPA_100FULL|LPA_10FULL)) { + ecmd->duplex = DUPLEX_FULL; + } else { + ecmd->duplex = DUPLEX_HALF; + } + if (tmp & (LPA_100FULL|LPA_100HALF)) { + ecmd->speed = SPEED_100; + } else { + ecmd->speed = SPEED_10; + } + } else { + if (tmp & BMCR_FULLDPLX) { + ecmd->duplex = DUPLEX_FULL; + } else { + ecmd->duplex = DUPLEX_HALF; + } + if (tmp & BMCR_SPEED100) { + ecmd->speed = SPEED_100; + } else { + ecmd->speed = SPEED_10; + } + } + + /* ignore maxtxpkt, maxrxpkt for now */ + + return 0; +} + +static int netdev_set_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd) +{ + struct ar2313_private *np = dev->priv; + u32 tmp; + + if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100) + return -EINVAL; + if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL) + return -EINVAL; + if (ecmd->port != PORT_TP) + return -EINVAL; + if (ecmd->transceiver != XCVR_INTERNAL) + return -EINVAL; + if (ecmd->autoneg != AUTONEG_DISABLE && ecmd->autoneg != AUTONEG_ENABLE) + return -EINVAL; + /* ignore phy_address, maxtxpkt, maxrxpkt for now */ + + /* WHEW! now lets bang some bits */ + + tmp = armiiread(np->phy, MII_BMCR); + if (ecmd->autoneg == AUTONEG_ENABLE) { + /* turn on autonegotiation */ + tmp |= BMCR_ANENABLE; + printk("%s: Enabling auto-neg\n", dev->name); + } else { + /* turn off auto negotiation, set speed and duplexity */ + tmp &= ~(BMCR_ANENABLE | BMCR_SPEED100 | BMCR_FULLDPLX); + if (ecmd->speed == SPEED_100) + tmp |= BMCR_SPEED100; + if (ecmd->duplex == DUPLEX_FULL) + tmp |= BMCR_FULLDPLX; + printk("%s: Hard coding %d/%s\n", dev->name, + (ecmd->speed == SPEED_100)? 100:10, + (ecmd->duplex == DUPLEX_FULL)? "full":"half"); + } + armiiwrite(np->phy, MII_BMCR, tmp); + np->phyData = 0; + return 0; +} + +static int netdev_ethtool_ioctl(struct net_device *dev, void *useraddr) +{ + struct ar2313_private *np = dev->priv; + u32 cmd; + + if (get_user(cmd, (u32 *)useraddr)) + return -EFAULT; + + switch (cmd) { + /* get settings */ + case ETHTOOL_GSET: { + struct ethtool_cmd ecmd = { ETHTOOL_GSET }; + spin_lock_irq(&np->lock); + netdev_get_ecmd(dev, &ecmd); + spin_unlock_irq(&np->lock); + if (copy_to_user(useraddr, &ecmd, sizeof(ecmd))) + return -EFAULT; + return 0; + } + /* set settings */ + case ETHTOOL_SSET: { + struct ethtool_cmd ecmd; + int r; + if (copy_from_user(&ecmd, useraddr, sizeof(ecmd))) + return -EFAULT; + spin_lock_irq(&np->lock); + r = netdev_set_ecmd(dev, &ecmd); + spin_unlock_irq(&np->lock); + return r; + } + /* restart autonegotiation */ + case ETHTOOL_NWAY_RST: { + int tmp; + int r = -EINVAL; + /* if autoneg is off, it's an error */ + tmp = armiiread(np->phy, MII_BMCR); + if (tmp & BMCR_ANENABLE) { + tmp |= (BMCR_ANRESTART); + armiiwrite(np->phy, MII_BMCR, tmp); + r = 0; + } + return r; + } + /* get link status */ + case ETHTOOL_GLINK: { + struct ethtool_value edata = {ETHTOOL_GLINK}; + edata.data = (armiiread(np->phy, MII_BMSR)&BMSR_LSTATUS) ? 1:0; + if (copy_to_user(useraddr, &edata, sizeof(edata))) + return -EFAULT; + return 0; + } + } + + return -EOPNOTSUPP; +} + +static int ar2313_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) +{ + struct mii_ioctl_data *data = (struct mii_ioctl_data *)&ifr->ifr_data; + + switch (cmd) { + case SIOCDEVPRIVATE: { + struct ar2313_cmd scmd; + + if (copy_from_user(&scmd, ifr->ifr_data, sizeof(scmd))) + return -EFAULT; + +#if DEBUG + printk("%s: ioctl devprivate c=%d a=%x l=%d m=%d d=%x,%x\n", + dev->name, scmd.cmd, + scmd.address, scmd.length, + scmd.mailbox, scmd.data[0], scmd.data[1]); +#endif /* DEBUG */ + + switch (scmd.cmd) { + case AR2313_READ_DATA: + if(scmd.length==4){ + scmd.data[0] = *((u32*)scmd.address); + } else if(scmd.length==2) { + scmd.data[0] = *((u16*)scmd.address); + } else if (scmd.length==1) { + scmd.data[0] = *((u8*)scmd.address); + } else { + return -EOPNOTSUPP; + } + if(copy_to_user(ifr->ifr_data, &scmd, sizeof(scmd))) + return -EFAULT; + break; + + case AR2313_WRITE_DATA: + if(scmd.length==4){ + *((u32*)scmd.address) = scmd.data[0]; + } else if(scmd.length==2) { + *((u16*)scmd.address) = scmd.data[0]; + } else if (scmd.length==1) { + *((u8*)scmd.address) = scmd.data[0]; + } else { + return -EOPNOTSUPP; + } + break; + + case AR2313_GET_VERSION: + // SAMEER: sprintf((char*) &scmd, "%s", ARUBA_VERSION); + if(copy_to_user(ifr->ifr_data, &scmd, sizeof(scmd))) + return -EFAULT; + break; + + default: + return -EOPNOTSUPP; + } + return 0; + } + + case SIOCETHTOOL: + return netdev_ethtool_ioctl(dev, (void *) ifr->ifr_data); + + case SIOCGMIIPHY: /* Get address of MII PHY in use. */ + data->phy_id = 1; + /* Fall Through */ + + case SIOCGMIIREG: /* Read MII PHY register. */ + case SIOCDEVPRIVATE+1: /* for binary compat, remove in 2.5 */ + data->val_out = armiiread(data->phy_id & 0x1f, + data->reg_num & 0x1f); + return 0; + case SIOCSMIIREG: /* Write MII PHY register. */ + case SIOCDEVPRIVATE+2: /* for binary compat, remove in 2.5 */ + if (!capable(CAP_NET_ADMIN)) + return -EPERM; + armiiwrite(data->phy_id & 0x1f, + data->reg_num & 0x1f, data->val_in); + return 0; + + case SIOCSIFHWADDR: + if (copy_from_user(dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr))) + return -EFAULT; + return 0; + + case SIOCGIFHWADDR: + if (copy_to_user(ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr))) + return -EFAULT; + return 0; + + default: + break; + } + + return -EOPNOTSUPP; +} + +static struct net_device_stats *ar2313_get_stats(struct net_device *dev) +{ + struct ar2313_private *sp = dev->priv; + return &sp->stats; +} + +static short +armiiread(short phy, short reg) +{ + volatile ETHERNET_STRUCT * ethernet; + + ethernet = (volatile ETHERNET_STRUCT *)ETHERNET_BASE; /* always MAC 0 */ + ethernet->mii_addr = ((reg << MII_ADDR_REG_SHIFT) | + (phy << MII_ADDR_PHY_SHIFT)); + while (ethernet->mii_addr & MII_ADDR_BUSY); + return (ethernet->mii_data >> MII_DATA_SHIFT); +} + +static void +armiiwrite(short phy, short reg, short data) +{ + volatile ETHERNET_STRUCT * ethernet; + + ethernet = (volatile ETHERNET_STRUCT *)ETHERNET_BASE; /* always MAC 0 */ + while (ethernet->mii_addr & MII_ADDR_BUSY); + ethernet->mii_data = data << MII_DATA_SHIFT; + ethernet->mii_addr = ((reg << MII_ADDR_REG_SHIFT) | + (phy << MII_ADDR_PHY_SHIFT) | + MII_ADDR_WRITE); +} + diff --git a/target/linux/aruba-2.6/files/drivers/net/ar2313/ar2313.h b/target/linux/aruba-2.6/files/drivers/net/ar2313/ar2313.h new file mode 100644 index 000000000..83e355962 --- /dev/null +++ b/target/linux/aruba-2.6/files/drivers/net/ar2313/ar2313.h @@ -0,0 +1,190 @@ +#ifndef _AR2313_H_ +#define _AR2313_H_ + +#include +#include +#include "platform.h" + +extern unsigned long mips_machtype; + +#undef ETHERNET_BASE +#define ETHERNET_BASE ar_eth_base +#define ETHERNET_SIZE 0x00100000 +#define ETHERNET_MACS 2 + +#undef DMA_BASE +#define DMA_BASE ar_dma_base +#define DMA_SIZE 0x00100000 + + +/* + * probe link timer - 5 secs + */ +#define LINK_TIMER (5*HZ) + +/* + * Interrupt register base address + */ +#define INTERRUPT_BASE PHYS_TO_K1(ar_int_base) + +/* + * Reset Register + */ +#define AR531X_RESET (AR531X_RESETTMR + 0x0020) +#define RESET_SYSTEM 0x00000001 /* cold reset full system */ +#define RESET_PROC 0x00000002 /* cold reset MIPS core */ +#define RESET_WLAN0 0x00000004 /* cold reset WLAN MAC and BB */ +#define RESET_EPHY0 0x00000008 /* cold reset ENET0 phy */ +#define RESET_EPHY1 0x00000010 /* cold reset ENET1 phy */ +#define RESET_ENET0 0x00000020 /* cold reset ENET0 mac */ +#define RESET_ENET1 0x00000040 /* cold reset ENET1 mac */ + +#define IS_DMA_TX_INT(X) (((X) & (DMA_STATUS_TI)) != 0) +#define IS_DMA_RX_INT(X) (((X) & (DMA_STATUS_RI)) != 0) +#define IS_DRIVER_OWNED(X) (((X) & (DMA_TX_OWN)) == 0) + +#ifndef K1_TO_PHYS +// hack +#define K1_TO_PHYS(x) (((unsigned int)(x)) & 0x1FFFFFFF) /* kseg1 to physical */ +#endif + +#ifndef PHYS_TO_K1 +// hack +#define PHYS_TO_K1(x) (((unsigned int)(x)) | 0xA0000000) /* physical to kseg1 */ +#endif + +#define AR2313_TX_TIMEOUT (HZ/4) + +/* + * Rings + */ +#define DSC_RING_ENTRIES_SIZE (AR2313_DESCR_ENTRIES * sizeof(struct desc)) +#define DSC_NEXT(idx) ((idx + 1) & (AR2313_DESCR_ENTRIES - 1)) + +static inline int tx_space (u32 csm, u32 prd) +{ + return (csm - prd - 1) & (AR2313_DESCR_ENTRIES - 1); +} + +#if MAX_SKB_FRAGS +#define TX_RESERVED (MAX_SKB_FRAGS+1) /* +1 for message header */ +#define tx_ring_full(csm, prd) (tx_space(csm, prd) <= TX_RESERVED) +#else +#define tx_ring_full 0 +#endif + +#define AR2313_MBGET 2 +#define AR2313_MBSET 3 +#define AR2313_PCI_RECONFIG 4 +#define AR2313_PCI_DUMP 5 +#define AR2313_TEST_PANIC 6 +#define AR2313_TEST_NULLPTR 7 +#define AR2313_READ_DATA 8 +#define AR2313_WRITE_DATA 9 +#define AR2313_GET_VERSION 10 +#define AR2313_TEST_HANG 11 +#define AR2313_SYNC 12 + + +struct ar2313_cmd { + u32 cmd; + u32 address; /* virtual address of image */ + u32 length; /* size of image to download */ + u32 mailbox; /* mailbox to get/set */ + u32 data[2]; /* contents of mailbox to read/write */ +}; + + +/* + * Struct private for the Sibyte. + * + * Elements are grouped so variables used by the tx handling goes + * together, and will go into the same cache lines etc. in order to + * avoid cache line contention between the rx and tx handling on SMP. + * + * Frequently accessed variables are put at the beginning of the + * struct to help the compiler generate better/shorter code. + */ +struct ar2313_private +{ + int version; + u32 mb[2]; + + volatile ETHERNET_STRUCT *eth_regs; + volatile DMA *dma_regs; + volatile u32 *int_regs; + + spinlock_t lock; /* Serialise access to device */ + + /* + * RX and TX descriptors, must be adjacent + */ + ar2313_descr_t *rx_ring; + ar2313_descr_t *tx_ring; + + + struct sk_buff **rx_skb; + struct sk_buff **tx_skb; + + /* + * RX elements + */ + u32 rx_skbprd; + u32 cur_rx; + + /* + * TX elements + */ + u32 tx_prd; + u32 tx_csm; + + /* + * Misc elements + */ + int board_idx; + char name[48]; + struct net_device_stats stats; + struct { + u32 address; + u32 length; + char *mapping; + } desc; + + + struct timer_list link_timer; + unsigned short phy; /* merlot phy = 1, samsung phy = 0x1f */ + unsigned short mac; + unsigned short link; /* 0 - link down, 1 - link up */ + u16 phyData; + + struct tasklet_struct rx_tasklet; + int unloading; +}; + + +/* + * Prototypes + */ +static int ar2313_init(struct net_device *dev); +#ifdef TX_TIMEOUT +static void ar2313_tx_timeout(struct net_device *dev); +#endif +#if 0 +static void ar2313_multicast_list(struct net_device *dev); +#endif +static int ar2313_restart(struct net_device *dev); +#if DEBUG +static void ar2313_dump_regs(struct net_device *dev); +#endif +static void ar2313_load_rx_ring(struct net_device *dev, int bufs); +static irqreturn_t ar2313_interrupt(int irq, void *dev_id); +static int ar2313_open(struct net_device *dev); +static int ar2313_start_xmit(struct sk_buff *skb, struct net_device *dev); +static int ar2313_close(struct net_device *dev); +static int ar2313_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd); +static void ar2313_init_cleanup(struct net_device *dev); +static int ar2313_setup_timer(struct net_device *dev); +static void ar2313_link_timer_fn(unsigned long data); +static void ar2313_check_link(struct net_device *dev); +static struct net_device_stats *ar2313_get_stats(struct net_device *dev); +#endif /* _AR2313_H_ */ diff --git a/target/linux/aruba-2.6/files/drivers/net/ar2313/ar2313_msg.h b/target/linux/aruba-2.6/files/drivers/net/ar2313/ar2313_msg.h new file mode 100644 index 000000000..d10d9eade --- /dev/null +++ b/target/linux/aruba-2.6/files/drivers/net/ar2313/ar2313_msg.h @@ -0,0 +1,17 @@ +#ifndef _AR2313_MSG_H_ +#define _AR2313_MSG_H_ + +#define AR2313_MTU 1692 +#define AR2313_PRIOS 1 +#define AR2313_QUEUES (2*AR2313_PRIOS) + +#define AR2313_DESCR_ENTRIES 64 + +typedef struct { + volatile unsigned int status; // OWN, Device control and status. + volatile unsigned int devcs; // pkt Control bits + Length + volatile unsigned int addr; // Current Address. + volatile unsigned int descr; // Next descriptor in chain. +} ar2313_descr_t; + +#endif /* _AR2313_MSG_H_ */ diff --git a/target/linux/aruba-2.6/files/drivers/net/ar2313/dma.h b/target/linux/aruba-2.6/files/drivers/net/ar2313/dma.h new file mode 100644 index 000000000..2f8c06af5 --- /dev/null +++ b/target/linux/aruba-2.6/files/drivers/net/ar2313/dma.h @@ -0,0 +1,135 @@ +#ifndef __ARUBA_DMA_H__ +#define __ARUBA_DMA_H__ + +/******************************************************************************* + * + * Copyright 2002 Integrated Device Technology, Inc. + * All rights reserved. + * + * DMA register definition. + * + * File : $Id: dma.h,v 1.3 2002/06/06 18:34:03 astichte Exp $ + * + * Author : ryan.holmQVist@idt.com + * Date : 20011005 + * Update : + * $Log: dma.h,v $ + * Revision 1.3 2002/06/06 18:34:03 astichte + * Added XXX_PhysicalAddress and XXX_VirtualAddress + * + * Revision 1.2 2002/06/05 18:30:46 astichte + * Removed IDTField + * + * Revision 1.1 2002/05/29 17:33:21 sysarch + * jba File moved from vcode/include/idt/acacia + * + * + ******************************************************************************/ + +#define AR_BIT(x) (1 << (x)) +#define DMA_RX_ERR_CRC AR_BIT(1) +#define DMA_RX_ERR_DRIB AR_BIT(2) +#define DMA_RX_ERR_MII AR_BIT(3) +#define DMA_RX_EV2 AR_BIT(5) +#define DMA_RX_ERR_COL AR_BIT(6) +#define DMA_RX_LONG AR_BIT(7) +#define DMA_RX_LS AR_BIT(8) /* last descriptor */ +#define DMA_RX_FS AR_BIT(9) /* first descriptor */ +#define DMA_RX_MF AR_BIT(10) /* multicast frame */ +#define DMA_RX_ERR_RUNT AR_BIT(11) /* runt frame */ +#define DMA_RX_ERR_LENGTH AR_BIT(12) /* length error */ +#define DMA_RX_ERR_DESC AR_BIT(14) /* descriptor error */ +#define DMA_RX_ERROR AR_BIT(15) /* error summary */ +#define DMA_RX_LEN_MASK 0x3fff0000 +#define DMA_RX_LEN_SHIFT 16 +#define DMA_RX_FILT AR_BIT(30) +#define DMA_RX_OWN AR_BIT(31) /* desc owned by DMA controller */ + +#define DMA_RX1_BSIZE_MASK 0x000007ff +#define DMA_RX1_BSIZE_SHIFT 0 +#define DMA_RX1_CHAINED AR_BIT(24) +#define DMA_RX1_RER AR_BIT(25) + +#define DMA_TX_ERR_UNDER AR_BIT(1) /* underflow error */ +#define DMA_TX_ERR_DEFER AR_BIT(2) /* excessive deferral */ +#define DMA_TX_COL_MASK 0x78 +#define DMA_TX_COL_SHIFT 3 +#define DMA_TX_ERR_HB AR_BIT(7) /* hearbeat failure */ +#define DMA_TX_ERR_COL AR_BIT(8) /* excessive collisions */ +#define DMA_TX_ERR_LATE AR_BIT(9) /* late collision */ +#define DMA_TX_ERR_LINK AR_BIT(10) /* no carrier */ +#define DMA_TX_ERR_LOSS AR_BIT(11) /* loss of carrier */ +#define DMA_TX_ERR_JABBER AR_BIT(14) /* transmit jabber timeout */ +#define DMA_TX_ERROR AR_BIT(15) /* frame aborted */ +#define DMA_TX_OWN AR_BIT(31) /* descr owned by DMA controller */ + +#define DMA_TX1_BSIZE_MASK 0x000007ff +#define DMA_TX1_BSIZE_SHIFT 0 +#define DMA_TX1_CHAINED AR_BIT(24) /* chained descriptors */ +#define DMA_TX1_TER AR_BIT(25) /* transmit end of ring */ +#define DMA_TX1_FS AR_BIT(29) /* first segment */ +#define DMA_TX1_LS AR_BIT(30) /* last segment */ +#define DMA_TX1_IC AR_BIT(31) /* interrupt on completion */ + +#define RCVPKT_LENGTH(X) (X >> 16) /* Received pkt Length */ + +#define MAC_CONTROL_RE AR_BIT(2) /* receive enable */ +#define MAC_CONTROL_TE AR_BIT(3) /* transmit enable */ +#define MAC_CONTROL_DC AR_BIT(5) /* Deferral check*/ +#define MAC_CONTROL_ASTP AR_BIT(8) /* Auto pad strip */ +#define MAC_CONTROL_DRTY AR_BIT(10) /* Disable retry */ +#define MAC_CONTROL_DBF AR_BIT(11) /* Disable bcast frames */ +#define MAC_CONTROL_LCC AR_BIT(12) /* late collision ctrl */ +#define MAC_CONTROL_HP AR_BIT(13) /* Hash Perfect filtering */ +#define MAC_CONTROL_HASH AR_BIT(14) /* Unicast hash filtering */ +#define MAC_CONTROL_HO AR_BIT(15) /* Hash only filtering */ +#define MAC_CONTROL_PB AR_BIT(16) /* Pass Bad frames */ +#define MAC_CONTROL_IF AR_BIT(17) /* Inverse filtering */ +#define MAC_CONTROL_PR AR_BIT(18) /* promiscuous mode (valid frames only) */ +#define MAC_CONTROL_PM AR_BIT(19) /* pass multicast */ +#define MAC_CONTROL_F AR_BIT(20) /* full-duplex */ +#define MAC_CONTROL_DRO AR_BIT(23) /* Disable Receive Own */ +#define MAC_CONTROL_HBD AR_BIT(28) /* heart-beat disabled (MUST BE SET) */ +#define MAC_CONTROL_BLE AR_BIT(30) /* big endian mode */ +#define MAC_CONTROL_RA AR_BIT(31) /* receive all (valid and invalid frames) */ + +#define MII_ADDR_BUSY AR_BIT(0) +#define MII_ADDR_WRITE AR_BIT(1) +#define MII_ADDR_REG_SHIFT 6 +#define MII_ADDR_PHY_SHIFT 11 +#define MII_DATA_SHIFT 0 + +#define FLOW_CONTROL_FCE AR_BIT(1) + +#define DMA_BUS_MODE_SWR AR_BIT(0) /* software reset */ +#define DMA_BUS_MODE_BLE AR_BIT(7) /* big endian mode */ +#define DMA_BUS_MODE_PBL_SHIFT 8 /* programmable burst length 32 */ +#define DMA_BUS_MODE_DBO AR_BIT(20) /* big-endian descriptors */ + +#define DMA_STATUS_TI AR_BIT(0) /* transmit interrupt */ +#define DMA_STATUS_TPS AR_BIT(1) /* transmit process stopped */ +#define DMA_STATUS_TU AR_BIT(2) /* transmit buffer unavailable */ +#define DMA_STATUS_TJT AR_BIT(3) /* transmit buffer timeout */ +#define DMA_STATUS_UNF AR_BIT(5) /* transmit underflow */ +#define DMA_STATUS_RI AR_BIT(6) /* receive interrupt */ +#define DMA_STATUS_RU AR_BIT(7) /* receive buffer unavailable */ +#define DMA_STATUS_RPS AR_BIT(8) /* receive process stopped */ +#define DMA_STATUS_ETI AR_BIT(10) /* early transmit interrupt */ +#define DMA_STATUS_FBE AR_BIT(13) /* fatal bus interrupt */ +#define DMA_STATUS_ERI AR_BIT(14) /* early receive interrupt */ +#define DMA_STATUS_AIS AR_BIT(15) /* abnormal interrupt summary */ +#define DMA_STATUS_NIS AR_BIT(16) /* normal interrupt summary */ +#define DMA_STATUS_RS_SHIFT 17 /* receive process state */ +#define DMA_STATUS_TS_SHIFT 20 /* transmit process state */ +#define DMA_STATUS_EB_SHIFT 23 /* error bits */ + +#define DMA_CONTROL_SR AR_BIT(1) /* start receive */ +#define DMA_CONTROL_ST AR_BIT(13) /* start transmit */ +#define DMA_CONTROL_SF AR_BIT(21) /* store and forward */ + +#endif // __ARUBA_DMA_H__ + + + + + diff --git a/target/linux/aruba-2.6/files/drivers/net/ar2313/platform.h b/target/linux/aruba-2.6/files/drivers/net/ar2313/platform.h new file mode 100644 index 000000000..67d8f5c08 --- /dev/null +++ b/target/linux/aruba-2.6/files/drivers/net/ar2313/platform.h @@ -0,0 +1,128 @@ +/******************************************************************************** + Title: $Source: platform.h,v $ + + Author: Dan Steinberg + Copyright Integrated Device Technology 2001 + + Purpose: AR2313 Register/Bit Definitions + + Update: + $Log: platform.h,v $ + + Notes: See Merlot architecture spec for complete details. Note, all + addresses are virtual addresses in kseg1 (Uncached, Unmapped). + +********************************************************************************/ + +#ifndef PLATFORM_H +#define PLATFORM_H + +#define BIT(x) (1 << (x)) + +#define RESET_BASE 0xBC003020 +#define RESET_VALUE 0x00000001 + +/******************************************************************** + * Device controller + ********************************************************************/ +typedef struct { + volatile unsigned int flash0; +} DEVICE; + +#define device (*((volatile DEVICE *) DEV_CTL_BASE)) + +// DDRC register +#define DEV_WP (1<<26) + +/******************************************************************** + * DDR controller + ********************************************************************/ +typedef struct { + volatile unsigned int ddrc0; + volatile unsigned int ddrc1; + volatile unsigned int ddrrefresh; +} DDR; + +#define ddr (*((volatile DDR *) DDR_BASE)) + +// DDRC register +#define DDRC_CS(i) ((i&0x3)<<0) +#define DDRC_WE (1<<2) + +/******************************************************************** + * Ethernet interfaces + ********************************************************************/ +#define ETHERNET_BASE 0xB8200000 + +// +// New Combo structure for Both Eth0 AND eth1 +// +typedef struct { + volatile unsigned int mac_control; /* 0x00 */ + volatile unsigned int mac_addr[2]; /* 0x04 - 0x08*/ + volatile unsigned int mcast_table[2]; /* 0x0c - 0x10 */ + volatile unsigned int mii_addr; /* 0x14 */ + volatile unsigned int mii_data; /* 0x18 */ + volatile unsigned int flow_control; /* 0x1c */ + volatile unsigned int vlan_tag; /* 0x20 */ + volatile unsigned int pad[7]; /* 0x24 - 0x3c */ + volatile unsigned int ucast_table[8]; /* 0x40-0x5c */ + +} ETHERNET_STRUCT; + +/******************************************************************** + * Interrupt controller + ********************************************************************/ + +typedef struct { + volatile unsigned int wdog_control; /* 0x08 */ + volatile unsigned int wdog_timer; /* 0x0c */ + volatile unsigned int misc_status; /* 0x10 */ + volatile unsigned int misc_mask; /* 0x14 */ + volatile unsigned int global_status; /* 0x18 */ + volatile unsigned int reserved; /* 0x1c */ + volatile unsigned int reset_control; /* 0x20 */ +} INTERRUPT; + +#define interrupt (*((volatile INTERRUPT *) INTERRUPT_BASE)) + +#define INTERRUPT_MISC_TIMER BIT(0) +#define INTERRUPT_MISC_AHBPROC BIT(1) +#define INTERRUPT_MISC_AHBDMA BIT(2) +#define INTERRUPT_MISC_GPIO BIT(3) +#define INTERRUPT_MISC_UART BIT(4) +#define INTERRUPT_MISC_UARTDMA BIT(5) +#define INTERRUPT_MISC_WATCHDOG BIT(6) +#define INTERRUPT_MISC_LOCAL BIT(7) + +#define INTERRUPT_GLOBAL_ETH BIT(2) +#define INTERRUPT_GLOBAL_WLAN BIT(3) +#define INTERRUPT_GLOBAL_MISC BIT(4) +#define INTERRUPT_GLOBAL_ITIMER BIT(5) + +/******************************************************************** + * DMA controller + ********************************************************************/ +#define DMA_BASE 0xB8201000 + +typedef struct { + volatile unsigned int bus_mode; /* 0x00 (CSR0) */ + volatile unsigned int xmt_poll; /* 0x04 (CSR1) */ + volatile unsigned int rcv_poll; /* 0x08 (CSR2) */ + volatile unsigned int rcv_base; /* 0x0c (CSR3) */ + volatile unsigned int xmt_base; /* 0x10 (CSR4) */ + volatile unsigned int status; /* 0x14 (CSR5) */ + volatile unsigned int control; /* 0x18 (CSR6) */ + volatile unsigned int intr_ena; /* 0x1c (CSR7) */ + volatile unsigned int rcv_missed; /* 0x20 (CSR8) */ + volatile unsigned int reserved[11]; /* 0x24-0x4c (CSR9-19) */ + volatile unsigned int cur_tx_buf_addr; /* 0x50 (CSR20) */ + volatile unsigned int cur_rx_buf_addr; /* 0x50 (CSR21) */ +} DMA; + +#define dma (*((volatile DMA *) DMA_BASE)) + +// macro to convert from virtual to physical address +#define phys_addr(x) (x & 0x1fffffff) + +#endif /* PLATFORM_H */ diff --git a/target/linux/aruba-2.6/files/drivers/net/rc32434_eth.c b/target/linux/aruba-2.6/files/drivers/net/rc32434_eth.c new file mode 100644 index 000000000..0acb8f944 --- /dev/null +++ b/target/linux/aruba-2.6/files/drivers/net/rc32434_eth.c @@ -0,0 +1,1273 @@ +/************************************************************************** + * + * BRIEF MODULE DESCRIPTION + * Driver for the IDT RC32434 on-chip ethernet controller. + * + * Copyright 2004 IDT Inc. (rischelp@idt.com) + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + * + ************************************************************************** + * May 2004 rkt, neb + * + * Based on the driver developed by B. Maruthanayakam, H. Kou and others. + * + * Aug 2004 Sadik + * + * Added NAPI + * + ************************************************************************** + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "rc32434_eth.h" + +#define DRIVER_VERSION "(mar2904)" + +#define DRIVER_NAME "rc32434 Ethernet driver. " DRIVER_VERSION + + +#define STATION_ADDRESS_HIGH(dev) (((dev)->dev_addr[0] << 8) | \ + ((dev)->dev_addr[1])) +#define STATION_ADDRESS_LOW(dev) (((dev)->dev_addr[2] << 24) | \ + ((dev)->dev_addr[3] << 16) | \ + ((dev)->dev_addr[4] << 8) | \ + ((dev)->dev_addr[5])) + +#define MII_CLOCK 1250000 /* no more than 2.5MHz */ +static char mac0[18] = "08:00:06:05:40:01"; + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,52) +module_param_string(mac0, mac0, 18, 0); +#else +MODULE_PARM(mac0, "c18"); +#endif +MODULE_PARM_DESC(mac0, "MAC address for RC32434 ethernet0"); + +static struct rc32434_if_t { + char *name; + struct net_device *dev; + char* mac_str; + int weight; + u32 iobase; + u32 rxdmabase; + u32 txdmabase; + int rx_dma_irq; + int tx_dma_irq; + int rx_ovr_irq; + int tx_und_irq; +} rc32434_iflist[] = +{ + { + "rc32434_eth0", NULL, mac0, + 64, + ETH0_PhysicalAddress, + ETH0_RX_DMA_ADDR, + ETH0_TX_DMA_ADDR, + ETH0_DMA_RX_IRQ, + ETH0_DMA_TX_IRQ, + ETH0_RX_OVR_IRQ, + ETH0_TX_UND_IRQ + } +}; + + +static int parse_mac_addr(struct net_device *dev, char* macstr) +{ + int i, j; + unsigned char result, value; + + for (i=0; i<6; i++) { + result = 0; + if (i != 5 && *(macstr+2) != ':') { + ERR("invalid mac address format: %d %c\n", + i, *(macstr+2)); + return -EINVAL; + } + for (j=0; j<2; j++) { + if (isxdigit(*macstr) && (value = isdigit(*macstr) ? *macstr-'0' : + toupper(*macstr)-'A'+10) < 16) { + result = result*16 + value; + macstr++; + } + else { + ERR("invalid mac address " + "character: %c\n", *macstr); + return -EINVAL; + } + } + + macstr++; + dev->dev_addr[i] = result; + } + + return 0; +} + + + +static inline void rc32434_abort_tx(struct net_device *dev) +{ + struct rc32434_local *lp = (struct rc32434_local *)dev->priv; + rc32434_abort_dma(dev, lp->tx_dma_regs); + +} + +static inline void rc32434_abort_rx(struct net_device *dev) +{ + struct rc32434_local *lp = (struct rc32434_local *)dev->priv; + rc32434_abort_dma(dev, lp->rx_dma_regs); + +} + +static inline void rc32434_start_tx(struct rc32434_local *lp, volatile DMAD_t td) +{ + rc32434_start_dma(lp->tx_dma_regs, CPHYSADDR(td)); +} + +static inline void rc32434_start_rx(struct rc32434_local *lp, volatile DMAD_t rd) +{ + rc32434_start_dma(lp->rx_dma_regs, CPHYSADDR(rd)); +} + +static inline void rc32434_chain_tx(struct rc32434_local *lp, volatile DMAD_t td) +{ + rc32434_chain_dma(lp->tx_dma_regs, CPHYSADDR(td)); +} + +static inline void rc32434_chain_rx(struct rc32434_local *lp, volatile DMAD_t rd) +{ + rc32434_chain_dma(lp->rx_dma_regs, CPHYSADDR(rd)); +} + +#ifdef RC32434_PROC_DEBUG +static int rc32434_read_proc(char *buf, char **start, off_t fpos, + int length, int *eof, void *data) +{ + struct net_device *dev = (struct net_device *)data; + struct rc32434_local *lp = (struct rc32434_local *)dev->priv; + int len = 0; + + /* print out header */ + len += sprintf(buf + len, "\n\tRC32434 Ethernet Debug\n\n"); + len += sprintf (buf + len, + "DMA halt count = %10d, DMA run count = %10d\n", + lp->dma_halt_cnt, lp->dma_run_cnt); + + if (fpos >= len) { + *start = buf; + *eof = 1; + return 0; + } + *start = buf + fpos; + + if ((len -= fpos) > length) + return length; + *eof = 1; + + return len; + +} +#endif + + +/* + * Restart the RC32434 ethernet controller. + */ +static int rc32434_restart(struct net_device *dev) +{ + struct rc32434_local *lp = (struct rc32434_local *)dev->priv; + + /* + * Disable interrupts + */ + disable_irq(lp->rx_irq); + disable_irq(lp->tx_irq); +#ifdef RC32434_REVISION + disable_irq(lp->ovr_irq); +#endif + disable_irq(lp->und_irq); + + /* Mask F E bit in Tx DMA */ + rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) | DMASM_f_m | DMASM_e_m, &lp->tx_dma_regs->dmasm); + /* Mask D H E bit in Rx DMA */ + rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) | DMASM_d_m | DMASM_h_m | DMASM_e_m, &lp->rx_dma_regs->dmasm); + + rc32434_init(dev); + rc32434_multicast_list(dev); + + enable_irq(lp->und_irq); +#ifdef RC32434_REVISION + enable_irq(lp->ovr_irq); +#endif + enable_irq(lp->tx_irq); + enable_irq(lp->rx_irq); + + return 0; +} + +int rc32434_init_module(void) +{ +#ifdef CONFIG_MACH_ARUBA + if (mips_machtype != MACH_ARUBA_AP70) + return 1; +#endif + + printk(KERN_INFO DRIVER_NAME " \n"); + return rc32434_probe(0); +} + +static int rc32434_probe(int port_num) +{ + struct rc32434_if_t *bif = &rc32434_iflist[port_num]; + struct rc32434_local *lp = NULL; + struct net_device *dev = NULL; + int i, retval,err; + + dev = alloc_etherdev(sizeof(struct rc32434_local)); + if(!dev) { + ERR("rc32434_eth: alloc_etherdev failed\n"); + return -1; + } + + SET_MODULE_OWNER(dev); + bif->dev = dev; + +#ifdef CONFIG_MACH_ARUBA + { + extern char * getenv(char *e); + memcpy(bif->mac_str, getenv("ethaddr"), 17); + } +#endif + + printk("mac: %s\n", bif->mac_str); + if ((retval = parse_mac_addr(dev, bif->mac_str))) { + ERR("MAC address parse failed\n"); + free_netdev(dev); + return -1; + } + + + /* Initialize the device structure. */ + if (dev->priv == NULL) { + lp = (struct rc32434_local *)kmalloc(sizeof(*lp), GFP_KERNEL); + memset(lp, 0, sizeof(struct rc32434_local)); + } + else { + lp = (struct rc32434_local *)dev->priv; + } + + lp->rx_irq = bif->rx_dma_irq; + lp->tx_irq = bif->tx_dma_irq; + lp->ovr_irq = bif->rx_ovr_irq; + lp->und_irq = bif->tx_und_irq; + + lp->eth_regs = ioremap_nocache(bif->iobase, sizeof(*lp->eth_regs)); + + if (!lp->eth_regs) { + ERR("Can't remap eth registers\n"); + retval = -ENXIO; + goto probe_err_out; + } + + lp->rx_dma_regs = ioremap_nocache(bif->rxdmabase, sizeof(struct DMA_Chan_s)); + + if (!lp->rx_dma_regs) { + ERR("Can't remap Rx DMA registers\n"); + retval = -ENXIO; + goto probe_err_out; + } + lp->tx_dma_regs = ioremap_nocache(bif->txdmabase,sizeof(struct DMA_Chan_s)); + + if (!lp->tx_dma_regs) { + ERR("Can't remap Tx DMA registers\n"); + retval = -ENXIO; + goto probe_err_out; + } + +#ifdef RC32434_PROC_DEBUG + lp->ps = create_proc_read_entry (bif->name, 0, proc_net, + rc32434_read_proc, dev); +#endif + + lp->td_ring = (DMAD_t)kmalloc(TD_RING_SIZE + RD_RING_SIZE, GFP_KERNEL); + if (!lp->td_ring) { + ERR("Can't allocate descriptors\n"); + retval = -ENOMEM; + goto probe_err_out; + } + + dma_cache_inv((unsigned long)(lp->td_ring), TD_RING_SIZE + RD_RING_SIZE); + + /* now convert TD_RING pointer to KSEG1 */ + lp->td_ring = (DMAD_t )KSEG1ADDR(lp->td_ring); + lp->rd_ring = &lp->td_ring[RC32434_NUM_TDS]; + + + spin_lock_init(&lp->lock); + + dev->base_addr = bif->iobase; + /* just use the rx dma irq */ + dev->irq = bif->rx_dma_irq; + + dev->priv = lp; + + dev->open = rc32434_open; + dev->stop = rc32434_close; + dev->hard_start_xmit = rc32434_send_packet; + dev->get_stats = rc32434_get_stats; + dev->set_multicast_list = &rc32434_multicast_list; + dev->tx_timeout = rc32434_tx_timeout; + dev->watchdog_timeo = RC32434_TX_TIMEOUT; + +#ifdef CONFIG_IDT_USE_NAPI + dev->poll = rc32434_poll; + dev->weight = bif->weight; + printk("Using NAPI with weight %d\n",dev->weight); +#else + lp->rx_tasklet = kmalloc(sizeof(struct tasklet_struct), GFP_KERNEL); + tasklet_init(lp->rx_tasklet, rc32434_rx_tasklet, (unsigned long)dev); +#endif + lp->tx_tasklet = kmalloc(sizeof(struct tasklet_struct), GFP_KERNEL); + tasklet_init(lp->tx_tasklet, rc32434_tx_tasklet, (unsigned long)dev); + + if ((err = register_netdev(dev))) { + printk(KERN_ERR "rc32434 ethernet. Cannot register net device %d\n", err); + free_netdev(dev); + retval = -EINVAL; + goto probe_err_out; + } + + INFO("Rx IRQ %d, Tx IRQ %d, ", bif->rx_dma_irq, bif->tx_dma_irq); + for (i = 0; i < 6; i++) { + printk("%2.2x", dev->dev_addr[i]); + if (i<5) + printk(":"); + } + printk("\n"); + + return 0; + + probe_err_out: + rc32434_cleanup_module(); + ERR(" failed. Returns %d\n", retval); + return retval; + +} + + +static void rc32434_cleanup_module(void) +{ + int i; + + for (i = 0; rc32434_iflist[i].iobase; i++) { + struct rc32434_if_t * bif = &rc32434_iflist[i]; + if (bif->dev != NULL) { + struct rc32434_local *lp = (struct rc32434_local *)bif->dev->priv; + if (lp != NULL) { + if (lp->eth_regs) + iounmap((void*)lp->eth_regs); + if (lp->rx_dma_regs) + iounmap((void*)lp->rx_dma_regs); + if (lp->tx_dma_regs) + iounmap((void*)lp->tx_dma_regs); + if (lp->td_ring) + kfree((void*)KSEG0ADDR(lp->td_ring)); + +#ifdef RC32434_PROC_DEBUG + if (lp->ps) { + remove_proc_entry(bif->name, proc_net); + } +#endif + kfree(lp); + } + + unregister_netdev(bif->dev); + free_netdev(bif->dev); + kfree(bif->dev); + } + } +} + + + +static int rc32434_open(struct net_device *dev) +{ + struct rc32434_local *lp = (struct rc32434_local *)dev->priv; + + /* Initialize */ + if (rc32434_init(dev)) { + ERR("Error: cannot open the Ethernet device\n"); + return -EAGAIN; + } + + /* Install the interrupt handler that handles the Done Finished Ovr and Und Events */ + if (request_irq(lp->rx_irq, &rc32434_rx_dma_interrupt, + SA_SHIRQ | SA_INTERRUPT, + "rc32434 ethernet Rx", dev)) { + ERR(": unable to get Rx DMA IRQ %d\n", + lp->rx_irq); + return -EAGAIN; + } + if (request_irq(lp->tx_irq, &rc32434_tx_dma_interrupt, + SA_SHIRQ | SA_INTERRUPT, + "rc32434 ethernet Tx", dev)) { + ERR(": unable to get Tx DMA IRQ %d\n", + lp->tx_irq); + free_irq(lp->rx_irq, dev); + return -EAGAIN; + } + +#ifdef RC32434_REVISION + /* Install handler for overrun error. */ + if (request_irq(lp->ovr_irq, &rc32434_ovr_interrupt, + SA_SHIRQ | SA_INTERRUPT, + "Ethernet Overflow", dev)) { + ERR(": unable to get OVR IRQ %d\n", + lp->ovr_irq); + free_irq(lp->rx_irq, dev); + free_irq(lp->tx_irq, dev); + return -EAGAIN; + } +#endif + + /* Install handler for underflow error. */ + if (request_irq(lp->und_irq, &rc32434_und_interrupt, + SA_SHIRQ | SA_INTERRUPT, + "Ethernet Underflow", dev)) { + ERR(": unable to get UND IRQ %d\n", + lp->und_irq); + free_irq(lp->rx_irq, dev); + free_irq(lp->tx_irq, dev); +#ifdef RC32434_REVISION + free_irq(lp->ovr_irq, dev); +#endif + return -EAGAIN; + } + + + return 0; +} + + + + +static int rc32434_close(struct net_device *dev) +{ + struct rc32434_local *lp = (struct rc32434_local *)dev->priv; + u32 tmp; + + /* Disable interrupts */ + disable_irq(lp->rx_irq); + disable_irq(lp->tx_irq); +#ifdef RC32434_REVISION + disable_irq(lp->ovr_irq); +#endif + disable_irq(lp->und_irq); + + tmp = rc32434_readl(&lp->tx_dma_regs->dmasm); + tmp = tmp | DMASM_f_m | DMASM_e_m; + rc32434_writel(tmp, &lp->tx_dma_regs->dmasm); + + tmp = rc32434_readl(&lp->rx_dma_regs->dmasm); + tmp = tmp | DMASM_d_m | DMASM_h_m | DMASM_e_m; + rc32434_writel(tmp, &lp->rx_dma_regs->dmasm); + + free_irq(lp->rx_irq, dev); + free_irq(lp->tx_irq, dev); +#ifdef RC32434_REVISION + free_irq(lp->ovr_irq, dev); +#endif + free_irq(lp->und_irq, dev); + return 0; +} + + +/* transmit packet */ +static int rc32434_send_packet(struct sk_buff *skb, struct net_device *dev) +{ + struct rc32434_local *lp = (struct rc32434_local *)dev->priv; + unsigned long flags; + u32 length; + DMAD_t td; + + + spin_lock_irqsave(&lp->lock, flags); + + td = &lp->td_ring[lp->tx_chain_tail]; + + /* stop queue when full, drop pkts if queue already full */ + if(lp->tx_count >= (RC32434_NUM_TDS - 2)) { + lp->tx_full = 1; + + if(lp->tx_count == (RC32434_NUM_TDS - 2)) { + netif_stop_queue(dev); + } + else { + lp->stats.tx_dropped++; + dev_kfree_skb_any(skb); + spin_unlock_irqrestore(&lp->lock, flags); + return 1; + } + } + + lp->tx_count ++; + + lp->tx_skb[lp->tx_chain_tail] = skb; + + length = skb->len; + + /* Setup the transmit descriptor. */ + td->ca = CPHYSADDR(skb->data); + + if(rc32434_readl(&(lp->tx_dma_regs->dmandptr)) == 0) { + if( lp->tx_chain_status == empty ) { + td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m; /* Update tail */ + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */ + rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr)); /* Write to NDPTR */ + lp->tx_chain_head = lp->tx_chain_tail; /* Move head to tail */ + } + else { + td->control = DMA_COUNT(length) |DMAD_cof_m|DMAD_iof_m; /* Update tail */ + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].control &= ~(DMAD_cof_m); /* Link to prev */ + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].link = CPHYSADDR(td); /* Link to prev */ + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */ + rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr)); /* Write to NDPTR */ + lp->tx_chain_head = lp->tx_chain_tail; /* Move head to tail */ + lp->tx_chain_status = empty; + } + } + else { + if( lp->tx_chain_status == empty ) { + td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m; /* Update tail */ + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */ + lp->tx_chain_status = filled; + } + else { + td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m; /* Update tail */ + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].control &= ~(DMAD_cof_m); /* Link to prev */ + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].link = CPHYSADDR(td); /* Link to prev */ + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */ + } + } + + dev->trans_start = jiffies; + + spin_unlock_irqrestore(&lp->lock, flags); + + return 0; +} + + +/* Ethernet MII-PHY Handler */ +static void rc32434_mii_handler(unsigned long data) +{ + struct net_device *dev = (struct net_device *)data; + struct rc32434_local *lp = (struct rc32434_local *)dev->priv; + unsigned long flags; + unsigned long duplex_status; + int port_addr = (lp->rx_irq == 0x2c? 1:0) << 8; + + spin_lock_irqsave(&lp->lock, flags); + + /* Two ports are using the same MII, the difference is the PHY address */ + rc32434_writel(0, &rc32434_eth0_regs->miimcfg); + rc32434_writel(0, &rc32434_eth0_regs->miimcmd); + rc32434_writel(port_addr |0x05, &rc32434_eth0_regs->miimaddr); + rc32434_writel(MIIMCMD_scn_m, &rc32434_eth0_regs->miimcmd); + while(rc32434_readl(&rc32434_eth0_regs->miimind) & MIIMIND_nv_m); + + ERR("irq:%x port_addr:%x RDD:%x\n", + lp->rx_irq, port_addr, rc32434_readl(&rc32434_eth0_regs->miimrdd)); + duplex_status = (rc32434_readl(&rc32434_eth0_regs->miimrdd) & 0x140)? ETHMAC2_fd_m: 0; + if(duplex_status != lp->duplex_mode) { + ERR("The MII-PHY is Auto-negotiated to %s-Duplex mode for Eth-%x\n", duplex_status? "Full":"Half", lp->rx_irq == 0x2c? 1:0); + lp->duplex_mode = duplex_status; + rc32434_restart(dev); + } + + lp->mii_phy_timer.expires = jiffies + 10 * HZ; + add_timer(&lp->mii_phy_timer); + + spin_unlock_irqrestore(&lp->lock, flags); + +} + +#ifdef RC32434_REVISION +/* Ethernet Rx Overflow interrupt */ +static irqreturn_t +rc32434_ovr_interrupt(int irq, void *dev_id) +{ + struct net_device *dev = (struct net_device *)dev_id; + struct rc32434_local *lp; + unsigned int ovr; + irqreturn_t retval = IRQ_NONE; + + ASSERT(dev != NULL); + + lp = (struct rc32434_local *)dev->priv; + spin_lock(&lp->lock); + ovr = rc32434_readl(&lp->eth_regs->ethintfc); + + if(ovr & ETHINTFC_ovr_m) { + netif_stop_queue(dev); + + /* clear OVR bit */ + rc32434_writel((ovr & ~ETHINTFC_ovr_m), &lp->eth_regs->ethintfc); + + /* Restart interface */ + rc32434_restart(dev); + retval = IRQ_HANDLED; + } + spin_unlock(&lp->lock); + + return retval; +} + +#endif + + +/* Ethernet Tx Underflow interrupt */ +static irqreturn_t +rc32434_und_interrupt(int irq, void *dev_id) +{ + struct net_device *dev = (struct net_device *)dev_id; + struct rc32434_local *lp; + unsigned int und; + irqreturn_t retval = IRQ_NONE; + + ASSERT(dev != NULL); + + lp = (struct rc32434_local *)dev->priv; + + spin_lock(&lp->lock); + + und = rc32434_readl(&lp->eth_regs->ethintfc); + + if(und & ETHINTFC_und_m) { + netif_stop_queue(dev); + + rc32434_writel((und & ~ETHINTFC_und_m), &lp->eth_regs->ethintfc); + + /* Restart interface */ + rc32434_restart(dev); + retval = IRQ_HANDLED; + } + + spin_unlock(&lp->lock); + + return retval; +} + + +/* Ethernet Rx DMA interrupt */ +static irqreturn_t +rc32434_rx_dma_interrupt(int irq, void *dev_id) +{ + struct net_device *dev = (struct net_device *)dev_id; + struct rc32434_local* lp; + volatile u32 dmas,dmasm; + irqreturn_t retval; + + ASSERT(dev != NULL); + + lp = (struct rc32434_local *)dev->priv; + + spin_lock(&lp->lock); + dmas = rc32434_readl(&lp->rx_dma_regs->dmas); + if(dmas & (DMAS_d_m|DMAS_h_m|DMAS_e_m)) { + /* Mask D H E bit in Rx DMA */ + dmasm = rc32434_readl(&lp->rx_dma_regs->dmasm); + rc32434_writel(dmasm | (DMASM_d_m | DMASM_h_m | DMASM_e_m), &lp->rx_dma_regs->dmasm); +#ifdef CONFIG_IDT_USE_NAPI + if(netif_rx_schedule_prep(dev)) + __netif_rx_schedule(dev); +#else + tasklet_hi_schedule(lp->rx_tasklet); +#endif + + if (dmas & DMAS_e_m) + ERR(": DMA error\n"); + + retval = IRQ_HANDLED; + } + else + retval = IRQ_NONE; + + spin_unlock(&lp->lock); + return retval; +} + +#ifdef CONFIG_IDT_USE_NAPI +static int rc32434_poll(struct net_device *rx_data_dev, int *budget) +#else +static void rc32434_rx_tasklet(unsigned long rx_data_dev) +#endif +{ + struct net_device *dev = (struct net_device *)rx_data_dev; + struct rc32434_local* lp = netdev_priv(dev); + volatile DMAD_t rd = &lp->rd_ring[lp->rx_next_done]; + struct sk_buff *skb, *skb_new; + u8* pkt_buf; + u32 devcs, count, pkt_len, pktuncrc_len; + volatile u32 dmas; +#ifdef CONFIG_IDT_USE_NAPI + u32 received = 0; + int rx_work_limit = min(*budget,dev->quota); +#else + unsigned long flags; + spin_lock_irqsave(&lp->lock, flags); +#endif + + while ( (count = RC32434_RBSIZE - (u32)DMA_COUNT(rd->control)) != 0) { +#ifdef CONFIG_IDT_USE_NAPI + if(--rx_work_limit <0) + { + break; + } +#endif + /* init the var. used for the later operations within the while loop */ + skb_new = NULL; + devcs = rd->devcs; + pkt_len = RCVPKT_LENGTH(devcs); + skb = lp->rx_skb[lp->rx_next_done]; + + if (count < 64) { + lp->stats.rx_errors++; + lp->stats.rx_dropped++; + } + else if ((devcs & ( ETHRX_ld_m)) != ETHRX_ld_m) { + /* check that this is a whole packet */ + /* WARNING: DMA_FD bit incorrectly set in Rc32434 (errata ref #077) */ + lp->stats.rx_errors++; + lp->stats.rx_dropped++; + } + else if ( (devcs & ETHRX_rok_m) ) { + + { + /* must be the (first and) last descriptor then */ + pkt_buf = (u8*)lp->rx_skb[lp->rx_next_done]->data; + + pktuncrc_len = pkt_len - 4; + /* invalidate the cache */ + dma_cache_inv((unsigned long)pkt_buf, pktuncrc_len); + + /* Malloc up new buffer. */ + skb_new = dev_alloc_skb(RC32434_RBSIZE + 2); + + if (skb_new != NULL){ + /* Make room */ + skb_put(skb, pktuncrc_len); + + skb->protocol = eth_type_trans(skb, dev); + + /* pass the packet to upper layers */ +#ifdef CONFIG_IDT_USE_NAPI + netif_receive_skb(skb); +#else + netif_rx(skb); +#endif + + dev->last_rx = jiffies; + lp->stats.rx_packets++; + lp->stats.rx_bytes += pktuncrc_len; + + if (IS_RCV_MP(devcs)) + lp->stats.multicast++; + + /* 16 bit align */ + skb_reserve(skb_new, 2); + + skb_new->dev = dev; + lp->rx_skb[lp->rx_next_done] = skb_new; + } + else { + ERR("no memory, dropping rx packet.\n"); + lp->stats.rx_errors++; + lp->stats.rx_dropped++; + } + } + + } + else { + /* This should only happen if we enable accepting broken packets */ + lp->stats.rx_errors++; + lp->stats.rx_dropped++; + + /* add statistics counters */ + if (IS_RCV_CRC_ERR(devcs)) { + DBG(2, "RX CRC error\n"); + lp->stats.rx_crc_errors++; + } + else if (IS_RCV_LOR_ERR(devcs)) { + DBG(2, "RX LOR error\n"); + lp->stats.rx_length_errors++; + } + else if (IS_RCV_LE_ERR(devcs)) { + DBG(2, "RX LE error\n"); + lp->stats.rx_length_errors++; + } + else if (IS_RCV_OVR_ERR(devcs)) { + lp->stats.rx_over_errors++; + } + else if (IS_RCV_CV_ERR(devcs)) { + /* code violation */ + DBG(2, "RX CV error\n"); + lp->stats.rx_frame_errors++; + } + else if (IS_RCV_CES_ERR(devcs)) { + DBG(2, "RX Preamble error\n"); + } + } + + rd->devcs = 0; + + /* restore descriptor's curr_addr */ + if(skb_new) + rd->ca = CPHYSADDR(skb_new->data); + else + rd->ca = CPHYSADDR(skb->data); + + rd->control = DMA_COUNT(RC32434_RBSIZE) |DMAD_cod_m |DMAD_iod_m; + lp->rd_ring[(lp->rx_next_done-1)& RC32434_RDS_MASK].control &= ~(DMAD_cod_m); + + lp->rx_next_done = (lp->rx_next_done + 1) & RC32434_RDS_MASK; + rd = &lp->rd_ring[lp->rx_next_done]; + rc32434_writel( ~DMAS_d_m, &lp->rx_dma_regs->dmas); + } +#ifdef CONFIG_IDT_USE_NAPI + dev->quota -= received; + *budget =- received; + if(rx_work_limit < 0) + goto not_done; +#endif + + dmas = rc32434_readl(&lp->rx_dma_regs->dmas); + + if(dmas & DMAS_h_m) { + rc32434_writel( ~(DMAS_h_m | DMAS_e_m), &lp->rx_dma_regs->dmas); +#ifdef RC32434_PROC_DEBUG + lp->dma_halt_cnt++; +#endif + rd->devcs = 0; + skb = lp->rx_skb[lp->rx_next_done]; + rd->ca = CPHYSADDR(skb->data); + rc32434_chain_rx(lp,rd); + } + +#ifdef CONFIG_IDT_USE_NAPI + netif_rx_complete(dev); +#endif + /* Enable D H E bit in Rx DMA */ + rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) & ~(DMASM_d_m | DMASM_h_m |DMASM_e_m), &lp->rx_dma_regs->dmasm); +#ifdef CONFIG_IDT_USE_NAPI + return 0; + not_done: + return 1; +#else + spin_unlock_irqrestore(&lp->lock, flags); + return; +#endif + + +} + + + +/* Ethernet Tx DMA interrupt */ +static irqreturn_t +rc32434_tx_dma_interrupt(int irq, void *dev_id) +{ + struct net_device *dev = (struct net_device *)dev_id; + struct rc32434_local *lp; + volatile u32 dmas,dmasm; + irqreturn_t retval; + + ASSERT(dev != NULL); + + lp = (struct rc32434_local *)dev->priv; + + spin_lock(&lp->lock); + + dmas = rc32434_readl(&lp->tx_dma_regs->dmas); + + if (dmas & (DMAS_f_m | DMAS_e_m)) { + dmasm = rc32434_readl(&lp->tx_dma_regs->dmasm); + /* Mask F E bit in Tx DMA */ + rc32434_writel(dmasm | (DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm); + + tasklet_hi_schedule(lp->tx_tasklet); + + if(lp->tx_chain_status == filled && (rc32434_readl(&(lp->tx_dma_regs->dmandptr)) == 0)) { + rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr)); + lp->tx_chain_status = empty; + lp->tx_chain_head = lp->tx_chain_tail; + dev->trans_start = jiffies; + } + + if (dmas & DMAS_e_m) + ERR(": DMA error\n"); + + retval = IRQ_HANDLED; + } + else + retval = IRQ_NONE; + + spin_unlock(&lp->lock); + + return retval; +} + + +static void rc32434_tx_tasklet(unsigned long tx_data_dev) +{ + struct net_device *dev = (struct net_device *)tx_data_dev; + struct rc32434_local* lp = (struct rc32434_local *)dev->priv; + volatile DMAD_t td = &lp->td_ring[lp->tx_next_done]; + u32 devcs; + unsigned long flags; + volatile u32 dmas; + + spin_lock_irqsave(&lp->lock, flags); + + /* process all desc that are done */ + while(IS_DMA_FINISHED(td->control)) { + if(lp->tx_full == 1) { + netif_wake_queue(dev); + lp->tx_full = 0; + } + + devcs = lp->td_ring[lp->tx_next_done].devcs; + if ((devcs & (ETHTX_fd_m | ETHTX_ld_m)) != (ETHTX_fd_m | ETHTX_ld_m)) { + lp->stats.tx_errors++; + lp->stats.tx_dropped++; + + /* should never happen */ + DBG(1, __FUNCTION__ ": split tx ignored\n"); + } + else if (IS_TX_TOK(devcs)) { + lp->stats.tx_packets++; + } + else { + lp->stats.tx_errors++; + lp->stats.tx_dropped++; + + /* underflow */ + if (IS_TX_UND_ERR(devcs)) + lp->stats.tx_fifo_errors++; + + /* oversized frame */ + if (IS_TX_OF_ERR(devcs)) + lp->stats.tx_aborted_errors++; + + /* excessive deferrals */ + if (IS_TX_ED_ERR(devcs)) + lp->stats.tx_carrier_errors++; + + /* collisions: medium busy */ + if (IS_TX_EC_ERR(devcs)) + lp->stats.collisions++; + + /* late collision */ + if (IS_TX_LC_ERR(devcs)) + lp->stats.tx_window_errors++; + + } + + /* We must always free the original skb */ + if (lp->tx_skb[lp->tx_next_done] != NULL) { + dev_kfree_skb_any(lp->tx_skb[lp->tx_next_done]); + lp->tx_skb[lp->tx_next_done] = NULL; + } + + lp->td_ring[lp->tx_next_done].control = DMAD_iof_m; + lp->td_ring[lp->tx_next_done].devcs = ETHTX_fd_m | ETHTX_ld_m; + lp->td_ring[lp->tx_next_done].link = 0; + lp->td_ring[lp->tx_next_done].ca = 0; + lp->tx_count --; + + /* go on to next transmission */ + lp->tx_next_done = (lp->tx_next_done + 1) & RC32434_TDS_MASK; + td = &lp->td_ring[lp->tx_next_done]; + + } + + dmas = rc32434_readl(&lp->tx_dma_regs->dmas); + rc32434_writel( ~dmas, &lp->tx_dma_regs->dmas); + + /* Enable F E bit in Tx DMA */ + rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) & ~(DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm); + spin_unlock_irqrestore(&lp->lock, flags); + +} + + +static struct net_device_stats * rc32434_get_stats(struct net_device *dev) +{ + struct rc32434_local *lp = (struct rc32434_local *)dev->priv; + return &lp->stats; +} + + +/* + * Set or clear the multicast filter for this adaptor. + */ +static void rc32434_multicast_list(struct net_device *dev) +{ + /* listen to broadcasts always and to treat */ + /* IFF bits independantly */ + struct rc32434_local *lp = (struct rc32434_local *)dev->priv; + unsigned long flags; + u32 recognise = ETHARC_ab_m; /* always accept broadcasts */ + + if (dev->flags & IFF_PROMISC) /* set promiscuous mode */ + recognise |= ETHARC_pro_m; + + if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 15)) + recognise |= ETHARC_am_m; /* all multicast & bcast */ + else if (dev->mc_count > 0) { + DBG(2, __FUNCTION__ ": mc_count %d\n", dev->mc_count); + recognise |= ETHARC_am_m; /* for the time being */ + } + + spin_lock_irqsave(&lp->lock, flags); + rc32434_writel(recognise, &lp->eth_regs->etharc); + spin_unlock_irqrestore(&lp->lock, flags); +} + + +static void rc32434_tx_timeout(struct net_device *dev) +{ + struct rc32434_local *lp = (struct rc32434_local *)dev->priv; + unsigned long flags; + + spin_lock_irqsave(&lp->lock, flags); + rc32434_restart(dev); + spin_unlock_irqrestore(&lp->lock, flags); + +} + + +/* + * Initialize the RC32434 ethernet controller. + */ +static int rc32434_init(struct net_device *dev) +{ + struct rc32434_local *lp = (struct rc32434_local *)dev->priv; + int i, j; + + /* Disable DMA */ + rc32434_abort_tx(dev); + rc32434_abort_rx(dev); + + /* reset ethernet logic */ + rc32434_writel(0, &lp->eth_regs->ethintfc); + while((rc32434_readl(&lp->eth_regs->ethintfc) & ETHINTFC_rip_m)) + dev->trans_start = jiffies; + + /* Enable Ethernet Interface */ + rc32434_writel(ETHINTFC_en_m, &lp->eth_regs->ethintfc); + +#ifndef CONFIG_IDT_USE_NAPI + tasklet_disable(lp->rx_tasklet); +#endif + tasklet_disable(lp->tx_tasklet); + + /* Initialize the transmit Descriptors */ + for (i = 0; i < RC32434_NUM_TDS; i++) { + lp->td_ring[i].control = DMAD_iof_m; + lp->td_ring[i].devcs = ETHTX_fd_m | ETHTX_ld_m; + lp->td_ring[i].ca = 0; + lp->td_ring[i].link = 0; + if (lp->tx_skb[i] != NULL) { + dev_kfree_skb_any(lp->tx_skb[i]); + lp->tx_skb[i] = NULL; + } + } + lp->tx_next_done = lp->tx_chain_head = lp->tx_chain_tail = lp->tx_full = lp->tx_count = 0; + lp-> tx_chain_status = empty; + + /* + * Initialize the receive descriptors so that they + * become a circular linked list, ie. let the last + * descriptor point to the first again. + */ + for (i=0; irx_skb[i]; + + if (lp->rx_skb[i] == NULL) { + skb = dev_alloc_skb(RC32434_RBSIZE + 2); + if (skb == NULL) { + ERR("No memory in the system\n"); + for (j = 0; j < RC32434_NUM_RDS; j ++) + if (lp->rx_skb[j] != NULL) + dev_kfree_skb_any(lp->rx_skb[j]); + + return 1; + } + else { + skb->dev = dev; + skb_reserve(skb, 2); + lp->rx_skb[i] = skb; + lp->rd_ring[i].ca = CPHYSADDR(skb->data); + + } + } + lp->rd_ring[i].control = DMAD_iod_m | DMA_COUNT(RC32434_RBSIZE); + lp->rd_ring[i].devcs = 0; + lp->rd_ring[i].ca = CPHYSADDR(skb->data); + lp->rd_ring[i].link = CPHYSADDR(&lp->rd_ring[i+1]); + + } + /* loop back */ + lp->rd_ring[RC32434_NUM_RDS-1].link = CPHYSADDR(&lp->rd_ring[0]); + lp->rx_next_done = 0; + + lp->rd_ring[RC32434_NUM_RDS-1].control |= DMAD_cod_m; + lp->rx_chain_head = 0; + lp->rx_chain_tail = 0; + lp->rx_chain_status = empty; + + rc32434_writel(0, &lp->rx_dma_regs->dmas); + /* Start Rx DMA */ + rc32434_start_rx(lp, &lp->rd_ring[0]); + + /* Enable F E bit in Tx DMA */ + rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) & ~(DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm); + /* Enable D H E bit in Rx DMA */ + rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) & ~(DMASM_d_m | DMASM_h_m | DMASM_e_m), &lp->rx_dma_regs->dmasm); + + /* Accept only packets destined for this Ethernet device address */ + rc32434_writel(ETHARC_ab_m, &lp->eth_regs->etharc); + + /* Set all Ether station address registers to their initial values */ + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal0); + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah0); + + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal1); + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah1); + + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal2); + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah2); + + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal3); + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah3); + + + /* Frame Length Checking, Pad Enable, CRC Enable, Full Duplex set */ + rc32434_writel(ETHMAC2_pe_m | ETHMAC2_cen_m | ETHMAC2_fd_m, &lp->eth_regs->ethmac2); + //ETHMAC2_flc_m ETHMAC2_fd_m lp->duplex_mode + + /* Back to back inter-packet-gap */ + rc32434_writel(0x15, &lp->eth_regs->ethipgt); + /* Non - Back to back inter-packet-gap */ + rc32434_writel(0x12, &lp->eth_regs->ethipgr); + + /* Management Clock Prescaler Divisor */ + /* Clock independent setting */ + rc32434_writel(((idt_cpu_freq)/MII_CLOCK+1) & ~1, + &lp->eth_regs->ethmcp); + + /* don't transmit until fifo contains 48b */ + rc32434_writel(48, &lp->eth_regs->ethfifott); + + rc32434_writel(ETHMAC1_re_m, &lp->eth_regs->ethmac1); + +#ifndef CONFIG_IDT_USE_NAPI + tasklet_enable(lp->rx_tasklet); +#endif + tasklet_enable(lp->tx_tasklet); + + netif_start_queue(dev); + + + return 0; + +} + + +#ifndef MODULE + +static int __init rc32434_setup(char *options) +{ + /* no options yet */ + return 1; +} + +static int __init rc32434_setup_ethaddr0(char *options) +{ + memcpy(mac0, options, 17); + mac0[17]= '\0'; + return 1; +} + +__setup("rc32434eth=", rc32434_setup); +__setup("ethaddr0=", rc32434_setup_ethaddr0); + + +#endif /* MODULE */ + +module_init(rc32434_init_module); +module_exit(rc32434_cleanup_module); + + + + + + + + + + + + + + diff --git a/target/linux/aruba-2.6/files/drivers/net/rc32434_eth.h b/target/linux/aruba-2.6/files/drivers/net/rc32434_eth.h new file mode 100644 index 000000000..d068f4fb9 --- /dev/null +++ b/target/linux/aruba-2.6/files/drivers/net/rc32434_eth.h @@ -0,0 +1,187 @@ +/************************************************************************** + * + * BRIEF MODULE DESCRIPTION + * Definitions for IDT RC32434 on-chip ethernet controller. + * + * Copyright 2004 IDT Inc. (rischelp@idt.com) + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + * + ************************************************************************** + * May 2004 rkt, neb + * + * Initial Release + * + * Aug 2004 + * + * Added NAPI + * + ************************************************************************** + */ + + +#include +#include +#include + +#define RC32434_DEBUG 2 +//#define RC32434_PROC_DEBUG +#undef RC32434_DEBUG + +#ifdef RC32434_DEBUG + +/* use 0 for production, 1 for verification, >2 for debug */ +static int rc32434_debug = RC32434_DEBUG; +#define ASSERT(expr) \ + if(!(expr)) { \ + printk( "Assertion failed! %s,%s,%s,line=%d\n", \ + #expr,__FILE__,__FUNCTION__,__LINE__); } +#define DBG(lvl, format, arg...) if (rc32434_debug > lvl) printk(KERN_INFO "%s: " format, dev->name , ## arg) +#else +#define ASSERT(expr) do {} while (0) +#define DBG(lvl, format, arg...) do {} while (0) +#endif + +#define INFO(format, arg...) printk(KERN_INFO "%s: " format, dev->name , ## arg) +#define ERR(format, arg...) printk(KERN_ERR "%s: " format, dev->name , ## arg) +#define WARN(format, arg...) printk(KERN_WARNING "%s: " format, dev->name , ## arg) + +#define ETH0_DMA_RX_IRQ GROUP1_IRQ_BASE + 0 +#define ETH0_DMA_TX_IRQ GROUP1_IRQ_BASE + 1 +#define ETH0_RX_OVR_IRQ GROUP3_IRQ_BASE + 9 +#define ETH0_TX_UND_IRQ GROUP3_IRQ_BASE + 10 + +#define ETH0_RX_DMA_ADDR (DMA0_PhysicalAddress + 0*DMA_CHAN_OFFSET) +#define ETH0_TX_DMA_ADDR (DMA0_PhysicalAddress + 1*DMA_CHAN_OFFSET) + +/* the following must be powers of two */ +#ifdef CONFIG_IDT_USE_NAPI +#define RC32434_NUM_RDS 64 /* number of receive descriptors */ +#define RC32434_NUM_TDS 64 /* number of transmit descriptors */ +#else +#define RC32434_NUM_RDS 128 /* number of receive descriptors */ +#define RC32434_NUM_TDS 128 /* number of transmit descriptors */ +#endif + +#define RC32434_RBSIZE 1536 /* size of one resource buffer = Ether MTU */ +#define RC32434_RDS_MASK (RC32434_NUM_RDS-1) +#define RC32434_TDS_MASK (RC32434_NUM_TDS-1) +#define RD_RING_SIZE (RC32434_NUM_RDS * sizeof(struct DMAD_s)) +#define TD_RING_SIZE (RC32434_NUM_TDS * sizeof(struct DMAD_s)) + +#define RC32434_TX_TIMEOUT HZ * 100 + +#define rc32434_eth0_regs ((ETH_t)(ETH0_VirtualAddress)) +#define rc32434_eth1_regs ((ETH_t)(ETH1_VirtualAddress)) + +enum status { filled, empty}; +#define IS_DMA_FINISHED(X) (((X) & (DMAD_f_m)) != 0) +#define IS_DMA_DONE(X) (((X) & (DMAD_d_m)) != 0) + + +/* Information that need to be kept for each board. */ +struct rc32434_local { + ETH_t eth_regs; + DMA_Chan_t rx_dma_regs; + DMA_Chan_t tx_dma_regs; + volatile DMAD_t td_ring; /* transmit descriptor ring */ + volatile DMAD_t rd_ring; /* receive descriptor ring */ + + struct sk_buff* tx_skb[RC32434_NUM_TDS]; /* skbuffs for pkt to trans */ + struct sk_buff* rx_skb[RC32434_NUM_RDS]; /* skbuffs for pkt to trans */ + +#ifndef CONFIG_IDT_USE_NAPI + struct tasklet_struct * rx_tasklet; +#endif + struct tasklet_struct * tx_tasklet; + + int rx_next_done; + int rx_chain_head; + int rx_chain_tail; + enum status rx_chain_status; + + int tx_next_done; + int tx_chain_head; + int tx_chain_tail; + enum status tx_chain_status; + int tx_count; + int tx_full; + + struct timer_list mii_phy_timer; + unsigned long duplex_mode; + + int rx_irq; + int tx_irq; + int ovr_irq; + int und_irq; + + struct net_device_stats stats; + spinlock_t lock; + + /* debug /proc entry */ + struct proc_dir_entry *ps; + int dma_halt_cnt; int dma_run_cnt; +}; + +extern unsigned int idt_cpu_freq; + +/* Index to functions, as function prototypes. */ +static int rc32434_open(struct net_device *dev); +static int rc32434_send_packet(struct sk_buff *skb, struct net_device *dev); +static void rc32434_mii_handler(unsigned long data); +static irqreturn_t rc32434_und_interrupt(int irq, void *dev_id); +static irqreturn_t rc32434_rx_dma_interrupt(int irq, void *dev_id); +static irqreturn_t rc32434_tx_dma_interrupt(int irq, void *dev_id); +#ifdef RC32434_REVISION +static irqreturn_t rc32434_ovr_interrupt(int irq, void *dev_id); +#endif +static int rc32434_close(struct net_device *dev); +static struct net_device_stats *rc32434_get_stats(struct net_device *dev); +static void rc32434_multicast_list(struct net_device *dev); +static int rc32434_init(struct net_device *dev); +static void rc32434_tx_timeout(struct net_device *dev); + +static void rc32434_tx_tasklet(unsigned long tx_data_dev); +#ifdef CONFIG_IDT_USE_NAPI +static int rc32434_poll(struct net_device *rx_data_dev, int *budget); +#else +static void rc32434_rx_tasklet(unsigned long rx_data_dev); +#endif +static void rc32434_cleanup_module(void); +static int rc32434_probe(int port_num); +int rc32434_init_module(void); + + +static inline void rc32434_abort_dma(struct net_device *dev, DMA_Chan_t ch) +{ + if (rc32434_readl(&ch->dmac) & DMAC_run_m) { + rc32434_writel(0x10, &ch->dmac); + + while (!(rc32434_readl(&ch->dmas) & DMAS_h_m)) + dev->trans_start = jiffies; + + rc32434_writel(0, &ch->dmas); + } + + rc32434_writel(0, &ch->dmadptr); + rc32434_writel(0, &ch->dmandptr); +} -- cgit v1.2.3