From 4a618c3a136008ff90590bb90e83ccac59dec57e Mon Sep 17 00:00:00 2001 From: juhosg Date: Sat, 29 Dec 2012 16:02:31 +0000 Subject: ar71xx: add support for 3.7 Signed-off-by: Gabor Juhos git-svn-id: svn://svn.openwrt.org/openwrt/trunk@34920 3c298f89-4303-0410-b956-a3cf2f4a3e73 --- ...add-SoC-detection-code-for-the-QCA9558-So.patch | 91 ++++++++++++++++++++++ 1 file changed, 91 insertions(+) create mode 100644 target/linux/ar71xx/patches-3.7/161-MIPS-ath79-add-SoC-detection-code-for-the-QCA9558-So.patch (limited to 'target/linux/ar71xx/patches-3.7/161-MIPS-ath79-add-SoC-detection-code-for-the-QCA9558-So.patch') diff --git a/target/linux/ar71xx/patches-3.7/161-MIPS-ath79-add-SoC-detection-code-for-the-QCA9558-So.patch b/target/linux/ar71xx/patches-3.7/161-MIPS-ath79-add-SoC-detection-code-for-the-QCA9558-So.patch new file mode 100644 index 000000000..1d9dd4beb --- /dev/null +++ b/target/linux/ar71xx/patches-3.7/161-MIPS-ath79-add-SoC-detection-code-for-the-QCA9558-So.patch @@ -0,0 +1,91 @@ +From 3c3c0eccf63b12fea98fd0eb65d0ccf69a7c5a57 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Sun, 24 Jun 2012 13:42:16 +0200 +Subject: [PATCH 17/34] MIPS: ath79: add SoC detection code for the QCA9558 SoC + +Signed-off-by: Gabor Juhos +--- + arch/mips/ath79/Kconfig | 4 ++++ + arch/mips/ath79/setup.c | 12 +++++++++++- + arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 2 ++ + arch/mips/include/asm/mach-ath79/ath79.h | 11 +++++++++++ + 4 files changed, 28 insertions(+), 1 deletions(-) + +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -88,6 +88,10 @@ config SOC_AR934X + select PCI_AR724X if PCI + def_bool n + ++config SOC_QCA955X ++ select USB_ARCH_HAS_EHCI ++ def_bool n ++ + config PCI_AR724X + def_bool n + +--- a/arch/mips/ath79/setup.c ++++ b/arch/mips/ath79/setup.c +@@ -164,13 +164,23 @@ static void __init ath79_detect_sys_type + rev = id & AR934X_REV_ID_REVISION_MASK; + break; + ++ case REV_ID_MAJOR_QCA9558: ++ ath79_soc = ATH79_SOC_QCA9558; ++ chip = "9558"; ++ rev = id & AR944X_REV_ID_REVISION_MASK; ++ break; ++ + default: + panic("ath79: unknown SoC, id:0x%08x", id); + } + + ath79_soc_rev = rev; + +- sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev); ++ if (soc_is_qca955x()) ++ sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u", ++ chip, rev); ++ else ++ sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev); + pr_info("SoC: %s\n", ath79_sys_type); + } + +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -391,6 +391,8 @@ + + #define AR934X_REV_ID_REVISION_MASK 0xf + ++#define AR944X_REV_ID_REVISION_MASK 0xf ++ + /* + * SPI block + */ +--- a/arch/mips/include/asm/mach-ath79/ath79.h ++++ b/arch/mips/include/asm/mach-ath79/ath79.h +@@ -32,6 +32,7 @@ enum ath79_soc_type { + ATH79_SOC_AR9341, + ATH79_SOC_AR9342, + ATH79_SOC_AR9344, ++ ATH79_SOC_QCA9558, + }; + + extern enum ath79_soc_type ath79_soc; +@@ -98,6 +99,16 @@ static inline int soc_is_ar934x(void) + return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344(); + } + ++static inline int soc_is_qca9558(void) ++{ ++ return ath79_soc == ATH79_SOC_QCA9558; ++} ++ ++static inline int soc_is_qca955x(void) ++{ ++ return soc_is_qca9558(); ++} ++ + extern void __iomem *ath79_ddr_base; + extern void __iomem *ath79_pll_base; + extern void __iomem *ath79_reset_base; -- cgit v1.2.3