From e96ea88268792c67a95db2ccb6572fd99404ff0e Mon Sep 17 00:00:00 2001 From: juhosg Date: Wed, 12 Sep 2012 19:06:38 +0000 Subject: ar71xx: define NAND controller base address and register size for AR934X/QCA955x git-svn-id: svn://svn.openwrt.org/openwrt/trunk@33382 3c298f89-4303-0410-b956-a3cf2f4a3e73 --- target/linux/ar71xx/patches-3.3/620-MIPS-ath79-OTP-support.patch | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'target/linux/ar71xx/patches-3.3/620-MIPS-ath79-OTP-support.patch') diff --git a/target/linux/ar71xx/patches-3.3/620-MIPS-ath79-OTP-support.patch b/target/linux/ar71xx/patches-3.3/620-MIPS-ath79-OTP-support.patch index 2ff6c3af5..087dbc082 100644 --- a/target/linux/ar71xx/patches-3.3/620-MIPS-ath79-OTP-support.patch +++ b/target/linux/ar71xx/patches-3.3/620-MIPS-ath79-OTP-support.patch @@ -149,9 +149,9 @@ #endif /* _ATH79_DEV_WMAC_H */ --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -@@ -125,6 +125,14 @@ - #define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) - #define QCA955X_GMAC_SIZE 0x40 +@@ -129,6 +129,14 @@ + #define QCA955X_NFC_BASE 0x1b000200 + #define QCA955X_NFC_SIZE 0xb8 +#define AR9300_OTP_BASE 0x14000 +#define AR9300_OTP_STATUS 0x15f18 -- cgit v1.2.3