From 41be3a0bd3c75498ef641c1611201e18cb94150c Mon Sep 17 00:00:00 2001 From: juhosg Date: Sat, 8 Sep 2012 13:39:09 +0000 Subject: ar71xx: fix CPU/DDR frequency calculation for SRIF PLLs on AR934x git-svn-id: svn://svn.openwrt.org/openwrt/trunk@33335 3c298f89-4303-0410-b956-a3cf2f4a3e73 --- .../163-MIPS-ath79-add-IRQ-handling-code-for-the-QCA955X-SoC.patch | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'target/linux/ar71xx/patches-3.3/163-MIPS-ath79-add-IRQ-handling-code-for-the-QCA955X-SoC.patch') diff --git a/target/linux/ar71xx/patches-3.3/163-MIPS-ath79-add-IRQ-handling-code-for-the-QCA955X-SoC.patch b/target/linux/ar71xx/patches-3.3/163-MIPS-ath79-add-IRQ-handling-code-for-the-QCA955X-SoC.patch index e4e2c30d9..8d24c742d 100644 --- a/target/linux/ar71xx/patches-3.3/163-MIPS-ath79-add-IRQ-handling-code-for-the-QCA955X-SoC.patch +++ b/target/linux/ar71xx/patches-3.3/163-MIPS-ath79-add-IRQ-handling-code-for-the-QCA955X-SoC.patch @@ -165,7 +165,7 @@ Signed-off-by: Gabor Juhos } --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -@@ -298,6 +298,7 @@ +@@ -300,6 +300,7 @@ #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac #define QCA955X_RESET_REG_BOOTSTRAP 0xb0 @@ -173,7 +173,7 @@ Signed-off-by: Gabor Juhos #define MISC_INT_ETHSW BIT(12) #define MISC_INT_TIMER4 BIT(10) -@@ -396,6 +397,37 @@ +@@ -398,6 +399,37 @@ AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \ AR934X_PCIE_WMAC_INT_PCIE_RC3) -- cgit v1.2.3