From 1c9cad5dceee0e2484e92ce5a713af0b0d48f3cf Mon Sep 17 00:00:00 2001
From: juhosg <juhosg@3c298f89-4303-0410-b956-a3cf2f4a3e73>
Date: Sat, 5 May 2012 13:56:35 +0000
Subject: ar71xx: update 3.3 patches

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@31602 3c298f89-4303-0410-b956-a3cf2f4a3e73
---
 ...th79-add-PCI-registration-code-for-AR934X.patch | 58 ----------------------
 1 file changed, 58 deletions(-)
 delete mode 100644 target/linux/ar71xx/patches-3.3/133-MIPS-ath79-add-PCI-registration-code-for-AR934X.patch

(limited to 'target/linux/ar71xx/patches-3.3/133-MIPS-ath79-add-PCI-registration-code-for-AR934X.patch')

diff --git a/target/linux/ar71xx/patches-3.3/133-MIPS-ath79-add-PCI-registration-code-for-AR934X.patch b/target/linux/ar71xx/patches-3.3/133-MIPS-ath79-add-PCI-registration-code-for-AR934X.patch
deleted file mode 100644
index 7f168b33e..000000000
--- a/target/linux/ar71xx/patches-3.3/133-MIPS-ath79-add-PCI-registration-code-for-AR934X.patch
+++ /dev/null
@@ -1,58 +0,0 @@
-From e30d942814a606c5258c7adafc6bbb49836573e9 Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Sat, 17 Dec 2011 10:13:08 +0100
-Subject: [PATCH 33/35] MIPS: ath79: add PCI registration code for AR934X
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
-Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
----
- arch/mips/ath79/Kconfig |    2 ++
- arch/mips/ath79/pci.c   |   13 ++++++++++++-
- 2 files changed, 14 insertions(+), 1 deletions(-)
-
---- a/arch/mips/ath79/Kconfig
-+++ b/arch/mips/ath79/Kconfig
-@@ -72,6 +72,8 @@ config SOC_AR933X
- 
- config SOC_AR934X
- 	select USB_ARCH_HAS_EHCI
-+	select HW_HAS_PCI
-+	select PCI_AR724X if PCI
- 	def_bool n
- 
- config PCI_AR724X
---- a/arch/mips/ath79/pci.c
-+++ b/arch/mips/ath79/pci.c
-@@ -14,6 +14,7 @@
- 
- #include <linux/init.h>
- #include <linux/pci.h>
-+#include <asm/mach-ath79/ar71xx_regs.h>
- #include <asm/mach-ath79/ath79.h>
- #include <asm/mach-ath79/irq.h>
- #include <asm/mach-ath79/pci.h>
-@@ -57,7 +58,9 @@ int __init pcibios_map_irq(const struct
- 		if (soc_is_ar71xx()) {
- 			ath79_pci_irq_map = ar71xx_pci_irq_map;
- 			ath79_pci_nr_irqs = ARRAY_SIZE(ar71xx_pci_irq_map);
--		} else if (soc_is_ar724x()) {
-+		} else if (soc_is_ar724x() ||
-+			   soc_is_ar9342() ||
-+			   soc_is_ar9344()) {
- 			ath79_pci_irq_map = ar724x_pci_irq_map;
- 			ath79_pci_nr_irqs = ARRAY_SIZE(ar724x_pci_irq_map);
- 		} else {
-@@ -115,5 +118,13 @@ int __init ath79_register_pci(void)
- 	if (soc_is_ar724x())
- 		return ar724x_pcibios_init(ATH79_CPU_IRQ_IP2);
- 
-+	if (soc_is_ar9342() || soc_is_ar9344()) {
-+		u32 bootstrap;
-+
-+		bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
-+		if (bootstrap & AR934X_BOOTSTRAP_PCIE_RC)
-+			return ar724x_pcibios_init(ATH79_IP2_IRQ(0));
-+	}
-+
- 	return -ENODEV;
- }
-- 
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