From 546b5ed544503182a9b3e981bc11feebd6042b21 Mon Sep 17 00:00:00 2001 From: juhosg Date: Mon, 21 Jul 2008 17:08:14 +0000 Subject: surprise :p git-svn-id: svn://svn.openwrt.org/openwrt/trunk@11894 3c298f89-4303-0410-b956-a3cf2f4a3e73 --- .../files/include/asm-mips/mach-ar71xx/war.h | 25 ++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/war.h (limited to 'target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/war.h') diff --git a/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/war.h b/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/war.h new file mode 100644 index 000000000..1ca6ffdc6 --- /dev/null +++ b/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MACH_AR71XX_WAR_H +#define __ASM_MACH_AR71XX_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MACH_AR71XX_WAR_H */ -- cgit v1.2.3