From c46ada5677763a31e1ca8f2589efd6bbcd0f99a7 Mon Sep 17 00:00:00 2001 From: juhosg Date: Tue, 7 Jul 2009 13:57:57 +0000 Subject: [ar71xx] AR7240 requires different IRQ unmasking code git-svn-id: svn://svn.openwrt.org/openwrt/trunk@16734 3c298f89-4303-0410-b956-a3cf2f4a3e73 --- target/linux/ar71xx/files/arch/mips/ar71xx/irq.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'target/linux/ar71xx/files/arch') diff --git a/target/linux/ar71xx/files/arch/mips/ar71xx/irq.c b/target/linux/ar71xx/files/arch/mips/ar71xx/irq.c index a912f3892..6bc1c6d5c 100644 --- a/target/linux/ar71xx/files/arch/mips/ar71xx/irq.c +++ b/target/linux/ar71xx/files/arch/mips/ar71xx/irq.c @@ -297,6 +297,22 @@ static void ar71xx_misc_irq_unmask(unsigned int irq) ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE); } +static void ar724x_misc_irq_unmask(unsigned int irq) +{ + irq -= AR71XX_MISC_IRQ_BASE; + ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, + ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE) | (1 << irq)); + + /* flush write */ + ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE); + + ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_STATUS, + ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS) & ~(1 << irq)); + + /* flush write */ + ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS); +} + static void ar71xx_misc_irq_mask(unsigned int irq) { irq -= AR71XX_MISC_IRQ_BASE; @@ -326,6 +342,9 @@ static void __init ar71xx_misc_irq_init(void) ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, 0); ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_STATUS, 0); + if (ar71xx_soc == AR71XX_SOC_AR7240) + ar71xx_misc_irq_chip.unmask = ar724x_misc_irq_unmask; + for (i = AR71XX_MISC_IRQ_BASE; i < AR71XX_MISC_IRQ_BASE + AR71XX_MISC_IRQ_COUNT; i++) { irq_desc[i].status = IRQ_DISABLED; -- cgit v1.2.3