From 05c930e80a27d5caac4ab057a906a075f59635ea Mon Sep 17 00:00:00 2001 From: ralph Date: Tue, 30 Mar 2010 13:56:30 +0000 Subject: [uboot-lantiq] add preliminary AR9 support attention: if caches enabled the network is broken attention: the network of the flash image doesn't work because of enabled caches git-svn-id: svn://svn.openwrt.org/openwrt/trunk@20606 3c298f89-4303-0410-b956-a3cf2f4a3e73 --- .../board/infineon/easy50812/ar9_ddr250_settings.h | 51 ++++++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr250_settings.h (limited to 'package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr250_settings.h') diff --git a/package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr250_settings.h b/package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr250_settings.h new file mode 100644 index 000000000..2e49db99d --- /dev/null +++ b/package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr250_settings.h @@ -0,0 +1,51 @@ +/* Settings for Denali DDR SDRAM controller */ +/* Optimise for AR9 Ref Board DDR 221 Mhz - by Ng Aik Ann 16th May 2008 */ + +#define MC_DC0_VALUE 0x1B1B +#define MC_DC1_VALUE 0x0 +#define MC_DC2_VALUE 0x0 +#define MC_DC3_VALUE 0x0 +#define MC_DC4_VALUE 0x0 +#define MC_DC5_VALUE 0x200 +#define MC_DC6_VALUE 0x306 +#define MC_DC7_VALUE 0x403 +#define MC_DC8_VALUE 0x103 +#define MC_DC9_VALUE 0xb0e +#define MC_DC10_VALUE 0x204 +#define MC_DC11_VALUE 0x1102 +#define MC_DC12_VALUE 0x2c8 +#define MC_DC13_VALUE 0x1 +#define MC_DC14_VALUE 0x0 +#define MC_DC15_VALUE 0x155 /* WDQS tuning for clk_wr*/ +#define MC_DC16_VALUE 0xc800 +#define MC_DC17_VALUE 0x13 +#define MC_DC18_VALUE 0x401 +#define MC_DC19_VALUE 0x200 +#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */ +#define MC_DC21_VALUE 0xc00 +#define MC_DC22_VALUE 0xc0c +#define MC_DC23_VALUE 0x0 +#define MC_DC24_VALUE 0x74 /* WDQS Tuning for DQS */ +#define MC_DC25_VALUE 0x0 +#define MC_DC26_VALUE 0x0 +#define MC_DC27_VALUE 0x0 +#define MC_DC28_VALUE 0x798 +#define MC_DC29_VALUE 0x445d +#define MC_DC30_VALUE 0xc351 +#define MC_DC31_VALUE 0x0 +#define MC_DC32_VALUE 0x0 +#define MC_DC33_VALUE 0x0 +#define MC_DC34_VALUE 0x0 +#define MC_DC35_VALUE 0x0 +#define MC_DC36_VALUE 0x0 +#define MC_DC37_VALUE 0x0 +#define MC_DC38_VALUE 0x0 +#define MC_DC39_VALUE 0x0 +#define MC_DC40_VALUE 0x0 +#define MC_DC41_VALUE 0x0 +#define MC_DC42_VALUE 0x0 +#define MC_DC43_VALUE 0x0 +#define MC_DC44_VALUE 0x0 +#define MC_DC45_VALUE 0x600 +//#define MC_DC45_VALUE 0x400 +#define MC_DC46_VALUE 0x0 -- cgit v1.2.3