From 2f214490a3b2e7983c27e7303d30adda2241235a Mon Sep 17 00:00:00 2001 From: hcg Date: Wed, 9 May 2007 08:52:32 +0000 Subject: Corrected inverted DCD/DTR logic git-svn-id: svn://svn.openwrt.org/openwrt/trunk@7145 3c298f89-4303-0410-b956-a3cf2f4a3e73 --- target/linux/at91-2.6/patches/008-fdl-serial.patch | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/linux/at91-2.6/patches/008-fdl-serial.patch b/target/linux/at91-2.6/patches/008-fdl-serial.patch index 2260ffb6f..379691597 100644 --- a/target/linux/at91-2.6/patches/008-fdl-serial.patch +++ b/target/linux/at91-2.6/patches/008-fdl-serial.patch @@ -10,9 +10,9 @@ + * USART 0 - Drive DTR and RI pins manually + */ + if (mctrl & TIOCM_DTR) -+ at91_set_gpio_value(AT91_PIN_PA19, 0); ++ at91_set_gpio_value(AT91_PIN_PB6, 0); + else -+ at91_set_gpio_value(AT91_PIN_PA19, 1); ++ at91_set_gpio_value(AT91_PIN_PB6, 1); + if (mctrl & TIOCM_RI) + at91_set_gpio_value(AT91_PIN_PB7, 0); + else @@ -25,9 +25,9 @@ + */ + if (port->mapbase == AT91RM9200_BASE_US3) { + if (mctrl & TIOCM_DTR) -+ at91_set_gpio_value(AT91_PIN_PA24, 0); ++ at91_set_gpio_value(AT91_PIN_PB29, 0); + else -+ at91_set_gpio_value(AT91_PIN_PA24, 1); ++ at91_set_gpio_value(AT91_PIN_PB29, 1); + if (mctrl & TIOCM_RI) + at91_set_gpio_value(AT91_PIN_PB2, 0); + else @@ -60,10 +60,10 @@ + * Read the GPIO's for the FDL VersaLink special case + */ + if (port->mapbase == AT91RM9200_BASE_US0) -+ if (!(at91_get_gpio_value(AT91_PIN_PB6))) ++ if (!(at91_get_gpio_value(AT91_PIN_PA19))) + ret |= TIOCM_CD; + if (port->mapbase == AT91RM9200_BASE_US3) -+ if (!(at91_get_gpio_value(AT91_PIN_PB29))) ++ if (!(at91_get_gpio_value(AT91_PIN_PA24))) + ret |= TIOCM_CD; + return ret; -- cgit v1.2.3