| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Serial patches for .21 | hcg | 2007-05-28 | 1 | -75/+71 |
| | | | | | git-svn-id: svn://svn.openwrt.org/openwrt/trunk@7375 3c298f89-4303-0410-b956-a3cf2f4a3e73 | ||||
| * | Midified UART init, added interrupt handlers for DCD lines | hcg | 2007-05-09 | 1 | -1/+94 |
| | | | | | git-svn-id: svn://svn.openwrt.org/openwrt/trunk@7146 3c298f89-4303-0410-b956-a3cf2f4a3e73 | ||||
| * | Corrected inverted DCD/DTR logic | hcg | 2007-05-09 | 1 | -6/+6 |
| | | | | | git-svn-id: svn://svn.openwrt.org/openwrt/trunk@7145 3c298f89-4303-0410-b956-a3cf2f4a3e73 | ||||
| * | Add support for VersaLink modem control on DCE ports 0 and 3 | hcg | 2007-05-09 | 1 | -0/+71 |
| git-svn-id: svn://svn.openwrt.org/openwrt/trunk@7144 3c298f89-4303-0410-b956-a3cf2f4a3e73 | |||||
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index : rtl819xx | |
| Realtek rtl819xx port to OpenWrt | Roman |
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