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* ar71xx: define NAND controller base address and register size for AR934X/QCA955xjuhosg2012-09-121-10/+20
| | | | git-svn-id: svn://svn.openwrt.org/openwrt/trunk@33382 3c298f89-4303-0410-b956-a3cf2f4a3e73
* ar71xx: fix QCA955X_EHCI_SIZEjuhosg2012-09-101-1/+1
| | | | git-svn-id: svn://svn.openwrt.org/openwrt/trunk@33360 3c298f89-4303-0410-b956-a3cf2f4a3e73
* ar71xx: use dynamic clock dividers on the 2nd MDIO of AR934xjuhosg2012-09-091-4/+14
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* ar71xx: fix CPU/DDR frequency calculation for SRIF PLLs on AR934xjuhosg2012-09-081-10/+10
| | | | git-svn-id: svn://svn.openwrt.org/openwrt/trunk@33335 3c298f89-4303-0410-b956-a3cf2f4a3e73
* ar71xx: add initial support for the QCA955X SoCsjuhosg2012-07-051-7/+26
| | | | git-svn-id: svn://svn.openwrt.org/openwrt/trunk@32606 3c298f89-4303-0410-b956-a3cf2f4a3e73
* ar71xx: refactor PCI code to allow registering multiple PCI controllersjuhosg2012-07-051-14/+11
| | | | git-svn-id: svn://svn.openwrt.org/openwrt/trunk@32605 3c298f89-4303-0410-b956-a3cf2f4a3e73
* ar71xx: update 3.3 patchesjuhosg2012-05-051-8/+37
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* ar71xx: add AR934x specific interface speed setup for ge0juhosg2012-03-191-4/+12
| | | | git-svn-id: svn://svn.openwrt.org/openwrt/trunk@31017 3c298f89-4303-0410-b956-a3cf2f4a3e73
* ar71xx: add preliminary support for 3.3juhosg2012-02-101-0/+231
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@30410 3c298f89-4303-0410-b956-a3cf2f4a3e73