rtl819xx - Realtek rtl819xx port to OpenWrt

	Commit message (Collapse)	Author	Age	Files	Lines
*	ar71xx: define NAND controller base address and register size for AR934X/QCA955x	juhosg	2012-09-12	1	-10/+20
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*	ar71xx: fix QCA955X_EHCI_SIZE	juhosg	2012-09-10	1	-1/+1
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*	ar71xx: use dynamic clock dividers on the 2nd MDIO of AR934x	juhosg	2012-09-09	1	-4/+14
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*	ar71xx: fix CPU/DDR frequency calculation for SRIF PLLs on AR934x	juhosg	2012-09-08	1	-10/+10
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*	ar71xx: add initial support for the QCA955X SoCs	juhosg	2012-07-05	1	-7/+26
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*	ar71xx: refactor PCI code to allow registering multiple PCI controllers	juhosg	2012-07-05	1	-14/+11
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*	ar71xx: update 3.3 patches	juhosg	2012-05-05	1	-8/+37
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*	ar71xx: add AR934x specific interface speed setup for ge0	juhosg	2012-03-19	1	-4/+12
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*	ar71xx: add preliminary support for 3.3	juhosg	2012-02-10	1	-0/+231
	git-svn-id: svn://svn.openwrt.org/openwrt/trunk@30410 3c298f89-4303-0410-b956-a3cf2f4a3e73