| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | ar71xx: use correct fractional dividers for {CPU,DDR}_PLL on QCA955x | juhosg | 2012-09-10 | 1 | -2/+2 |
| | | | | | git-svn-id: svn://svn.openwrt.org/openwrt/trunk@33362 3c298f89-4303-0410-b956-a3cf2f4a3e73 | ||||
| * | ar71xx: fix CPU/DDR frequency calculation for SRIF PLLs on AR934x | juhosg | 2012-09-08 | 1 | -6/+6 |
| | | | | | git-svn-id: svn://svn.openwrt.org/openwrt/trunk@33335 3c298f89-4303-0410-b956-a3cf2f4a3e73 | ||||
| * | ar71xx: add initial support for the QCA955X SoCs | juhosg | 2012-07-05 | 1 | -0/+167 |
| git-svn-id: svn://svn.openwrt.org/openwrt/trunk@32606 3c298f89-4303-0410-b956-a3cf2f4a3e73 | |||||
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index : rtl819xx | |
| Realtek rtl819xx port to OpenWrt | Roman |
| summaryrefslogtreecommitdiffstats |
path: root/target/linux/ar71xx/patches-3.3/162-MIPS-ath79-add-clock-setup-for-the-QCA955X-SoCs.patch