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path: root/target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c
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* ar71xx: use ar71xx_pci_fixup on ar71xx SoCs onlyjuhosg2009-10-011-0/+5
| | | | git-svn-id: svn://svn.openwrt.org/openwrt/trunk@17807 3c298f89-4303-0410-b956-a3cf2f4a3e73
* [ar71xx] reorganize PCI codejuhosg2009-07-051-27/+7
| | | | git-svn-id: svn://svn.openwrt.org/openwrt/trunk@16672 3c298f89-4303-0410-b956-a3cf2f4a3e73
* [ar71xx] rename DDR registersjuhosg2008-11-261-8/+8
| | | | git-svn-id: svn://svn.openwrt.org/openwrt/trunk@13363 3c298f89-4303-0410-b956-a3cf2f4a3e73
* [ar71xx] fix the PCI byte lane enable generation code, based on a patch by ↵juhosg2008-09-171-5/+6
| | | | | | Chris Dearman git-svn-id: svn://svn.openwrt.org/openwrt/trunk@12617 3c298f89-4303-0410-b956-a3cf2f4a3e73
* surprise :pjuhosg2008-07-211-0/+346
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@11894 3c298f89-4303-0410-b956-a3cf2f4a3e73
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