rtl819xx - Realtek rtl819xx port to OpenWrt

	Commit message (Collapse)	Author	Age	Files	Lines
*	ar71xx: disable PHY_SWAP and PHY_ADDR_SWAP bits on ↵	juhosg	2013-01-07	1	-2/+2
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	TL-WR703N/MR3020/MR3040/MR11U boards The PHY_SWAP and PHY_ADDR_SWAP bits are initialized differently by different versions of the bootloader. This leads to broken ethernet connection with OpenWrt on some boards. Turn both SWAP bits OFF on these boards to make it consistent regardless of the bootloader used. Based on a patch by Michel Stempin <michel.stempin@wanadoo.fr>. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> git-svn-id: svn://svn.openwrt.org/openwrt/trunk@35037 3c298f89-4303-0410-b956-a3cf2f4a3e73
*	ar71xx: use gpio_request_one instead of ath79_set_usb_power_gpio	juhosg	2012-11-05	1	-2/+3
\| \| \| \| \| \|	Signed-off-by: Gabor Juhos <juhosg@openwrt.org> git-svn-id: svn://svn.openwrt.org/openwrt/trunk@34087 3c298f89-4303-0410-b956-a3cf2f4a3e73
*	ar71xx: add a common function to configure USB power GPIOs	juhosg	2012-06-19	1	-2/+2
\| \| \| \|	git-svn-id: svn://svn.openwrt.org/openwrt/trunk@32454 3c298f89-4303-0410-b956-a3cf2f4a3e73
*	ar71xx: fix PHY setup on TL-MR3020 (fixes #11572)	nbd	2012-06-06	1	-0/+4
\| \| \| \|	git-svn-id: svn://svn.openwrt.org/openwrt/trunk@32093 3c298f89-4303-0410-b956-a3cf2f4a3e73
*	ar71xx: merge files-3.2 to files	juhosg	2012-02-10	1	-0/+121
	git-svn-id: svn://svn.openwrt.org/openwrt/trunk@30405 3c298f89-4303-0410-b956-a3cf2f4a3e73