rtl819xx - Realtek rtl819xx port to OpenWrt

	Commit message (Collapse)	Author	Age	Files	Lines
*	ar71xx: use dynamic clock dividers on the 2nd MDIO of AR934x	juhosg	2012-09-09	1	-0/+33
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*	Revert "ar71xx: only allow RGMII mode on the 2nd ethernet MAC of the AR7240"	juhosg	2012-08-29	1	-8/+1
\| \| \| \| \| \|	That was based on assumptions. git-svn-id: svn://svn.openwrt.org/openwrt/trunk@33310 3c298f89-4303-0410-b956-a3cf2f4a3e73
*	ar71xx: only allow RGMII mode on the 2nd ethernet MAC of the AR7240	juhosg	2012-08-27	1	-1/+8
\| \| \| \| \| \|	Signed-off-by: Daniel Golle <dgolle@allnet.de> git-svn-id: svn://svn.openwrt.org/openwrt/trunk@33280 3c298f89-4303-0410-b956-a3cf2f4a3e73
*	ar71xx: add initial support for the QCA955X SoCs	juhosg	2012-07-05	1	-1/+9
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*	ar71xx: add a helper function for setting up PHY4 swapping on ar933x	nbd	2012-06-06	1	-0/+18
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*	ar71xx: fix MII clock settings for various chips, improves ethernet ↵	nbd	2012-05-27	1	-2/+10
\| \| \| \| \| \|	stability on AR934x git-svn-id: svn://svn.openwrt.org/openwrt/trunk@31925 3c298f89-4303-0410-b956-a3cf2f4a3e73
*	ar71xx: allow to disable link polling on unused PHYs	juhosg	2012-04-29	1	-0/+4
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*	ar71xx: add AR934x specific interface speed setup for ge0	juhosg	2012-03-19	1	-4/+9
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*	ar71xx: reset the switch on AR934x before ethernet device registration	juhosg	2012-03-13	1	-0/+4
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*	ar71xx: use a dummy callback for interfaces with fixed speed	juhosg	2012-03-12	1	-28/+7
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*	ar71xx: merge ar934x_bo_ddr_flush patch	juhosg	2012-03-12	1	-12/+5
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*	ar71xx: merge files-3.2 to files	juhosg	2012-02-10	1	-0/+971
	git-svn-id: svn://svn.openwrt.org/openwrt/trunk@30405 3c298f89-4303-0410-b956-a3cf2f4a3e73