rtl819xx - Realtek rtl819xx port to OpenWrt

	Commit message (Collapse)	Author	Age	Files	Lines
*	[ar7] move files to file-2.6.30	florian	2010-02-04	3	-801/+0
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*	I recently came across an ar7 device which has the vlynq hardwired	florian	2009-05-25	1	-23/+127
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	so that the clocks are always generated by the remote device instead of the local one. Upon initialization the current version of vlynq driver disables remote clock generation and causes the entire bus to hang on my device. This patch adds support for detecting which device (local or remote) is responsible of clock generation and implements clock initialization based on detection result. Signed-off-by: Antti Seppala <a.seppala at gmail.com> git-svn-id: svn://svn.openwrt.org/openwrt/trunk@16049 3c298f89-4303-0410-b956-a3cf2f4a3e73
*	Treat vlynq external divisor just like automatic, fix comment about it, ↵	florian	2008-09-01	1	-1/+3
\| \| \| \| \| \|	thanks sn9 git-svn-id: svn://svn.openwrt.org/openwrt/trunk@12467 3c298f89-4303-0410-b956-a3cf2f4a3e73
*	Fix divisor calculation and configuration from previous commit, thanks sn9	florian	2008-09-01	1	-37/+16
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*	Fix divisor settings for external devices like wireless devices, thanks sn9	florian	2008-08-31	1	-13/+41
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*	ar7: remove unneeded packed and array initialization	matteo	2008-04-07	1	-1/+1
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*	vlynq: small fixes	matteo	2008-04-02	1	-1/+2
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*	add proper email addresses to the comment headers	matteo	2008-04-02	1	-1/+1
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*	Let authors holds copyright of the AR7 code (closes #2369)	matteo	2008-04-02	1	-1/+1
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*	vlynq: probe for an external clock first, needed to enable acx on the ↵	matteo	2008-04-02	1	-9/+8
\| \| \| \| \| \|	Leonardo board git-svn-id: svn://svn.openwrt.org/openwrt/trunk@10707 3c298f89-4303-0410-b956-a3cf2f4a3e73
*	Fix VLYNQ device enable for DG834Gv1	nbd	2007-12-04	1	-1/+1
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	This patch allows VLYNQ devices on the DG834Gv1 to be successfully enabled. Currently the "__vlynq_enable_device" function attempts to set the VLYNQ device clock divisor to values from 1 through 8 until a link is successfully established. On the DG834Gv1 (but not the DG834Gv2), setting the VLYNQ device clock divisor to 1 (full rate) results in all further VLYNQ operations failing (including software reset), so the device is never enabled. This patches changes the function to only attempt divisors 2 through 8, and hence the device is successfully enabled. Signed-off-by: Nick Forbes <nick.forbes@huntsworth.com> --------- git-svn-id: svn://svn.openwrt.org/openwrt/trunk@9656 3c298f89-4303-0410-b956-a3cf2f4a3e73
*	cleanup vlynq. drop vlynq-pci	ejka	2007-10-05	3	-0/+688
	git-svn-id: svn://svn.openwrt.org/openwrt/trunk@9143 3c298f89-4303-0410-b956-a3cf2f4a3e73