diff options
Diffstat (limited to 'toolchain')
22 files changed, 1340 insertions, 0 deletions
diff --git a/toolchain/gcc/Config.in b/toolchain/gcc/Config.in index f87d62792..7979e9857 100644 --- a/toolchain/gcc/Config.in +++ b/toolchain/gcc/Config.in @@ -20,6 +20,9 @@ choice select GCC_VERSION_4_8_0 bool "gcc 4.8.0" + config GCC_VERSION_4_5_LINARO + bool "gcc 4.5.x with Linaro enhancements" + config GCC_USE_VERSION_4_6_LINARO select GCC_VERSION_4_6_LINARO bool "gcc 4.6.x with Linaro enhancements" diff --git a/toolchain/gcc/Config.version b/toolchain/gcc/Config.version index 167da7616..7f36ad583 100644 --- a/toolchain/gcc/Config.version +++ b/toolchain/gcc/Config.version @@ -20,6 +20,7 @@ config GCC_VERSION default "4.4.7" if GCC_VERSION_4_4_7 default "4.6.3" if GCC_VERSION_4_6_3 default "4.8.0" if GCC_VERSION_4_8_0 + default "4.5-linaro" if GCC_VERSION_4_5_LINARO default "4.6-linaro" if GCC_VERSION_4_6_LINARO default "4.8-linaro" if GCC_VERSION_4_8_LINARO default "4.6-linaro" @@ -28,6 +29,10 @@ config GCC_VERSION_4_4 bool default y if GCC_VERSION_4_4_7 +config GCC_VERSION_4_5 + bool + default y if GCC_VERSION_4_5_LINARO + config GCC_VERSION_4_6 bool default y if (GCC_VERSION_4_6_3 || GCC_VERSION_4_6_LINARO) diff --git a/toolchain/gcc/common.mk b/toolchain/gcc/common.mk index 9544133bd..0c99abfbd 100644 --- a/toolchain/gcc/common.mk +++ b/toolchain/gcc/common.mk @@ -26,6 +26,12 @@ PKG_VERSION:=$(firstword $(subst +, ,$(GCC_VERSION))) GCC_DIR:=$(PKG_NAME)-$(PKG_VERSION) ifeq ($(findstring linaro, $(CONFIG_GCC_VERSION)),linaro) + ifeq ($(CONFIG_GCC_VERSION),"4.5-linaro") + PKG_REV:=4.5-2012.03 + PKG_VERSION:=4.5.4 + PKG_VERSION_MAJOR:=4.5 + PKG_MD5SUM:=0c25f93e15e362e352c933e4649a7fc6 + endif ifeq ($(CONFIG_GCC_VERSION),"4.6-linaro") PKG_REV:=4.6-2012.12 PKG_VERSION:=4.6.4 diff --git a/toolchain/gcc/patches/4.5-linaro/010-documentation.patch b/toolchain/gcc/patches/4.5-linaro/010-documentation.patch new file mode 100644 index 000000000..4d5e275f5 --- /dev/null +++ b/toolchain/gcc/patches/4.5-linaro/010-documentation.patch @@ -0,0 +1,23 @@ +--- a/gcc/Makefile.in ++++ b/gcc/Makefile.in +@@ -4040,18 +4040,10 @@ + doc/gccint.info: $(TEXI_GCCINT_FILES) + doc/cppinternals.info: $(TEXI_CPPINT_FILES) + +-doc/%.info: %.texi +- if [ x$(BUILD_INFO) = xinfo ]; then \ +- $(MAKEINFO) $(MAKEINFOFLAGS) -I . -I $(gcc_docdir) \ +- -I $(gcc_docdir)/include -o $@ $<; \ +- fi ++doc/%.info: + + # Duplicate entry to handle renaming of gccinstall.info +-doc/gccinstall.info: $(TEXI_GCCINSTALL_FILES) +- if [ x$(BUILD_INFO) = xinfo ]; then \ +- $(MAKEINFO) $(MAKEINFOFLAGS) -I $(gcc_docdir) \ +- -I $(gcc_docdir)/include -o $@ $<; \ +- fi ++doc/gccinstall.info: + + doc/cpp.dvi: $(TEXI_CPP_FILES) + doc/gcc.dvi: $(TEXI_GCC_FILES) diff --git a/toolchain/gcc/patches/4.5-linaro/100-uclibc-conf.patch b/toolchain/gcc/patches/4.5-linaro/100-uclibc-conf.patch new file mode 100644 index 000000000..5c77de9b4 --- /dev/null +++ b/toolchain/gcc/patches/4.5-linaro/100-uclibc-conf.patch @@ -0,0 +1,33 @@ +--- a/contrib/regression/objs-gcc.sh ++++ b/contrib/regression/objs-gcc.sh +@@ -106,6 +106,10 @@ if [ $H_REAL_TARGET = $H_REAL_HOST -a $H + then + make all-gdb all-dejagnu all-ld || exit 1 + make install-gdb install-dejagnu install-ld || exit 1 ++elif [ $H_REAL_TARGET = $H_REAL_HOST -a $H_REAL_TARGET = i686-pc-linux-uclibc ] ++ then ++ make all-gdb all-dejagnu all-ld || exit 1 ++ make install-gdb install-dejagnu install-ld || exit 1 + elif [ $H_REAL_TARGET = $H_REAL_HOST ] ; then + make bootstrap || exit 1 + make install || exit 1 +--- a/libjava/classpath/ltconfig ++++ b/libjava/classpath/ltconfig +@@ -603,7 +603,7 @@ host_os=`echo $host | sed 's/^\([^-]*\)- + + # Transform linux* to *-*-linux-gnu*, to support old configure scripts. + case $host_os in +-linux-gnu*) ;; ++linux-gnu*|linux-uclibc*) ;; + linux*) host=`echo $host | sed 's/^\(.*-.*-linux\)\(.*\)$/\1-gnu\2/'` + esac + +@@ -1251,7 +1251,7 @@ linux-gnuoldld* | linux-gnuaout* | linux + ;; + + # This must be Linux ELF. +-linux-gnu*) ++linux*) + version_type=linux + need_lib_prefix=no + need_version=no diff --git a/toolchain/gcc/patches/4.5-linaro/200-musl.patch b/toolchain/gcc/patches/4.5-linaro/200-musl.patch new file mode 100644 index 000000000..d68f67241 --- /dev/null +++ b/toolchain/gcc/patches/4.5-linaro/200-musl.patch @@ -0,0 +1,222 @@ +--- a/config.sub ++++ b/config.sub +@@ -125,6 +125,7 @@ esac + maybe_os=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\2/'` + case $maybe_os in + nto-qnx* | linux-gnu* | linux-android* | linux-dietlibc | linux-newlib* | \ ++ linux-musl* | \ + linux-uclibc* | uclinux-uclibc* | uclinux-gnu* | kfreebsd*-gnu* | \ + knetbsd*-gnu* | netbsd*-gnu* | \ + kopensolaris*-gnu* | \ +--- a/gcc/config/arm/linux-eabi.h ++++ b/gcc/config/arm/linux-eabi.h +@@ -63,6 +63,10 @@ + #undef GLIBC_DYNAMIC_LINKER + #define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.3" + ++/* musl has no "classic" (i.e. broken) mode */ ++#undef MUSL_DYNAMIC_LINKER ++#define MUSL_DYNAMIC_LINKER "/lib/ld-musl-arm.so.1" ++ + /* At this point, bpabi.h will have clobbered LINK_SPEC. We want to + use the GNU/Linux version, not the generic BPABI version. */ + #undef LINK_SPEC +--- a/gcc/config/i386/linux.h ++++ b/gcc/config/i386/linux.h +@@ -101,6 +101,7 @@ along with GCC; see the file COPYING3. + /* These macros may be overridden in k*bsd-gnu.h and i386/k*bsd-gnu.h. */ + #define LINK_EMULATION "elf_i386" + #define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2" ++#define MUSL_DYNAMIC_LINKER "/lib/ld-musl-i386.so.1" + + #undef ASM_SPEC + #define ASM_SPEC \ +--- a/gcc/config/i386/linux64.h ++++ b/gcc/config/i386/linux64.h +@@ -61,6 +61,9 @@ see the files COPYING3 and COPYING.RUNTI + #define GLIBC_DYNAMIC_LINKER32 "/lib/ld-linux.so.2" + #define GLIBC_DYNAMIC_LINKER64 "/lib64/ld-linux-x86-64.so.2" + ++#define MUSL_DYNAMIC_LINKER32 "/lib/ld-musl-i386.so.1" ++#define MUSL_DYNAMIC_LINKER64 "/lib/ld-musl-x86_64.so.1" ++ + #if TARGET_64BIT_DEFAULT + #define SPEC_32 "m32" + #define SPEC_64 "!m32" +--- a/gcc/config/linux.h ++++ b/gcc/config/linux.h +@@ -86,6 +86,7 @@ see the files COPYING3 and COPYING.RUNTI + #define OPTION_GLIBC (linux_libc == LIBC_GLIBC) + #define OPTION_UCLIBC (linux_libc == LIBC_UCLIBC) + #define OPTION_BIONIC (linux_libc == LIBC_BIONIC) ++#define OPTION_MUSL (linux_libc == LIBC_MUSL) + + #define LINUX_TARGET_OS_CPP_BUILTINS() \ + do { \ +@@ -120,18 +121,21 @@ see the files COPYING3 and COPYING.RUNTI + uClibc or Bionic is the default C library and whether + -muclibc or -mglibc or -mbionic has been passed to change the default. */ + +-#define CHOOSE_DYNAMIC_LINKER1(LIBC1, LIBC2, LIBC3, LD1, LD2, LD3) \ +- "%{" LIBC2 ":" LD2 ";:%{" LIBC3 ":" LD3 ";:" LD1 "}}" ++#define CHOOSE_DYNAMIC_LINKER1(LIBC1, LIBC2, LIBC3, LIBC4, LD1, LD2, LD3, LD4) \ ++ "%{" LIBC2 ":" LD2 ";:%{" LIBC3 ":" LD3 ";:%{" LIBC4 ":" LD4 ";:" LD1 "}}}" + + #if DEFAULT_LIBC == LIBC_GLIBC +-#define CHOOSE_DYNAMIC_LINKER(G, U, B) \ +- CHOOSE_DYNAMIC_LINKER1 ("mglibc", "muclibc", "mbionic", G, U, B) ++#define CHOOSE_DYNAMIC_LINKER(G, U, B, M) \ ++ CHOOSE_DYNAMIC_LINKER1 ("mglibc", "muclibc", "mbionic", "mmusl", G, U, B, M) + #elif DEFAULT_LIBC == LIBC_UCLIBC +-#define CHOOSE_DYNAMIC_LINKER(G, U, B) \ +- CHOOSE_DYNAMIC_LINKER1 ("muclibc", "mglibc", "mbionic", U, G, B) ++#define CHOOSE_DYNAMIC_LINKER(G, U, B, M) \ ++ CHOOSE_DYNAMIC_LINKER1 ("muclibc", "mglibc", "mbionic", "mmusl", U, G, B, M) + #elif DEFAULT_LIBC == LIBC_BIONIC +-#define CHOOSE_DYNAMIC_LINKER(G, U, B) \ +- CHOOSE_DYNAMIC_LINKER1 ("mbionic", "mglibc", "muclibc", B, G, U) ++#define CHOOSE_DYNAMIC_LINKER(G, U, B, M) \ ++ CHOOSE_DYNAMIC_LINKER1 ("mbionic", "mglibc", "muclibc", "mmusl", B, G, U, M) ++#elif DEFAULT_LIBC == LIBC_MUSL ++#define CHOOSE_DYNAMIC_LINKER(G, U, B, M) \ ++ CHOOSE_DYNAMIC_LINKER1 ("mmusl", "mglibc", "muclibc", "mbionic", M, G, U, B) + #else + #error "Unsupported DEFAULT_LIBC" + #endif /* DEFAULT_LIBC */ +@@ -149,13 +153,13 @@ see the files COPYING3 and COPYING.RUNTI + + #define LINUX_DYNAMIC_LINKER \ + CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER, UCLIBC_DYNAMIC_LINKER, \ +- BIONIC_DYNAMIC_LINKER) ++ BIONIC_DYNAMIC_LINKER, MUSL_DYNAMIC_LINKER) + #define LINUX_DYNAMIC_LINKER32 \ + CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER32, UCLIBC_DYNAMIC_LINKER32, \ +- BIONIC_DYNAMIC_LINKER32) ++ BIONIC_DYNAMIC_LINKER32, MUSL_DYNAMIC_LINKER32) + #define LINUX_DYNAMIC_LINKER64 \ + CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER64, UCLIBC_DYNAMIC_LINKER64, \ +- BIONIC_DYNAMIC_LINKER64) ++ BIONIC_DYNAMIC_LINKER64, MUSL_DYNAMIC_LINKER64) + + /* Determine whether the entire c99 runtime + is present in the runtime library. */ +--- a/gcc/config/linux.opt ++++ b/gcc/config/linux.opt +@@ -30,3 +30,7 @@ Use GNU C library + muclibc + Target Report RejectNegative Var(linux_libc,LIBC_UCLIBC) VarExists Negative(mbionic) + Use uClibc C library ++ ++mmusl ++Target Report RejectNegative Var(linux_libc,LIBC_MUSL) Negative(mglibc) ++Use musl C library +--- a/gcc/config/mips/linux.h ++++ b/gcc/config/mips/linux.h +@@ -66,6 +66,8 @@ along with GCC; see the file COPYING3. + + #define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1" + ++#define MUSL_DYNAMIC_LINKER "/lib/ld-musl-mips.so.1" ++ + /* Borrowed from sparc/linux.h */ + #undef LINK_SPEC + #define LINK_SPEC \ +--- a/gcc/config/mips/linux64.h ++++ b/gcc/config/mips/linux64.h +@@ -39,8 +39,11 @@ along with GCC; see the file COPYING3. + #define GLIBC_DYNAMIC_LINKER64 "/lib64/ld.so.1" + #define GLIBC_DYNAMIC_LINKERN32 "/lib32/ld.so.1" + #define UCLIBC_DYNAMIC_LINKERN32 "/lib32/ld-uClibc.so.0" ++#define MUSL_DYNAMIC_LINKERN32 "/lib32/ld-musl-mips.so.1" ++#define MUSL_DYNAMIC_LINKER32 "/lib32/ld-musl-mips.so.1" ++#define MUSL_DYNAMIC_LINKER64 "/lib64/ld-musl-mips.so.1" + #define LINUX_DYNAMIC_LINKERN32 \ +- CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKERN32, UCLIBC_DYNAMIC_LINKERN32) ++ CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKERN32, UCLIBC_DYNAMIC_LINKERN32, MUSL_DYNAMIC_LINKERN32) + + #undef LINK_SPEC + #define LINK_SPEC "\ +--- a/gcc/config.gcc ++++ b/gcc/config.gcc +@@ -514,7 +514,7 @@ case ${target} in + tmake_file="$tmake_file t-gnu";; + esac + # Common C libraries. +- tm_defines="$tm_defines LIBC_GLIBC=1 LIBC_UCLIBC=2 LIBC_BIONIC=3" ++ tm_defines="$tm_defines LIBC_GLIBC=1 LIBC_UCLIBC=2 LIBC_BIONIC=3 LIBC_MUSL=4" + # glibc / uclibc / bionic switch. + # uclibc and bionic aren't usable for GNU/Hurd and neither for GNU/k*BSD. + case $target in +@@ -530,6 +530,9 @@ case ${target} in + *-*-*uclibc*) + tm_defines="$tm_defines DEFAULT_LIBC=LIBC_UCLIBC" + ;; ++ *-*-*musl*) ++ tm_defines="$tm_defines DEFAULT_LIBC=LIBC_MUSL" ++ ;; + *) + tm_defines="$tm_defines DEFAULT_LIBC=LIBC_GLIBC" + ;; +--- a/gcc/ginclude/stddef.h ++++ b/gcc/ginclude/stddef.h +@@ -183,6 +183,7 @@ typedef __PTRDIFF_TYPE__ ptrdiff_t; + #ifndef _GCC_SIZE_T + #ifndef _SIZET_ + #ifndef __size_t ++#ifndef __DEFINED_size_t /* musl */ + #define __size_t__ /* BeOS */ + #define __SIZE_T__ /* Cray Unicos/Mk */ + #define _SIZE_T +@@ -199,6 +200,7 @@ typedef __PTRDIFF_TYPE__ ptrdiff_t; + #define ___int_size_t_h + #define _GCC_SIZE_T + #define _SIZET_ ++#define __DEFINED_size_t /* musl */ + #if defined (__FreeBSD__) && (__FreeBSD__ >= 5) + /* __size_t is a typedef on FreeBSD 5!, must not trash it. */ + #else +@@ -213,6 +215,7 @@ typedef __SIZE_TYPE__ size_t; + typedef long ssize_t; + #endif /* __BEOS__ */ + #endif /* !(defined (__GNUG__) && defined (size_t)) */ ++#endif /* __DEFINED_size_t */ + #endif /* __size_t */ + #endif /* _SIZET_ */ + #endif /* _GCC_SIZE_T */ +--- a/libgomp/config/posix/time.c ++++ b/libgomp/config/posix/time.c +@@ -28,6 +28,8 @@ + The following implementation uses the most simple POSIX routines. + If present, POSIX 4 clocks should be used instead. */ + ++#define _POSIX_C_SOURCE 199309L /* for clocks */ ++ + #include "libgomp.h" + #include <unistd.h> + #if TIME_WITH_SYS_TIME +--- a/libstdc++-v3/configure.host ++++ b/libstdc++-v3/configure.host +@@ -236,6 +236,13 @@ case "${host_os}" in + os_include_dir="os/bsd/freebsd" + ;; + gnu* | linux* | kfreebsd*-gnu | knetbsd*-gnu) ++ # check for musl by target ++ case "${host_os}" in ++ *-musl*) ++ os_include_dir="os/generic" ++ ;; ++ *) ++ + if [ "$uclibc" = "yes" ]; then + os_include_dir="os/uclibc" + elif [ "$bionic" = "yes" ]; then +@@ -244,6 +251,9 @@ case "${host_os}" in + os_include_dir="os/gnu-linux" + fi + ;; ++ ++ esac ++ ;; + hpux*) + os_include_dir="os/hpux" + ;; diff --git a/toolchain/gcc/patches/4.5-linaro/200-ppc_include_config_linux_h.patch b/toolchain/gcc/patches/4.5-linaro/200-ppc_include_config_linux_h.patch new file mode 100644 index 000000000..f5580356a --- /dev/null +++ b/toolchain/gcc/patches/4.5-linaro/200-ppc_include_config_linux_h.patch @@ -0,0 +1,11 @@ +--- a/gcc/config.gcc ++++ b/gcc/config.gcc +@@ -2031,7 +2031,7 @@ powerpc-*-rtems*) + tmake_file="rs6000/t-fprules rs6000/t-fprules-fpbit rs6000/t-rtems t-rtems rs6000/t-ppccomm" + ;; + powerpc-*-linux* | powerpc64-*-linux*) +- tm_file="${tm_file} dbxelf.h elfos.h linux.h freebsd-spec.h rs6000/sysv4.h" ++ tm_file="${tm_file} dbxelf.h elfos.h svr4.h linux.h freebsd-spec.h rs6000/sysv4.h" + extra_options="${extra_options} rs6000/sysv4.opt" + tmake_file="t-dfprules rs6000/t-fprules rs6000/t-ppcos ${tmake_file} rs6000/t-ppccomm" + maybe_biarch=yes diff --git a/toolchain/gcc/patches/4.5-linaro/301-missing-execinfo_h.patch b/toolchain/gcc/patches/4.5-linaro/301-missing-execinfo_h.patch new file mode 100644 index 000000000..b3f1e68d3 --- /dev/null +++ b/toolchain/gcc/patches/4.5-linaro/301-missing-execinfo_h.patch @@ -0,0 +1,11 @@ +--- a/boehm-gc/include/gc.h ++++ b/boehm-gc/include/gc.h +@@ -503,7 +503,7 @@ GC_API GC_PTR GC_malloc_atomic_ignore_of + #if defined(__linux__) || defined(__GLIBC__) + # include <features.h> + # if (__GLIBC__ == 2 && __GLIBC_MINOR__ >= 1 || __GLIBC__ > 2) \ +- && !defined(__ia64__) ++ && !defined(__ia64__) && !defined(__UCLIBC__) + # ifndef GC_HAVE_BUILTIN_BACKTRACE + # define GC_HAVE_BUILTIN_BACKTRACE + # endif diff --git a/toolchain/gcc/patches/4.5-linaro/302-c99-snprintf.patch b/toolchain/gcc/patches/4.5-linaro/302-c99-snprintf.patch new file mode 100644 index 000000000..ddbe43d81 --- /dev/null +++ b/toolchain/gcc/patches/4.5-linaro/302-c99-snprintf.patch @@ -0,0 +1,11 @@ +--- a/libstdc++-v3/include/c_global/cstdio ++++ b/libstdc++-v3/include/c_global/cstdio +@@ -139,7 +139,7 @@ _GLIBCXX_BEGIN_NAMESPACE(std) + + _GLIBCXX_END_NAMESPACE + +-#if _GLIBCXX_USE_C99 ++#if _GLIBCXX_USE_C99 || defined __UCLIBC__ + + #undef snprintf + #undef vfscanf diff --git a/toolchain/gcc/patches/4.5-linaro/305-libmudflap-susv3-legacy.patch b/toolchain/gcc/patches/4.5-linaro/305-libmudflap-susv3-legacy.patch new file mode 100644 index 000000000..8e2d15f81 --- /dev/null +++ b/toolchain/gcc/patches/4.5-linaro/305-libmudflap-susv3-legacy.patch @@ -0,0 +1,47 @@ +--- a/libmudflap/mf-hooks2.c ++++ b/libmudflap/mf-hooks2.c +@@ -421,7 +421,7 @@ WRAPPER2(void, bzero, void *s, size_t n) + { + TRACE ("%s\n", __PRETTY_FUNCTION__); + MF_VALIDATE_EXTENT(s, n, __MF_CHECK_WRITE, "bzero region"); +- bzero (s, n); ++ memset (s, 0, n); + } + + +@@ -431,7 +431,7 @@ WRAPPER2(void, bcopy, const void *src, v + TRACE ("%s\n", __PRETTY_FUNCTION__); + MF_VALIDATE_EXTENT(src, n, __MF_CHECK_READ, "bcopy src"); + MF_VALIDATE_EXTENT(dest, n, __MF_CHECK_WRITE, "bcopy dest"); +- bcopy (src, dest, n); ++ memmove (dest, src, n); + } + + +@@ -441,7 +441,7 @@ WRAPPER2(int, bcmp, const void *s1, cons + TRACE ("%s\n", __PRETTY_FUNCTION__); + MF_VALIDATE_EXTENT(s1, n, __MF_CHECK_READ, "bcmp 1st arg"); + MF_VALIDATE_EXTENT(s2, n, __MF_CHECK_READ, "bcmp 2nd arg"); +- return bcmp (s1, s2, n); ++ return n == 0 ? 0 : memcmp (s1, s2, n); + } + + +@@ -450,7 +450,7 @@ WRAPPER2(char *, index, const char *s, i + size_t n = strlen (s); + TRACE ("%s\n", __PRETTY_FUNCTION__); + MF_VALIDATE_EXTENT(s, CLAMPADD(n, 1), __MF_CHECK_READ, "index region"); +- return index (s, c); ++ return strchr (s, c); + } + + +@@ -459,7 +459,7 @@ WRAPPER2(char *, rindex, const char *s, + size_t n = strlen (s); + TRACE ("%s\n", __PRETTY_FUNCTION__); + MF_VALIDATE_EXTENT(s, CLAMPADD(n, 1), __MF_CHECK_READ, "rindex region"); +- return rindex (s, c); ++ return strrchr (s, c); + } + + /* XXX: stpcpy, memccpy */ diff --git a/toolchain/gcc/patches/4.5-linaro/810-arm-softfloat-libgcc.patch b/toolchain/gcc/patches/4.5-linaro/810-arm-softfloat-libgcc.patch new file mode 100644 index 000000000..60cfde407 --- /dev/null +++ b/toolchain/gcc/patches/4.5-linaro/810-arm-softfloat-libgcc.patch @@ -0,0 +1,26 @@ +--- a/gcc/config/arm/linux-elf.h ++++ b/gcc/config/arm/linux-elf.h +@@ -60,7 +60,7 @@ + %{shared:-lc} \ + %{!shared:%{profile:-lc_p}%{!profile:-lc}}" + +-#define LIBGCC_SPEC "%{msoft-float:-lfloat} %{mfloat-abi=soft*:-lfloat} -lgcc" ++#define LIBGCC_SPEC "-lgcc" + + #define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2" + +--- a/gcc/config/arm/t-linux ++++ b/gcc/config/arm/t-linux +@@ -23,7 +23,11 @@ TARGET_LIBGCC2_CFLAGS = -fomit-frame-poi + + LIB1ASMSRC = arm/lib1funcs.asm + LIB1ASMFUNCS = _udivsi3 _divsi3 _umodsi3 _modsi3 _dvmd_lnx _clzsi2 _clzdi2 \ +- _arm_addsubdf3 _arm_addsubsf3 ++ _arm_addsubdf3 _arm_addsubsf3 \ ++ _arm_negdf2 _arm_muldivdf3 _arm_cmpdf2 _arm_unorddf2 \ ++ _arm_fixdfsi _arm_fixunsdfsi _arm_truncdfsf2 \ ++ _arm_negsf2 _arm_muldivsf3 _arm_cmpsf2 _arm_unordsf2 \ ++ _arm_fixsfsi _arm_fixunssfsi + + # MULTILIB_OPTIONS = mhard-float/msoft-float + # MULTILIB_DIRNAMES = hard-float soft-float diff --git a/toolchain/gcc/patches/4.5-linaro/820-libgcc_pic.patch b/toolchain/gcc/patches/4.5-linaro/820-libgcc_pic.patch new file mode 100644 index 000000000..7cde82acc --- /dev/null +++ b/toolchain/gcc/patches/4.5-linaro/820-libgcc_pic.patch @@ -0,0 +1,36 @@ +--- a/libgcc/Makefile.in ++++ b/libgcc/Makefile.in +@@ -746,11 +746,12 @@ $(libgcov-objects): %$(objext): $(gcc_sr + + # Static libraries. + libgcc.a: $(libgcc-objects) ++libgcc_pic.a: $(libgcc-s-objects) + libgcov.a: $(libgcov-objects) + libunwind.a: $(libunwind-objects) + libgcc_eh.a: $(libgcc-eh-objects) + +-libgcc.a libgcov.a libunwind.a libgcc_eh.a: ++libgcc.a libgcov.a libunwind.a libgcc_eh.a libgcc_pic.a: + -rm -f $@ + + objects="$(objects)"; \ +@@ -772,7 +773,7 @@ libgcc_s$(SHLIB_EXT): libunwind$(SHLIB_E + endif + + ifeq ($(enable_shared),yes) +-all: libgcc_eh.a libgcc_s$(SHLIB_EXT) ++all: libgcc_eh.a libgcc_pic.a libgcc_s$(SHLIB_EXT) + ifneq ($(LIBUNWIND),) + all: libunwind$(SHLIB_EXT) + endif +@@ -945,6 +946,10 @@ install-shared: + chmod 644 $(DESTDIR)$(inst_libdir)/libgcc_eh.a + $(RANLIB) $(DESTDIR)$(inst_libdir)/libgcc_eh.a + ++ $(INSTALL_DATA) libgcc_pic.a $(mapfile) $(DESTDIR)$(inst_libdir)/ ++ chmod 644 $(DESTDIR)$(inst_libdir)/libgcc_pic.a ++ $(RANLIB) $(DESTDIR)$(inst_libdir)/libgcc_pic.a ++ + $(subst @multilib_dir@,$(MULTIDIR),$(subst \ + @shlib_base_name@,libgcc_s,$(subst \ + @shlib_slibdir_qual@,$(MULTIOSSUBDIR),$(SHLIB_INSTALL)))) diff --git a/toolchain/gcc/patches/4.5-linaro/830-arm_unbreak_armv4t.patch b/toolchain/gcc/patches/4.5-linaro/830-arm_unbreak_armv4t.patch new file mode 100644 index 000000000..0788b63ae --- /dev/null +++ b/toolchain/gcc/patches/4.5-linaro/830-arm_unbreak_armv4t.patch @@ -0,0 +1,13 @@ +http://sourceware.org/ml/crossgcc/2008-05/msg00009.html + +--- a/gcc/config/arm/linux-eabi.h ++++ b/gcc/config/arm/linux-eabi.h +@@ -44,7 +44,7 @@ + The ARM10TDMI core is the default for armv5t, so set + SUBTARGET_CPU_DEFAULT to achieve this. */ + #undef SUBTARGET_CPU_DEFAULT +-#define SUBTARGET_CPU_DEFAULT TARGET_CPU_arm10tdmi ++#define SUBTARGET_CPU_DEFAULT TARGET_CPU_arm9tdmi + + /* TARGET_BIG_ENDIAN_DEFAULT is set in + config.gcc for big endian configurations. */ diff --git a/toolchain/gcc/patches/4.5-linaro/840-armv4_pass_fix-v4bx_to_ld.patch b/toolchain/gcc/patches/4.5-linaro/840-armv4_pass_fix-v4bx_to_ld.patch new file mode 100644 index 000000000..97ef38590 --- /dev/null +++ b/toolchain/gcc/patches/4.5-linaro/840-armv4_pass_fix-v4bx_to_ld.patch @@ -0,0 +1,18 @@ +--- a/gcc/config/arm/linux-eabi.h ++++ b/gcc/config/arm/linux-eabi.h +@@ -67,10 +67,14 @@ + #undef MUSL_DYNAMIC_LINKER + #define MUSL_DYNAMIC_LINKER "/lib/ld-musl-arm.so.1" + ++/* For armv4 we pass --fix-v4bx to linker to support EABI */ ++#undef TARGET_FIX_V4BX_SPEC ++#define TARGET_FIX_V4BX_SPEC " %{mcpu=arm8|mcpu=arm810|mcpu=strongarm*|march=armv4:--fix-v4bx}" ++ + /* At this point, bpabi.h will have clobbered LINK_SPEC. We want to + use the GNU/Linux version, not the generic BPABI version. */ + #undef LINK_SPEC +-#define LINK_SPEC BE8_LINK_SPEC \ ++#define LINK_SPEC BE8_LINK_SPEC TARGET_FIX_V4BX_SPEC \ + LINUX_OR_ANDROID_LD (LINUX_TARGET_LINK_SPEC, \ + LINUX_TARGET_LINK_SPEC " " ANDROID_LINK_SPEC) + diff --git a/toolchain/gcc/patches/4.5-linaro/850-use_shared_libgcc.patch b/toolchain/gcc/patches/4.5-linaro/850-use_shared_libgcc.patch new file mode 100644 index 000000000..875287b93 --- /dev/null +++ b/toolchain/gcc/patches/4.5-linaro/850-use_shared_libgcc.patch @@ -0,0 +1,68 @@ +--- a/gcc/config/arm/linux-eabi.h ++++ b/gcc/config/arm/linux-eabi.h +@@ -99,10 +99,6 @@ + #define ENDFILE_SPEC \ + LINUX_OR_ANDROID_LD (LINUX_TARGET_ENDFILE_SPEC, ANDROID_ENDFILE_SPEC) + +-/* Use the default LIBGCC_SPEC, not the version in linux-elf.h, as we +- do not use -lfloat. */ +-#undef LIBGCC_SPEC +- + /* Clear the instruction cache from `beg' to `end'. This is + implemented in lib1funcs.asm, so ensure an error if this definition + is used. */ +--- a/gcc/config/arm/linux-elf.h ++++ b/gcc/config/arm/linux-elf.h +@@ -60,8 +60,6 @@ + %{shared:-lc} \ + %{!shared:%{profile:-lc_p}%{!profile:-lc}}" + +-#define LIBGCC_SPEC "-lgcc" +- + #define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2" + + #define LINUX_TARGET_LINK_SPEC "%{h*} %{version:-v} \ +--- a/gcc/config/linux.h ++++ b/gcc/config/linux.h +@@ -117,6 +117,10 @@ see the files COPYING3 and COPYING.RUNTI + #define USE_LD_AS_NEEDED 1 + #endif + ++#ifndef LIBGCC_SPEC ++#define LIBGCC_SPEC "%{static|static-libgcc:-lgcc}%{!static:%{!static-libgcc:-lgcc_s}}" ++#endif ++ + /* Determine which dynamic linker to use depending on whether GLIBC or + uClibc or Bionic is the default C library and whether + -muclibc or -mglibc or -mbionic has been passed to change the default. */ +--- a/gcc/mkmap-symver.awk ++++ b/gcc/mkmap-symver.awk +@@ -132,5 +132,5 @@ function output(lib) { + else if (inherit[lib]) + printf("} %s;\n", inherit[lib]); + else +- printf ("\n local:\n\t*;\n};\n"); ++ printf ("\n\t*;\n};\n"); + } +--- a/libgcc/Makefile.in ++++ b/libgcc/Makefile.in +@@ -265,7 +265,7 @@ ifeq ($(enable_shared),yes) + # For -fvisibility=hidden. We need both a -fvisibility=hidden on + # the command line, and a #define to prevent libgcc2.h etc from + # overriding that with #pragmas. +-vis_hide = @vis_hide@ ++vis_hide = + + ifneq (,$(vis_hide)) + +--- a/gcc/config/rs6000/linux.h ++++ b/gcc/config/rs6000/linux.h +@@ -85,6 +85,8 @@ + #define USE_LD_AS_NEEDED 1 + #endif + ++#define LIBGCC_SPEC "%{!static:%{!static-libgcc:-lgcc_s}} -lgcc" ++ + #undef TARGET_VERSION + #define TARGET_VERSION fprintf (stderr, " (PowerPC GNU/Linux)"); + diff --git a/toolchain/gcc/patches/4.5-linaro/901-lexra.patch b/toolchain/gcc/patches/4.5-linaro/901-lexra.patch new file mode 100644 index 000000000..7a6f7ba28 --- /dev/null +++ b/toolchain/gcc/patches/4.5-linaro/901-lexra.patch @@ -0,0 +1,86 @@ +Index: gcc-linaro-4.5-2011.08/gcc/config/mips/mips.c +=================================================================== +--- gcc-linaro-4.5-2011.08.orig/gcc/config/mips/mips.c ++++ gcc-linaro-4.5-2011.08/gcc/config/mips/mips.c +@@ -6575,6 +6575,8 @@ mips_block_move_straight (rtx dest, rtx + if (MEM_ALIGN (src) == BITS_PER_WORD / 2 + && MEM_ALIGN (dest) == BITS_PER_WORD / 2) + bits = BITS_PER_WORD / 2; ++ else if (TARGET_LEXRA) ++ bits = MIN (MEM_ALIGN (src), MEM_ALIGN (dest)); + else + bits = BITS_PER_WORD; + +@@ -6956,6 +6958,8 @@ mips_expand_ext_as_unaligned_load (rtx d + } + else + { ++ if (TARGET_LEXRA) ++ return false; + emit_insn (gen_mov_lwl (temp, src, left)); + emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp)); + } +@@ -6989,6 +6993,8 @@ mips_expand_ins_as_unaligned_store (rtx + } + else + { ++ if (TARGET_LEXRA) ++ return false; + emit_insn (gen_mov_swl (dest, src, left)); + emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right)); + } +Index: gcc-linaro-4.5-2011.08/gcc/config/mips/mips.md +=================================================================== +--- gcc-linaro-4.5-2011.08.orig/gcc/config/mips/mips.md ++++ gcc-linaro-4.5-2011.08/gcc/config/mips/mips.md +@@ -3756,7 +3756,7 @@ + (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m") + (match_operand:QI 2 "memory_operand" "m")] + UNSPEC_LOAD_LEFT))] +- "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])" ++ "!TARGET_MIPS16 && !TARGET_LEXRA && mips_mem_fits_mode_p (<MODE>mode, operands[1])" + "<load>l\t%0,%2" + [(set_attr "move_type" "load") + (set_attr "mode" "<MODE>")]) +@@ -3767,7 +3767,7 @@ + (match_operand:QI 2 "memory_operand" "m") + (match_operand:GPR 3 "register_operand" "0")] + UNSPEC_LOAD_RIGHT))] +- "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])" ++ "!TARGET_MIPS16 && !TARGET_LEXRA && mips_mem_fits_mode_p (<MODE>mode, operands[1])" + "<load>r\t%0,%2" + [(set_attr "move_type" "load") + (set_attr "mode" "<MODE>")]) +@@ -3777,7 +3777,7 @@ + (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ") + (match_operand:QI 2 "memory_operand" "m")] + UNSPEC_STORE_LEFT))] +- "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])" ++ "!TARGET_MIPS16 && !TARGET_LEXRA && mips_mem_fits_mode_p (<MODE>mode, operands[0])" + "<store>l\t%z1,%2" + [(set_attr "move_type" "store") + (set_attr "mode" "<MODE>")]) +@@ -3788,7 +3788,7 @@ + (match_operand:QI 2 "memory_operand" "m") + (match_dup 0)] + UNSPEC_STORE_RIGHT))] +- "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])" ++ "!TARGET_MIPS16 && !TARGET_LEXRA && mips_mem_fits_mode_p (<MODE>mode, operands[0])" + "<store>r\t%z1,%2" + [(set_attr "move_type" "store") + (set_attr "mode" "<MODE>")]) +Index: gcc-linaro-4.5-2011.08/gcc/config/mips/mips.opt +=================================================================== +--- gcc-linaro-4.5-2011.08.orig/gcc/config/mips/mips.opt ++++ gcc-linaro-4.5-2011.08/gcc/config/mips/mips.opt +@@ -244,6 +244,10 @@ mpaired-single + Target Report Mask(PAIRED_SINGLE_FLOAT) + Use paired-single floating-point instructions + ++mlexra ++Target Report Mask(LEXRA) ++Do not use lwl/lwr/swl/swr instructions absent in Lexra chips ++ + mr10k-cache-barrier= + Target Joined RejectNegative + -mr10k-cache-barrier=SETTING Specify when r10k cache barriers should be inserted diff --git a/toolchain/gcc/patches/4.5-linaro/902-rlx.patch b/toolchain/gcc/patches/4.5-linaro/902-rlx.patch new file mode 100644 index 000000000..358015bb1 --- /dev/null +++ b/toolchain/gcc/patches/4.5-linaro/902-rlx.patch @@ -0,0 +1,173 @@ +Index: gcc-linaro-4.5-2011.08/gcc/config/mips/mips.c +=================================================================== +--- gcc-linaro-4.5-2011.08.orig/gcc/config/mips/mips.c ++++ gcc-linaro-4.5-2011.08/gcc/config/mips/mips.c +@@ -669,6 +669,12 @@ static const struct mips_cpu_info mips_c + { "r3000", PROCESSOR_R3000, 1, 0 }, + { "r2000", PROCESSOR_R3000, 1, 0 }, + { "r3900", PROCESSOR_R3900, 1, 0 }, ++ { "lx4180", PROCESSOR_LX4180, 1, 0 }, ++ { "rlx4181", PROCESSOR_RLX4181, 1, 0 }, ++ { "rlx4281", PROCESSOR_RLX4281, 1, 0 }, ++ { "rlx5181", PROCESSOR_RLX5181, 1, 0 }, ++ { "lx5280", PROCESSOR_LX5280, 1, 0 }, ++ { "rlx5281", PROCESSOR_RLX5281, 1, 0 }, + + /* MIPS II processors. */ + { "r6000", PROCESSOR_R6000, 2, 0 }, +@@ -6575,7 +6581,7 @@ mips_block_move_straight (rtx dest, rtx + if (MEM_ALIGN (src) == BITS_PER_WORD / 2 + && MEM_ALIGN (dest) == BITS_PER_WORD / 2) + bits = BITS_PER_WORD / 2; +- else if (TARGET_LEXRA) ++ else if (TARGET_LEXRA || TARGET_RLX) + bits = MIN (MEM_ALIGN (src), MEM_ALIGN (dest)); + else + bits = BITS_PER_WORD; +@@ -6958,7 +6964,7 @@ mips_expand_ext_as_unaligned_load (rtx d + } + else + { +- if (TARGET_LEXRA) ++ if (TARGET_LEXRA || TARGET_RLX) + return false; + emit_insn (gen_mov_lwl (temp, src, left)); + emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp)); +@@ -6993,7 +6999,7 @@ mips_expand_ins_as_unaligned_store (rtx + } + else + { +- if (TARGET_LEXRA) ++ if (TARGET_LEXRA || TARGET_RLX) + return false; + emit_insn (gen_mov_swl (dest, src, left)); + emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right)); +@@ -15281,14 +15287,25 @@ mips_matching_cpu_name_p (const char *ca + + /* If not, try comparing based on numerical designation alone. + See if GIVEN is an unadorned number, or 'r' followed by a number. */ +- if (TOLOWER (*given) == 'r') ++ if (TOLOWER (given[0]) == 'l' && TOLOWER (given[1]) == 'x') ++ given += 2; ++ else if (TOLOWER (given[0]) == 'r' && ++ TOLOWER (given[1]) == 'l' && TOLOWER (given[2]) == 'x') ++ given += 3; ++ else if (TOLOWER (*given) == 'r') + given++; ++ + if (!ISDIGIT (*given)) + return false; + + /* Skip over some well-known prefixes in the canonical name, + hoping to find a number there too. */ +- if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') ++ if (TOLOWER (canonical[0]) == 'l' && TOLOWER (canonical[1]) == 'x') ++ canonical += 2; ++ else if (TOLOWER (canonical[0]) == 'r' && ++ TOLOWER (canonical[1]) == 'l' && TOLOWER (canonical[2]) == 'x') ++ canonical += 3; ++ else if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') + canonical += 2; + else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') + canonical += 2; +Index: gcc-linaro-4.5-2011.08/gcc/config/mips/mips.h +=================================================================== +--- gcc-linaro-4.5-2011.08.orig/gcc/config/mips/mips.h ++++ gcc-linaro-4.5-2011.08/gcc/config/mips/mips.h +@@ -58,10 +58,16 @@ enum processor_type { + PROCESSOR_R4111, + PROCESSOR_R4120, + PROCESSOR_R4130, ++ PROCESSOR_LX4180, ++ PROCESSOR_RLX4181, ++ PROCESSOR_RLX4281, + PROCESSOR_R4300, + PROCESSOR_R4600, + PROCESSOR_R4650, + PROCESSOR_R5000, ++ PROCESSOR_RLX5181, ++ PROCESSOR_LX5280, ++ PROCESSOR_RLX5281, + PROCESSOR_R5400, + PROCESSOR_R5500, + PROCESSOR_R7000, +@@ -273,6 +279,15 @@ enum mips_code_readable_setting { + #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000) + #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120) + #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130) ++#define TARGET_MIPS4180 (mips_arch == PROCESSOR_LX4180) ++#define TARGET_MIPS4181 (mips_arch == PROCESSOR_RLX4181) ++#define TARGET_MIPS4281 (mips_arch == PROCESSOR_RLX4281) ++#define TARGET_MIPS5181 (mips_arch == PROCESSOR_RLX5181) ++#define TARGET_MIPS5280 (mips_arch == PROCESSOR_LX5280) ++#define TARGET_MIPS5281 (mips_arch == PROCESSOR_RLX5281) ++#define TARGET_RLX (TARGET_MIPS4180 || TARGET_MIPS4181 || \ ++ TARGET_MIPS4281 || TARGET_MIPS4181 || \ ++ TARGET_MIPS5280 || TARGET_MIPS5281) + #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400) + #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500) + #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000) +@@ -293,12 +308,22 @@ enum mips_code_readable_setting { + || mips_tune == PROCESSOR_74KF3_2) + #define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \ + || mips_tune == PROCESSOR_LOONGSON_2F) +-#define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000) ++/* JMM fixme - guessing r3000 is good enough for now */ ++#define TUNE_MIPS3000 ((mips_tune == PROCESSOR_R3000) || TUNE_RLX) + #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900) + #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000) + #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120) + #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130) ++#define TUNE_MIPS4180 (mips_tune == PROCESSOR_LX4180) ++#define TUNE_MIPS4181 (mips_tune == PROCESSOR_RLX4181) ++#define TUNE_MIPS4281 (mips_tune == PROCESSOR_RLX4281) + #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000) ++#define TUNE_MIPS5181 (mips_tune == PROCESSOR_RLX5181) ++#define TUNE_MIPS5280 (mips_tune == PROCESSOR_LX5280) ++#define TUNE_MIPS5281 (mips_tune == PROCESSOR_RLX5281) ++#define TUNE_RLX (TUNE_MIPS4180 || TUNE_MIPS4181 || \ ++ TUNE_MIPS4281 || TUNE_MIPS4181 || \ ++ TUNE_MIPS5280 || TUNE_MIPS5281) + #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400) + #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500) + #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000) +Index: gcc-linaro-4.5-2011.08/gcc/config/mips/mips.md +=================================================================== +--- gcc-linaro-4.5-2011.08.orig/gcc/config/mips/mips.md ++++ gcc-linaro-4.5-2011.08/gcc/config/mips/mips.md +@@ -3756,7 +3756,7 @@ + (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m") + (match_operand:QI 2 "memory_operand" "m")] + UNSPEC_LOAD_LEFT))] +- "!TARGET_MIPS16 && !TARGET_LEXRA && mips_mem_fits_mode_p (<MODE>mode, operands[1])" ++ "!TARGET_MIPS16 && !TARGET_LEXRA && !TARGET_RLX && mips_mem_fits_mode_p (<MODE>mode, operands[1])" + "<load>l\t%0,%2" + [(set_attr "move_type" "load") + (set_attr "mode" "<MODE>")]) +@@ -3767,7 +3767,7 @@ + (match_operand:QI 2 "memory_operand" "m") + (match_operand:GPR 3 "register_operand" "0")] + UNSPEC_LOAD_RIGHT))] +- "!TARGET_MIPS16 && !TARGET_LEXRA && mips_mem_fits_mode_p (<MODE>mode, operands[1])" ++ "!TARGET_MIPS16 && !TARGET_LEXRA && !TARGET_RLX && mips_mem_fits_mode_p (<MODE>mode, operands[1])" + "<load>r\t%0,%2" + [(set_attr "move_type" "load") + (set_attr "mode" "<MODE>")]) +@@ -3777,7 +3777,7 @@ + (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ") + (match_operand:QI 2 "memory_operand" "m")] + UNSPEC_STORE_LEFT))] +- "!TARGET_MIPS16 && !TARGET_LEXRA && mips_mem_fits_mode_p (<MODE>mode, operands[0])" ++ "!TARGET_MIPS16 && !TARGET_LEXRA && !TARGET_RLX && mips_mem_fits_mode_p (<MODE>mode, operands[0])" + "<store>l\t%z1,%2" + [(set_attr "move_type" "store") + (set_attr "mode" "<MODE>")]) +@@ -3788,7 +3788,7 @@ + (match_operand:QI 2 "memory_operand" "m") + (match_dup 0)] + UNSPEC_STORE_RIGHT))] +- "!TARGET_MIPS16 && !TARGET_LEXRA && mips_mem_fits_mode_p (<MODE>mode, operands[0])" ++ "!TARGET_MIPS16 && !TARGET_LEXRA && !TARGET_RLX && mips_mem_fits_mode_p (<MODE>mode, operands[0])" + "<store>r\t%z1,%2" + [(set_attr "move_type" "store") + (set_attr "mode" "<MODE>")]) diff --git a/toolchain/gcc/patches/4.5-linaro/910-mbsd_multi.patch b/toolchain/gcc/patches/4.5-linaro/910-mbsd_multi.patch new file mode 100644 index 000000000..b9d5ffa24 --- /dev/null +++ b/toolchain/gcc/patches/4.5-linaro/910-mbsd_multi.patch @@ -0,0 +1,253 @@ + + This patch brings over a few features from MirBSD: + * -fhonour-copts + If this option is not given, it's warned (depending + on environment variables). This is to catch errors + of misbuilt packages which override CFLAGS themselves. + * -Werror-maybe-reset + Has the effect of -Wno-error if GCC_NO_WERROR is + set and not '0', a no-operation otherwise. This is + to be able to use -Werror in "make" but prevent + GNU autoconf generated configure scripts from + freaking out. + * Make -fno-strict-aliasing and -fno-delete-null-pointer-checks + the default for -O2/-Os, because they trigger gcc bugs + and can delete code with security implications. + + This patch was authored by Thorsten Glaser <tg at mirbsd.de> + with copyright assignment to the FSF in effect. + +--- a/gcc/c-opts.c ++++ b/gcc/c-opts.c +@@ -106,6 +106,9 @@ static size_t deferred_count; + /* Number of deferred options scanned for -include. */ + static size_t include_cursor; + ++/* Check if a port honours COPTS. */ ++static int honour_copts = 0; ++ + static void set_Wimplicit (int); + static void handle_OPT_d (const char *); + static void set_std_cxx98 (int); +@@ -472,6 +475,9 @@ c_common_handle_option (size_t scode, co + enable_warning_as_error ("implicit-function-declaration", value, CL_C | CL_ObjC); + break; + ++ case OPT_Werror_maybe_reset: ++ break; ++ + case OPT_Wformat: + set_Wformat (value); + break; +@@ -704,6 +710,12 @@ c_common_handle_option (size_t scode, co + flag_exceptions = value; + break; + ++ case OPT_fhonour_copts: ++ if (c_language == clk_c) { ++ honour_copts++; ++ } ++ break; ++ + case OPT_fimplement_inlines: + flag_implement_inlines = value; + break; +@@ -1240,6 +1252,47 @@ c_common_init (void) + return false; + } + ++ if (c_language == clk_c) { ++ char *ev = getenv ("GCC_HONOUR_COPTS"); ++ int evv; ++ if (ev == NULL) ++ evv = -1; ++ else if ((*ev == '0') || (*ev == '\0')) ++ evv = 0; ++ else if (*ev == '1') ++ evv = 1; ++ else if (*ev == '2') ++ evv = 2; ++ else if (*ev == 's') ++ evv = -1; ++ else { ++ warning (0, "unknown GCC_HONOUR_COPTS value, assuming 1"); ++ evv = 1; /* maybe depend this on something like MIRBSD_NATIVE? */ ++ } ++ if (evv == 1) { ++ if (honour_copts == 0) { ++ error ("someone does not honour COPTS at all in lenient mode"); ++ return false; ++ } else if (honour_copts != 1) { ++ warning (0, "someone does not honour COPTS correctly, passed %d times", ++ honour_copts); ++ } ++ } else if (evv == 2) { ++ if (honour_copts == 0) { ++ error ("someone does not honour COPTS at all in strict mode"); ++ return false; ++ } else if (honour_copts != 1) { ++ error ("someone does not honour COPTS correctly, passed %d times", ++ honour_copts); ++ return false; ++ } ++ } else if (evv == 0) { ++ if (honour_copts != 1) ++ inform (0, "someone does not honour COPTS correctly, passed %d times", ++ honour_copts); ++ } ++ } ++ + return true; + } + +--- a/gcc/c.opt ++++ b/gcc/c.opt +@@ -219,6 +219,10 @@ Werror-implicit-function-declaration + C ObjC RejectNegative Warning + This switch is deprecated; use -Werror=implicit-function-declaration instead + ++Werror-maybe-reset ++C ObjC C++ ObjC++ ++; Documented in common.opt ++ + Wfloat-equal + C ObjC C++ ObjC++ Var(warn_float_equal) Warning + Warn if testing floating point numbers for equality +@@ -637,6 +641,9 @@ C++ ObjC++ Optimization + fhonor-std + C++ ObjC++ + ++fhonour-copts ++C ObjC C++ ObjC++ RejectNegative ++ + fhosted + C ObjC + Assume normal C execution environment +--- a/gcc/common.opt ++++ b/gcc/common.opt +@@ -105,6 +105,10 @@ Werror= + Common Joined + Treat specified warning as error + ++Werror-maybe-reset ++Common ++If environment variable GCC_NO_WERROR is set, act as -Wno-error ++ + Wextra + Common Var(extra_warnings) Warning + Print extra (possibly unwanted) warnings +@@ -625,6 +629,9 @@ fguess-branch-probability + Common Report Var(flag_guess_branch_prob) Optimization + Enable guessing of branch probabilities + ++fhonour-copts ++Common RejectNegative ++ + ; Nonzero means ignore `#ident' directives. 0 means handle them. + ; Generate position-independent code for executables if possible + ; On SVR4 targets, it also controls whether or not to emit a +--- a/gcc/opts.c ++++ b/gcc/opts.c +@@ -897,8 +897,6 @@ decode_options (unsigned int argc, const + flag_schedule_insns_after_reload = opt2; + #endif + flag_regmove = opt2; +- flag_strict_aliasing = opt2; +- flag_strict_overflow = opt2; + flag_reorder_blocks = opt2; + flag_reorder_functions = opt2; + flag_tree_vrp = opt2; +@@ -920,6 +918,8 @@ decode_options (unsigned int argc, const + + /* -O3 optimizations. */ + opt3 = (optimize >= 3); ++ flag_strict_aliasing = opt3; ++ flag_strict_overflow = opt3; + flag_predictive_commoning = opt3; + flag_inline_functions = opt3; + flag_unswitch_loops = opt3; +@@ -1648,6 +1648,17 @@ common_handle_option (size_t scode, cons + enable_warning_as_error (arg, value, lang_mask); + break; + ++ case OPT_Werror_maybe_reset: ++ { ++ char *ev = getenv ("GCC_NO_WERROR"); ++ if ((ev != NULL) && (*ev != '0')) ++ warnings_are_errors = 0; ++ } ++ break; ++ ++ case OPT_fhonour_copts: ++ break; ++ + case OPT_Wlarger_than_: + /* This form corresponds to -Wlarger-than-. + Kept for backward compatibility. +--- a/gcc/doc/cppopts.texi ++++ b/gcc/doc/cppopts.texi +@@ -164,6 +164,11 @@ in older programs. This warning is on b + Make all warnings into hard errors. Source code which triggers warnings + will be rejected. + ++ at item -Werror-maybe-reset ++ at opindex Werror-maybe-reset ++Act like @samp{-Wno-error} if the @env{GCC_NO_WERROR} environment ++variable is set to anything other than 0 or empty. ++ + @item -Wsystem-headers + @opindex Wsystem-headers + Issue warnings for code in system headers. These are normally unhelpful +--- a/gcc/doc/invoke.texi ++++ b/gcc/doc/invoke.texi +@@ -235,7 +235,7 @@ Objective-C and Objective-C++ Dialects}. + -Wconversion -Wcoverage-mismatch -Wno-deprecated @gol + -Wno-deprecated-declarations -Wdisabled-optimization @gol + -Wno-div-by-zero -Wdouble-promotion -Wempty-body -Wenum-compare @gol +--Wno-endif-labels -Werror -Werror=* @gol ++-Wno-endif-labels -Werror -Werror=* -Werror-maybe-reset @gol + -Wfatal-errors -Wfloat-equal -Wformat -Wformat=2 @gol + -Wno-format-contains-nul -Wno-format-extra-args -Wformat-nonliteral @gol + -Wformat-security -Wformat-y2k @gol +@@ -4360,6 +4360,22 @@ This option is only supported for C and + @option{-Wall} and by @option{-pedantic}, which can be disabled with + @option{-Wno-pointer-sign}. + ++ at item -Werror-maybe-reset ++ at opindex Werror-maybe-reset ++Act like @samp{-Wno-error} if the @env{GCC_NO_WERROR} environment ++variable is set to anything other than 0 or empty. ++ ++ at item -fhonour-copts ++ at opindex fhonour-copts ++If @env{GCC_HONOUR_COPTS} is set to 1, abort if this option is not ++given at least once, and warn if it is given more than once. ++If @env{GCC_HONOUR_COPTS} is set to 2, abort if this option is not ++given exactly once. ++If @env{GCC_HONOUR_COPTS} is set to 0 or unset, warn if this option ++is not given exactly once. ++The warning is quelled if @env{GCC_HONOUR_COPTS} is set to @samp{s}. ++This flag and environment variable only affect the C language. ++ + @item -Wstack-protector + @opindex Wstack-protector + @opindex Wno-stack-protector +@@ -6114,7 +6130,7 @@ so, the first branch is redirected to ei + second branch or a point immediately following it, depending on whether + the condition is known to be true or false. + +-Enabled at levels @option{-O2}, @option{-O3}, @option{-Os}. ++Enabled at levels @option{-O3}. + + @item -fsplit-wide-types + @opindex fsplit-wide-types +--- a/gcc/java/jvspec.c ++++ b/gcc/java/jvspec.c +@@ -667,6 +667,7 @@ lang_specific_pre_link (void) + class name. Append dummy `.c' that can be stripped by set_input so %b + is correct. */ + set_input (concat (main_class_name, "main.c", NULL)); ++ putenv ("GCC_HONOUR_COPTS=s"); /* XXX hack! */ + err = do_spec (jvgenmain_spec); + if (err == 0) + { diff --git a/toolchain/gcc/patches/4.5-linaro/920-specs_nonfatal_getenv.patch b/toolchain/gcc/patches/4.5-linaro/920-specs_nonfatal_getenv.patch new file mode 100644 index 000000000..001088a25 --- /dev/null +++ b/toolchain/gcc/patches/4.5-linaro/920-specs_nonfatal_getenv.patch @@ -0,0 +1,14 @@ +--- a/gcc/gcc.c ++++ b/gcc/gcc.c +@@ -8583,7 +8583,10 @@ getenv_spec_function (int argc, const ch + + value = getenv (argv[0]); + if (!value) +- fatal ("environment variable \"%s\" not defined", argv[0]); ++ { ++ error ("warning: environment variable \"%s\" not defined", argv[0]); ++ value = ""; ++ } + + /* We have to escape every character of the environment variable so + they are not interpreted as active spec characters. A diff --git a/toolchain/gcc/patches/4.5-linaro/993-arm_insn-opinit-RTX_CODE-fixup.patch b/toolchain/gcc/patches/4.5-linaro/993-arm_insn-opinit-RTX_CODE-fixup.patch new file mode 100644 index 000000000..57feb328f --- /dev/null +++ b/toolchain/gcc/patches/4.5-linaro/993-arm_insn-opinit-RTX_CODE-fixup.patch @@ -0,0 +1,14 @@ +--- a/gcc/config/arm/arm-protos.h ++++ b/gcc/config/arm/arm-protos.h +@@ -44,10 +44,10 @@ extern unsigned int arm_dbx_register_num + extern void arm_output_fn_unwind (FILE *, bool); + + +-#ifdef RTX_CODE + extern bool arm_vector_mode_supported_p (enum machine_mode); + extern int arm_hard_regno_mode_ok (unsigned int, enum machine_mode); + extern int const_ok_for_arm (HOST_WIDE_INT); ++#ifdef RTX_CODE + extern int arm_split_constant (RTX_CODE, enum machine_mode, rtx, + HOST_WIDE_INT, rtx, rtx, int); + extern RTX_CODE arm_canonicalize_comparison (RTX_CODE, rtx *, rtx *); diff --git a/toolchain/gcc/patches/4.5-linaro/995-fa526.patch b/toolchain/gcc/patches/4.5-linaro/995-fa526.patch new file mode 100644 index 000000000..700bb4a90 --- /dev/null +++ b/toolchain/gcc/patches/4.5-linaro/995-fa526.patch @@ -0,0 +1,257 @@ +--- a/gcc/config/arm/arm-cores.def ++++ b/gcc/config/arm/arm-cores.def +@@ -74,6 +74,7 @@ ARM_CORE("strongarm", strongarm, 4, + ARM_CORE("strongarm110", strongarm110, 4, FL_MODE26 | FL_LDSCHED | FL_STRONG, fastmul) + ARM_CORE("strongarm1100", strongarm1100, 4, FL_MODE26 | FL_LDSCHED | FL_STRONG, fastmul) + ARM_CORE("strongarm1110", strongarm1110, 4, FL_MODE26 | FL_LDSCHED | FL_STRONG, fastmul) ++ARM_CORE("fa526", fa526, 4, FL_LDSCHED, fastmul) + + /* V4T Architecture Processors */ + ARM_CORE("arm7tdmi", arm7tdmi, 4T, FL_CO_PROC , fastmul) +--- a/gcc/config/arm/arm.md ++++ b/gcc/config/arm/arm.md +@@ -435,7 +435,7 @@ + + (define_attr "generic_sched" "yes,no" + (const (if_then_else +- (ior (eq_attr "tune" "arm926ejs,arm1020e,arm1026ejs,arm1136js,arm1136jfs,cortexa5,cortexa8,cortexa9,cortexm4") ++ (ior (eq_attr "tune" "fa526,arm926ejs,arm1020e,arm1026ejs,arm1136js,arm1136jfs,cortexa5,cortexa8,cortexa9,cortexm4") + (eq_attr "tune_cortexr4" "yes")) + (const_string "no") + (const_string "yes")))) +@@ -467,6 +467,7 @@ + (include "arm1020e.md") + (include "arm1026ejs.md") + (include "arm1136jfs.md") ++(include "fa526.md") + (include "cortex-a5.md") + (include "cortex-a8.md") + (include "cortex-a9.md") +--- a/gcc/config/arm/arm-tune.md ++++ b/gcc/config/arm/arm-tune.md +@@ -1,5 +1,5 @@ + ;; -*- buffer-read-only: t -*- + ;; Generated automatically by gentune.sh from arm-cores.def + (define_attr "tune" +- "arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,arm1156t2fs,cortexa5,cortexa8,cortexa9,cortexr4,cortexr4f,cortexm4,cortexm3,cortexm1,cortexm0" ++ "arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,fa526,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,arm1156t2fs,cortexa5,cortexa8,cortexa9,cortexr4,cortexr4f,cortexm4,cortexm3,cortexm1,cortexm0" + (const (symbol_ref "((enum attr_tune) arm_tune)"))) +--- a/gcc/config/arm/bpabi.h ++++ b/gcc/config/arm/bpabi.h +@@ -52,7 +52,8 @@ + /* The BPABI integer comparison routines return { -1, 0, 1 }. */ + #define TARGET_LIB_INT_CMP_BIASED !TARGET_BPABI + +-#define TARGET_FIX_V4BX_SPEC " %{mcpu=arm8|mcpu=arm810|mcpu=strongarm*|march=armv4:--fix-v4bx}" ++#define TARGET_FIX_V4BX_SPEC " %{mcpu=arm8|mcpu=arm810|mcpu=strongarm*\ ++|march=armv4|mcpu=fa526:--fix-v4bx}" + + #define BE8_LINK_SPEC " %{mbig-endian:%{march=armv7-a|mcpu=cortex-a5|mcpu=cortex-a8|mcpu=cortex-a9:%{!r:--be8}}}" + +--- /dev/null ++++ b/gcc/config/arm/fa526.md +@@ -0,0 +1,161 @@ ++;; Faraday FA526 Pipeline Description ++;; Copyright (C) 2010 Free Software Foundation, Inc. ++;; Written by I-Jui Sung, based on ARM926EJ-S Pipeline Description. ++ ++;; This file is part of GCC. ++;; ++;; GCC is free software; you can redistribute it and/or modify it under ++;; the terms of the GNU General Public License as published by the Free ++;; Software Foundation; either version 3, or (at your option) any later ++;; version. ++;; ++;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY ++;; WARRANTY; without even the implied warranty of MERCHANTABILITY or ++;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++;; for more details. ++;; ++;; You should have received a copy of the GNU General Public License ++;; along with GCC; see the file COPYING3. If not see ++;; <http://www.gnu.org/licenses/>. */ ++ ++;; These descriptions are based on the information contained in the ++;; FA526 Core Design Note, Copyright (c) 2010 Faraday Technology Corp. ++;; ++;; Modeled pipeline characteristics: ++;; LD -> any use: latency = 3 (2 cycle penalty). ++;; ALU -> any use: latency = 2 (1 cycle penalty). ++ ++;; This automaton provides a pipeline description for the Faraday ++;; FA526 core. ++;; ++;; The model given here assumes that the condition for all conditional ++;; instructions is "true", i.e., that all of the instructions are ++;; actually executed. ++ ++(define_automaton "fa526") ++ ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;; Pipelines ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++ ++;; There is a single pipeline ++;; ++;; The ALU pipeline has fetch, decode, execute, memory, and ++;; write stages. We only need to model the execute, memory and write ++;; stages. ++ ++;; S E M W ++ ++(define_cpu_unit "fa526_core" "fa526") ++ ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;; ALU Instructions ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++ ++;; ALU instructions require two cycles to execute, and use the ALU ++;; pipeline in each of the three stages. The results are available ++;; after the execute stage stage has finished. ++;; ++;; If the destination register is the PC, the pipelines are stalled ++;; for several cycles. That case is not modeled here. ++ ++;; ALU operations ++(define_insn_reservation "526_alu_op" 1 ++ (and (eq_attr "tune" "fa526") ++ (eq_attr "type" "alu")) ++ "fa526_core") ++ ++(define_insn_reservation "526_alu_shift_op" 2 ++ (and (eq_attr "tune" "fa526") ++ (eq_attr "type" "alu_shift,alu_shift_reg")) ++ "fa526_core") ++ ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;; Multiplication Instructions ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++ ++(define_insn_reservation "526_mult1" 2 ++ (and (eq_attr "tune" "fa526") ++ (eq_attr "insn" "smlalxy,smulxy,smlaxy,smlalxy")) ++ "fa526_core") ++ ++(define_insn_reservation "526_mult2" 5 ++ (and (eq_attr "tune" "fa526") ++ (eq_attr "insn" "mul,mla,muls,mlas,umull,umlal,smull,smlal,umulls,\ ++ umlals,smulls,smlals,smlawx")) ++ "fa526_core*4") ++ ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;; Load/Store Instructions ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++ ++;; The models for load/store instructions do not accurately describe ++;; the difference between operations with a base register writeback ++;; (such as "ldm!"). These models assume that all memory references ++;; hit in dcache. ++ ++(define_insn_reservation "526_load1_op" 3 ++ (and (eq_attr "tune" "fa526") ++ (eq_attr "type" "load1,load_byte")) ++ "fa526_core") ++ ++(define_insn_reservation "526_load2_op" 4 ++ (and (eq_attr "tune" "fa526") ++ (eq_attr "type" "load2")) ++ "fa526_core*2") ++ ++(define_insn_reservation "526_load3_op" 5 ++ (and (eq_attr "tune" "fa526") ++ (eq_attr "type" "load3")) ++ "fa526_core*3") ++ ++(define_insn_reservation "526_load4_op" 6 ++ (and (eq_attr "tune" "fa526") ++ (eq_attr "type" "load4")) ++ "fa526_core*4") ++ ++(define_insn_reservation "526_store1_op" 0 ++ (and (eq_attr "tune" "fa526") ++ (eq_attr "type" "store1")) ++ "fa526_core") ++ ++(define_insn_reservation "526_store2_op" 1 ++ (and (eq_attr "tune" "fa526") ++ (eq_attr "type" "store2")) ++ "fa526_core*2") ++ ++(define_insn_reservation "526_store3_op" 2 ++ (and (eq_attr "tune" "fa526") ++ (eq_attr "type" "store3")) ++ "fa526_core*3") ++ ++(define_insn_reservation "526_store4_op" 3 ++ (and (eq_attr "tune" "fa526") ++ (eq_attr "type" "store4")) ++ "fa526_core*4") ++ ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;; Branch and Call Instructions ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++ ++;; Branch instructions are difficult to model accurately. The FA526 ++;; core can predict most branches. If the branch is predicted ++;; correctly, and predicted early enough, the branch can be completely ++;; eliminated from the instruction stream. Some branches can ++;; therefore appear to require zero cycle to execute. We assume that ++;; all branches are predicted correctly, and that the latency is ++;; therefore the minimum value. ++ ++(define_insn_reservation "526_branch_op" 0 ++ (and (eq_attr "tune" "fa526") ++ (eq_attr "type" "branch")) ++ "fa526_core") ++ ++;; The latency for a call is actually the latency when the result is available. ++;; i.e. R0 ready for int return value. For most cases, the return value is set ++;; by a mov instruction, which has 1 cycle latency. ++(define_insn_reservation "526_call_op" 1 ++ (and (eq_attr "tune" "fa526") ++ (eq_attr "type" "call")) ++ "fa526_core") ++ +--- a/gcc/config/arm/t-arm ++++ b/gcc/config/arm/t-arm +@@ -23,6 +23,7 @@ MD_INCLUDES= $(srcdir)/config/arm/arm-tu + $(srcdir)/config/arm/arm-generic.md \ + $(srcdir)/config/arm/arm1020e.md \ + $(srcdir)/config/arm/arm1026ejs.md \ ++ $(srcdir)/config/arm/fa526.md \ + $(srcdir)/config/arm/arm1136jfs.md \ + $(srcdir)/config/arm/arm926ejs.md \ + $(srcdir)/config/arm/cirrus.md \ +--- a/gcc/config/arm/t-arm-elf ++++ b/gcc/config/arm/t-arm-elf +@@ -36,6 +36,10 @@ MULTILIB_DIRNAMES = arm thumb + MULTILIB_EXCEPTIONS = + MULTILIB_MATCHES = + ++#MULTILIB_OPTIONS += mcpu=fa526 ++#MULTILIB_DIRNAMES += fa526 ++#MULTILIB_EXCEPTIONS += *mthumb*/*mcpu=fa526 ++ + #MULTILIB_OPTIONS += march=armv7 + #MULTILIB_DIRNAMES += thumb2 + #MULTILIB_EXCEPTIONS += march=armv7* marm/*march=armv7* +@@ -52,6 +56,7 @@ MULTILIB_MATCHES = + MULTILIB_OPTIONS += mfloat-abi=hard + MULTILIB_DIRNAMES += fpu + MULTILIB_EXCEPTIONS += *mthumb/*mfloat-abi=hard* ++MULTILIB_EXCEPTIONS += *mcpu=fa526/*mfloat-abi=hard* + + # MULTILIB_OPTIONS += mcpu=ep9312 + # MULTILIB_DIRNAMES += ep9312 +--- a/gcc/doc/invoke.texi ++++ b/gcc/doc/invoke.texi +@@ -9923,7 +9923,8 @@ assembly code. Permissible names are: @ + @samp{cortex-r4}, @samp{cortex-r4f}, @samp{cortex-m4}, @samp{cortex-m3}, + @samp{cortex-m1}, + @samp{cortex-m0}, +-@samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}. ++@samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}, ++@samp{fa526}. + + @item -mtune=@var{name} + @opindex mtune diff --git a/toolchain/gcc/patches/4.5-linaro/999-coldfire.patch b/toolchain/gcc/patches/4.5-linaro/999-coldfire.patch new file mode 100644 index 000000000..fabb8ef3a --- /dev/null +++ b/toolchain/gcc/patches/4.5-linaro/999-coldfire.patch @@ -0,0 +1,10 @@ +--- a/gcc/config.gcc ++++ b/gcc/config.gcc +@@ -1693,6 +1693,7 @@ m68k-*-linux*) # Motorola m68k's runnin + if test x$sjlj != x1; then + tmake_file="$tmake_file m68k/t-slibgcc-elf-ver" + fi ++ tmake_file="m68k/t-floatlib m68k/t-m68kbare m68k/t-m68kelf" + ;; + m68k-*-rtems*) + default_m68k_cpu=68020 |