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-rw-r--r--toolchain/uClibc/common.mk1
-rw-r--r--toolchain/uClibc/config-0.9.33.2/lexra17
-rw-r--r--toolchain/uClibc/patches-0.9.33.2/999-lexra.patch76
3 files changed, 94 insertions, 0 deletions
diff --git a/toolchain/uClibc/common.mk b/toolchain/uClibc/common.mk
index 5f3bd2944..2d3a81ac5 100644
--- a/toolchain/uClibc/common.mk
+++ b/toolchain/uClibc/common.mk
@@ -33,6 +33,7 @@ UCLIBC_TARGET_ARCH:=$(shell echo $(ARCH) | sed -e s'/-.*//' \
-e 's/sh64/sh/' \
-e 's/sh[234].*/sh/' \
-e 's/mips.*/mips/' \
+ -e 's/lexra/mips/' \
-e 's/mipsel.*/mips/' \
-e 's/cris.*/cris/' \
)
diff --git a/toolchain/uClibc/config-0.9.33.2/lexra b/toolchain/uClibc/config-0.9.33.2/lexra
new file mode 100644
index 000000000..e369c2628
--- /dev/null
+++ b/toolchain/uClibc/config-0.9.33.2/lexra
@@ -0,0 +1,17 @@
+ARCH_ANY_ENDIAN=y
+ARCH_BIG_ENDIAN=y
+ARCH_CFLAGS="-mno-split-addresses"
+ARCH_WANTS_BIG_ENDIAN=y
+CONFIG_MIPS_ISA_1=y
+# CONFIG_MIPS_ISA_2 is not set
+# CONFIG_MIPS_ISA_3 is not set
+# CONFIG_MIPS_ISA_4 is not set
+# CONFIG_MIPS_ISA_MIPS32 is not set
+# CONFIG_MIPS_ISA_MIPS32R2 is not set
+# CONFIG_MIPS_ISA_MIPS64 is not set
+# CONFIG_MIPS_N32_ABI is not set
+# CONFIG_MIPS_N64_ABI is not set
+CONFIG_MIPS_O32_ABI=y
+TARGET_ARCH="mips"
+TARGET_mips=y
+# UCLIBC_HAS_FPU is not set
diff --git a/toolchain/uClibc/patches-0.9.33.2/999-lexra.patch b/toolchain/uClibc/patches-0.9.33.2/999-lexra.patch
new file mode 100644
index 000000000..aff55abe6
--- /dev/null
+++ b/toolchain/uClibc/patches-0.9.33.2/999-lexra.patch
@@ -0,0 +1,76 @@
+Index: uClibc/libc/string/mips/memcpy.S
+===================================================================
+--- uClibc.orig/libc/string/mips/memcpy.S
++++ uClibc/libc/string/mips/memcpy.S
+@@ -167,10 +167,19 @@ ENTRY (memcpy)
+ andi t1, 0x3 # a0/a1 are aligned, but are we
+ beq t1, zero, L(chk8w) # starting in the middle of a word?
+ subu a2, t1
++#if 0
+ LWHI t0, 0(a1) # Yes we are... take care of that
+ addu a1, t1
+ SWHI t0, 0(a0)
+ addu a0, t1
++#else
++4: lbu t2, 0(a1)
++ subu t1, 1
++ sb t2, 0(a0)
++ addiu a1, 1
++ bnez t1, 4b
++ addiu a0, 1
++#endif
+
+ L(chk8w):
+ andi t0, a2, 0x1f # 32 or more bytes left?
+@@ -225,6 +234,7 @@ L(lst8e):
+ jr ra # Bye, bye
+ nop
+
++#if 0
+ L(shift):
+ subu a3, zero, a0 # Src and Dest unaligned
+ andi a3, 0x3 # (unoptimized case...)
+@@ -248,6 +258,23 @@ L(shfth):
+ sw t1, -4(a0)
+ b L(last8) # Handle anything which may be left
+ move a2, t0
++#else
++L(shift):
++ beqz a2, L(done)
++ nop
++
++L(copy_bytes):
++ lbu t0, 0(a1)
++ subu a2, a2, 1
++ sb t0, 0(a0)
++ addiu a1, a1, 1
++ bnez a2, L(copy_bytes)
++ addiu a0, a0, 1
++
++L(done):
++ jr ra
++ nop
++#endif
+
+ .set reorder
+ END (memcpy)
+Index: uClibc/libc/string/mips/memset.S
+===================================================================
+--- uClibc.orig/libc/string/mips/memset.S
++++ uClibc/libc/string/mips/memset.S
+@@ -118,8 +118,15 @@ L(ueven):
+ andi t0, 0x3
+ beq t0, zero, L(chkw)
+ subu a2, t0
++#if 0
+ SWHI a1, 0(a0) # Yes, handle first unaligned part
+ addu a0, t0 # Now both a0 and a2 are updated
++#else
++ addu t1, a0, t0
++4: addiu a0, 1
++ bne t1, a0, 4b
++ sb a1, -1(a0)
++#endif
+
+ L(chkw):
+ andi t0, a2, 0x7 # Enough left for one loop iteration?