diff options
Diffstat (limited to 'target')
| -rw-r--r-- | target/linux/brcm47xx/base-files/lib/preinit/05_init_interfaces_brcm | 1 | ||||
| -rw-r--r-- | target/linux/brcm47xx/modules.mk | 15 | ||||
| -rw-r--r-- | target/linux/brcm47xx/patches-3.6/750-bgmac.patch | 1680 | ||||
| -rw-r--r-- | target/linux/generic/config-3.6 | 1 | ||||
| -rw-r--r-- | target/linux/generic/config-3.7 | 1 |
5 files changed, 1698 insertions, 0 deletions
diff --git a/target/linux/brcm47xx/base-files/lib/preinit/05_init_interfaces_brcm b/target/linux/brcm47xx/base-files/lib/preinit/05_init_interfaces_brcm index d4a3b682c..dca36b711 100644 --- a/target/linux/brcm47xx/base-files/lib/preinit/05_init_interfaces_brcm +++ b/target/linux/brcm47xx/base-files/lib/preinit/05_init_interfaces_brcm @@ -7,6 +7,7 @@ set_preinit_iface() { insmod hwmon insmod tg3 insmod b44 + insmod bgmac # hardware specific overrides case "$(cat /proc/diag/model)" in diff --git a/target/linux/brcm47xx/modules.mk b/target/linux/brcm47xx/modules.mk index abc2c9c00..2ea637df0 100644 --- a/target/linux/brcm47xx/modules.mk +++ b/target/linux/brcm47xx/modules.mk @@ -36,3 +36,18 @@ define KernelPackage/ocf-ubsec-ssb/description endef $(eval $(call KernelPackage,ocf-ubsec-ssb)) + +define KernelPackage/bgmac + TITLE:=Broadcom bgmac driver + KCONFIG:=CONFIG_BGMAC + DEPENDS:=@TARGET_brcm47xx + SUBMENU:=$(NETWORK_DEVICES_MENU) + FILES:=$(LINUX_DIR)/drivers/net/ethernet/broadcom/bgmac.ko + AUTOLOAD:=$(call AutoLoad,50,bgmac) +endef + +define KernelPackage/bgmac/description + Kernel modules for Broadcom bgmac Ethernet adapters. +endef + +$(eval $(call KernelPackage,bgmac)) diff --git a/target/linux/brcm47xx/patches-3.6/750-bgmac.patch b/target/linux/brcm47xx/patches-3.6/750-bgmac.patch new file mode 100644 index 000000000..13698dbf7 --- /dev/null +++ b/target/linux/brcm47xx/patches-3.6/750-bgmac.patch @@ -0,0 +1,1680 @@ +--- a/drivers/bcma/driver_chipcommon_pmu.c ++++ b/drivers/bcma/driver_chipcommon_pmu.c +@@ -263,7 +263,7 @@ static u32 bcma_pmu_pll_clock_bcm4706(st + } + + /* query bus clock frequency for PMU-enabled chipcommon */ +-static u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc) ++u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc) + { + struct bcma_bus *bus = cc->core->bus; + +@@ -292,6 +292,7 @@ static u32 bcma_pmu_get_bus_clock(struct + } + return BCMA_CC_PMU_HT_CLOCK; + } ++EXPORT_SYMBOL_GPL(bcma_pmu_get_bus_clock); + + /* query cpu clock frequency for PMU-enabled chipcommon */ + u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc) +--- a/drivers/net/ethernet/broadcom/Kconfig ++++ b/drivers/net/ethernet/broadcom/Kconfig +@@ -120,4 +120,10 @@ config BNX2X + To compile this driver as a module, choose M here: the module + will be called bnx2x. This is recommended. + ++config BGMAC ++ tristate "Broadcom Gigabit driver" ++ depends on BCMA ++ ---help--- ++ This driver supports Broadcom Gigabit core found in some BCM47xx SoCs. ++ + endif # NET_VENDOR_BROADCOM +--- a/drivers/net/ethernet/broadcom/Makefile ++++ b/drivers/net/ethernet/broadcom/Makefile +@@ -9,3 +9,4 @@ obj-$(CONFIG_CNIC) += cnic.o + obj-$(CONFIG_BNX2X) += bnx2x/ + obj-$(CONFIG_SB1250_MAC) += sb1250-mac.o + obj-$(CONFIG_TIGON3) += tg3.o ++obj-$(CONFIG_BGMAC) += bgmac.o +--- /dev/null ++++ b/drivers/net/ethernet/broadcom/bgmac.c +@@ -0,0 +1,1202 @@ ++#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt ++ ++#define bgmac_err(bgmac, fmt, ...) \ ++ pr_err("u%d: " fmt, (bgmac)->core->core_unit, ##__VA_ARGS__) ++#define bgmac_warn(bgmac, fmt, ...) \ ++ pr_warn("u%d: " fmt, (bgmac)->core->core_unit, ##__VA_ARGS__) ++#define bgmac_info(bgmac, fmt, ...) \ ++ pr_info("u%d: " fmt, (bgmac)->core->core_unit, ##__VA_ARGS__) ++#define bgmac_debug(bgmac, fmt, ...) \ ++ pr_debug("u%d: " fmt, (bgmac)->core->core_unit, ##__VA_ARGS__) ++ ++#include <linux/kernel.h> ++#include <linux/module.h> ++#include <linux/delay.h> ++#include <linux/etherdevice.h> ++#include <linux/mii.h> ++#include <linux/interrupt.h> ++#include <linux/dma-mapping.h> ++#include <bcm47xx_nvram.h> ++ ++#include "bgmac.h" ++ ++#define ETHER_MAX_LEN 1518 ++ ++MODULE_LICENSE("GPL"); ++ ++static const struct bcma_device_id bgmac_bcma_tbl[] = { ++ BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_4706_MAC_GBIT, BCMA_ANY_REV, BCMA_ANY_CLASS), ++ BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_MAC_GBIT, BCMA_ANY_REV, BCMA_ANY_CLASS), ++ BCMA_CORETABLE_END ++}; ++MODULE_DEVICE_TABLE(bcma, bgmac_bcma_tbl); ++ ++static bool bgmac_wait_value(struct bcma_device *core, u16 reg, u32 mask, ++ u32 value, int timeout) ++{ ++ u32 val; ++ int i; ++ ++ for (i = 0; i < timeout / 10; i++) { ++ val = bcma_read32(core, reg); ++ if ((val & mask) == value) ++ return true; ++ udelay(10); ++ } ++ pr_err("Timeout waiting for reg 0x%X\n", reg); ++ return false; ++} ++ ++/************************************************** ++ * DMA ++ **************************************************/ ++ ++static void bgmac_dma_tx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring) ++{ ++ u32 val; ++ int i; ++ ++ if (!ring->mmio_base) ++ return; ++ ++ /* Susend DMA TX ring first. ++ * bgmac_wait_value doesn't support waiting for any of few values, so ++ * implement whole loop here. ++ */ ++ bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, ++ BGMAC_DMA_TX_SUSPEND); ++ for (i = 0; i < 10000 / 10; i++) { ++ val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS); ++ if (val == BGMAC_DMA_TX_STAT_DISABLED || ++ val == BGMAC_DMA_TX_STAT_IDLEWAIT || ++ val == BGMAC_DMA_TX_STAT_STOPPED) { ++ i = 0; ++ break; ++ } ++ udelay(10); ++ } ++ if (i) ++ bgmac_err(bgmac, "Timeout suspending DMA TX ring 0x%X\n", ring->mmio_base); ++ ++ /* Remove SUSPEND bit */ ++ bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, 0); ++ if (!bgmac_wait_value(bgmac->core, ++ ring->mmio_base + BGMAC_DMA_TX_STATUS, ++ BGMAC_DMA_TX_STAT, BGMAC_DMA_TX_STAT_DISABLED, ++ 10000)) { ++ bgmac_warn(bgmac, "DMA TX ring 0x%X wasn't disabled on time, waiting additional 300us\n", ring->mmio_base); ++ udelay(300); ++ val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS); ++ if ((val & BGMAC_DMA_TX_STAT) != BGMAC_DMA_TX_STAT_DISABLED) ++ bgmac_err(bgmac, "Reset of DMA TX ring 0x%X failed\n", ring->mmio_base); ++ } ++} ++ ++static void bgmac_dma_tx_enable(struct bgmac *bgmac, ++ struct bgmac_dma_ring *ring) ++{ ++ u32 ctl; ++ ++ ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL); ++ ctl |= BGMAC_DMA_TX_ENABLE; ++ ctl |= BGMAC_DMA_TX_PARITY_DISABLE; ++ bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, ctl); ++} ++ ++static netdev_tx_t bgmac_dma_tx_add(struct bgmac *bgmac, ++ struct bgmac_dma_ring *ring, ++ struct sk_buff *skb) ++{ ++ struct device *dma_dev = bgmac->core->dma_dev; ++ struct bgmac_dma_desc *dma_desc; ++ struct bgmac_slot_info *slot; ++ u32 ctl0, ctl1; ++ int free_slots; ++ ++ if (skb->len > BGMAC_DESC_CTL1_LEN) { ++ bgmac_err(bgmac, "Too long skb (%d)\n", skb->len); ++ return NETDEV_TX_BUSY; ++ } ++ ++ if (ring->start <= ring->end) ++ free_slots = ring->start - ring->end + BGMAC_TX_RING_SLOTS; ++ else ++ free_slots = ring->start - ring->end; ++ if (free_slots <= 1) { ++ bgmac_err(bgmac, "No free slots on ring 0x%X!\n", ring->mmio_base); ++ netif_stop_queue(bgmac->net_dev); ++ return NETDEV_TX_BUSY; ++ } ++ ++ slot = &ring->slots[ring->end]; ++ slot->skb = skb; ++ slot->dma_addr = dma_map_single(dma_dev, skb->data, skb->len, DMA_TO_DEVICE); ++ if (dma_mapping_error(dma_dev, slot->dma_addr)) { ++ bgmac_err(bgmac, "Mapping error of skb on ring 0x%X\n", ring->mmio_base); ++ return NETDEV_TX_BUSY; ++ } ++ ++ ctl0 = BGMAC_DESC_CTL0_IOC | BGMAC_DESC_CTL0_SOF | BGMAC_DESC_CTL0_EOF; ++ if (ring->end == ring->num_slots - 1) ++ ctl0 |= BGMAC_DESC_CTL0_EOT; ++ ctl1 = skb->len & BGMAC_DESC_CTL1_LEN; ++ ++ dma_desc = ring->cpu_base; ++ dma_desc += ring->end; ++ dma_desc->addr_low = cpu_to_le32(lower_32_bits(slot->dma_addr)); ++ dma_desc->addr_high = cpu_to_le32(upper_32_bits(slot->dma_addr)); ++ dma_desc->ctl0 = cpu_to_le32(ctl0); ++ dma_desc->ctl1 = cpu_to_le32(ctl1); ++ ++ wmb(); ++ ++ /* Increase ring->end to point empty slot. We tell hardware the first ++ * slot it shold *not* read. ++ */ ++ if (++ring->end >= BGMAC_TX_RING_SLOTS) ++ ring->end = 0; ++ bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_INDEX, ++ ring->end * sizeof(struct bgmac_dma_desc)); ++ ++ return NETDEV_TX_OK; ++} ++ ++/* Free transmitted packets */ ++static void bgmac_dma_tx_free(struct bgmac *bgmac, struct bgmac_dma_ring *ring) ++{ ++ struct device *dma_dev = bgmac->core->dma_dev; ++ struct bgmac_dma_desc *dma_desc; ++ struct bgmac_slot_info *slot; ++ int empty_slot; ++ ++ /* The last slot that hardware didn't consume yet */ ++ empty_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS); ++ empty_slot &= BGMAC_DMA_TX_STATDPTR; ++ empty_slot /= sizeof(struct bgmac_dma_desc); ++ ++ while (ring->start != empty_slot) { ++ /* Set pointers */ ++ dma_desc = ring->cpu_base; ++ dma_desc += ring->start; ++ slot = &ring->slots[ring->start]; ++ ++ if (slot->skb) { ++ /* Unmap no longer used buffer */ ++ dma_unmap_single(dma_dev, slot->dma_addr, ++ slot->skb->len, DMA_TO_DEVICE); ++ slot->dma_addr = 0; ++ ++ /* Free memory! */ ++ dev_kfree_skb_any(slot->skb); ++ slot->skb = NULL; ++ } else { ++ bgmac_err(bgmac, "Hardware reported transmission for empty TX ring slot %d! End of ring: %d", ring->start, ring->end); ++ } ++ ++ if (++ring->start >= BGMAC_TX_RING_SLOTS) ++ ring->start = 0; ++ } ++} ++ ++static void bgmac_dma_rx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring) ++{ ++ if (!ring->mmio_base) ++ return; ++ ++ bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, 0); ++ if (!bgmac_wait_value(bgmac->core, ++ ring->mmio_base + BGMAC_DMA_RX_STATUS, ++ BGMAC_DMA_RX_STAT, BGMAC_DMA_RX_STAT_DISABLED, ++ 10000)) ++ bgmac_err(bgmac, "Reset of ring 0x%X RX failed\n", ring->mmio_base); ++} ++ ++static void bgmac_dma_rx_enable(struct bgmac *bgmac, ++ struct bgmac_dma_ring *ring) ++{ ++ u32 ctl; ++ ++ ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL); ++ ctl &= BGMAC_DMA_RX_ADDREXT_MASK; ++ ctl |= BGMAC_DMA_RX_ENABLE; ++ ctl |= BGMAC_DMA_RX_PARITY_DISABLE; ++ ctl |= BGMAC_DMA_RX_OVERFLOW_CONT; ++ ctl |= BGMAC_RX_FRAME_OFFSET << BGMAC_DMA_RX_FRAME_OFFSET_SHIFT; ++ bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, ctl); ++} ++ ++static void bgmac_dma_rx_skb_for_slot(struct bgmac *bgmac, ++ struct bgmac_slot_info *slot) ++{ ++ struct device *dma_dev = bgmac->core->dma_dev; ++ struct bgmac_rx_header *rx; ++ ++ /* Alloc skb */ ++ slot->skb = netdev_alloc_skb(bgmac->net_dev, BGMAC_RX_BUF_SIZE); ++ if (!slot->skb) ++ bgmac_err(bgmac, "Allocation of skb failed!\n"); ++ ++ /* Poison - if everything goes fine, hardware will overwrite it */ ++ rx = (struct bgmac_rx_header *)slot->skb->data; ++ rx->len = cpu_to_le16(0xdead); ++ rx->flags = cpu_to_le16(0xbeef); ++ ++ /* Map skb for the DMA */ ++ slot->dma_addr = dma_map_single(dma_dev, slot->skb->data, ++ BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE); ++ if (dma_mapping_error(dma_dev, slot->dma_addr)) ++ bgmac_err(bgmac, "DMA mapping error\n"); ++ if (slot->dma_addr & 0xC0000000) ++ bgmac_warn(bgmac, "DMA address using 0xC0000000 bit(s), it may need translation trick\n"); ++} ++ ++static void bgmac_dma_rx_read(struct bgmac *bgmac, struct bgmac_dma_ring *ring) ++{ ++ struct device *dma_dev = bgmac->core->dma_dev; ++ struct bgmac_dma_desc *dma_desc; ++ struct bgmac_slot_info *slot; ++ struct sk_buff *skb; ++ struct bgmac_rx_header *rx; ++ u32 end_slot; ++ u16 len, flags; ++ ++ end_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_STATUS); ++ end_slot &= BGMAC_DMA_RX_STATDPTR; ++ end_slot /= sizeof(struct bgmac_dma_desc); ++ ++ ring->end = end_slot; ++ ++ while (ring->start != ring->end) { ++ /* Set pointers */ ++ dma_desc = ring->cpu_base; ++ dma_desc += ring->start; ++ slot = &ring->slots[ring->start]; ++ skb = slot->skb; ++ ++ /* Unmap buffer to make it accessible to the CPU */ ++ dma_unmap_single(dma_dev, slot->dma_addr, BGMAC_RX_BUF_SIZE, ++ DMA_FROM_DEVICE); ++ ++ /* Get info from the header */ ++ rx = (struct bgmac_rx_header *)skb->data; ++ len = le16_to_cpu(rx->len); ++ flags = le16_to_cpu(rx->flags); ++ ++ /* Check for poison and drop or pass packet */ ++ if (len == 0xdead && flags == 0xbeef) { ++ bgmac_err(bgmac, "Found poisoned packet at slot %d, DMA issue!\n", ring->start); ++ dev_kfree_skb_any(skb); ++ } else { ++ /* Remove header from the skb and pass it to the net */ ++ skb_put(skb, BGMAC_RX_FRAME_OFFSET + len); ++ skb_pull(skb, BGMAC_RX_FRAME_OFFSET); ++ skb->protocol = eth_type_trans(skb, bgmac->net_dev); ++ netif_receive_skb(skb); ++ } ++ ++ /* Alloc new skb */ ++ bgmac_dma_rx_skb_for_slot(bgmac, slot); ++ dma_desc->addr_low = cpu_to_le32(lower_32_bits(slot->dma_addr)); ++ dma_desc->addr_high = cpu_to_le32(upper_32_bits(slot->dma_addr)); ++ ++ if (++ring->start >= BGMAC_RX_RING_SLOTS) ++ ring->start = 0; ++ } ++} ++ ++/* Does ring support unaligned addressing? */ ++static bool bgmac_dma_unaligned(struct bgmac *bgmac, ++ struct bgmac_dma_ring *ring) ++{ ++ if (ring->tx) { ++ bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO, ++ 0xff0); ++ if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO)) ++ return true; ++ } else { ++ bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO, ++ 0xff0); ++ if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO)) ++ return true; ++ } ++ return false; ++} ++ ++static int bgmac_dma_alloc(struct bgmac *bgmac) ++{ ++ struct device *dma_dev = bgmac->core->dma_dev; ++ struct bgmac_dma_ring *ring; ++ u16 ring_base[] = { BGMAC_DMA_BASE0, BGMAC_DMA_BASE1, BGMAC_DMA_BASE2, ++ BGMAC_DMA_BASE3, }; ++ int size; /* ring size: different for Tx and Rx */ ++ int i; ++ ++ BUILD_BUG_ON(BGMAC_MAX_TX_RINGS > ARRAY_SIZE(ring_base)); ++ BUILD_BUG_ON(BGMAC_MAX_RX_RINGS > ARRAY_SIZE(ring_base)); ++ ++ if (!(bcma_aread32(bgmac->core, BCMA_IOST) & BCMA_IOST_DMA64)) { ++ bgmac_err(bgmac, "Core does not report 64-bit DMA\n"); ++ return -ENOTSUPP; ++ } ++ ++ for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) { ++ ring = &bgmac->tx_ring[i]; ++ ring->tx = true; ++ ring->num_slots = BGMAC_TX_RING_SLOTS; ++ ring->mmio_base = ring_base[i]; ++ if (bgmac_dma_unaligned(bgmac, ring)) ++ bgmac_warn(bgmac, "TX on ring 0x%X supports unaligned addressing but this feature is not implemented\n", ring->mmio_base); ++ ++ /* Alloc ring of descriptors */ ++ size = ring->num_slots * sizeof(struct bgmac_dma_desc); ++ ring->cpu_base = dma_zalloc_coherent(dma_dev, size, ++ &(ring->dma_base), ++ GFP_KERNEL); ++ if (!ring->cpu_base) ++ bgmac_err(bgmac, "Allocation of TX ring failed\n"); ++ if (ring->dma_base & 0xC0000000) ++ bgmac_warn(bgmac, "DMA address using 0xC0000000 bit(s), it may need translation trick\n"); ++ ++ /* No need to alloc TX slots yet */ ++ } ++ ++ for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) { ++ ring = &bgmac->rx_ring[i]; ++ ring->tx = false; ++ ring->num_slots = BGMAC_RX_RING_SLOTS; ++ ring->mmio_base = ring_base[i]; ++ if (bgmac_dma_unaligned(bgmac, ring)) ++ bgmac_warn(bgmac, "RX on ring 0x%X supports unaligned addressing but this feature is not implemented\n", ring->mmio_base); ++ ++ /* Alloc ring of descriptors */ ++ size = ring->num_slots * sizeof(struct bgmac_dma_desc); ++ ring->cpu_base = dma_zalloc_coherent(dma_dev, size, ++ &(ring->dma_base), ++ GFP_KERNEL); ++ if (!ring->cpu_base) ++ bgmac_err(bgmac, "Allocation of RX ring failed\n"); ++ if (ring->dma_base & 0xC0000000) ++ bgmac_warn(bgmac, "DMA address using 0xC0000000 bit(s), it may need translation trick\n"); ++ ++ /* Alloc RX slots */ ++ for (i = 0; i < ring->num_slots; i++) ++ bgmac_dma_rx_skb_for_slot(bgmac, &ring->slots[i]); ++ } ++ ++ return 0; ++} ++ ++static void bgmac_dma_init(struct bgmac *bgmac) ++{ ++ struct bgmac_dma_ring *ring; ++ struct bgmac_dma_desc *dma_desc; ++ u32 ctl0, ctl1; ++ int i; ++ ++ for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) { ++ ring = &bgmac->tx_ring[i]; ++ ++ /* We don't implement unaligned addressing, so enable first */ ++ bgmac_dma_tx_enable(bgmac, ring); ++ bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO, ++ lower_32_bits(ring->dma_base)); ++ bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGHI, ++ upper_32_bits(ring->dma_base)); ++ ++ ring->start = 0; ++ ring->end = 0; /* Points the slot that should *not* be read */ ++ } ++ ++ for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) { ++ ring = &bgmac->rx_ring[i]; ++ ++ /* We don't implement unaligned addressing, so enable first */ ++ bgmac_dma_rx_enable(bgmac, ring); ++ bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO, ++ lower_32_bits(ring->dma_base)); ++ bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGHI, ++ upper_32_bits(ring->dma_base)); ++ ++ for (i = 0, dma_desc = ring->cpu_base; i < ring->num_slots; ++ i++, dma_desc++) { ++ ctl0 = ctl1 = 0; ++ ++ if (i == ring->num_slots - 1) ++ ctl0 |= BGMAC_DESC_CTL0_EOT; ++ ctl1 |= BGMAC_RX_BUF_SIZE & BGMAC_DESC_CTL1_LEN; ++ /* Is there any BGMAC device that requires extension? */ ++ /* ctl1 |= (addrext << B43_DMA64_DCTL1_ADDREXT_SHIFT) & ++ * B43_DMA64_DCTL1_ADDREXT_MASK; ++ */ ++ ++ dma_desc->addr_low = cpu_to_le32(lower_32_bits(ring->slots[i].dma_addr)); ++ dma_desc->addr_high = cpu_to_le32(upper_32_bits(ring->slots[i].dma_addr)); ++ dma_desc->ctl0 = cpu_to_le32(ctl0); ++ dma_desc->ctl1 = cpu_to_le32(ctl1); ++ } ++ ++ bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_INDEX, ++ ring->num_slots * sizeof(struct bgmac_dma_desc)); ++ ++ ring->start = 0; ++ ring->end = 0; ++ } ++} ++ ++/************************************************** ++ * PHY ops ++ **************************************************/ ++ ++u16 bgmac_phy_read(struct bgmac *bgmac, u8 phyaddr, u8 reg) ++{ ++ struct bcma_device *core; ++ u16 phy_access_addr; ++ u16 phy_ctl_addr; ++ u32 tmp; ++ ++ BUILD_BUG_ON(BGMAC_PA_DATA_MASK != BCMA_GMAC_CMN_PA_DATA_MASK); ++ BUILD_BUG_ON(BGMAC_PA_ADDR_MASK != BCMA_GMAC_CMN_PA_ADDR_MASK); ++ BUILD_BUG_ON(BGMAC_PA_ADDR_SHIFT != BCMA_GMAC_CMN_PA_ADDR_SHIFT); ++ BUILD_BUG_ON(BGMAC_PA_REG_MASK != BCMA_GMAC_CMN_PA_REG_MASK); ++ BUILD_BUG_ON(BGMAC_PA_REG_SHIFT != BCMA_GMAC_CMN_PA_REG_SHIFT); ++ BUILD_BUG_ON(BGMAC_PA_WRITE != BCMA_GMAC_CMN_PA_WRITE); ++ BUILD_BUG_ON(BGMAC_PA_START != BCMA_GMAC_CMN_PA_START); ++ BUILD_BUG_ON(BGMAC_PC_EPA_MASK != BCMA_GMAC_CMN_PC_EPA_MASK); ++ BUILD_BUG_ON(BGMAC_PC_MCT_MASK != BCMA_GMAC_CMN_PC_MCT_MASK); ++ BUILD_BUG_ON(BGMAC_PC_MCT_SHIFT != BCMA_GMAC_CMN_PC_MCT_SHIFT); ++ BUILD_BUG_ON(BGMAC_PC_MTE != BCMA_GMAC_CMN_PC_MTE); ++ ++ if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT) { ++ core = bgmac->core->bus->drv_gmac_cmn.core; ++ phy_access_addr = BCMA_GMAC_CMN_PHY_ACCESS; ++ phy_ctl_addr = BCMA_GMAC_CMN_PHY_CTL; ++ } else { ++ core = bgmac->core; ++ phy_access_addr = BGMAC_PHY_ACCESS; ++ phy_ctl_addr = BGMAC_PHY_CNTL; ++ } ++ ++ tmp = bcma_read32(core, phy_ctl_addr); ++ tmp &= ~BGMAC_PC_EPA_MASK; ++ tmp |= phyaddr; ++ bcma_write32(core, phy_ctl_addr, tmp); ++ ++ tmp = BGMAC_PA_START; ++ tmp |= phyaddr << BGMAC_PA_ADDR_SHIFT; ++ tmp |= reg << BGMAC_PA_REG_SHIFT; ++ bcma_write32(core, phy_access_addr, tmp); ++ ++ if (!bgmac_wait_value(core, phy_access_addr, BGMAC_PA_START, 0, 1000)) { ++ bgmac_err(bgmac, "Reading PHY %d register 0x%X failed\n", ++ phyaddr, reg); ++ return 0xffff; ++ } ++ ++ return bcma_read32(core, phy_access_addr) & BGMAC_PA_DATA_MASK; ++} ++ ++/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphywr */ ++void bgmac_phy_write(struct bgmac *bgmac, u8 phyaddr, u8 reg, u16 value) ++{ ++ struct bcma_device *core; ++ u16 phy_access_addr; ++ u16 phy_ctl_addr; ++ u32 tmp; ++ ++ if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT) { ++ core = bgmac->core->bus->drv_gmac_cmn.core; ++ phy_access_addr = BCMA_GMAC_CMN_PHY_ACCESS; ++ phy_ctl_addr = BCMA_GMAC_CMN_PHY_CTL; ++ } else { ++ core = bgmac->core; ++ phy_access_addr = BGMAC_PHY_ACCESS; ++ phy_ctl_addr = BGMAC_PHY_CNTL; ++ } ++ ++ tmp = bcma_read32(core, phy_ctl_addr); ++ tmp &= ~BGMAC_PC_EPA_MASK; ++ tmp |= phyaddr; ++ bcma_write32(core, phy_ctl_addr, tmp); ++ ++ bgmac_write(bgmac, BGMAC_INT_STATUS, BGMAC_IS_MDIO); ++ if (bgmac_read(bgmac, BGMAC_INT_STATUS) & BGMAC_IS_MDIO) ++ bgmac_warn(bgmac, "Error setting MDIO int\n"); ++ ++ tmp = BGMAC_PA_START; ++ tmp |= BGMAC_PA_WRITE; ++ tmp |= phyaddr << BGMAC_PA_ADDR_SHIFT; ++ tmp |= reg << BGMAC_PA_REG_SHIFT; ++ tmp |= value; ++ bcma_write32(core, phy_access_addr, tmp); ++ ++ if (!bgmac_wait_value(core, phy_access_addr, BGMAC_PA_START, 0, 1000)) ++ bgmac_err(bgmac, "Writing to PHY %d register 0x%X failed\n", ++ phyaddr, reg); ++} ++ ++/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyforce */ ++static void bgmac_phy_force(struct bgmac *bgmac) ++{ ++ u16 ctl; ++ u16 mask = ~(BGMAC_PHY_CTL_SPEED | BGMAC_PHY_CTL_SPEED_MSB | ++ BGMAC_PHY_CTL_ANENAB | BGMAC_PHY_CTL_DUPLEX); ++ ++ if (bgmac->phyaddr == BGMAC_PHY_NOREGS) ++ return; ++ ++ if (bgmac->autoneg) ++ return; ++ ++ ctl = bgmac_phy_read(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL); ++ ctl &= mask; ++ if (bgmac->full_duplex) ++ ctl |= BGMAC_PHY_CTL_DUPLEX; ++ if (bgmac->speed == BGMAC_SPEED_100) ++ ctl |= BGMAC_PHY_CTL_SPEED_100; ++ else if (bgmac->speed == BGMAC_SPEED_1000) ++ ctl |= BGMAC_PHY_CTL_SPEED_1000; ++ bgmac_phy_write(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL, ctl); ++} ++ ++/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyadvertise */ ++static void bgmac_phy_advertise(struct bgmac *bgmac) ++{ ++ u16 adv; ++ ++ if (bgmac->phyaddr == BGMAC_PHY_NOREGS) ++ return; ++ ++ if (bgmac->autoneg) ++ return; ++ ++ /* Adv selected 10/100 speeds */ ++ adv = bgmac_phy_read(bgmac, bgmac->phyaddr, BGMAC_PHY_ADV); ++ adv &= ~(BGMAC_PHY_ADV_10HALF | BGMAC_PHY_ADV_10FULL | ++ BGMAC_PHY_ADV_100HALF | BGMAC_PHY_ADV_100FULL); ++ if (!bgmac->full_duplex && bgmac->speed & BGMAC_SPEED_10) ++ adv |= BGMAC_PHY_ADV_10HALF; ++ if (!bgmac->full_duplex && bgmac->speed & BGMAC_SPEED_100) ++ adv |= BGMAC_PHY_ADV_100HALF; ++ if (bgmac->full_duplex && bgmac->speed & BGMAC_SPEED_10) ++ adv |= BGMAC_PHY_ADV_10FULL; ++ if (bgmac->full_duplex && bgmac->speed & BGMAC_SPEED_100) ++ adv |= BGMAC_PHY_ADV_100FULL; ++ bgmac_phy_write(bgmac, bgmac->phyaddr, BGMAC_PHY_ADV, adv); ++ ++ /* Adv selected 1000 speeds */ ++ adv = bgmac_phy_read(bgmac, bgmac->phyaddr, BGMAC_PHY_ADV2); ++ adv &= ~(BGMAC_PHY_ADV2_1000HALF | BGMAC_PHY_ADV2_1000FULL); ++ if (!bgmac->full_duplex && bgmac->speed & BGMAC_SPEED_1000) ++ adv |= BGMAC_PHY_ADV2_1000HALF; ++ if (bgmac->full_duplex && bgmac->speed & BGMAC_SPEED_1000) ++ adv |= BGMAC_PHY_ADV2_1000FULL; ++ bgmac_phy_write(bgmac, bgmac->phyaddr, BGMAC_PHY_ADV2, adv); ++ ++ /* Restart */ ++ bgmac_phy_write(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL, ++ bgmac_phy_read(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL) | ++ BGMAC_PHY_CTL_RESTART); ++} ++ ++/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyinit */ ++static void bgmac_phy_init(struct bgmac *bgmac) ++{ ++ struct bcma_chipinfo *ci = &bgmac->core->bus->chipinfo; ++ struct bcma_drv_cc *cc = &bgmac->core->bus->drv_cc; ++ u8 i; ++ ++ if (ci->id == BCMA_CHIP_ID_BCM5356) { ++ for (i = 0; i < 5; i++) { ++ bgmac_phy_write(bgmac, i, 0x1f, 0x008b); ++ bgmac_phy_write(bgmac, i, 0x15, 0x0100); ++ bgmac_phy_write(bgmac, i, 0x1f, 0x000f); ++ bgmac_phy_write(bgmac, i, 0x12, 0x2aaa); ++ bgmac_phy_write(bgmac, i, 0x1f, 0x000b); ++ } ++ } ++ if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg != 10) || ++ (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg != 10) || ++ (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg != 9)) { ++ bcma_chipco_chipctl_maskset(cc, 2, ~0xc0000000, 0); ++ bcma_chipco_chipctl_maskset(cc, 4, ~0x80000000, 0); ++ for (i = 0; i < 5; i++) { ++ bgmac_phy_write(bgmac, i, 0x1f, 0x000f); ++ bgmac_phy_write(bgmac, i, 0x16, 0x5284); ++ bgmac_phy_write(bgmac, i, 0x1f, 0x000b); ++ bgmac_phy_write(bgmac, i, 0x17, 0x0010); ++ bgmac_phy_write(bgmac, i, 0x1f, 0x000f); ++ bgmac_phy_write(bgmac, i, 0x16, 0x5296); ++ bgmac_phy_write(bgmac, i, 0x17, 0x1073); ++ bgmac_phy_write(bgmac, i, 0x17, 0x9073); ++ bgmac_phy_write(bgmac, i, 0x16, 0x52b6); ++ bgmac_phy_write(bgmac, i, 0x17, 0x9273); ++ bgmac_phy_write(bgmac, i, 0x1f, 0x000b); ++ } ++ } ++} ++ ++/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyreset */ ++static void bgmac_phy_reset(struct bgmac *bgmac) ++{ ++ if (bgmac->phyaddr == BGMAC_PHY_NOREGS) ++ return; ++ ++ bgmac_phy_write(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL, ++ BGMAC_PHY_CTL_RESET); ++ udelay(100); ++ if (bgmac_phy_read(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL) & ++ BGMAC_PHY_CTL_RESET) ++ bgmac_err(bgmac, "PHY reset failed\n"); ++ bgmac_phy_init(bgmac); ++} ++ ++/************************************************** ++ * Chip ops ++ **************************************************/ ++ ++/* TODO: can we just drop @force? Can we don't reset MAC at all if there is ++ * nothing to change? Try if after stabilizng driver. ++ */ ++static void bgmac_cmdcfg_maskset(struct bgmac *bgmac, u32 mask, u32 set, ++ bool force) ++{ ++ u32 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG); ++ u32 new_val = (cmdcfg & mask) | set; ++ ++ bgmac_set(bgmac, BGMAC_CMDCFG, BGMAC_CMDCFG_SR); ++ udelay(2); ++ ++ if (new_val != cmdcfg || force) ++ bgmac_write(bgmac, BGMAC_CMDCFG, new_val); ++ ++ bgmac_mask(bgmac, BGMAC_CMDCFG, ~BGMAC_CMDCFG_SR); ++ udelay(2); ++} ++ ++static void bgmac_chip_stats_update(struct bgmac *bgmac) ++{ ++ int i; ++ ++ if (bgmac->core->id.id != BCMA_CORE_4706_MAC_GBIT) { ++ for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++) ++ bgmac->mib_tx_regs[i] = ++ bgmac_read(bgmac, ++ BGMAC_TX_GOOD_OCTETS + (i * 4)); ++ for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++) ++ bgmac->mib_rx_regs[i] = ++ bgmac_read(bgmac, ++ BGMAC_RX_GOOD_OCTETS + (i * 4)); ++ } ++ ++ /* TODO: what else? how to handle BCM4706? */ ++} ++ ++static void bgmac_clear_mib(struct bgmac *bgmac) ++{ ++ int i; ++ ++ if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT) ++ return; ++ ++ bgmac_set(bgmac, BGMAC_DEV_CTL, BGMAC_DC_MROR); ++ for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++) ++ bgmac_read(bgmac, BGMAC_TX_GOOD_OCTETS + (i * 4)); ++ for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++) ++ bgmac_read(bgmac, BGMAC_RX_GOOD_OCTETS + (i * 4)); ++} ++ ++/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_speed */ ++static void bgmac_speed(struct bgmac *bgmac, int speed) ++{ ++ u32 mask = ~(BGMAC_CMDCFG_ES_MASK | BGMAC_CMDCFG_HD); ++ u32 set = 0; ++ ++ if (speed & BGMAC_SPEED_10) ++ set |= BGMAC_CMDCFG_ES_10; ++ if (speed & BGMAC_SPEED_100) ++ set |= BGMAC_CMDCFG_ES_100; ++ if (speed & BGMAC_SPEED_1000) ++ set |= BGMAC_CMDCFG_ES_1000; ++ if (!bgmac->full_duplex) ++ set |= BGMAC_CMDCFG_HD; ++ bgmac_cmdcfg_maskset(bgmac, mask, set, true); ++} ++ ++static void bgmac_miiconfig(struct bgmac *bgmac) ++{ ++ u8 imode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & BGMAC_DS_MM_MASK) >> ++ BGMAC_DS_MM_SHIFT; ++ if (imode == 0 || imode == 1) { ++ if (bgmac->autoneg) ++ bgmac_speed(bgmac, BGMAC_SPEED_100); ++ else ++ bgmac_speed(bgmac, bgmac->speed); ++ } ++} ++ ++/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipreset */ ++static void bgmac_chip_reset(struct bgmac *bgmac) ++{ ++ struct bcma_device *core = bgmac->core; ++ struct bcma_bus *bus = core->bus; ++ struct bcma_chipinfo *ci = &bus->chipinfo; ++ u32 flags = 0; ++ u32 iost; ++ int i; ++ ++ if (bcma_core_is_enabled(core)) { ++ if (!bgmac->stats_grabbed) { ++ bgmac_chip_stats_update(bgmac); ++ bgmac->stats_grabbed = true; ++ } ++ ++ for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) ++ bgmac_dma_tx_reset(bgmac, &bgmac->tx_ring[i]); ++ ++ bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false); ++ udelay(1); ++ ++ for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) ++ bgmac_dma_rx_reset(bgmac, &bgmac->rx_ring[i]); ++ ++ /* TODO: Clear software multicast filter list */ ++ } ++ ++ iost = bcma_aread32(core, BCMA_IOST); ++ if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == 10) || ++ (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg == 10) || ++ (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == 9)) ++ iost &= ~BGMAC_BCMA_IOST_ATTACHED; ++ ++ if (iost & BGMAC_BCMA_IOST_ATTACHED) { ++ flags = BGMAC_BCMA_IOCTL_SW_CLKEN; ++ if (!bgmac->has_robosw) ++ flags |= BGMAC_BCMA_IOCTL_SW_RESET; ++ } ++ ++ bcma_core_enable(core, flags); ++ ++ if (core->id.rev > 2) { ++ bgmac_set(bgmac, BCMA_CLKCTLST, 1 << 8); ++ bgmac_wait_value(bgmac->core, BCMA_CLKCTLST, 1 << 24, 1 << 24, ++ 1000); ++ } ++ ++ if (ci->id == BCMA_CHIP_ID_BCM5357 || ci->id == BCMA_CHIP_ID_BCM4749 || ++ ci->id == BCMA_CHIP_ID_BCM53572) { ++ struct bcma_drv_cc *cc = &bgmac->core->bus->drv_cc; ++ u8 et_swtype = 0; ++ u8 sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHY | ++ BGMAC_CHIPCTL_1_IF_TYPE_RMII; ++ char buf[2]; ++ if (bcm47xx_nvram_getenv("et_swtype", buf, 1) > 0) { ++ if (kstrtou8(buf, 0, &et_swtype)) ++ bgmac_err(bgmac, "Failed to parse et_swtype (%s)\n", buf); ++ et_swtype &= 0x0f; ++ et_swtype <<= 4; ++ sw_type = et_swtype; ++ } else if (ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == 9) { ++ sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHYRMII; ++ } else if (0) { ++ /* TODO */ ++ } ++ bcma_chipco_chipctl_maskset(cc, 1, ++ ~(BGMAC_CHIPCTL_1_IF_TYPE_MASK | ++ BGMAC_CHIPCTL_1_SW_TYPE_MASK), ++ sw_type); ++ } ++ ++ if (iost & BGMAC_BCMA_IOST_ATTACHED && !bgmac->has_robosw) ++ bcma_awrite32(core, BCMA_IOCTL, ++ bcma_aread32(core, BCMA_IOCTL) & ++ ~BGMAC_BCMA_IOCTL_SW_RESET); ++ ++ /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_reset ++ * Specs don't say about using BGMAC_CMDCFG_SR, but in this routine ++ * BGMAC_CMDCFG is read _after_ putting chip in a reset. So it has to ++ * be keps until taking MAC out of the reset. ++ */ ++ bgmac_cmdcfg_maskset(bgmac, ++ ~(BGMAC_CMDCFG_TE | ++ BGMAC_CMDCFG_RE | ++ BGMAC_CMDCFG_RPI | ++ BGMAC_CMDCFG_TAI | ++ BGMAC_CMDCFG_HD | ++ BGMAC_CMDCFG_ML | ++ BGMAC_CMDCFG_CFE | ++ BGMAC_CMDCFG_RL | ++ BGMAC_CMDCFG_RED | ++ BGMAC_CMDCFG_PE | ++ BGMAC_CMDCFG_TPI | ++ BGMAC_CMDCFG_PAD_EN | ++ BGMAC_CMDCFG_PF), ++ BGMAC_CMDCFG_PROM | ++ BGMAC_CMDCFG_NLC | ++ BGMAC_CMDCFG_CFE | ++ BGMAC_CMDCFG_SR, ++ false); ++ ++ bgmac_clear_mib(bgmac); ++ if (core->id.id == BCMA_CORE_4706_MAC_GBIT) ++ bcma_maskset32(bgmac->cmn, BCMA_GMAC_CMN_PHY_CTL, ~0, ++ BCMA_GMAC_CMN_PC_MTE); ++ else ++ bgmac_set(bgmac, BGMAC_PHY_CNTL, BGMAC_PC_MTE); ++ bgmac_miiconfig(bgmac); ++ bgmac_phy_init(bgmac); ++ ++ bgmac->int_status = 0; ++} ++ ++static void bgmac_chip_intrs_on(struct bgmac *bgmac) ++{ ++ bgmac_write(bgmac, BGMAC_INT_MASK, bgmac->int_mask); ++} ++ ++static void bgmac_chip_intrs_off(struct bgmac *bgmac) ++{ ++ bgmac_write(bgmac, BGMAC_INT_MASK, 0); ++} ++ ++/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_enable */ ++static void bgmac_enable(struct bgmac *bgmac) ++{ ++ struct bcma_chipinfo *ci = &bgmac->core->bus->chipinfo; ++ u32 cmdcfg; ++ u32 mode; ++ u32 rxq_ctl; ++ u32 fl_ctl; ++ u16 bp_clk; ++ u8 mdp; ++ ++ cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG); ++ bgmac_cmdcfg_maskset(bgmac, ~(BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE), ++ BGMAC_CMDCFG_SR, true); ++ udelay(2); ++ cmdcfg |= BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE; ++ bgmac_write(bgmac, BGMAC_CMDCFG, cmdcfg); ++ ++ mode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & BGMAC_DS_MM_MASK) >> ++ BGMAC_DS_MM_SHIFT; ++ if (ci->id != BCMA_CHIP_ID_BCM47162 || mode != 0) ++ bgmac_set(bgmac, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT); ++ if (ci->id == BCMA_CHIP_ID_BCM47162 && mode == 2) ++ bcma_chipco_chipctl_maskset(&bgmac->core->bus->drv_cc, 1, ~0, ++ BGMAC_CHIPCTL_1_RXC_DLL_BYPASS); ++ ++ switch (ci->id) { ++ case BCMA_CHIP_ID_BCM5357: ++ case BCMA_CHIP_ID_BCM4749: ++ case BCMA_CHIP_ID_BCM53572: ++ case BCMA_CHIP_ID_BCM4716: ++ case BCMA_CHIP_ID_BCM47162: ++ fl_ctl = 0x03cb04cb; ++ if (ci->id == BCMA_CHIP_ID_BCM5357 || ++ ci->id == BCMA_CHIP_ID_BCM4749 || ++ ci->id == BCMA_CHIP_ID_BCM53572) ++ fl_ctl = 0x2300e1; ++ bgmac_write(bgmac, BGMAC_FLOW_CTL_THRESH, fl_ctl); ++ bgmac_write(bgmac, BGMAC_PAUSE_CTL, 0x27fff); ++ break; ++ } ++ ++ rxq_ctl = bgmac_read(bgmac, BGMAC_RXQ_CTL); ++ rxq_ctl &= ~BGMAC_RXQ_CTL_MDP_MASK; ++ bp_clk = bcma_pmu_get_bus_clock(&bgmac->core->bus->drv_cc) / 1000000; ++ mdp = (bp_clk * 128 / 1000) - 3; ++ rxq_ctl |= (mdp << BGMAC_RXQ_CTL_MDP_SHIFT); ++ bgmac_write(bgmac, BGMAC_RXQ_CTL, rxq_ctl); ++} ++ ++/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipinit */ ++static void bgmac_chip_init(struct bgmac *bgmac, bool full_init) ++{ ++ struct ssb_sprom *sprom = &bgmac->core->bus->sprom; ++ struct bgmac_dma_ring *ring; ++ u32 tmp; ++ u8 *mac; ++ int i; ++ ++ /* 1 interrupt per received frame */ ++ bgmac_write(bgmac, BGMAC_INT_RECV_LAZY, 1 << BGMAC_IRL_FC_SHIFT); ++ ++ /* enable 802.3x tx flow control (honor received PAUSE frames) */ ++ bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_RPI, 0, true); ++ ++ if (bgmac->net_dev->flags & IFF_PROMISC) ++ bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_PROM, false); ++ else ++ bgmac_warn(bgmac, "Software filtering is not supported yet\n"); ++ ++ mac = bgmac->core->core_unit ? sprom->et1mac : sprom->et0mac; ++ tmp = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3]; ++ bgmac_write(bgmac, BGMAC_MACADDR_HIGH, tmp); ++ tmp = (mac[4] << 8) | mac[5]; ++ bgmac_write(bgmac, BGMAC_MACADDR_LOW, tmp); ++ memcpy(bgmac->net_dev->dev_addr, mac, 6); ++ ++ if (bgmac->loopback) ++ bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, true); ++ else ++ bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_ML, 0, true); ++ ++ bgmac_write(bgmac, BGMAC_RXMAX_LENGTH, 32 + ETHER_MAX_LEN); ++ ++ if (!bgmac->autoneg) { ++ bgmac_speed(bgmac, bgmac->speed); ++ bgmac_phy_force(bgmac); ++ } else if (bgmac->speed) { /* if there is anything to adv */ ++ bgmac_phy_advertise(bgmac); ++ } ++ ++ if (full_init) { ++ bgmac_dma_init(bgmac); ++ if (1) /* FIXME: is there any case we don't want IRQs? */ ++ bgmac_chip_intrs_on(bgmac); ++ } else { ++ for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) { ++ ring = &bgmac->rx_ring[i]; ++ bgmac_dma_rx_enable(bgmac, ring); ++ } ++ } ++ ++ bgmac_enable(bgmac); ++} ++ ++static irqreturn_t bgmac_interrupt(int irq, void *dev_id) ++{ ++ struct bgmac *bgmac = netdev_priv(dev_id); ++ ++ u32 int_status = bgmac_read(bgmac, BGMAC_INT_STATUS); ++ int_status &= bgmac->int_mask; ++ ++ if (!int_status) ++ return IRQ_NONE; ++ ++ /* Ack */ ++ bgmac_write(bgmac, BGMAC_INT_STATUS, int_status); ++ ++ /* Disable new interrupts until handling existing ones */ ++ bgmac_chip_intrs_off(bgmac); ++ ++ bgmac->int_status = int_status; ++ ++ return IRQ_WAKE_THREAD; ++} ++ ++static irqreturn_t bgmac_interrupt_thread(int irq, void *dev_id) ++{ ++ struct bgmac *bgmac = netdev_priv(dev_id); ++ struct bgmac_dma_ring *ring; ++ ++ if (bgmac->int_status & BGMAC_IS_TX0) { ++ ring = &bgmac->tx_ring[0]; ++ bgmac_dma_tx_free(bgmac, ring); ++ bgmac->int_status &= ~BGMAC_IS_TX0; ++ } ++ ++ if (bgmac->int_status & BGMAC_IS_RX) { ++ ring = &bgmac->rx_ring[0]; ++ bgmac_dma_rx_read(bgmac, ring); ++ bgmac->int_status &= ~BGMAC_IS_RX; ++ } ++ ++ if (bgmac->int_status) { ++ bgmac_err(bgmac, "Unknown IRQs: 0x%08X\n", bgmac->int_status); ++ bgmac->int_status = 0; ++ } ++ ++ bgmac_chip_intrs_on(bgmac); ++ return IRQ_HANDLED; ++} ++ ++/************************************************** ++ * net_device ops ++ **************************************************/ ++ ++static int bgmac_open(struct net_device *net_dev) ++{ ++ struct bgmac *bgmac = netdev_priv(net_dev); ++ ++ bgmac_chip_reset(bgmac); ++ /* Specs say about reclaiming rings here, but we do that in DMA init */ ++ bgmac_chip_init(bgmac, true); ++ ++ if (request_threaded_irq(bgmac->core->irq, bgmac_interrupt, ++ bgmac_interrupt_thread, IRQF_SHARED, ++ KBUILD_MODNAME, net_dev) < 0) ++ bgmac_err(bgmac, "IRQ request error!\n"); ++ ++ return 0; ++} ++ ++static int bgmac_stop(struct net_device *net_dev) ++{ ++ struct bgmac *bgmac = netdev_priv(net_dev); ++ ++ bgmac_chip_intrs_off(bgmac); ++ ++ free_irq(bgmac->core->irq, net_dev); ++ ++ /* TODO */ ++ ++ return 0; ++} ++ ++static int bgmac_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd) ++{ ++ struct bgmac *bgmac = netdev_priv(net_dev); ++ struct mii_ioctl_data *data = if_mii(ifr); ++ ++ switch (cmd) { ++ case SIOCGMIIPHY: ++ data->phy_id = bgmac->phyaddr; ++ /* fallthru */ ++ case SIOCGMIIREG: ++ if (!netif_running(net_dev)) ++ return -EAGAIN; ++ data->val_out = bgmac_phy_read(bgmac, bgmac->phyaddr, ++ data->reg_num & 0x1f); ++ return 0; ++ case SIOCSMIIREG: ++ if (!netif_running(net_dev)) ++ return -EAGAIN; ++ bgmac_phy_write(bgmac, bgmac->phyaddr, data->reg_num & 0x1f, ++ data->val_in); ++ return 0; ++ default: ++ return -EOPNOTSUPP; ++ } ++} ++ ++static netdev_tx_t bgmac_start_xmit(struct sk_buff *skb, ++ struct net_device *net_dev) ++{ ++ struct bgmac *bgmac = netdev_priv(net_dev); ++ struct bgmac_dma_ring *ring; ++ ++ /* No QOS support yet */ ++ ring = &bgmac->tx_ring[0]; ++ return bgmac_dma_tx_add(bgmac, ring, skb); ++} ++ ++static const struct net_device_ops bgmac_netdev_ops = { ++ .ndo_open = bgmac_open, ++ .ndo_stop = bgmac_stop, ++ .ndo_do_ioctl = bgmac_ioctl, ++ .ndo_start_xmit = bgmac_start_xmit, ++}; ++ ++/************************************************** ++ * BCMA bus ops ++ **************************************************/ ++ ++/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipattach */ ++static int bgmac_probe(struct bcma_device *core) ++{ ++ struct net_device *net_dev; ++ struct bgmac *bgmac; ++ struct ssb_sprom *sprom = &core->bus->sprom; ++ int err; ++ ++ /* Allocation and references */ ++ net_dev = alloc_etherdev(sizeof(*bgmac)); ++ if (!net_dev) ++ return -ENOMEM; ++ net_dev->netdev_ops = &bgmac_netdev_ops; ++ net_dev->irq = core->irq; ++ bgmac = netdev_priv(net_dev); ++ bgmac->net_dev = net_dev; ++ bgmac->core = core; ++ bcma_set_drvdata(core, bgmac); ++ ++ /* Defaults */ ++ bgmac->autoneg = true; ++ bgmac->full_duplex = true; ++ bgmac->speed = BGMAC_SPEED_10 | BGMAC_SPEED_100 | BGMAC_SPEED_1000; ++ ++ /* On BCM4706 we need common core to access PHY */ ++ if (core->id.id == BCMA_CORE_4706_MAC_GBIT && ++ !core->bus->drv_gmac_cmn.core) { ++ bgmac_err(bgmac, "GMAC CMN core not found (required for BCM4706)\n"); ++ return -ENODEV; ++ } ++ bgmac->cmn = core->bus->drv_gmac_cmn.core; ++ ++ bgmac->phyaddr = core->core_unit ? sprom->et1phyaddr : ++ sprom->et0phyaddr; ++ bgmac->phyaddr &= BGMAC_PHY_MASK; ++ if (bgmac->phyaddr == BGMAC_PHY_MASK) { ++ bgmac_err(bgmac, "No PHY found\n"); ++ return -ENODEV; ++ } ++ bgmac_info(bgmac, "Found PHY addr: %d\n", bgmac->phyaddr); ++ ++ if (core->bus->hosttype == BCMA_HOSTTYPE_PCI) { ++ bgmac_err(bgmac, "PCI setup not implemented\n"); ++ return -ENOTSUPP; ++ } ++ ++ bgmac_chip_reset(bgmac); ++ ++ bgmac_dma_alloc(bgmac); ++ ++ bgmac->int_mask = BGMAC_IS_ERRMASK | BGMAC_IS_RX | BGMAC_IS_TX_MASK; ++ if (bcm47xx_nvram_getenv("et0_no_txint", NULL, 0) > 0) ++ bgmac->int_mask &= ~BGMAC_IS_TX_MASK; ++ ++ /* TODO: reset the external phy */ ++ bgmac_phy_reset(bgmac); ++ ++ bgmac->has_robosw = !!(core->bus->sprom.boardflags_lo & ++ BGMAC_BFL_ENETROBO); ++ if (bgmac->has_robosw) ++ bgmac_err(bgmac, "Support for Roboswitch not implemented\n"); ++ ++ if (core->bus->sprom.boardflags_lo & BGMAC_BFL_ENETADM) ++ bgmac_err(bgmac, "Support for ADMtek ethernet switch not implemented\n"); ++ ++ err = register_netdev(bgmac->net_dev); ++ if (err) { ++ bgmac_err(bgmac, "Cannot register net device\n"); ++ return -ENOTSUPP; ++ } ++ ++ return 0; ++} ++ ++static void bgmac_remove(struct bcma_device *core) ++{ ++ struct bgmac *bgmac = bcma_get_drvdata(core); ++ ++ unregister_netdev(bgmac->net_dev); ++ free_netdev(bgmac->net_dev); ++ bcma_set_drvdata(core, NULL); ++} ++ ++static struct bcma_driver bgmac_bcma_driver = { ++ .name = KBUILD_MODNAME, ++ .id_table = bgmac_bcma_tbl, ++ .probe = bgmac_probe, ++ .remove = bgmac_remove, ++}; ++ ++static int __init bgmac_init(void) ++{ ++ int err; ++ ++ err = bcma_driver_register(&bgmac_bcma_driver); ++ if (err) ++ return err; ++ pr_info("Broadcom 47xx GMAC driver loaded\n"); ++ ++ return 0; ++} ++ ++static void __exit bgmac_exit(void) ++{ ++ bcma_driver_unregister(&bgmac_bcma_driver); ++} ++ ++module_init(bgmac_init) ++module_exit(bgmac_exit) +--- /dev/null ++++ b/drivers/net/ethernet/broadcom/bgmac.h +@@ -0,0 +1,424 @@ ++#ifndef _BGMAC_H ++#define _BGMAC_H ++ ++#include <linux/bcma/bcma.h> ++ ++#define BGMAC_DEV_CTL 0x000 ++#define BGMAC_DC_TSM 0x00000002 ++#define BGMAC_DC_CFCO 0x00000004 ++#define BGMAC_DC_RLSS 0x00000008 ++#define BGMAC_DC_MROR 0x00000010 ++#define BGMAC_DC_FCM_MASK 0x00000060 ++#define BGMAC_DC_FCM_SHIFT 5 ++#define BGMAC_DC_NAE 0x00000080 ++#define BGMAC_DC_TF 0x00000100 ++#define BGMAC_DC_RDS_MASK 0x00030000 ++#define BGMAC_DC_RDS_SHIFT 16 ++#define BGMAC_DC_TDS_MASK 0x000c0000 ++#define BGMAC_DC_TDS_SHIFT 18 ++#define BGMAC_DEV_STATUS 0x004 /* Configuration of the interface */ ++#define BGMAC_DS_RBF 0x00000001 ++#define BGMAC_DS_RDF 0x00000002 ++#define BGMAC_DS_RIF 0x00000004 ++#define BGMAC_DS_TBF 0x00000008 ++#define BGMAC_DS_TDF 0x00000010 ++#define BGMAC_DS_TIF 0x00000020 ++#define BGMAC_DS_PO 0x00000040 ++#define BGMAC_DS_MM_MASK 0x00000300 /* Mode of the interface */ ++#define BGMAC_DS_MM_SHIFT 8 ++#define BGMAC_BIST_STATUS 0x00c ++#define BGMAC_INT_STATUS 0x020 /* Interrupt status */ ++#define BGMAC_IS_MRO 0x00000001 ++#define BGMAC_IS_MTO 0x00000002 ++#define BGMAC_IS_TFD 0x00000004 ++#define BGMAC_IS_LS 0x00000008 ++#define BGMAC_IS_MDIO 0x00000010 ++#define BGMAC_IS_MR 0x00000020 ++#define BGMAC_IS_MT 0x00000040 ++#define BGMAC_IS_TO 0x00000080 ++#define BGMAC_IS_DESC_ERR 0x00000400 /* Descriptor error */ ++#define BGMAC_IS_DATA_ERR 0x00000800 /* Data error */ ++#define BGMAC_IS_DESC_PROT_ERR 0x00001000 /* Descriptor protocol error */ ++#define BGMAC_IS_RX_DESC_UNDERF 0x00002000 /* Receive descriptor underflow */ ++#define BGMAC_IS_RX_F_OVERF 0x00004000 /* Receive fifi overflow */ ++#define BGMAC_IS_TX_F_UNDERF 0x00008000 /* Transmit fifo underflow */ ++#define BGMAC_IS_RX 0x00010000 /* Interrupt for RX queue 0 */ ++#define BGMAC_IS_TX0 0x01000000 /* Interrupt for TX queue 0 */ ++#define BGMAC_IS_TX1 0x02000000 /* Interrupt for TX queue 1 */ ++#define BGMAC_IS_TX2 0x04000000 /* Interrupt for TX queue 2 */ ++#define BGMAC_IS_TX3 0x08000000 /* Interrupt for TX queue 3 */ ++#define BGMAC_IS_TX_MASK 0x0f000000 ++#define BGMAC_IS_INTMASK 0x0f01fcff ++#define BGMAC_IS_ERRMASK 0x0000fc00 ++#define BGMAC_INT_MASK 0x024 /* Interrupt mask */ ++#define BGMAC_GP_TIMER 0x028 ++#define BGMAC_INT_RECV_LAZY 0x100 ++#define BGMAC_IRL_TO_MASK 0x00ffffff ++#define BGMAC_IRL_FC_MASK 0xff000000 ++#define BGMAC_IRL_FC_SHIFT 24 /* Shift the number of interrupts triggered per received frame */ ++#define BGMAC_FLOW_CTL_THRESH 0x104 /* Flow control thresholds */ ++#define BGMAC_WRRTHRESH 0x108 ++#define BGMAC_GMAC_IDLE_CNT_THRESH 0x10c ++#define BGMAC_PHY_ACCESS 0x180 /* PHY access address */ ++#define BGMAC_PA_DATA_MASK 0x0000ffff ++#define BGMAC_PA_ADDR_MASK 0x001f0000 ++#define BGMAC_PA_ADDR_SHIFT 16 ++#define BGMAC_PA_REG_MASK 0x1f000000 ++#define BGMAC_PA_REG_SHIFT 24 ++#define BGMAC_PA_WRITE 0x20000000 ++#define BGMAC_PA_START 0x40000000 ++#define BGMAC_PHY_CNTL 0x188 /* PHY control address */ ++#define BGMAC_PC_EPA_MASK 0x0000001f ++#define BGMAC_PC_MCT_MASK 0x007f0000 ++#define BGMAC_PC_MCT_SHIFT 16 ++#define BGMAC_PC_MTE 0x00800000 ++#define BGMAC_TXQ_CTL 0x18c ++#define BGMAC_TXQ_CTL_DBT_MASK 0x00000fff ++#define BGMAC_TXQ_CTL_DBT_SHIFT 0 ++#define BGMAC_RXQ_CTL 0x190 ++#define BGMAC_RXQ_CTL_DBT_MASK 0x00000fff ++#define BGMAC_RXQ_CTL_DBT_SHIFT 0 ++#define BGMAC_RXQ_CTL_PTE 0x00001000 ++#define BGMAC_RXQ_CTL_MDP_MASK 0x3f000000 ++#define BGMAC_RXQ_CTL_MDP_SHIFT 24 ++#define BGMAC_GPIO_SELECT 0x194 ++#define BGMAC_GPIO_OUTPUT_EN 0x198 ++/* For 0x1e0 see BCMA_CLKCTLST */ ++#define BGMAC_HW_WAR 0x1e4 ++#define BGMAC_PWR_CTL 0x1e8 ++#define BGMAC_DMA_BASE0 0x200 /* Tx and Rx controller */ ++#define BGMAC_DMA_BASE1 0x240 /* Tx controller only */ ++#define BGMAC_DMA_BASE2 0x280 /* Tx controller only */ ++#define BGMAC_DMA_BASE3 0x2C0 /* Tx controller only */ ++#define BGMAC_TX_GOOD_OCTETS 0x300 ++#define BGMAC_TX_GOOD_OCTETS_HIGH 0x304 ++#define BGMAC_TX_GOOD_PKTS 0x308 ++#define BGMAC_TX_OCTETS 0x30c ++#define BGMAC_TX_OCTETS_HIGH 0x310 ++#define BGMAC_TX_PKTS 0x314 ++#define BGMAC_TX_BROADCAST_PKTS 0x318 ++#define BGMAC_TX_MULTICAST_PKTS 0x31c ++#define BGMAC_TX_LEN_64 0x320 ++#define BGMAC_TX_LEN_65_TO_127 0x324 ++#define BGMAC_TX_LEN_128_TO_255 0x328 ++#define BGMAC_TX_LEN_256_TO_511 0x32c ++#define BGMAC_TX_LEN_512_TO_1023 0x330 ++#define BGMAC_TX_LEN_1024_TO_1522 0x334 ++#define BGMAC_TX_LEN_1523_TO_2047 0x338 ++#define BGMAC_TX_LEN_2048_TO_4095 0x33c ++#define BGMAC_TX_LEN_4095_TO_8191 0x340 ++#define BGMAC_TX_LEN_8192_TO_MAX 0x344 ++#define BGMAC_TX_JABBER_PKTS 0x348 /* Error */ ++#define BGMAC_TX_OVERSIZE_PKTS 0x34c /* Error */ ++#define BGMAC_TX_FRAGMENT_PKTS 0x350 ++#define BGMAC_TX_UNDERRUNS 0x354 /* Error */ ++#define BGMAC_TX_TOTAL_COLS 0x358 ++#define BGMAC_TX_SINGLE_COLS 0x35c ++#define BGMAC_TX_MULTIPLE_COLS 0x360 ++#define BGMAC_TX_EXCESSIVE_COLS 0x364 /* Error */ ++#define BGMAC_TX_LATE_COLS 0x368 /* Error */ ++#define BGMAC_TX_DEFERED 0x36c ++#define BGMAC_TX_CARRIER_LOST 0x370 ++#define BGMAC_TX_PAUSE_PKTS 0x374 ++#define BGMAC_TX_UNI_PKTS 0x378 ++#define BGMAC_TX_Q0_PKTS 0x37c ++#define BGMAC_TX_Q0_OCTETS 0x380 ++#define BGMAC_TX_Q0_OCTETS_HIGH 0x384 ++#define BGMAC_TX_Q1_PKTS 0x388 ++#define BGMAC_TX_Q1_OCTETS 0x38c ++#define BGMAC_TX_Q1_OCTETS_HIGH 0x390 ++#define BGMAC_TX_Q2_PKTS 0x394 ++#define BGMAC_TX_Q2_OCTETS 0x398 ++#define BGMAC_TX_Q2_OCTETS_HIGH 0x39c ++#define BGMAC_TX_Q3_PKTS 0x3a0 ++#define BGMAC_TX_Q3_OCTETS 0x3a4 ++#define BGMAC_TX_Q3_OCTETS_HIGH 0x3a8 ++#define BGMAC_RX_GOOD_OCTETS 0x3b0 ++#define BGMAC_RX_GOOD_OCTETS_HIGH 0x3b4 ++#define BGMAC_RX_GOOD_PKTS 0x3b8 ++#define BGMAC_RX_OCTETS 0x3bc ++#define BGMAC_RX_OCTETS_HIGH 0x3c0 ++#define BGMAC_RX_PKTS 0x3c4 ++#define BGMAC_RX_BROADCAST_PKTS 0x3c8 ++#define BGMAC_RX_MULTICAST_PKTS 0x3cc ++#define BGMAC_RX_LEN_64 0x3d0 ++#define BGMAC_RX_LEN_65_TO_127 0x3d4 ++#define BGMAC_RX_LEN_128_TO_255 0x3d8 ++#define BGMAC_RX_LEN_256_TO_511 0x3dc ++#define BGMAC_RX_LEN_512_TO_1023 0x3e0 ++#define BGMAC_RX_LEN_1024_TO_1522 0x3e4 ++#define BGMAC_RX_LEN_1523_TO_2047 0x3e8 ++#define BGMAC_RX_LEN_2048_TO_4095 0x3ec ++#define BGMAC_RX_LEN_4095_TO_8191 0x3f0 ++#define BGMAC_RX_LEN_8192_TO_MAX 0x3f4 ++#define BGMAC_RX_JABBER_PKTS 0x3f8 /* Error */ ++#define BGMAC_RX_OVERSIZE_PKTS 0x3fc /* Error */ ++#define BGMAC_RX_FRAGMENT_PKTS 0x400 ++#define BGMAC_RX_MISSED_PKTS 0x404 /* Error */ ++#define BGMAC_RX_CRC_ALIGN_ERRS 0x408 /* Error */ ++#define BGMAC_RX_UNDERSIZE 0x40c /* Error */ ++#define BGMAC_RX_CRC_ERRS 0x410 /* Error */ ++#define BGMAC_RX_ALIGN_ERRS 0x414 /* Error */ ++#define BGMAC_RX_SYMBOL_ERRS 0x418 /* Error */ ++#define BGMAC_RX_PAUSE_PKTS 0x41c ++#define BGMAC_RX_NONPAUSE_PKTS 0x420 ++#define BGMAC_RX_SACHANGES 0x424 ++#define BGMAC_RX_UNI_PKTS 0x428 ++#define BGMAC_UNIMAC_VERSION 0x800 ++#define BGMAC_HDBKP_CTL 0x804 ++#define BGMAC_CMDCFG 0x808 /* Configuration */ ++#define BGMAC_CMDCFG_TE 0x00000001 /* Set to activate TX */ ++#define BGMAC_CMDCFG_RE 0x00000002 /* Set to activate RX */ ++#define BGMAC_CMDCFG_ES_MASK 0x0000000c /* Ethernet speed see gmac_speed */ ++#define BGMAC_CMDCFG_ES_10 0x00000000 ++#define BGMAC_CMDCFG_ES_100 0x00000004 ++#define BGMAC_CMDCFG_ES_1000 0x00000008 ++#define BGMAC_CMDCFG_PROM 0x00000010 /* Set to activate promiscuous mode */ ++#define BGMAC_CMDCFG_PAD_EN 0x00000020 ++#define BGMAC_CMDCFG_CF 0x00000040 ++#define BGMAC_CMDCFG_PF 0x00000080 ++#define BGMAC_CMDCFG_RPI 0x00000100 /* Unset to enable 802.3x tx flow control */ ++#define BGMAC_CMDCFG_TAI 0x00000200 ++#define BGMAC_CMDCFG_HD 0x00000400 /* Set if in half duplex mode */ ++#define BGMAC_CMDCFG_HD_SHIFT 10 ++#define BGMAC_CMDCFG_SR 0x00000800 /* Set to reset mode */ ++#define BGMAC_CMDCFG_ML 0x00008000 /* Set to activate mac loopback mode */ ++#define BGMAC_CMDCFG_AE 0x00400000 ++#define BGMAC_CMDCFG_CFE 0x00800000 ++#define BGMAC_CMDCFG_NLC 0x01000000 ++#define BGMAC_CMDCFG_RL 0x02000000 ++#define BGMAC_CMDCFG_RED 0x04000000 ++#define BGMAC_CMDCFG_PE 0x08000000 ++#define BGMAC_CMDCFG_TPI 0x10000000 ++#define BGMAC_CMDCFG_AT 0x20000000 ++#define BGMAC_MACADDR_HIGH 0x80c /* High 4 octets of own mac address */ ++#define BGMAC_MACADDR_LOW 0x810 /* Low 2 octets of own mac address */ ++#define BGMAC_RXMAX_LENGTH 0x814 /* Max receive frame length with vlan tag */ ++#define BGMAC_PAUSEQUANTA 0x818 ++#define BGMAC_MAC_MODE 0x844 ++#define BGMAC_OUTERTAG 0x848 ++#define BGMAC_INNERTAG 0x84c ++#define BGMAC_TXIPG 0x85c ++#define BGMAC_PAUSE_CTL 0xb30 ++#define BGMAC_TX_FLUSH 0xb34 ++#define BGMAC_RX_STATUS 0xb38 ++#define BGMAC_TX_STATUS 0xb3c ++ ++#define BGMAC_PHY_CTL 0x00 ++#define BGMAC_PHY_CTL_SPEED_MSB 0x0040 ++#define BGMAC_PHY_CTL_DUPLEX 0x0100 /* duplex mode */ ++#define BGMAC_PHY_CTL_RESTART 0x0200 /* restart autonegotiation */ ++#define BGMAC_PHY_CTL_ANENAB 0x1000 /* enable autonegotiation */ ++#define BGMAC_PHY_CTL_SPEED 0x2000 ++#define BGMAC_PHY_CTL_LOOP 0x4000 /* loopback */ ++#define BGMAC_PHY_CTL_RESET 0x8000 /* reset */ ++/* Helpers */ ++#define BGMAC_PHY_CTL_SPEED_10 0 ++#define BGMAC_PHY_CTL_SPEED_100 BGMAC_PHY_CTL_SPEED ++#define BGMAC_PHY_CTL_SPEED_1000 BGMAC_PHY_CTL_SPEED_MSB ++#define BGMAC_PHY_ADV 0x04 ++#define BGMAC_PHY_ADV_10HALF 0x0020 /* advertise 10MBits/s half duplex */ ++#define BGMAC_PHY_ADV_10FULL 0x0040 /* advertise 10MBits/s full duplex */ ++#define BGMAC_PHY_ADV_100HALF 0x0080 /* advertise 100MBits/s half duplex */ ++#define BGMAC_PHY_ADV_100FULL 0x0100 /* advertise 100MBits/s full duplex */ ++#define BGMAC_PHY_ADV2 0x09 ++#define BGMAC_PHY_ADV2_1000HALF 0x0100 /* advertise 1000MBits/s half duplex */ ++#define BGMAC_PHY_ADV2_1000FULL 0x0200 /* advertise 1000MBits/s full duplex */ ++ ++/* BCMA GMAC core specific IO Control (BCMA_IOCTL) flags */ ++#define BGMAC_BCMA_IOCTL_SW_CLKEN 0x00000004 /* PHY Clock Enable */ ++#define BGMAC_BCMA_IOCTL_SW_RESET 0x00000008 /* PHY Reset */ ++ ++/* BCMA GMAC core specific IO status (BCMA_IOST) flags */ ++#define BGMAC_BCMA_IOST_ATTACHED 0x00000800 ++ ++#define BGMAC_NUM_MIB_TX_REGS \ ++ (((BGMAC_TX_Q3_OCTETS_HIGH - BGMAC_TX_GOOD_OCTETS) / 4) + 1) ++#define BGMAC_NUM_MIB_RX_REGS \ ++ (((BGMAC_RX_UNI_PKTS - BGMAC_RX_GOOD_OCTETS) / 4) + 1) ++ ++#define BGMAC_DMA_TX_CTL 0x00 ++#define BGMAC_DMA_TX_ENABLE 0x00000001 ++#define BGMAC_DMA_TX_SUSPEND 0x00000002 ++#define BGMAC_DMA_TX_LOOPBACK 0x00000004 ++#define BGMAC_DMA_TX_FLUSH 0x00000010 ++#define BGMAC_DMA_TX_PARITY_DISABLE 0x00000800 ++#define BGMAC_DMA_TX_ADDREXT_MASK 0x00030000 ++#define BGMAC_DMA_TX_ADDREXT_SHIFT 16 ++#define BGMAC_DMA_TX_INDEX 0x04 ++#define BGMAC_DMA_TX_RINGLO 0x08 ++#define BGMAC_DMA_TX_RINGHI 0x0C ++#define BGMAC_DMA_TX_STATUS 0x10 ++#define BGMAC_DMA_TX_STATDPTR 0x00001FFF ++#define BGMAC_DMA_TX_STAT 0xF0000000 ++#define BGMAC_DMA_TX_STAT_DISABLED 0x00000000 ++#define BGMAC_DMA_TX_STAT_ACTIVE 0x10000000 ++#define BGMAC_DMA_TX_STAT_IDLEWAIT 0x20000000 ++#define BGMAC_DMA_TX_STAT_STOPPED 0x30000000 ++#define BGMAC_DMA_TX_STAT_SUSP 0x40000000 ++#define BGMAC_DMA_TX_ERROR 0x14 ++#define BGMAC_DMA_TX_ERRDPTR 0x0001FFFF ++#define BGMAC_DMA_TX_ERR 0xF0000000 ++#define BGMAC_DMA_TX_ERR_NOERR 0x00000000 ++#define BGMAC_DMA_TX_ERR_PROT 0x10000000 ++#define BGMAC_DMA_TX_ERR_UNDERRUN 0x20000000 ++#define BGMAC_DMA_TX_ERR_TRANSFER 0x30000000 ++#define BGMAC_DMA_TX_ERR_DESCREAD 0x40000000 ++#define BGMAC_DMA_TX_ERR_CORE 0x50000000 ++#define BGMAC_DMA_RX_CTL 0x20 ++#define BGMAC_DMA_RX_ENABLE 0x00000001 ++#define BGMAC_DMA_RX_FRAME_OFFSET_MASK 0x000000FE ++#define BGMAC_DMA_RX_FRAME_OFFSET_SHIFT 1 ++#define BGMAC_DMA_RX_DIRECT_FIFO 0x00000100 ++#define BGMAC_DMA_RX_OVERFLOW_CONT 0x00000400 ++#define BGMAC_DMA_RX_PARITY_DISABLE 0x00000800 ++#define BGMAC_DMA_RX_ADDREXT_MASK 0x00030000 ++#define BGMAC_DMA_RX_ADDREXT_SHIFT 16 ++#define BGMAC_DMA_RX_INDEX 0x24 ++#define BGMAC_DMA_RX_RINGLO 0x28 ++#define BGMAC_DMA_RX_RINGHI 0x2C ++#define BGMAC_DMA_RX_STATUS 0x30 ++#define BGMAC_DMA_RX_STATDPTR 0x00001FFF ++#define BGMAC_DMA_RX_STAT 0xF0000000 ++#define BGMAC_DMA_RX_STAT_DISABLED 0x00000000 ++#define BGMAC_DMA_RX_STAT_ACTIVE 0x10000000 ++#define BGMAC_DMA_RX_STAT_IDLEWAIT 0x20000000 ++#define BGMAC_DMA_RX_STAT_STOPPED 0x30000000 ++#define BGMAC_DMA_RX_STAT_SUSP 0x40000000 ++#define BGMAC_DMA_RX_ERROR 0x34 ++#define BGMAC_DMA_RX_ERRDPTR 0x0001FFFF ++#define BGMAC_DMA_RX_ERR 0xF0000000 ++#define BGMAC_DMA_RX_ERR_NOERR 0x00000000 ++#define BGMAC_DMA_RX_ERR_PROT 0x10000000 ++#define BGMAC_DMA_RX_ERR_UNDERRUN 0x20000000 ++#define BGMAC_DMA_RX_ERR_TRANSFER 0x30000000 ++#define BGMAC_DMA_RX_ERR_DESCREAD 0x40000000 ++#define BGMAC_DMA_RX_ERR_CORE 0x50000000 ++ ++#define BGMAC_DESC_CTL0_EOT 0x10000000 /* End of ring */ ++#define BGMAC_DESC_CTL0_IOC 0x20000000 /* IRQ on complete */ ++#define BGMAC_DESC_CTL0_SOF 0x40000000 /* Start of frame */ ++#define BGMAC_DESC_CTL0_EOF 0x80000000 /* End of frame */ ++#define BGMAC_DESC_CTL1_LEN 0x00001FFF ++ ++#define BGMAC_PHY_NOREGS 0x1E ++#define BGMAC_PHY_MASK 0x1F ++ ++#define BGMAC_MAX_TX_RINGS 4 ++#define BGMAC_MAX_RX_RINGS 1 ++ ++#define BGMAC_TX_RING_SLOTS 128 ++#define BGMAC_RX_RING_SLOTS 512 - 1 /* Why -1? Well, Broadcom does that... */ ++ ++#define BGMAC_RX_HEADER_LEN 28 /* Last 24 bytes are unused. Well... */ ++#define BGMAC_RX_FRAME_OFFSET 30 /* There are 2 unused bytes between header and real data */ ++#define BGMAC_RX_MAX_FRAME_SIZE 1536 /* Copied from b44/tg3 */ ++#define BGMAC_RX_BUF_SIZE (BGMAC_RX_FRAME_OFFSET + BGMAC_RX_MAX_FRAME_SIZE) ++ ++#define BGMAC_BFL_ENETROBO 0x0010 /* has ephy roboswitch spi */ ++#define BGMAC_BFL_ENETADM 0x0080 /* has ADMtek switch */ ++#define BGMAC_BFL_ENETVLAN 0x0100 /* can do vlan */ ++ ++#define BGMAC_CHIPCTL_1_IF_TYPE_MASK 0x00000030 ++#define BGMAC_CHIPCTL_1_IF_TYPE_RMII 0x00000000 ++#define BGMAC_CHIPCTL_1_IF_TYPE_MI 0x00000010 ++#define BGMAC_CHIPCTL_1_IF_TYPE_RGMII 0x00000020 ++#define BGMAC_CHIPCTL_1_SW_TYPE_MASK 0x000000C0 ++#define BGMAC_CHIPCTL_1_SW_TYPE_EPHY 0x00000000 ++#define BGMAC_CHIPCTL_1_SW_TYPE_EPHYMII 0x00000040 ++#define BGMAC_CHIPCTL_1_SW_TYPE_EPHYRMII 0x00000080 ++#define BGMAC_CHIPCTL_1_SW_TYPE_RGMI 0x000000C0 ++#define BGMAC_CHIPCTL_1_RXC_DLL_BYPASS 0x00010000 ++ ++#define BGMAC_SPEED_10 0x0001 ++#define BGMAC_SPEED_100 0x0002 ++#define BGMAC_SPEED_1000 0x0004 ++ ++struct bgmac_slot_info { ++ struct sk_buff *skb; ++ dma_addr_t dma_addr; ++}; ++ ++struct bgmac_dma_desc { ++ __le32 ctl0; ++ __le32 ctl1; ++ __le32 addr_low; ++ __le32 addr_high; ++} __packed; ++ ++struct bgmac_dma_ring { ++ bool tx; ++ u16 num_slots; ++ u16 start; ++ u16 end; ++ ++ u16 mmio_base; ++ void *cpu_base; ++ dma_addr_t dma_base; ++ ++ struct bgmac_slot_info slots[BGMAC_RX_RING_SLOTS]; ++}; ++ ++struct bgmac_rx_header { ++ __le16 len; ++ __le16 flags; ++ __le16 pad[12]; ++}; ++ ++struct bgmac { ++ struct bcma_device *core; ++ struct bcma_device *cmn; /* Reference to CMN core for BCM4706 */ ++ struct net_device *net_dev; ++ ++ u8 phyaddr; ++ bool has_robosw; ++ ++ u32 int_mask; ++ u32 int_status; ++ ++ bool loopback; ++ ++ bool autoneg; ++ bool full_duplex; ++ int speed; ++ ++ /* DMA */ ++ struct bgmac_dma_ring tx_ring[BGMAC_MAX_TX_RINGS]; ++ struct bgmac_dma_ring rx_ring[BGMAC_MAX_RX_RINGS]; ++ ++ /* Stats */ ++ bool stats_grabbed; ++ u32 mib_tx_regs[BGMAC_NUM_MIB_TX_REGS]; ++ u32 mib_rx_regs[BGMAC_NUM_MIB_RX_REGS]; ++}; ++ ++static inline u32 bgmac_read(struct bgmac *bgmac, u16 offset) ++{ ++ return bcma_read32(bgmac->core, offset); ++} ++ ++static inline void bgmac_write(struct bgmac *bgmac, u16 offset, u32 value) ++{ ++ bcma_write32(bgmac->core, offset, value); ++} ++ ++static inline void bgmac_maskset(struct bgmac *bgmac, u16 offset, u32 mask, ++ u32 set) ++{ ++ bgmac_write(bgmac, offset, (bgmac_read(bgmac, offset) & mask) | set); ++} ++ ++static inline void bgmac_mask(struct bgmac *bgmac, u16 offset, u32 mask) ++{ ++ bgmac_maskset(bgmac, offset, mask, 0); ++} ++ ++static inline void bgmac_set(struct bgmac *bgmac, u16 offset, u32 set) ++{ ++ bgmac_maskset(bgmac, offset, ~0, set); ++} ++ ++u16 bgmac_phy_read(struct bgmac *bgmac, u8 phyaddr, u8 reg); ++void bgmac_phy_write(struct bgmac *bgmac, u8 phyaddr, u8 reg, u16 value); ++ ++#endif /* _BGMAC_H */ +--- a/include/linux/bcma/bcma_driver_chipcommon.h ++++ b/include/linux/bcma/bcma_driver_chipcommon.h +@@ -627,4 +627,6 @@ int bcma_nflash_erase(struct bcma_drv_cc + int bcma_nflash_commit(struct bcma_drv_cc *cc, u32 offset, u32 len, const u8 *buf); + #endif + ++extern u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc); ++ + #endif /* LINUX_BCMA_DRIVER_CC_H_ */ diff --git a/target/linux/generic/config-3.6 b/target/linux/generic/config-3.6 index 4e3eb6a49..c44062292 100644 --- a/target/linux/generic/config-3.6 +++ b/target/linux/generic/config-3.6 @@ -205,6 +205,7 @@ CONFIG_BCMA_POSSIBLE=y # CONFIG_BE2NET is not set # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set +# CONFIG_BGMAC is not set # CONFIG_BINARY_PRINTF is not set # CONFIG_BINFMT_AOUT is not set CONFIG_BINFMT_ELF=y diff --git a/target/linux/generic/config-3.7 b/target/linux/generic/config-3.7 index 7c5d2b42f..8e7a45027 100644 --- a/target/linux/generic/config-3.7 +++ b/target/linux/generic/config-3.7 @@ -209,6 +209,7 @@ CONFIG_BCMA_POSSIBLE=y # CONFIG_BE2NET is not set # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set +# CONFIG_BGMAC is not set # CONFIG_BINARY_PRINTF is not set # CONFIG_BINFMT_AOUT is not set CONFIG_BINFMT_ELF=y |