diff options
Diffstat (limited to 'target/linux')
| -rw-r--r-- | target/linux/ramips/files/drivers/net/ramips_esw.c | 52 |
1 files changed, 49 insertions, 3 deletions
diff --git a/target/linux/ramips/files/drivers/net/ramips_esw.c b/target/linux/ramips/files/drivers/net/ramips_esw.c index 7aa5fd151..18e5fa57d 100644 --- a/target/linux/ramips/files/drivers/net/ramips_esw.c +++ b/target/linux/ramips/files/drivers/net/ramips_esw.c @@ -37,6 +37,20 @@ #define RT305X_ESW_VMSC_MSC_M 0xff #define RT305X_ESW_VMSC_MSC_S 8 +#define RT305X_ESW_SOCPC_DISUN2CPU_S 0 +#define RT305X_ESW_SOCPC_DISMC2CPU_S 8 +#define RT305X_ESW_SOCPC_DISBC2CPU_S 16 +#define RT305X_ESW_SOCPC_CRC_PADDING BIT(25) + +#define RT305X_ESW_POC1_EN_BP_S 0 +#define RT305X_ESW_POC1_EN_FC_S 8 +#define RT305X_ESW_POC1_DIS_RMC2CPU_S 16 +#define RT305X_ESW_POC1_DIS_PORT_S 23 + +#define RT305X_ESW_POC3_UNTAG_EN_S 0 +#define RT305X_ESW_POC3_ENAGING_S 8 +#define RT305X_ESW_POC3_DIS_UC_PAUSE_S 16 + #define RT305X_ESW_PORT0 0 #define RT305X_ESW_PORT1 1 #define RT305X_ESW_PORT2 2 @@ -45,6 +59,19 @@ #define RT305X_ESW_PORT5 5 #define RT305X_ESW_PORT6 6 +#define RT305X_ESW_PORTS_INTERNAL \ + (BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT1) | \ + BIT(RT305X_ESW_PORT2) | BIT(RT305X_ESW_PORT3) | \ + BIT(RT305X_ESW_PORT4)) + +#define RT305X_ESW_PORTS_NOCPU \ + (RT305X_ESW_PORTS_INTERNAL | BIT(RT305X_ESW_PORT5)) + +#define RT305X_ESW_PORTS_CPU BIT(RT305X_ESW_PORT6) + +#define RT305X_ESW_PORTS_ALL \ + (RT305X_ESW_PORTS_NOCPU | RT305X_ESW_PORTS_CPU) + struct rt305x_esw { void __iomem *base; struct rt305x_esw_platform_data *pdata; @@ -170,11 +197,30 @@ rt305x_esw_hw_init(struct rt305x_esw *esw) rt305x_esw_wr(esw, 0xC8A07850, RT305X_ESW_REG_FCT0); rt305x_esw_wr(esw, 0x00000000, RT305X_ESW_REG_SGC2); rt305x_esw_wr(esw, 0x00405555, RT305X_ESW_REG_PFC1); - rt305x_esw_wr(esw, 0x00007f7f, RT305X_ESW_REG_POC1); - rt305x_esw_wr(esw, 0x00007f3f, RT305X_ESW_REG_POC3); + + /* Enable Back Pressure, and Flow Control */ + rt305x_esw_wr(esw, + ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC1_EN_BP_S) | + (RT305X_ESW_PORTS_ALL << RT305X_ESW_POC1_EN_FC_S)), + RT305X_ESW_REG_POC1); + + /* Enable Aging, and VLAN TAG removal */ + rt305x_esw_wr(esw, + ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC3_ENAGING_S) | + (RT305X_ESW_PORTS_NOCPU << RT305X_ESW_POC3_UNTAG_EN_S)), + RT305X_ESW_REG_POC3); + rt305x_esw_wr(esw, 0x00d6500c, RT305X_ESW_REG_FCT2); rt305x_esw_wr(esw, 0x0008a301, RT305X_ESW_REG_SGC); - rt305x_esw_wr(esw, 0x02404040, RT305X_ESW_REG_SOCPC); + + /* Setup SoC Port control register */ + rt305x_esw_wr(esw, + (RT305X_ESW_SOCPC_CRC_PADDING | + (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISUN2CPU_S) | + (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISMC2CPU_S) | + (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISBC2CPU_S)), + RT305X_ESW_REG_SOCPC); + rt305x_esw_set_pvid(esw, RT305X_ESW_PORT4, 2); rt305x_esw_set_pvid(esw, RT305X_ESW_PORT5, 1); rt305x_esw_wr(esw, 0x3f502b28, RT305X_ESW_REG_FPA2); |