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-rw-r--r--target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/Makefile42
-rw-r--r--target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/dummy.c4
-rw-r--r--target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/head.S85
-rw-r--r--target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/ld.script151
-rw-r--r--target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/misc.c242
-rw-r--r--target/linux/xburst/files-2.6.32/arch/mips/boot/tools/entry12
-rw-r--r--target/linux/xburst/files-2.6.32/arch/mips/boot/tools/filesize7
-rw-r--r--target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/board-n516.h39
-rw-r--r--target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/board-qi_lb60.h51
-rw-r--r--target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/clock.h31
-rw-r--r--target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/dma.h90
-rw-r--r--target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/gpio.h393
-rw-r--r--target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/irq.h55
-rw-r--r--target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/jz4740.h35
-rw-r--r--target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/platform.h34
-rw-r--r--target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/regs.h519
-rw-r--r--target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/serial.h30
-rw-r--r--target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/timer.h22
-rw-r--r--target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/war.h25
-rw-r--r--target/linux/xburst/files-2.6.32/arch/mips/jz4740/Kconfig40
-rw-r--r--target/linux/xburst/files-2.6.32/arch/mips/jz4740/Makefile21
-rw-r--r--target/linux/xburst/files-2.6.32/arch/mips/jz4740/board-n516-display.c395
-rw-r--r--target/linux/xburst/files-2.6.32/arch/mips/jz4740/board-n516.c201
-rw-r--r--target/linux/xburst/files-2.6.32/arch/mips/jz4740/board-n526.c333
-rw-r--r--target/linux/xburst/files-2.6.32/arch/mips/jz4740/board-qi_lb60.c424
-rw-r--r--target/linux/xburst/files-2.6.32/arch/mips/jz4740/clock-debugfs.c109
-rw-r--r--target/linux/xburst/files-2.6.32/arch/mips/jz4740/clock.c930
-rw-r--r--target/linux/xburst/files-2.6.32/arch/mips/jz4740/clock.h75
-rw-r--r--target/linux/xburst/files-2.6.32/arch/mips/jz4740/dma.c339
-rw-r--r--target/linux/xburst/files-2.6.32/arch/mips/jz4740/gpio.c540
-rw-r--r--target/linux/xburst/files-2.6.32/arch/mips/jz4740/irq.c166
-rw-r--r--target/linux/xburst/files-2.6.32/arch/mips/jz4740/platform.c246
-rw-r--r--target/linux/xburst/files-2.6.32/arch/mips/jz4740/pm.c65
-rw-r--r--target/linux/xburst/files-2.6.32/arch/mips/jz4740/prom.c111
-rw-r--r--target/linux/xburst/files-2.6.32/arch/mips/jz4740/reset.c52
-rw-r--r--target/linux/xburst/files-2.6.32/arch/mips/jz4740/setup.c97
-rw-r--r--target/linux/xburst/files-2.6.32/arch/mips/jz4740/time.c256
37 files changed, 0 insertions, 6267 deletions
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/Makefile b/target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/Makefile
deleted file mode 100644
index 90f36e63c..000000000
--- a/target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/Makefile
+++ /dev/null
@@ -1,42 +0,0 @@
-#
-# linux/arch/mips/boot/compressed/Makefile
-#
-# create a compressed zImage from the original vmlinux
-#
-
-targets := zImage vmlinuz vmlinux.bin.gz head.o misc.o piggy.o dummy.o
-
-OBJS := $(obj)/head.o $(obj)/misc.o
-
-LD_ARGS := -T $(obj)/ld.script -Ttext 0x80600000 -Bstatic
-OBJCOPY_ARGS := -O elf32-tradlittlemips
-
-ENTRY := $(obj)/../tools/entry
-FILESIZE := $(obj)/../tools/filesize
-
-drop-sections = .reginfo .mdebug .comment .note .pdr .options .MIPS.options
-strip-flags = $(addprefix --remove-section=,$(drop-sections))
-
-
-$(obj)/vmlinux.bin.gz: vmlinux
- rm -f $(obj)/vmlinux.bin.gz
- $(OBJCOPY) -O binary $(strip-flags) vmlinux $(obj)/vmlinux.bin
- gzip -v9f $(obj)/vmlinux.bin
-
-$(obj)/head.o: $(obj)/head.S $(obj)/vmlinux.bin.gz vmlinux
- $(CC) $(KBUILD_AFLAGS) \
- -DIMAGESIZE=$(shell sh $(FILESIZE) $(obj)/vmlinux.bin.gz) \
- -DKERNEL_ENTRY=$(shell sh $(ENTRY) $(NM) vmlinux ) \
- -DLOADADDR=$(loadaddr) \
- -c -o $(obj)/head.o $<
-
-$(obj)/vmlinuz: $(OBJS) $(obj)/ld.script $(obj)/vmlinux.bin.gz $(obj)/dummy.o
- $(OBJCOPY) \
- --add-section=.image=$(obj)/vmlinux.bin.gz \
- --set-section-flags=.image=contents,alloc,load,readonly,data \
- $(obj)/dummy.o $(obj)/piggy.o
- $(LD) $(LD_ARGS) -o $@ $(OBJS) $(obj)/piggy.o
- $(OBJCOPY) $(OBJCOPY_ARGS) $@ $@ -R .comment -R .stab -R .stabstr -R .initrd -R .sysmap
-
-zImage: $(obj)/vmlinuz
- $(OBJCOPY) -O binary $(obj)/vmlinuz $(obj)/zImage
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/dummy.c b/target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/dummy.c
deleted file mode 100644
index 31dbf45bf..000000000
--- a/target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/dummy.c
+++ /dev/null
@@ -1,4 +0,0 @@
-int main(void)
-{
- return 0;
-}
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/head.S b/target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/head.S
deleted file mode 100644
index d9700eb50..000000000
--- a/target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/head.S
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * linux/arch/mips/boot/compressed/head.S
- *
- * Copyright (C) 2005-2008 Ingenic Semiconductor Inc.
- */
-
-#include <asm/asm.h>
-#include <asm/cacheops.h>
-#include <asm/cachectl.h>
-#include <asm/regdef.h>
-
-#define IndexInvalidate_I 0x00
-#define IndexWriteBack_D 0x01
-
- .set noreorder
- LEAF(startup)
-startup:
- move s0, a0 /* Save the boot loader transfered args */
- move s1, a1
- move s2, a2
- move s3, a3
-
- la a0, _edata
- la a1, _end
-1: sw zero, 0(a0) /* Clear BSS section */
- bne a1, a0, 1b
- addu a0, 4
-
- la sp, (.stack + 8192)
-
- la a0, __image_begin
- la a1, IMAGESIZE
- la a2, LOADADDR
- la ra, 1f
- la k0, decompress_kernel
- jr k0
- nop
-1:
-
- move a0, s0
- move a1, s1
- move a2, s2
- move a3, s3
- li k0, KERNEL_ENTRY
- jr k0
- nop
-2:
- b 32
- END(startup)
-
-
- LEAF(flushcaches)
- la t0, 1f
- la t1, 0xa0000000
- or t0, t0, t1
- jr t0
- nop
-1:
- li k0, 0x80000000 # start address
- li k1, 0x80004000 # end address (16KB I-Cache)
- subu k1, 128
-
-2:
- .set mips3
- cache IndexWriteBack_D, 0(k0)
- cache IndexWriteBack_D, 32(k0)
- cache IndexWriteBack_D, 64(k0)
- cache IndexWriteBack_D, 96(k0)
- cache IndexInvalidate_I, 0(k0)
- cache IndexInvalidate_I, 32(k0)
- cache IndexInvalidate_I, 64(k0)
- cache IndexInvalidate_I, 96(k0)
- .set mips0
-
- bne k0, k1, 2b
- addu k0, k0, 128
- la t0, 3f
- jr t0
- nop
-3:
- jr ra
- nop
- END(flushcaches)
-
- .comm .stack,4096*2,4
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/ld.script b/target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/ld.script
deleted file mode 100644
index fcf8ba041..000000000
--- a/target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/ld.script
+++ /dev/null
@@ -1,151 +0,0 @@
-OUTPUT_ARCH(mips)
-ENTRY(startup)
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
-
- .init : { *(.init) } =0
- .text :
- {
- _ftext = . ;
- *(.text)
- *(.rodata)
- *(.rodata1)
- /* .gnu.warning sections are handled specially by elf32.em. */
- *(.gnu.warning)
- } =0
- .kstrtab : { *(.kstrtab) }
-
- . = ALIGN(16); /* Exception table */
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- __start___dbe_table = .; /* Exception table for data bus errors */
- __dbe_table : { *(__dbe_table) }
- __stop___dbe_table = .;
-
- __start___ksymtab = .; /* Kernel symbol table */
- __ksymtab : { *(__ksymtab) }
- __stop___ksymtab = .;
-
- _etext = .;
-
- . = ALIGN(8192);
- .data.init_task : { *(.data.init_task) }
-
- /* Startup code */
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(16);
- __setup_start = .;
- .setup.init : { *(.setup.init) }
- __setup_end = .;
- __initcall_start = .;
- .initcall.init : { *(.initcall.init) }
- __initcall_end = .;
- . = ALIGN(4096); /* Align double page for init_task_union */
- __init_end = .;
-
- . = ALIGN(4096);
- .data.page_aligned : { *(.data.idt) }
-
- . = ALIGN(32);
- .data.cacheline_aligned : { *(.data.cacheline_aligned) }
-
- .fini : { *(.fini) } =0
- .reginfo : { *(.reginfo) }
- /* Adjust the address for the data segment. We want to adjust up to
- the same address within the page on the next page up. It would
- be more correct to do this:
- . = .;
- The current expression does not correctly handle the case of a
- text segment ending precisely at the end of a page; it causes the
- data segment to skip a page. The above expression does not have
- this problem, but it will currently (2/95) cause BFD to allocate
- a single segment, combining both text and data, for this case.
- This will prevent the text segment from being shared among
- multiple executions of the program; I think that is more
- important than losing a page of the virtual address space (note
- that no actual memory is lost; the page which is skipped can not
- be referenced). */
- . = .;
- .data :
- {
- _fdata = . ;
- *(.data)
-
- /* Put the compressed image here, so bss is on the end. */
- __image_begin = .;
- *(.image)
- __image_end = .;
- /* Align the initial ramdisk image (INITRD) on page boundaries. */
- . = ALIGN(4096);
- __ramdisk_begin = .;
- *(.initrd)
- __ramdisk_end = .;
- . = ALIGN(4096);
-
- CONSTRUCTORS
- }
- .data1 : { *(.data1) }
- _gp = . + 0x8000;
- .lit8 : { *(.lit8) }
- .lit4 : { *(.lit4) }
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
- .got : { *(.got.plt) *(.got) }
- .dynamic : { *(.dynamic) }
- /* We want the small data sections together, so single-instruction offsets
- can access them all, and initialized data all before uninitialized, so
- we can shorten the on-disk segment size. */
- .sdata : { *(.sdata) }
- . = ALIGN(4);
- _edata = .;
- PROVIDE (edata = .);
-
- __bss_start = .;
- _fbss = .;
- .sbss : { *(.sbss) *(.scommon) }
- .bss :
- {
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- _end = . ;
- PROVIDE (end = .);
- }
-
- /* Sections to be discarded */
- /DISCARD/ :
- {
- *(.text.exit)
- *(.data.exit)
- *(.exitcall.exit)
- }
-
- /* This is the MIPS specific mdebug section. */
- .mdebug : { *(.mdebug) }
- /* These are needed for ELF backends which have not yet been
- converted to the new style linker. */
- .stab 0 : { *(.stab) }
- .stabstr 0 : { *(.stabstr) }
- /* DWARF debug sections.
- Symbols in the .debug DWARF section are relative to the beginning of the
- section so we begin .debug at 0. It's not clear yet what needs to happen
- for the others. */
- .debug 0 : { *(.debug) }
- .debug_srcinfo 0 : { *(.debug_srcinfo) }
- .debug_aranges 0 : { *(.debug_aranges) }
- .debug_pubnames 0 : { *(.debug_pubnames) }
- .debug_sfnames 0 : { *(.debug_sfnames) }
- .line 0 : { *(.line) }
- /* These must appear regardless of . */
- .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }
- .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }
- .comment : { *(.comment) }
- .note : { *(.note) }
-}
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/misc.c b/target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/misc.c
deleted file mode 100644
index 2309feea3..000000000
--- a/target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/misc.c
+++ /dev/null
@@ -1,242 +0,0 @@
-/*
- * linux/arch/mips/boot/compressed/misc.c
- *
- * This is a collection of several routines from gzip-1.0.3
- * adapted for Linux.
- *
- * malloc by Hannu Savolainen 1993 and Matthias Urlichs 1994
- *
- * Adapted for JZSOC by Peter Wei, 2008
- *
- */
-
-#define size_t int
-#define NULL 0
-
-/*
- * gzip declarations
- */
-
-#define OF(args) args
-#define STATIC static
-
-#undef memset
-#undef memcpy
-#define memzero(s, n) memset ((s), 0, (n))
-
-typedef unsigned char uch;
-typedef unsigned short ush;
-typedef unsigned long ulg;
-
-#define WSIZE 0x8000 /* Window size must be at least 32k, */
- /* and a power of two */
-
-static uch *inbuf; /* input buffer */
-static uch window[WSIZE]; /* Sliding window buffer */
-
-static unsigned insize = 0; /* valid bytes in inbuf */
-static unsigned inptr = 0; /* index of next byte to be processed in inbuf */
-static unsigned outcnt = 0; /* bytes in output buffer */
-
-/* gzip flag byte */
-#define ASCII_FLAG 0x01 /* bit 0 set: file probably ASCII text */
-#define CONTINUATION 0x02 /* bit 1 set: continuation of multi-part gzip file */
-#define EXTRA_FIELD 0x04 /* bit 2 set: extra field present */
-#define ORIG_NAME 0x08 /* bit 3 set: original file name present */
-#define COMMENT 0x10 /* bit 4 set: file comment present */
-#define ENCRYPTED 0x20 /* bit 5 set: file is encrypted */
-#define RESERVED 0xC0 /* bit 6,7: reserved */
-
-#define get_byte() (inptr < insize ? inbuf[inptr++] : fill_inbuf())
-
-/* Diagnostic functions */
-#ifdef DEBUG
-# define Assert(cond,msg) {if(!(cond)) error(msg);}
-# define Trace(x) fprintf x
-# define Tracev(x) {if (verbose) fprintf x ;}
-# define Tracevv(x) {if (verbose>1) fprintf x ;}
-# define Tracec(c,x) {if (verbose && (c)) fprintf x ;}
-# define Tracecv(c,x) {if (verbose>1 && (c)) fprintf x ;}
-#else
-# define Assert(cond,msg)
-# define Trace(x)
-# define Tracev(x)
-# define Tracevv(x)
-# define Tracec(c,x)
-# define Tracecv(c,x)
-#endif
-
-static int fill_inbuf(void);
-static void flush_window(void);
-static void error(char *m);
-static void gzip_mark(void **);
-static void gzip_release(void **);
-
-void* memset(void* s, int c, size_t n);
-void* memcpy(void* __dest, __const void* __src, size_t __n);
-
-extern void flushcaches(void); /* defined in head.S */
-
-char *input_data;
-int input_len;
-
-static long bytes_out = 0;
-static uch *output_data;
-static unsigned long output_ptr = 0;
-
-
-static void *malloc(int size);
-static void free(void *where);
-static void error(char *m);
-static void gzip_mark(void **);
-static void gzip_release(void **);
-
-static void puts(const char *str)
-{
-}
-
-extern unsigned char _end[];
-static unsigned long free_mem_ptr;
-static unsigned long free_mem_end_ptr;
-
-#define HEAP_SIZE 0x10000
-
-#include "../../../../lib/inflate.c"
-
-static void *malloc(int size)
-{
- void *p;
-
- if (size <0) error("Malloc error\n");
- if (free_mem_ptr == 0) error("Memory error\n");
-
- free_mem_ptr = (free_mem_ptr + 3) & ~3; /* Align */
-
- p = (void *)free_mem_ptr;
- free_mem_ptr += size;
-
- if (free_mem_ptr >= free_mem_end_ptr)
- error("\nOut of memory\n");
-
- return p;
-}
-
-static void free(void *where)
-{ /* Don't care */
-}
-
-static void gzip_mark(void **ptr)
-{
- *ptr = (void *) free_mem_ptr;
-}
-
-static void gzip_release(void **ptr)
-{
- free_mem_ptr = (long) *ptr;
-}
-
-void* memset(void* s, int c, size_t n)
-{
- int i;
- char *ss = (char*)s;
-
- for (i=0;i<n;i++) ss[i] = c;
- return s;
-}
-
-void* memcpy(void* __dest, __const void* __src, size_t __n)
-{
- int i = 0;
- unsigned char *d = (unsigned char *)__dest, *s = (unsigned char *)__src;
-
- for (i = __n >> 3; i > 0; i--) {
- *d++ = *s++;
- *d++ = *s++;
- *d++ = *s++;
- *d++ = *s++;
- *d++ = *s++;
- *d++ = *s++;
- *d++ = *s++;
- *d++ = *s++;
- }
-
- if (__n & 1 << 2) {
- *d++ = *s++;
- *d++ = *s++;
- *d++ = *s++;
- *d++ = *s++;
- }
-
- if (__n & 1 << 1) {
- *d++ = *s++;
- *d++ = *s++;
- }
-
- if (__n & 1)
- *d++ = *s++;
-
- return __dest;
-}
-
-/* ===========================================================================
- * Fill the input buffer. This is called only when the buffer is empty
- * and at least one byte is really needed.
- */
-static int fill_inbuf(void)
-{
- if (insize != 0) {
- error("ran out of input data\n");
- }
-
- inbuf = input_data;
- insize = input_len;
- inptr = 1;
- return inbuf[0];
-}
-
-/* ===========================================================================
- * Write the output window window[0..outcnt-1] and update crc and bytes_out.
- * (Used for the decompressed data only.)
- */
-static void flush_window(void)
-{
- ulg c = crc; /* temporary variable */
- unsigned n;
- uch *in, *out, ch;
-
- in = window;
- out = &output_data[output_ptr];
- for (n = 0; n < outcnt; n++) {
- ch = *out++ = *in++;
- c = crc_32_tab[((int)c ^ ch) & 0xff] ^ (c >> 8);
- }
- crc = c;
- bytes_out += (ulg)outcnt;
- output_ptr += (ulg)outcnt;
- outcnt = 0;
-}
-
-static void error(char *x)
-{
- puts("\n\n");
- puts(x);
- puts("\n\n -- System halted");
-
- while(1); /* Halt */
-}
-
-void decompress_kernel(unsigned int imageaddr, unsigned int imagesize, unsigned int loadaddr)
-{
- input_data = (char *)imageaddr;
- input_len = imagesize;
- output_ptr = 0;
- output_data = (uch *)loadaddr;
- free_mem_ptr = (unsigned long)_end;
- free_mem_end_ptr = free_mem_ptr + HEAP_SIZE;
-
- makecrc();
- puts("Uncompressing Linux...");
- gunzip();
- flushcaches();
- puts("Ok, booting the kernel.");
-}
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/boot/tools/entry b/target/linux/xburst/files-2.6.32/arch/mips/boot/tools/entry
deleted file mode 100644
index 376e822a6..000000000
--- a/target/linux/xburst/files-2.6.32/arch/mips/boot/tools/entry
+++ /dev/null
@@ -1,12 +0,0 @@
-#!/bin/sh
-
-# grab the kernel_entry address from the vmlinux elf image
-entry=`$1 $2 | grep kernel_entry`
-
-fs=`echo $entry | grep ffffffff` # check toolchain output
-
-if [ -n "$fs" ]; then
- echo "0x"`$1 $2 | grep kernel_entry | cut -c9- | awk '{print $1}'`
-else
- echo "0x"`$1 $2 | grep kernel_entry | cut -c1- | awk '{print $1}'`
-fi
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/boot/tools/filesize b/target/linux/xburst/files-2.6.32/arch/mips/boot/tools/filesize
deleted file mode 100644
index 2142ad5af..000000000
--- a/target/linux/xburst/files-2.6.32/arch/mips/boot/tools/filesize
+++ /dev/null
@@ -1,7 +0,0 @@
-#!/bin/sh
-HOSTNAME=`uname`
-if [ "$HOSTNAME" = "Linux" ]; then
-echo `ls -l $1 | awk '{print $5}'`
-else
-echo `ls -l $1 | awk '{print $6}'`
-fi
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/board-n516.h b/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/board-n516.h
deleted file mode 100644
index cbe654477..000000000
--- a/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/board-n516.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * linux/include/asm-mips/mach-jz4740/board-n516.h
- *
- * JZ4730-based N516 board definition.
- *
- * Copyright (C) 2009, Yauhen Kharuzhy <jekhor@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef __ASM_JZ4740_N516_H__
-#define __ASM_JZ4740_N516_H__
-
-#include <asm/mach-jz4740/gpio.h>
-
-/*
- * GPIO
- */
-#define GPIO_SD_VCC_EN_N JZ_GPIO_PORTD(17)
-#define GPIO_SD_CD_N JZ_GPIO_PORTD(7)
-#define GPIO_SD_WP JZ_GPIO_PORTD(15)
-#define GPIO_USB_DETECT JZ_GPIO_PORTD(19)
-#define GPIO_CHARG_STAT_N JZ_GPIO_PORTD(16)
-#define GPIO_LED_ENABLE JZ_GPIO_PORTD(28)
-#define GPIO_LPC_INT JZ_GPIO_PORTD(14)
-#define GPIO_HPHONE_DETECT JZ_GPIO_PORTD(20)
-#define GPIO_SPEAKER_ENABLE JZ_GPIO_PORTD(21)
-
-/* Display */
-#define GPIO_DISPLAY_RST_L JZ_GPIO_PORTB(18)
-#define GPIO_DISPLAY_RDY JZ_GPIO_PORTB(17)
-#define GPIO_DISPLAY_STBY JZ_GPIO_PORTC(22)
-#define GPIO_DISPLAY_ERR JZ_GPIO_PORTC(23)
-#define GPIO_DISPLAY_OFF_N JZ_GPIO_PORTD(1)
-
-#endif /* __ASM_JZ4740_N516_H__ */
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/board-qi_lb60.h b/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/board-qi_lb60.h
deleted file mode 100644
index cfbf0733b..000000000
--- a/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/board-qi_lb60.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Copyright (c) 2009 Qi Hardware Inc.,
- * Author: Xiangfu Liu <xiangfu@qi-hardware.com>
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef __ASM_JZ4740_QI_LB60_H__
-#define __ASM_JZ4740_QI_LB60_H__
-
-#include <linux/gpio.h>
-
-/*
- * GPIO
- */
-#define GPIO_DC_DETE_N JZ_GPIO_PORTC(26)
-#define GPIO_CHARG_STAT_N JZ_GPIO_PORTC(27)
-#define GPIO_LED_EN JZ_GPIO_PORTC(28)
-#define GPIO_LCD_CS JZ_GPIO_PORTC(21)
-#define GPIO_DISP_OFF_N JZ_GPIO_PORTD(21)
-#define GPIO_PWM JZ_GPIO_PORTD(27)
-#define GPIO_WAKEUP_N JZ_GPIO_PORTD(29)
-
-#define GPIO_AMP_EN JZ_GPIO_PORTD(4)
-
-#define GPIO_SD_CD_N JZ_GPIO_PORTD(0)
-#define GPIO_SD_VCC_EN_N JZ_GPIO_PORTD(2)
-
-#define GPIO_USB_DETE JZ_GPIO_PORTD(28)
-#define GPIO_BUZZ_PWM JZ_GPIO_PORTD(27)
-#define GPIO_UDC_HOTPLUG GPIO_USB_DETE
-
-#define GPIO_AUDIO_POP JZ_GPIO_PORTB(29)
-#define GPIO_COB_TEST JZ_GPIO_PORTB(30)
-
-#define GPIO_KEYOUT_BASE JZ_GPIO_PORTC(10)
-#define GPIO_KEYIN_BASE JZ_GPIO_PORTD(18)
-#define GPIO_KEYIN_8 JZ_GPIO_PORTD(26)
-
-#endif /* __ASM_JZ4740_QI_LB60_H__ */
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/clock.h b/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/clock.h
deleted file mode 100644
index 1f8e53b25..000000000
--- a/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/clock.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * linux/include/asm-mips/mach-jz4740/clock.h
- *
- * JZ4740 clocks definition.
- *
- * Copyright (C) 2006 - 2007 Ingenic Semiconductor Inc.
- *
- * Author: <lhhuang@ingenic.cn>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_JZ4740_CLOCK_H__
-#define __ASM_JZ4740_CLOCK_H__
-
-#include <asm/mach-jz4740/regs.h>
-
-enum jz4740_wait_mode
-{
- JZ4740_WAIT_MODE_IDLE,
- JZ4740_WAIT_MODE_SLEEP,
-};
-
-void jz4740_clock_set_wait_mode(enum jz4740_wait_mode mode);
-
-void jz4740_clock_udc_enable_auto_suspend(void);
-void jz4740_clock_udc_disable_auto_suspend(void);
-
-#endif /* __ASM_JZ4740_CLOCK_H__ */
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/dma.h b/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/dma.h
deleted file mode 100644
index e7f474e4c..000000000
--- a/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/dma.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
- * JZ7420/JZ4740 DMA definitions
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-
-#ifndef __ASM_MACH_JZ4740_DMA_H__
-#define __ASM_MACH_JZ4740_DMA_H__
-
-struct jz4740_dma_chan;
-
-enum jz4740_dma_request_type {
- JZ4740_DMA_TYPE_AUTO_REQUEST = 8,
- JZ4740_DMA_TYPE_UART_TRANSMIT = 20,
- JZ4740_DMA_TYPE_UART_RECEIVE = 21,
- JZ4740_DMA_TYPE_SPI_TRANSMIT = 22,
- JZ4740_DMA_TYPE_SPI_RECEIVE = 23,
- JZ4740_DMA_TYPE_AIC_TRANSMIT = 24,
- JZ4740_DMA_TYPE_AIC_RECEIVE = 25,
- JZ4740_DMA_TYPE_MMC_TRANSMIT = 26,
- JZ4740_DMA_TYPE_MMC_RECEIVE = 27,
- JZ4740_DMA_TYPE_TCU = 28,
- JZ4740_DMA_TYPE_SADC = 29,
- JZ4740_DMA_TYPE_SLCD = 30,
-};
-
-enum jz4740_dma_width {
- JZ4740_DMA_WIDTH_8BIT,
- JZ4740_DMA_WIDTH_16BIT,
- JZ4740_DMA_WIDTH_32BIT,
-};
-
-enum jz4740_dma_transfer_size {
- JZ4740_DMA_TRANSFER_SIZE_4BYTE = 0,
- JZ4740_DMA_TRANSFER_SIZE_1BYTE = 1,
- JZ4740_DMA_TRANSFER_SIZE_2BYTE = 2,
- JZ4740_DMA_TRANSFER_SIZE_16BYTE = 3,
- JZ4740_DMA_TRANSFER_SIZE_32BYTE = 4,
-};
-
-enum jz4740_dma_flags {
- JZ4740_DMA_SRC_AUTOINC = 0x2,
- JZ4740_DMA_DST_AUTOINC = 0x1,
-};
-
-enum jz4740_dma_mode {
- JZ4740_DMA_MODE_SINGLE = 0,
- JZ4740_DMA_MODE_BLOCK = 1,
-};
-
-struct jz4740_dma_config {
- enum jz4740_dma_width src_width;
- enum jz4740_dma_width dst_width;
- enum jz4740_dma_transfer_size transfer_size;
- enum jz4740_dma_request_type request_type;
- enum jz4740_dma_flags flags;
- enum jz4740_dma_mode mode;
-};
-
-typedef void (*jz4740_dma_complete_callback_t)(struct jz4740_dma_chan *, int , void *);
-
-struct jz4740_dma_chan* jz4740_dma_request(void *dev, const char *name);
-void jz4740_dma_free(struct jz4740_dma_chan *dma);
-
-void jz4740_dma_configure(struct jz4740_dma_chan *dma,
- const struct jz4740_dma_config *config);
-
-
-void jz4740_dma_enable(struct jz4740_dma_chan *dma);
-void jz4740_dma_disable(struct jz4740_dma_chan *dma);
-
-void jz4740_dma_set_src_addr(struct jz4740_dma_chan *dma, dma_addr_t src);
-void jz4740_dma_set_dst_addr(struct jz4740_dma_chan *dma, dma_addr_t dst);
-void jz4740_dma_set_transfer_count(struct jz4740_dma_chan *dma, uint32_t count);
-
-uint32_t jz4740_dma_get_residue(const struct jz4740_dma_chan *dma);
-
-void jz4740_dma_set_complete_cb(struct jz4740_dma_chan *dma,
- jz4740_dma_complete_callback_t cb);
-
-#endif /* __ASM_JZ4740_DMA_H__ */
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/gpio.h b/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/gpio.h
deleted file mode 100644
index 99206dd7b..000000000
--- a/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/gpio.h
+++ /dev/null
@@ -1,393 +0,0 @@
-/*
- * Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
- * JZ7420/JZ4740 GPIO pin definitions
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-
-#ifndef _JZ_GPIO_H
-#define _JZ_GPIO_H
-
-#include <linux/types.h>
-
-enum jz_gpio_function {
- JZ_GPIO_FUNC_NONE,
- JZ_GPIO_FUNC1,
- JZ_GPIO_FUNC2,
- JZ_GPIO_FUNC3,
-};
-
-
-/*
- Usually a driver for a SoC component has to request several gpio pins and
- configure them as funcion pins.
- jz_gpio_bulk_request can be used to ease this process.
- Usually one would do something like:
-
- const static struct jz_gpio_bulk_request i2c_pins[] = {
- JZ_GPIO_BULK_PIN(I2C_SDA),
- JZ_GPIO_BULK_PIN(I2C_SCK),
- };
-
- inside the probe function:
-
- ret = jz_gpio_bulk_request(i2c_pins, ARRAY_SIZE(i2c_pins));
- if (ret) {
- ...
-
- inside the remove function:
-
- jz_gpio_bulk_free(i2c_pins, ARRAY_SIZE(i2c_pins));
-
-
-*/
-struct jz_gpio_bulk_request {
- int gpio;
- const char *name;
- enum jz_gpio_function function;
-};
-
-#define JZ_GPIO_BULK_PIN(pin) { \
- .gpio = JZ_GPIO_ ## pin, \
- .name = #pin, \
- .function = JZ_GPIO_FUNC_ ## pin \
-}
-
-int jz_gpio_bulk_request(const struct jz_gpio_bulk_request *request, size_t num);
-void jz_gpio_bulk_free(const struct jz_gpio_bulk_request *request, size_t num);
-void jz_gpio_bulk_suspend(const struct jz_gpio_bulk_request *request, size_t num);
-void jz_gpio_bulk_resume(const struct jz_gpio_bulk_request *request, size_t num);
-void jz_gpio_enable_pullup(unsigned gpio);
-void jz_gpio_disable_pullup(unsigned gpio);
-int jz_gpio_set_function(int gpio, enum jz_gpio_function function);
-
-int jz_gpio_port_direction_input(int port, uint32_t mask);
-int jz_gpio_port_direction_output(int port, uint32_t mask);
-void jz_gpio_port_set_value(int port, uint32_t value, uint32_t mask);
-uint32_t jz_gpio_port_get_value(int port, uint32_t mask);
-
-#include <asm/mach-generic/gpio.h>
-
-#define JZ_GPIO_PORTA(x) ((x) + 32 * 0)
-#define JZ_GPIO_PORTB(x) ((x) + 32 * 1)
-#define JZ_GPIO_PORTC(x) ((x) + 32 * 2)
-#define JZ_GPIO_PORTD(x) ((x) + 32 * 3)
-
-/* Port A function pins */
-#define JZ_GPIO_MEM_DATA0 JZ_GPIO_PORTA(0)
-#define JZ_GPIO_MEM_DATA1 JZ_GPIO_PORTA(1)
-#define JZ_GPIO_MEM_DATA2 JZ_GPIO_PORTA(2)
-#define JZ_GPIO_MEM_DATA3 JZ_GPIO_PORTA(3)
-#define JZ_GPIO_MEM_DATA4 JZ_GPIO_PORTA(4)
-#define JZ_GPIO_MEM_DATA5 JZ_GPIO_PORTA(5)
-#define JZ_GPIO_MEM_DATA6 JZ_GPIO_PORTA(6)
-#define JZ_GPIO_MEM_DATA7 JZ_GPIO_PORTA(7)
-#define JZ_GPIO_MEM_DATA8 JZ_GPIO_PORTA(8)
-#define JZ_GPIO_MEM_DATA9 JZ_GPIO_PORTA(9)
-#define JZ_GPIO_MEM_DATA10 JZ_GPIO_PORTA(10)
-#define JZ_GPIO_MEM_DATA11 JZ_GPIO_PORTA(11)
-#define JZ_GPIO_MEM_DATA12 JZ_GPIO_PORTA(12)
-#define JZ_GPIO_MEM_DATA13 JZ_GPIO_PORTA(13)
-#define JZ_GPIO_MEM_DATA14 JZ_GPIO_PORTA(14)
-#define JZ_GPIO_MEM_DATA15 JZ_GPIO_PORTA(15)
-#define JZ_GPIO_MEM_DATA16 JZ_GPIO_PORTA(16)
-#define JZ_GPIO_MEM_DATA17 JZ_GPIO_PORTA(17)
-#define JZ_GPIO_MEM_DATA18 JZ_GPIO_PORTA(18)
-#define JZ_GPIO_MEM_DATA19 JZ_GPIO_PORTA(19)
-#define JZ_GPIO_MEM_DATA20 JZ_GPIO_PORTA(20)
-#define JZ_GPIO_MEM_DATA21 JZ_GPIO_PORTA(21)
-#define JZ_GPIO_MEM_DATA22 JZ_GPIO_PORTA(22)
-#define JZ_GPIO_MEM_DATA23 JZ_GPIO_PORTA(23)
-#define JZ_GPIO_MEM_DATA24 JZ_GPIO_PORTA(24)
-#define JZ_GPIO_MEM_DATA25 JZ_GPIO_PORTA(25)
-#define JZ_GPIO_MEM_DATA26 JZ_GPIO_PORTA(26)
-#define JZ_GPIO_MEM_DATA27 JZ_GPIO_PORTA(27)
-#define JZ_GPIO_MEM_DATA28 JZ_GPIO_PORTA(28)
-#define JZ_GPIO_MEM_DATA29 JZ_GPIO_PORTA(29)
-#define JZ_GPIO_MEM_DATA30 JZ_GPIO_PORTA(30)
-#define JZ_GPIO_MEM_DATA31 JZ_GPIO_PORTA(31)
-
-#define JZ_GPIO_FUNC_MEM_DATA0 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA1 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA2 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA3 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA4 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA5 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA6 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA7 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA8 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA9 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA10 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA11 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA12 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA13 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA14 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA15 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA16 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA17 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA18 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA19 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA20 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA21 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA22 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA23 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA24 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA25 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA26 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA27 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA28 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA29 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA30 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA31 JZ_GPIO_FUNC1
-
-/* Port B function pins */
-#define JZ_GPIO_MEM_ADDR0 JZ_GPIO_PORTB(0)
-#define JZ_GPIO_MEM_ADDR1 JZ_GPIO_PORTB(1)
-#define JZ_GPIO_MEM_ADDR2 JZ_GPIO_PORTB(2)
-#define JZ_GPIO_MEM_ADDR3 JZ_GPIO_PORTB(3)
-#define JZ_GPIO_MEM_ADDR4 JZ_GPIO_PORTB(4)
-#define JZ_GPIO_MEM_ADDR5 JZ_GPIO_PORTB(5)
-#define JZ_GPIO_MEM_ADDR6 JZ_GPIO_PORTB(6)
-#define JZ_GPIO_MEM_ADDR7 JZ_GPIO_PORTB(7)
-#define JZ_GPIO_MEM_ADDR8 JZ_GPIO_PORTB(8)
-#define JZ_GPIO_MEM_ADDR9 JZ_GPIO_PORTB(9)
-#define JZ_GPIO_MEM_ADDR10 JZ_GPIO_PORTB(10)
-#define JZ_GPIO_MEM_ADDR11 JZ_GPIO_PORTB(11)
-#define JZ_GPIO_MEM_ADDR12 JZ_GPIO_PORTB(12)
-#define JZ_GPIO_MEM_ADDR13 JZ_GPIO_PORTB(13)
-#define JZ_GPIO_MEM_ADDR14 JZ_GPIO_PORTB(14)
-#define JZ_GPIO_MEM_ADDR15 JZ_GPIO_PORTB(15)
-#define JZ_GPIO_MEM_ADDR16 JZ_GPIO_PORTB(16)
-#define JZ_GPIO_MEM_CLS JZ_GPIO_PORTB(17)
-#define JZ_GPIO_MEM_SPL JZ_GPIO_PORTB(18)
-#define JZ_GPIO_MEM_DCS JZ_GPIO_PORTB(19)
-#define JZ_GPIO_MEM_RAS JZ_GPIO_PORTB(20)
-#define JZ_GPIO_MEM_CAS JZ_GPIO_PORTB(21)
-#define JZ_GPIO_MEM_SDWE JZ_GPIO_PORTB(22)
-#define JZ_GPIO_MEM_CKE JZ_GPIO_PORTB(23)
-#define JZ_GPIO_MEM_CKO JZ_GPIO_PORTB(24)
-#define JZ_GPIO_MEM_CS0 JZ_GPIO_PORTB(25)
-#define JZ_GPIO_MEM_CS1 JZ_GPIO_PORTB(26)
-#define JZ_GPIO_MEM_CS2 JZ_GPIO_PORTB(27)
-#define JZ_GPIO_MEM_CS3 JZ_GPIO_PORTB(28)
-#define JZ_GPIO_MEM_RD JZ_GPIO_PORTB(29)
-#define JZ_GPIO_MEM_WR JZ_GPIO_PORTB(30)
-#define JZ_GPIO_MEM_WE0 JZ_GPIO_PORTB(31)
-
-#define JZ_GPIO_FUNC_MEM_ADDR0 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_ADDR1 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_ADDR2 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_ADDR3 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_ADDR4 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_ADDR5 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_ADDR6 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_ADDR7 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_ADDR8 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_ADDR9 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_ADDR10 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_ADDR11 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_ADDR12 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_ADDR13 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_ADDR14 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_ADDR15 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_ADDR16 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_CLS JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_SPL JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DCS JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_RAS JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_CAS JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_SDWE JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_CKE JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_CKO JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_CS0 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_CS1 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_CS2 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_CS3 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_RD JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_WR JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_WE0 JZ_GPIO_FUNC1
-
-
-#define JZ_GPIO_MEM_ADDR21 JZ_GPIO_PORTB(17)
-#define JZ_GPIO_MEM_ADDR22 JZ_GPIO_PORTB(18)
-
-#define JZ_GPIO_FUNC_MEM_ADDR21 JZ_GPIO_FUNC2
-#define JZ_GPIO_FUNC_MEM_ADDR22 JZ_GPIO_FUNC2
-
-/* Port C function pins */
-#define JZ_GPIO_LCD_DATA0 JZ_GPIO_PORTC(0)
-#define JZ_GPIO_LCD_DATA1 JZ_GPIO_PORTC(1)
-#define JZ_GPIO_LCD_DATA2 JZ_GPIO_PORTC(2)
-#define JZ_GPIO_LCD_DATA3 JZ_GPIO_PORTC(3)
-#define JZ_GPIO_LCD_DATA4 JZ_GPIO_PORTC(4)
-#define JZ_GPIO_LCD_DATA5 JZ_GPIO_PORTC(5)
-#define JZ_GPIO_LCD_DATA6 JZ_GPIO_PORTC(6)
-#define JZ_GPIO_LCD_DATA7 JZ_GPIO_PORTC(7)
-#define JZ_GPIO_LCD_DATA8 JZ_GPIO_PORTC(8)
-#define JZ_GPIO_LCD_DATA9 JZ_GPIO_PORTC(9)
-#define JZ_GPIO_LCD_DATA10 JZ_GPIO_PORTC(10)
-#define JZ_GPIO_LCD_DATA11 JZ_GPIO_PORTC(11)
-#define JZ_GPIO_LCD_DATA12 JZ_GPIO_PORTC(12)
-#define JZ_GPIO_LCD_DATA13 JZ_GPIO_PORTC(13)
-#define JZ_GPIO_LCD_DATA14 JZ_GPIO_PORTC(14)
-#define JZ_GPIO_LCD_DATA15 JZ_GPIO_PORTC(15)
-#define JZ_GPIO_LCD_DATA16 JZ_GPIO_PORTC(16)
-#define JZ_GPIO_LCD_DATA17 JZ_GPIO_PORTC(17)
-#define JZ_GPIO_LCD_PCLK JZ_GPIO_PORTC(18)
-#define JZ_GPIO_LCD_HSYNC JZ_GPIO_PORTC(19)
-#define JZ_GPIO_LCD_VSYNC JZ_GPIO_PORTC(20)
-#define JZ_GPIO_LCD_DE JZ_GPIO_PORTC(21)
-#define JZ_GPIO_LCD_PS JZ_GPIO_PORTC(22)
-#define JZ_GPIO_LCD_REV JZ_GPIO_PORTC(23)
-#define JZ_GPIO_MEM_WE1 JZ_GPIO_PORTC(24)
-#define JZ_GPIO_MEM_WE2 JZ_GPIO_PORTC(25)
-#define JZ_GPIO_MEM_WE3 JZ_GPIO_PORTC(26)
-#define JZ_GPIO_MEM_WAIT JZ_GPIO_PORTC(27)
-#define JZ_GPIO_MEM_FRE JZ_GPIO_PORTC(28)
-#define JZ_GPIO_MEM_FWE JZ_GPIO_PORTC(29)
-
-#define JZ_GPIO_FUNC_LCD_DATA0 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_DATA1 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_DATA2 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_DATA3 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_DATA4 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_DATA5 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_DATA6 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_DATA7 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_DATA8 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_DATA9 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_DATA10 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_DATA11 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_DATA12 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_DATA13 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_DATA14 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_DATA15 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_DATA16 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_DATA17 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_PCLK JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_VSYNC JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_HSYNC JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_DE JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_PS JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_REV JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_WE1 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_WE2 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_WE3 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_WAIT JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_FRE JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_FWE JZ_GPIO_FUNC1
-
-
-#define JZ_GPIO_MEM_ADDR19 JZ_GPIO_PORTB(22)
-#define JZ_GPIO_MEM_ADDR20 JZ_GPIO_PORTB(23)
-
-#define JZ_GPIO_FUNC_MEM_ADDR19 JZ_GPIO_FUNC2
-#define JZ_GPIO_FUNC_MEM_ADDR20 JZ_GPIO_FUNC2
-
-/* Port D function pins */
-#define JZ_GPIO_CIM_DATA0 JZ_GPIO_PORTD(0)
-#define JZ_GPIO_CIM_DATA1 JZ_GPIO_PORTD(1)
-#define JZ_GPIO_CIM_DATA2 JZ_GPIO_PORTD(2)
-#define JZ_GPIO_CIM_DATA3 JZ_GPIO_PORTD(3)
-#define JZ_GPIO_CIM_DATA4 JZ_GPIO_PORTD(4)
-#define JZ_GPIO_CIM_DATA5 JZ_GPIO_PORTD(5)
-#define JZ_GPIO_CIM_DATA6 JZ_GPIO_PORTD(6)
-#define JZ_GPIO_CIM_DATA7 JZ_GPIO_PORTD(7)
-#define JZ_GPIO_MSC_CMD JZ_GPIO_PORTD(8)
-#define JZ_GPIO_MSC_CLK JZ_GPIO_PORTD(9)
-#define JZ_GPIO_MSC_DATA0 JZ_GPIO_PORTD(10)
-#define JZ_GPIO_MSC_DATA1 JZ_GPIO_PORTD(11)
-#define JZ_GPIO_MSC_DATA2 JZ_GPIO_PORTD(12)
-#define JZ_GPIO_MSC_DATA3 JZ_GPIO_PORTD(13)
-#define JZ_GPIO_CIM_MCLK JZ_GPIO_PORTD(14)
-#define JZ_GPIO_CIM_PCLK JZ_GPIO_PORTD(15)
-#define JZ_GPIO_CIM_VSYNC JZ_GPIO_PORTD(16)
-#define JZ_GPIO_CIM_HSYNC JZ_GPIO_PORTD(17)
-#define JZ_GPIO_SPI_CLK JZ_GPIO_PORTD(18)
-#define JZ_GPIO_SPI_CE0 JZ_GPIO_PORTD(19)
-#define JZ_GPIO_SPI_DT JZ_GPIO_PORTD(20)
-#define JZ_GPIO_SPI_DR JZ_GPIO_PORTD(21)
-#define JZ_GPIO_SPI_CE1 JZ_GPIO_PORTD(22)
-#define JZ_GPIO_PWM0 JZ_GPIO_PORTD(23)
-#define JZ_GPIO_PWM1 JZ_GPIO_PORTD(24)
-#define JZ_GPIO_PWM2 JZ_GPIO_PORTD(25)
-#define JZ_GPIO_PWM3 JZ_GPIO_PORTD(26)
-#define JZ_GPIO_PWM4 JZ_GPIO_PORTD(27)
-#define JZ_GPIO_PWM5 JZ_GPIO_PORTD(28)
-#define JZ_GPIO_PWM6 JZ_GPIO_PORTD(30)
-#define JZ_GPIO_PWM7 JZ_GPIO_PORTD(31)
-
-#define JZ_GPIO_FUNC_CIM_DATA0 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_CIM_DATA1 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_CIM_DATA2 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_CIM_DATA3 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_CIM_DATA4 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_CIM_DATA5 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_CIM_DATA6 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_CIM_DATA7 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MSC_CMD JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MSC_CLK JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MSC_DATA0 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MSC_DATA1 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MSC_DATA2 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MSC_DATA3 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_CIM_MCLK JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_CIM_PCLK JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_CIM_VSYNC JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_CIM_HSYNC JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_SPI_CLK JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_SPI_CE0 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_SPI_DT JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_SPI_DR JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_SPI_CE1 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_PWM0 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_PWM1 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_PWM2 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_PWM3 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_PWM4 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_PWM5 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_PWM6 JZ_GPIO_FUNC1
-
-#define JZ_GPIO_MEM_SCLK_RSTN JZ_GPIO_PORTD(18)
-#define JZ_GPIO_MEM_BCLK JZ_GPIO_PORTD(19)
-#define JZ_GPIO_MEM_SDATO JZ_GPIO_PORTD(20)
-#define JZ_GPIO_MEM_SDATI JZ_GPIO_PORTD(21)
-#define JZ_GPIO_MEM_SYNC JZ_GPIO_PORTD(22)
-#define JZ_GPIO_I2C_SDA JZ_GPIO_PORTD(23)
-#define JZ_GPIO_I2C_SCK JZ_GPIO_PORTD(24)
-#define JZ_GPIO_UART0_TXD JZ_GPIO_PORTD(25)
-#define JZ_GPIO_UART0_RXD JZ_GPIO_PORTD(26)
-#define JZ_GPIO_MEM_ADDR17 JZ_GPIO_PORTD(27)
-#define JZ_GPIO_MEM_ADDR18 JZ_GPIO_PORTD(28)
-#define JZ_GPIO_UART0_CTS JZ_GPIO_PORTD(30)
-#define JZ_GPIO_UART0_RTS JZ_GPIO_PORTD(31)
-
-#define JZ_GPIO_FUNC_MEM_SCLK_RSTN JZ_GPIO_FUNC2
-#define JZ_GPIO_FUNC_MEM_BCLK JZ_GPIO_FUNC2
-#define JZ_GPIO_FUNC_MEM_SDATO JZ_GPIO_FUNC2
-#define JZ_GPIO_FUNC_MEM_SDATI JZ_GPIO_FUNC2
-#define JZ_GPIO_FUNC_MEM_SYNC JZ_GPIO_FUNC2
-#define JZ_GPIO_FUNC_I2C_SDA JZ_GPIO_FUNC2
-#define JZ_GPIO_FUNC_I2C_SCK JZ_GPIO_FUNC2
-#define JZ_GPIO_FUNC_UART0_TXD JZ_GPIO_FUNC2
-#define JZ_GPIO_FUNC_UART0_RXD JZ_GPIO_FUNC2
-#define JZ_GPIO_FUNC_MEM_ADDR17 JZ_GPIO_FUNC2
-#define JZ_GPIO_FUNC_MEM_ADDR18 JZ_GPIO_FUNC2
-#define JZ_GPIO_FUNC_UART0_CTS JZ_GPIO_FUNC2
-#define JZ_GPIO_FUNC_UART0_RTS JZ_GPIO_FUNC2
-
-#define JZ_GPIO_UART1_RXD JZ_GPIO_PORTD(30)
-#define JZ_GPIO_UART1_TXD JZ_GPIO_PORTD(31)
-
-#define JZ_GPIO_FUNC_UART1_RXD JZ_GPIO_FUNC3
-#define JZ_GPIO_FUNC_UART1_TXD JZ_GPIO_FUNC3
-
-#endif
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/irq.h b/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/irq.h
deleted file mode 100644
index 59f0ea51a..000000000
--- a/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/irq.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
- * JZ7420/JZ4740 IRQ definitions
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-
-#ifndef __ASM_MACH_JZ4740_IRQ_H__
-#define __ASM_MACH_JZ4740_IRQ_H__
-
-#define MIPS_CPU_IRQ_BASE 0
-#define JZ_IRQ_BASE 8
-
-/* 1st-level interrupts */
-#define JZ_IRQ(x) (JZ_IRQ_BASE + (x))
-#define JZ_IRQ_I2C JZ_IRQ(1)
-#define JZ_IRQ_UHC JZ_IRQ(3)
-#define JZ_IRQ_UART1 JZ_IRQ(8)
-#define JZ_IRQ_UART0 JZ_IRQ(9)
-#define JZ_IRQ_SADC JZ_IRQ(12)
-#define JZ_IRQ_MSC JZ_IRQ(14)
-#define JZ_IRQ_RTC JZ_IRQ(15)
-#define JZ_IRQ_SSI JZ_IRQ(16)
-#define JZ_IRQ_CIM JZ_IRQ(17)
-#define JZ_IRQ_AIC JZ_IRQ(18)
-#define JZ_IRQ_ETH JZ_IRQ(19)
-#define JZ_IRQ_DMAC JZ_IRQ(20)
-#define JZ_IRQ_TCU2 JZ_IRQ(21)
-#define JZ_IRQ_TCU1 JZ_IRQ(22)
-#define JZ_IRQ_TCU0 JZ_IRQ(23)
-#define JZ_IRQ_UDC JZ_IRQ(24)
-#define JZ_IRQ_GPIO3 JZ_IRQ(25)
-#define JZ_IRQ_GPIO2 JZ_IRQ(26)
-#define JZ_IRQ_GPIO1 JZ_IRQ(27)
-#define JZ_IRQ_GPIO0 JZ_IRQ(28)
-#define JZ_IRQ_IPU JZ_IRQ(29)
-#define JZ_IRQ_LCD JZ_IRQ(30)
-
-/* 2nd-level interrupts */
-#define JZ_IRQ_DMA(x) ((x) + JZ_IRQ(32)) /* 32 to 37 for DMAC channel 0 to 5 */
-
-#define JZ_IRQ_INTC_GPIO(x) (JZ_IRQ_GPIO0 - (x))
-#define JZ_IRQ_GPIO(x) (JZ_IRQ(48) + (x))
-
-#define NR_IRQS (JZ_IRQ_GPIO(127) + 1)
-
-#endif
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/jz4740.h b/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/jz4740.h
deleted file mode 100644
index 9885db243..000000000
--- a/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/jz4740.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * linux/include/asm-mips/mach-jz4740/jz4740.h
- *
- * JZ4740 common definition.
- *
- * Copyright (C) 2006 - 2007 Ingenic Semiconductor Inc.
- *
- * Author: <lhhuang@ingenic.cn>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_JZ4740_H__
-#define __ASM_JZ4740_H__
-
-#include <asm/mach-jz4740/regs.h>
-#include <asm/mach-jz4740/dma.h>
-
-/*------------------------------------------------------------------
- * Platform definitions
- */
-
-#ifdef CONFIG_JZ4740_QI_LB60
-#include <asm/mach-jz4740/board-qi_lb60.h>
-#endif
-
-/*------------------------------------------------------------------
- * Follows are related to platform definitions
- */
-
-#include <asm/mach-jz4740/serial.h>
-
-#endif /* __ASM_JZ4740_H__ */
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/platform.h b/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/platform.h
deleted file mode 100644
index 42de1c13a..000000000
--- a/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/platform.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
- * JZ7420/JZ4740 platform device definitions
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-
-
-#ifndef __JZ4740_PLATFORM_H
-#define __JZ4740_PLATFORM_H
-
-#include <linux/platform_device.h>
-
-extern struct platform_device jz4740_usb_ohci_device;
-extern struct platform_device jz4740_usb_gdt_device;
-extern struct platform_device jz4740_mmc_device;
-extern struct platform_device jz4740_rtc_device;
-extern struct platform_device jz4740_i2c_device;
-extern struct platform_device jz4740_nand_device;
-extern struct platform_device jz4740_framebuffer_device;
-extern struct platform_device jz4740_i2s_device;
-extern struct platform_device jz4740_codec_device;
-extern struct platform_device jz4740_adc_device;
-extern struct platform_device jz4740_battery_device;
-
-#endif
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/regs.h b/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/regs.h
deleted file mode 100644
index 2ea90ca06..000000000
--- a/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/regs.h
+++ /dev/null
@@ -1,519 +0,0 @@
-/*
- * linux/include/asm-mips/mach-jz4740/regs.h
- *
- * Ingenic's JZ4740 common include.
- *
- * Copyright (C) 2006 - 2007 Ingenic Semiconductor Inc.
- *
- * Author: <yliu@ingenic.cn>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __JZ4740_REGS_H__
-#define __JZ4740_REGS_H__
-
-#if defined(__ASSEMBLY__) || defined(__LANGUAGE_ASSEMBLY)
-#define REG8(addr) (addr)
-#define REG16(addr) (addr)
-#define REG32(addr) (addr)
-#else
-#define REG8(addr) *((volatile unsigned char *)(addr))
-#define REG16(addr) *((volatile unsigned short *)(addr))
-#define REG32(addr) *((volatile unsigned int *)(addr))
-#endif
-
-/*
- * Define the module base addresses
- */
-#define CPM_BASE 0xB0000000
-#define INTC_BASE 0xB0001000
-#define TCU_BASE 0xB0002000
-#define WDT_BASE 0xB0002000
-#define RTC_BASE 0xB0003000
-#define GPIO_BASE 0xB0010000
-#define AIC_BASE 0xB0020000
-#define ICDC_BASE 0xB0020000
-#define MSC_BASE 0xB0021000
-#define UART0_BASE 0xB0030000
-#define UART1_BASE 0xB0031000
-#define I2C_BASE 0xB0042000
-#define SSI_BASE 0xB0043000
-#define SADC_BASE 0xB0070000
-#define EMC_BASE 0xB3010000
-#define DMAC_BASE 0xB3020000
-#define UHC_BASE 0xB3030000
-#define UDC_BASE 0xB3040000
-#define LCD_BASE 0xB3050000
-#define SLCD_BASE 0xB3050000
-#define CIM_BASE 0xB3060000
-#define IPU_BASE 0xB3080000
-#define ETH_BASE 0xB3100000
-
-/*************************************************************************
- * UART
- *************************************************************************/
-
-#define IRDA_BASE UART0_BASE
-#define UART_BASE UART0_BASE
-#define UART_OFF 0x1000
-
-/* Register Offset */
-#define OFF_RDR (0x00) /* R 8b H'xx */
-#define OFF_TDR (0x00) /* W 8b H'xx */
-#define OFF_DLLR (0x00) /* RW 8b H'00 */
-#define OFF_DLHR (0x04) /* RW 8b H'00 */
-#define OFF_IER (0x04) /* RW 8b H'00 */
-#define OFF_ISR (0x08) /* R 8b H'01 */
-#define OFF_FCR (0x08) /* W 8b H'00 */
-#define OFF_LCR (0x0C) /* RW 8b H'00 */
-#define OFF_MCR (0x10) /* RW 8b H'00 */
-#define OFF_LSR (0x14) /* R 8b H'00 */
-#define OFF_MSR (0x18) /* R 8b H'00 */
-#define OFF_SPR (0x1C) /* RW 8b H'00 */
-#define OFF_SIRCR (0x20) /* RW 8b H'00, UART0 */
-#define OFF_UMR (0x24) /* RW 8b H'00, UART M Register */
-#define OFF_UACR (0x28) /* RW 8b H'00, UART Add Cycle Register */
-
-/* Register Address */
-#define UART0_RDR (UART0_BASE + OFF_RDR)
-#define UART0_TDR (UART0_BASE + OFF_TDR)
-#define UART0_DLLR (UART0_BASE + OFF_DLLR)
-#define UART0_DLHR (UART0_BASE + OFF_DLHR)
-#define UART0_IER (UART0_BASE + OFF_IER)
-#define UART0_ISR (UART0_BASE + OFF_ISR)
-#define UART0_FCR (UART0_BASE + OFF_FCR)
-#define UART0_LCR (UART0_BASE + OFF_LCR)
-#define UART0_MCR (UART0_BASE + OFF_MCR)
-#define UART0_LSR (UART0_BASE + OFF_LSR)
-#define UART0_MSR (UART0_BASE + OFF_MSR)
-#define UART0_SPR (UART0_BASE + OFF_SPR)
-#define UART0_SIRCR (UART0_BASE + OFF_SIRCR)
-#define UART0_UMR (UART0_BASE + OFF_UMR)
-#define UART0_UACR (UART0_BASE + OFF_UACR)
-
-/*
- * Define macros for UARTIER
- * UART Interrupt Enable Register
- */
-#define UARTIER_RIE (1 << 0) /* 0: receive fifo full interrupt disable */
-#define UARTIER_TIE (1 << 1) /* 0: transmit fifo empty interrupt disable */
-#define UARTIER_RLIE (1 << 2) /* 0: receive line status interrupt disable */
-#define UARTIER_MIE (1 << 3) /* 0: modem status interrupt disable */
-#define UARTIER_RTIE (1 << 4) /* 0: receive timeout interrupt disable */
-
-/*
- * Define macros for UARTISR
- * UART Interrupt Status Register
- */
-#define UARTISR_IP (1 << 0) /* 0: interrupt is pending 1: no interrupt */
-#define UARTISR_IID (7 << 1) /* Source of Interrupt */
-#define UARTISR_IID_MSI (0 << 1) /* Modem status interrupt */
-#define UARTISR_IID_THRI (1 << 1) /* Transmitter holding register empty */
-#define UARTISR_IID_RDI (2 << 1) /* Receiver data interrupt */
-#define UARTISR_IID_RLSI (3 << 1) /* Receiver line status interrupt */
-#define UARTISR_IID_RTO (6 << 1) /* Receive timeout */
-#define UARTISR_FFMS (3 << 6) /* FIFO mode select, set when UARTFCR.FE is set to 1 */
-#define UARTISR_FFMS_NO_FIFO (0 << 6)
-#define UARTISR_FFMS_FIFO_MODE (3 << 6)
-
-/*
- * Define macros for UARTFCR
- * UART FIFO Control Register
- */
-#define UARTFCR_FE (1 << 0) /* 0: non-FIFO mode 1: FIFO mode */
-#define UARTFCR_RFLS (1 << 1) /* write 1 to flush receive FIFO */
-#define UARTFCR_TFLS (1 << 2) /* write 1 to flush transmit FIFO */
-#define UARTFCR_DMS (1 << 3) /* 0: disable DMA mode */
-#define UARTFCR_UUE (1 << 4) /* 0: disable UART */
-#define UARTFCR_RTRG (3 << 6) /* Receive FIFO Data Trigger */
-#define UARTFCR_RTRG_1 (0 << 6)
-#define UARTFCR_RTRG_4 (1 << 6)
-#define UARTFCR_RTRG_8 (2 << 6)
-#define UARTFCR_RTRG_15 (3 << 6)
-
-/*
- * Define macros for UARTLCR
- * UART Line Control Register
- */
-#define UARTLCR_WLEN (3 << 0) /* word length */
-#define UARTLCR_WLEN_5 (0 << 0)
-#define UARTLCR_WLEN_6 (1 << 0)
-#define UARTLCR_WLEN_7 (2 << 0)
-#define UARTLCR_WLEN_8 (3 << 0)
-#define UARTLCR_STOP (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8
- 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
-#define UARTLCR_STOP1 (0 << 2)
-#define UARTLCR_STOP2 (1 << 2)
-#define UARTLCR_PE (1 << 3) /* 0: parity disable */
-#define UARTLCR_PROE (1 << 4) /* 0: even parity 1: odd parity */
-#define UARTLCR_SPAR (1 << 5) /* 0: sticky parity disable */
-#define UARTLCR_SBRK (1 << 6) /* write 0 normal, write 1 send break */
-#define UARTLCR_DLAB (1 << 7) /* 0: access UARTRDR/TDR/IER 1: access UARTDLLR/DLHR */
-
-/*
- * Define macros for UARTLSR
- * UART Line Status Register
- */
-#define UARTLSR_DR (1 << 0) /* 0: receive FIFO is empty 1: receive data is ready */
-#define UARTLSR_ORER (1 << 1) /* 0: no overrun error */
-#define UARTLSR_PER (1 << 2) /* 0: no parity error */
-#define UARTLSR_FER (1 << 3) /* 0; no framing error */
-#define UARTLSR_BRK (1 << 4) /* 0: no break detected 1: receive a break signal */
-#define UARTLSR_TDRQ (1 << 5) /* 1: transmit FIFO half "empty" */
-#define UARTLSR_TEMT (1 << 6) /* 1: transmit FIFO and shift registers empty */
-#define UARTLSR_RFER (1 << 7) /* 0: no receive error 1: receive error in FIFO mode */
-
-/*
- * Define macros for UARTMCR
- * UART Modem Control Register
- */
-#define UARTMCR_RTS (1 << 1) /* 0: RTS_ output high, 1: RTS_ output low */
-#define UARTMCR_LOOP (1 << 4) /* 0: normal 1: loopback mode */
-#define UARTMCR_MCE (1 << 7) /* 0: modem function is disable */
-
-/*
- * Define macros for UARTMSR
- * UART Modem Status Register
- */
-#define UARTMSR_CCTS (1 << 0) /* 1: a change on CTS_ pin */
-#define UARTMSR_CTS (1 << 4) /* 0: CTS_ pin is high */
-
-/*
- * Define macros for SIRCR
- * Slow IrDA Control Register
- */
-#define SIRCR_TSIRE (1 << 0) /* 0: transmitter is in UART mode 1: SIR mode */
-#define SIRCR_RSIRE (1 << 1) /* 0: receiver is in UART mode 1: SIR mode */
-#define SIRCR_TPWS (1 << 2) /* 0: transmit 0 pulse width is 3/16 of bit length
- 1: 0 pulse width is 1.6us for 115.2Kbps */
-#define SIRCR_TDPL (1 << 3) /* 0: encoder generates a positive pulse for 0 */
-#define SIRCR_RDPL (1 << 4) /* 0: decoder interprets positive pulse as 0 */
-
-
-/*************************************************************************
- * EMC (External Memory Controller)
- *************************************************************************/
-#define EMC_SMCR0 (EMC_BASE + 0x10) /* Static Memory Control Register 0 */
-#define EMC_SMCR1 (EMC_BASE + 0x14) /* Static Memory Control Register 1 */
-#define EMC_SMCR2 (EMC_BASE + 0x18) /* Static Memory Control Register 2 */
-#define EMC_SMCR3 (EMC_BASE + 0x1c) /* Static Memory Control Register 3 */
-#define EMC_SMCR4 (EMC_BASE + 0x20) /* Static Memory Control Register 4 */
-#define EMC_SACR0 (EMC_BASE + 0x30) /* Static Memory Bank 0 Addr Config Reg */
-#define EMC_SACR1 (EMC_BASE + 0x34) /* Static Memory Bank 1 Addr Config Reg */
-#define EMC_SACR2 (EMC_BASE + 0x38) /* Static Memory Bank 2 Addr Config Reg */
-#define EMC_SACR3 (EMC_BASE + 0x3c) /* Static Memory Bank 3 Addr Config Reg */
-#define EMC_SACR4 (EMC_BASE + 0x40) /* Static Memory Bank 4 Addr Config Reg */
-
-#define EMC_NFCSR (EMC_BASE + 0x050) /* NAND Flash Control/Status Register */
-#define EMC_NFECR (EMC_BASE + 0x100) /* NAND Flash ECC Control Register */
-#define EMC_NFECC (EMC_BASE + 0x104) /* NAND Flash ECC Data Register */
-#define EMC_NFPAR0 (EMC_BASE + 0x108) /* NAND Flash RS Parity 0 Register */
-#define EMC_NFPAR1 (EMC_BASE + 0x10c) /* NAND Flash RS Parity 1 Register */
-#define EMC_NFPAR2 (EMC_BASE + 0x110) /* NAND Flash RS Parity 2 Register */
-#define EMC_NFINTS (EMC_BASE + 0x114) /* NAND Flash Interrupt Status Register */
-#define EMC_NFINTE (EMC_BASE + 0x118) /* NAND Flash Interrupt Enable Register */
-#define EMC_NFERR0 (EMC_BASE + 0x11c) /* NAND Flash RS Error Report 0 Register */
-#define EMC_NFERR1 (EMC_BASE + 0x120) /* NAND Flash RS Error Report 1 Register */
-#define EMC_NFERR2 (EMC_BASE + 0x124) /* NAND Flash RS Error Report 2 Register */
-#define EMC_NFERR3 (EMC_BASE + 0x128) /* NAND Flash RS Error Report 3 Register */
-
-#define EMC_DMCR (EMC_BASE + 0x80) /* DRAM Control Register */
-#define EMC_RTCSR (EMC_BASE + 0x84) /* Refresh Time Control/Status Register */
-#define EMC_RTCNT (EMC_BASE + 0x88) /* Refresh Timer Counter */
-#define EMC_RTCOR (EMC_BASE + 0x8c) /* Refresh Time Constant Register */
-#define EMC_DMAR0 (EMC_BASE + 0x90) /* SDRAM Bank 0 Addr Config Register */
-#define EMC_SDMR0 (EMC_BASE + 0xa000) /* Mode Register of SDRAM bank 0 */
-
-
-#define REG_EMC_SMCR0 REG32(EMC_SMCR0)
-#define REG_EMC_SMCR1 REG32(EMC_SMCR1)
-#define REG_EMC_SMCR2 REG32(EMC_SMCR2)
-#define REG_EMC_SMCR3 REG32(EMC_SMCR3)
-#define REG_EMC_SMCR4 REG32(EMC_SMCR4)
-#define REG_EMC_SACR0 REG32(EMC_SACR0)
-#define REG_EMC_SACR1 REG32(EMC_SACR1)
-#define REG_EMC_SACR2 REG32(EMC_SACR2)
-#define REG_EMC_SACR3 REG32(EMC_SACR3)
-#define REG_EMC_SACR4 REG32(EMC_SACR4)
-
-#define REG_EMC_NFCSR REG32(EMC_NFCSR)
-#define REG_EMC_NFECR REG32(EMC_NFECR)
-#define REG_EMC_NFECC REG32(EMC_NFECC)
-#define REG_EMC_NFPAR0 REG32(EMC_NFPAR0)
-#define REG_EMC_NFPAR1 REG32(EMC_NFPAR1)
-#define REG_EMC_NFPAR2 REG32(EMC_NFPAR2)
-#define REG_EMC_NFINTS REG32(EMC_NFINTS)
-#define REG_EMC_NFINTE REG32(EMC_NFINTE)
-#define REG_EMC_NFERR0 REG32(EMC_NFERR0)
-#define REG_EMC_NFERR1 REG32(EMC_NFERR1)
-#define REG_EMC_NFERR2 REG32(EMC_NFERR2)
-#define REG_EMC_NFERR3 REG32(EMC_NFERR3)
-
-#define REG_EMC_DMCR REG32(EMC_DMCR)
-#define REG_EMC_RTCSR REG16(EMC_RTCSR)
-#define REG_EMC_RTCNT REG16(EMC_RTCNT)
-#define REG_EMC_RTCOR REG16(EMC_RTCOR)
-#define REG_EMC_DMAR0 REG32(EMC_DMAR0)
-
-/* Static Memory Control Register */
-#define EMC_SMCR_STRV_BIT 24
-#define EMC_SMCR_STRV_MASK (0x0f << EMC_SMCR_STRV_BIT)
-#define EMC_SMCR_TAW_BIT 20
-#define EMC_SMCR_TAW_MASK (0x0f << EMC_SMCR_TAW_BIT)
-#define EMC_SMCR_TBP_BIT 16
-#define EMC_SMCR_TBP_MASK (0x0f << EMC_SMCR_TBP_BIT)
-#define EMC_SMCR_TAH_BIT 12
-#define EMC_SMCR_TAH_MASK (0x07 << EMC_SMCR_TAH_BIT)
-#define EMC_SMCR_TAS_BIT 8
-#define EMC_SMCR_TAS_MASK (0x07 << EMC_SMCR_TAS_BIT)
-#define EMC_SMCR_BW_BIT 6
-#define EMC_SMCR_BW_MASK (0x03 << EMC_SMCR_BW_BIT)
- #define EMC_SMCR_BW_8BIT (0 << EMC_SMCR_BW_BIT)
- #define EMC_SMCR_BW_16BIT (1 << EMC_SMCR_BW_BIT)
- #define EMC_SMCR_BW_32BIT (2 << EMC_SMCR_BW_BIT)
-#define EMC_SMCR_BCM (1 << 3)
-#define EMC_SMCR_BL_BIT 1
-#define EMC_SMCR_BL_MASK (0x03 << EMC_SMCR_BL_BIT)
- #define EMC_SMCR_BL_4 (0 << EMC_SMCR_BL_BIT)
- #define EMC_SMCR_BL_8 (1 << EMC_SMCR_BL_BIT)
- #define EMC_SMCR_BL_16 (2 << EMC_SMCR_BL_BIT)
- #define EMC_SMCR_BL_32 (3 << EMC_SMCR_BL_BIT)
-#define EMC_SMCR_SMT (1 << 0)
-
-/* Static Memory Bank Addr Config Reg */
-#define EMC_SACR_BASE_BIT 8
-#define EMC_SACR_BASE_MASK (0xff << EMC_SACR_BASE_BIT)
-#define EMC_SACR_MASK_BIT 0
-#define EMC_SACR_MASK_MASK (0xff << EMC_SACR_MASK_BIT)
-
-/* NAND Flash Control/Status Register */
-#define EMC_NFCSR_NFCE4 (1 << 7) /* NAND Flash Enable */
-#define EMC_NFCSR_NFE4 (1 << 6) /* NAND Flash FCE# Assertion Enable */
-#define EMC_NFCSR_NFCE3 (1 << 5)
-#define EMC_NFCSR_NFE3 (1 << 4)
-#define EMC_NFCSR_NFCE2 (1 << 3)
-#define EMC_NFCSR_NFE2 (1 << 2)
-#define EMC_NFCSR_NFCE1 (1 << 1)
-#define EMC_NFCSR_NFE1 (1 << 0)
-
-/* NAND Flash ECC Control Register */
-#define EMC_NFECR_PRDY (1 << 4) /* Parity Ready */
-#define EMC_NFECR_RS_DECODING (0 << 3) /* RS is in decoding phase */
-#define EMC_NFECR_RS_ENCODING (1 << 3) /* RS is in encoding phase */
-#define EMC_NFECR_HAMMING (0 << 2) /* Select HAMMING Correction Algorithm */
-#define EMC_NFECR_RS (1 << 2) /* Select RS Correction Algorithm */
-#define EMC_NFECR_ERST (1 << 1) /* ECC Reset */
-#define EMC_NFECR_ECCE (1 << 0) /* ECC Enable */
-
-/* NAND Flash ECC Data Register */
-#define EMC_NFECC_ECC2_BIT 16
-#define EMC_NFECC_ECC2_MASK (0xff << EMC_NFECC_ECC2_BIT)
-#define EMC_NFECC_ECC1_BIT 8
-#define EMC_NFECC_ECC1_MASK (0xff << EMC_NFECC_ECC1_BIT)
-#define EMC_NFECC_ECC0_BIT 0
-#define EMC_NFECC_ECC0_MASK (0xff << EMC_NFECC_ECC0_BIT)
-
-/* NAND Flash Interrupt Status Register */
-#define EMC_NFINTS_ERRCNT_BIT 29 /* Error Count */
-#define EMC_NFINTS_ERRCNT_MASK (0x7 << EMC_NFINTS_ERRCNT_BIT)
-#define EMC_NFINTS_PADF (1 << 4) /* Padding Finished */
-#define EMC_NFINTS_DECF (1 << 3) /* Decoding Finished */
-#define EMC_NFINTS_ENCF (1 << 2) /* Encoding Finished */
-#define EMC_NFINTS_UNCOR (1 << 1) /* Uncorrectable Error Occurred */
-#define EMC_NFINTS_ERR (1 << 0) /* Error Occurred */
-
-/* NAND Flash Interrupt Enable Register */
-#define EMC_NFINTE_PADFE (1 << 4) /* Padding Finished Interrupt Enable */
-#define EMC_NFINTE_DECFE (1 << 3) /* Decoding Finished Interrupt Enable */
-#define EMC_NFINTE_ENCFE (1 << 2) /* Encoding Finished Interrupt Enable */
-#define EMC_NFINTE_UNCORE (1 << 1) /* Uncorrectable Error Occurred Intr Enable */
-#define EMC_NFINTE_ERRE (1 << 0) /* Error Occurred Interrupt */
-
-/* NAND Flash RS Error Report Register */
-#define EMC_NFERR_INDEX_BIT 16 /* Error Symbol Index */
-#define EMC_NFERR_INDEX_MASK (0x1ff << EMC_NFERR_INDEX_BIT)
-#define EMC_NFERR_MASK_BIT 0 /* Error Symbol Value */
-#define EMC_NFERR_MASK_MASK (0x1ff << EMC_NFERR_MASK_BIT)
-
-
-/* DRAM Control Register */
-#define EMC_DMCR_BW_BIT 31
-#define EMC_DMCR_BW (1 << EMC_DMCR_BW_BIT)
-#define EMC_DMCR_CA_BIT 26
-#define EMC_DMCR_CA_MASK (0x07 << EMC_DMCR_CA_BIT)
- #define EMC_DMCR_CA_8 (0 << EMC_DMCR_CA_BIT)
- #define EMC_DMCR_CA_9 (1 << EMC_DMCR_CA_BIT)
- #define EMC_DMCR_CA_10 (2 << EMC_DMCR_CA_BIT)
- #define EMC_DMCR_CA_11 (3 << EMC_DMCR_CA_BIT)
- #define EMC_DMCR_CA_12 (4 << EMC_DMCR_CA_BIT)
-#define EMC_DMCR_RMODE (1 << 25)
-#define EMC_DMCR_RFSH (1 << 24)
-#define EMC_DMCR_MRSET (1 << 23)
-#define EMC_DMCR_RA_BIT 20
-#define EMC_DMCR_RA_MASK (0x03 << EMC_DMCR_RA_BIT)
- #define EMC_DMCR_RA_11 (0 << EMC_DMCR_RA_BIT)
- #define EMC_DMCR_RA_12 (1 << EMC_DMCR_RA_BIT)
- #define EMC_DMCR_RA_13 (2 << EMC_DMCR_RA_BIT)
-#define EMC_DMCR_BA_BIT 19
-#define EMC_DMCR_BA (1 << EMC_DMCR_BA_BIT)
-#define EMC_DMCR_PDM (1 << 18)
-#define EMC_DMCR_EPIN (1 << 17)
-#define EMC_DMCR_TRAS_BIT 13
-#define EMC_DMCR_TRAS_MASK (0x07 << EMC_DMCR_TRAS_BIT)
-#define EMC_DMCR_RCD_BIT 11
-#define EMC_DMCR_RCD_MASK (0x03 << EMC_DMCR_RCD_BIT)
-#define EMC_DMCR_TPC_BIT 8
-#define EMC_DMCR_TPC_MASK (0x07 << EMC_DMCR_TPC_BIT)
-#define EMC_DMCR_TRWL_BIT 5
-#define EMC_DMCR_TRWL_MASK (0x03 << EMC_DMCR_TRWL_BIT)
-#define EMC_DMCR_TRC_BIT 2
-#define EMC_DMCR_TRC_MASK (0x07 << EMC_DMCR_TRC_BIT)
-#define EMC_DMCR_TCL_BIT 0
-#define EMC_DMCR_TCL_MASK (0x03 << EMC_DMCR_TCL_BIT)
-
-/* Refresh Time Control/Status Register */
-#define EMC_RTCSR_CMF (1 << 7)
-#define EMC_RTCSR_CKS_BIT 0
-#define EMC_RTCSR_CKS_MASK (0x07 << EMC_RTCSR_CKS_BIT)
- #define EMC_RTCSR_CKS_DISABLE (0 << EMC_RTCSR_CKS_BIT)
- #define EMC_RTCSR_CKS_4 (1 << EMC_RTCSR_CKS_BIT)
- #define EMC_RTCSR_CKS_16 (2 << EMC_RTCSR_CKS_BIT)
- #define EMC_RTCSR_CKS_64 (3 << EMC_RTCSR_CKS_BIT)
- #define EMC_RTCSR_CKS_256 (4 << EMC_RTCSR_CKS_BIT)
- #define EMC_RTCSR_CKS_1024 (5 << EMC_RTCSR_CKS_BIT)
- #define EMC_RTCSR_CKS_2048 (6 << EMC_RTCSR_CKS_BIT)
- #define EMC_RTCSR_CKS_4096 (7 << EMC_RTCSR_CKS_BIT)
-
-/* SDRAM Bank Address Configuration Register */
-#define EMC_DMAR_BASE_BIT 8
-#define EMC_DMAR_BASE_MASK (0xff << EMC_DMAR_BASE_BIT)
-#define EMC_DMAR_MASK_BIT 0
-#define EMC_DMAR_MASK_MASK (0xff << EMC_DMAR_MASK_BIT)
-
-/* Mode Register of SDRAM bank 0 */
-#define EMC_SDMR_BM (1 << 9) /* Write Burst Mode */
-#define EMC_SDMR_OM_BIT 7 /* Operating Mode */
-#define EMC_SDMR_OM_MASK (3 << EMC_SDMR_OM_BIT)
- #define EMC_SDMR_OM_NORMAL (0 << EMC_SDMR_OM_BIT)
-#define EMC_SDMR_CAS_BIT 4 /* CAS Latency */
-#define EMC_SDMR_CAS_MASK (7 << EMC_SDMR_CAS_BIT)
- #define EMC_SDMR_CAS_1 (1 << EMC_SDMR_CAS_BIT)
- #define EMC_SDMR_CAS_2 (2 << EMC_SDMR_CAS_BIT)
- #define EMC_SDMR_CAS_3 (3 << EMC_SDMR_CAS_BIT)
-#define EMC_SDMR_BT_BIT 3 /* Burst Type */
-#define EMC_SDMR_BT_MASK (1 << EMC_SDMR_BT_BIT)
- #define EMC_SDMR_BT_SEQ (0 << EMC_SDMR_BT_BIT) /* Sequential */
- #define EMC_SDMR_BT_INT (1 << EMC_SDMR_BT_BIT) /* Interleave */
-#define EMC_SDMR_BL_BIT 0 /* Burst Length */
-#define EMC_SDMR_BL_MASK (7 << EMC_SDMR_BL_BIT)
- #define EMC_SDMR_BL_1 (0 << EMC_SDMR_BL_BIT)
- #define EMC_SDMR_BL_2 (1 << EMC_SDMR_BL_BIT)
- #define EMC_SDMR_BL_4 (2 << EMC_SDMR_BL_BIT)
- #define EMC_SDMR_BL_8 (3 << EMC_SDMR_BL_BIT)
-
-#define EMC_SDMR_CAS2_16BIT \
- (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2)
-#define EMC_SDMR_CAS2_32BIT \
- (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4)
-#define EMC_SDMR_CAS3_16BIT \
- (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2)
-#define EMC_SDMR_CAS3_32BIT \
- (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4)
-
-/*************************************************************************
- * WDT (WatchDog Timer)
- *************************************************************************/
-#define WDT_TDR (WDT_BASE + 0x00)
-#define WDT_TCER (WDT_BASE + 0x04)
-#define WDT_TCNT (WDT_BASE + 0x08)
-#define WDT_TCSR (WDT_BASE + 0x0C)
-
-#define REG_WDT_TDR REG16(WDT_TDR)
-#define REG_WDT_TCER REG8(WDT_TCER)
-#define REG_WDT_TCNT REG16(WDT_TCNT)
-#define REG_WDT_TCSR REG16(WDT_TCSR)
-
-// Register definition
-#define WDT_TCSR_PRESCALE_BIT 3
-#define WDT_TCSR_PRESCALE_MASK (0x7 << WDT_TCSR_PRESCALE_BIT)
- #define WDT_TCSR_PRESCALE1 (0x0 << WDT_TCSR_PRESCALE_BIT)
- #define WDT_TCSR_PRESCALE4 (0x1 << WDT_TCSR_PRESCALE_BIT)
- #define WDT_TCSR_PRESCALE16 (0x2 << WDT_TCSR_PRESCALE_BIT)
- #define WDT_TCSR_PRESCALE64 (0x3 << WDT_TCSR_PRESCALE_BIT)
- #define WDT_TCSR_PRESCALE256 (0x4 << WDT_TCSR_PRESCALE_BIT)
- #define WDT_TCSR_PRESCALE1024 (0x5 << WDT_TCSR_PRESCALE_BIT)
-#define WDT_TCSR_EXT_EN (1 << 2)
-#define WDT_TCSR_RTC_EN (1 << 1)
-#define WDT_TCSR_PCK_EN (1 << 0)
-
-#define WDT_TCER_TCEN (1 << 0)
-
-/*************************************************************************
- * RTC
- *************************************************************************/
-#define RTC_RCR (RTC_BASE + 0x00) /* RTC Control Register */
-#define RTC_RSR (RTC_BASE + 0x04) /* RTC Second Register */
-#define RTC_RSAR (RTC_BASE + 0x08) /* RTC Second Alarm Register */
-#define RTC_RGR (RTC_BASE + 0x0c) /* RTC Regulator Register */
-
-#define RTC_HCR (RTC_BASE + 0x20) /* Hibernate Control Register */
-#define RTC_HWFCR (RTC_BASE + 0x24) /* Hibernate Wakeup Filter Counter Reg */
-#define RTC_HRCR (RTC_BASE + 0x28) /* Hibernate Reset Counter Register */
-#define RTC_HWCR (RTC_BASE + 0x2c) /* Hibernate Wakeup Control Register */
-#define RTC_HWRSR (RTC_BASE + 0x30) /* Hibernate Wakeup Status Register */
-#define RTC_HSPR (RTC_BASE + 0x34) /* Hibernate Scratch Pattern Register */
-
-#define REG_RTC_RCR REG32(RTC_RCR)
-#define REG_RTC_RSR REG32(RTC_RSR)
-#define REG_RTC_RSAR REG32(RTC_RSAR)
-#define REG_RTC_RGR REG32(RTC_RGR)
-#define REG_RTC_HCR REG32(RTC_HCR)
-#define REG_RTC_HWFCR REG32(RTC_HWFCR)
-#define REG_RTC_HRCR REG32(RTC_HRCR)
-#define REG_RTC_HWCR REG32(RTC_HWCR)
-#define REG_RTC_HWRSR REG32(RTC_HWRSR)
-#define REG_RTC_HSPR REG32(RTC_HSPR)
-
-/* RTC Control Register */
-#define RTC_RCR_WRDY_BIT 7
-#define RTC_RCR_WRDY (1 << 7) /* Write Ready Flag */
-#define RTC_RCR_1HZ_BIT 6
-#define RTC_RCR_1HZ (1 << RTC_RCR_1HZ_BIT) /* 1Hz Flag */
-#define RTC_RCR_1HZIE (1 << 5) /* 1Hz Interrupt Enable */
-#define RTC_RCR_AF_BIT 4
-#define RTC_RCR_AF (1 << RTC_RCR_AF_BIT) /* Alarm Flag */
-#define RTC_RCR_AIE (1 << 3) /* Alarm Interrupt Enable */
-#define RTC_RCR_AE (1 << 2) /* Alarm Enable */
-#define RTC_RCR_RTCE (1 << 0) /* RTC Enable */
-
-/* RTC Regulator Register */
-#define RTC_RGR_LOCK (1 << 31) /* Lock Bit */
-#define RTC_RGR_ADJC_BIT 16
-#define RTC_RGR_ADJC_MASK (0x3ff << RTC_RGR_ADJC_BIT)
-#define RTC_RGR_NC1HZ_BIT 0
-#define RTC_RGR_NC1HZ_MASK (0xffff << RTC_RGR_NC1HZ_BIT)
-
-/* Hibernate Control Register */
-#define RTC_HCR_PD (1 << 0) /* Power Down */
-
-/* Hibernate Wakeup Filter Counter Register */
-#define RTC_HWFCR_BIT 5
-#define RTC_HWFCR_MASK (0x7ff << RTC_HWFCR_BIT)
-
-/* Hibernate Reset Counter Register */
-#define RTC_HRCR_BIT 5
-#define RTC_HRCR_MASK (0x7f << RTC_HRCR_BIT)
-
-/* Hibernate Wakeup Control Register */
-#define RTC_HWCR_EALM (1 << 0) /* RTC alarm wakeup enable */
-
-/* Hibernate Wakeup Status Register */
-#define RTC_HWRSR_HR (1 << 5) /* Hibernate reset */
-#define RTC_HWRSR_PPR (1 << 4) /* PPR reset */
-#define RTC_HWRSR_PIN (1 << 1) /* Wakeup pin status bit */
-#define RTC_HWRSR_ALM (1 << 0) /* RTC alarm status bit */
-
-#endif /* __JZ4740_REGS_H__ */
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/serial.h b/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/serial.h
deleted file mode 100644
index c4819b982..000000000
--- a/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/serial.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * linux/include/asm-mips/mach-jz4740/serial.h
- *
- * Ingenic's JZ4740 common include.
- *
- * Copyright (C) 2006 - 2007 Ingenic Semiconductor Inc.
- *
- * Author: <yliu@ingenic.cn>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_BOARD_SERIAL_H__
-#define __ASM_BOARD_SERIAL_H__
-
-#ifndef CONFIG_SERIAL_MANY_PORTS
-#undef RS_TABLE_SIZE
-#define RS_TABLE_SIZE 1
-#endif
-
-#define JZ_BASE_BAUD (12000000/16)
-
-#define JZ_SERIAL_PORT_DEFNS \
- { .baud_base = JZ_BASE_BAUD, .irq = IRQ_UART0, \
- .flags = STD_COM_FLAGS, .iomem_base = (u8 *)UART0_BASE, \
- .iomem_reg_shift = 2, .io_type = SERIAL_IO_MEM },
-
-#endif /* __ASM_BORAD_SERIAL_H__ */
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/timer.h b/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/timer.h
deleted file mode 100644
index 3214f3611..000000000
--- a/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/timer.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
- * JZ4740 platform timer support
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-
-#ifndef __ASM_MACH_JZ4740_TIMER
-#define __ASM_MACH_JZ4740_TIMER
-
-void jz4740_timer_enable_watchdog(void);
-void jz4740_timer_disable_watchdog(void);
-
-#endif
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/war.h b/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/war.h
deleted file mode 100644
index 3a5bc17e2..000000000
--- a/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/war.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MIPS_MACH_JZ4740_WAR_H
-#define __ASM_MIPS_MACH_JZ4740_WAR_H
-
-#define R4600_V1_INDEX_ICACHEOP_WAR 0
-#define R4600_V1_HIT_CACHEOP_WAR 0
-#define R4600_V2_HIT_CACHEOP_WAR 0
-#define R5432_CP0_INTERRUPT_WAR 0
-#define BCM1250_M3_WAR 0
-#define SIBYTE_1956_WAR 0
-#define MIPS4K_ICACHE_REFILL_WAR 0
-#define MIPS_CACHE_SYNC_WAR 0
-#define TX49XX_ICACHE_INDEX_INV_WAR 0
-#define RM9000_CDEX_SMP_WAR 0
-#define ICACHE_REFILLS_WORKAROUND_WAR 0
-#define R10000_LLSC_WAR 0
-#define MIPS34K_MISSED_ITLB_WAR 0
-
-#endif /* __ASM_MIPS_MACH_JZ4740_WAR_H */
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/Kconfig b/target/linux/xburst/files-2.6.32/arch/mips/jz4740/Kconfig
deleted file mode 100644
index 71d35f7a0..000000000
--- a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/Kconfig
+++ /dev/null
@@ -1,40 +0,0 @@
-choice
- prompt "Machine type"
- depends on MACH_JZ
- default JZ4740_QI_LB60
-
-config JZ4740_QI_LB60
- bool "Qi Hardware Ben NanoNote"
- select DMA_NONCOHERENT
- select SOC_JZ4740
-
-config JZ4740_N516
- bool "Hanvon n516 eBook reader"
- select DMA_NONCOHERENT
- select SOC_JZ4740
-
-config JZ4740_N526
- bool "Hanvon n526 eBook reader"
- select DMA_NONCOHERENT
- select SOC_JZ4740
-
-
-endchoice
-
-config SOC_JZ4740
- bool
- select JZSOC
- select GENERIC_GPIO
- select ARCH_REQUIRE_GPIOLIB
- select SYS_HAS_EARLY_PRINTK
- select SYS_SUPPORTS_LITTLE_ENDIAN
- select IRQ_CPU
-
-config JZSOC
- bool
- select JZRISC
- select SYS_HAS_CPU_MIPS32_R1
- select SYS_SUPPORTS_32BIT_KERNEL
-
-config JZRISC
- bool
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/Makefile b/target/linux/xburst/files-2.6.32/arch/mips/jz4740/Makefile
deleted file mode 100644
index f298174e5..000000000
--- a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/Makefile
+++ /dev/null
@@ -1,21 +0,0 @@
-#
-# Makefile for the Ingenic JZ4740.
-#
-
-# Object file lists.
-
-obj-y += prom.o irq.o time.o reset.o setup.o dma.o \
- gpio.o clock.o platform.o
-
-obj-$(CONFIG_DEBUG_FS) += clock-debugfs.o
-
-# board specific support
-
-obj-$(CONFIG_JZ4740_QI_LB60) += board-qi_lb60.o
-obj-$(CONFIG_JZ4740_N516) += board-n516.o board-n516-display.o
-obj-$(CONFIG_JZ4740_N526) += board-n526.o
-
-# PM support
-
-obj-$(CONFIG_PM) += pm.o
-
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/board-n516-display.c b/target/linux/xburst/files-2.6.32/arch/mips/jz4740/board-n516-display.c
deleted file mode 100644
index a0485da20..000000000
--- a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/board-n516-display.c
+++ /dev/null
@@ -1,395 +0,0 @@
-/*
- * board-n516-display.c -- Platform device for N516 display
- *
- * Copyright (C) 2009, Yauhen Kharuzhy <jekhor@gmail.com>
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file COPYING in the main directory of this archive for
- * more details.
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/string.h>
-#include <linux/delay.h>
-#include <linux/interrupt.h>
-#include <linux/fb.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/irq.h>
-#include <linux/gpio.h>
-#include <linux/jz4740_fb.h>
-
-#include <asm/mach-jz4740/platform.h>
-#include <asm/mach-jz4740/board-n516.h>
-
-#include <video/metronomefb.h>
-#include <linux/console.h>
-
-extern struct platform_device jz_lcd_device;
-
-static struct fb_videomode n516_fb_modes[] = {
- [0] = {
- .name = "Metronome 800x600",
- .refresh = 50,
- .xres = 400,
- .yres = 624,
- .hsync_len = 31,
- .vsync_len = 23,
- .right_margin = 31,
- .left_margin = 5,
- .upper_margin = 1,
- .lower_margin = 2,
- .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
- },
-};
-
-static struct jz4740_fb_platform_data n516_fb_pdata = {
- .num_modes = ARRAY_SIZE(n516_fb_modes),
- .modes = n516_fb_modes,
- .bpp = 16,
- .lcd_type = JZ_LCD_TYPE_GENERIC_16_BIT,
-};
-
-struct n516_board_info {
- uint8_t *metromem;
- size_t wfm_size;
- struct fb_info *host_fbinfo; /* the host LCD controller's fbi */
- unsigned int fw;
- unsigned int fh;
-};
-
-static struct platform_device *n516_device;
-static struct n516_board_info n516_board_info;
-
-static int metronome_gpios[] = {
- GPIO_DISPLAY_STBY,
- GPIO_DISPLAY_RST_L,
- GPIO_DISPLAY_RDY,
- GPIO_DISPLAY_ERR,
-/* GPIO_DISPLAY_OFF,*/
-};
-
-static const char *metronome_gpio_names[] = {
- "Metronome STDBY",
- "Metronome RST",
- "Metronome RDY",
- "Metronome ERR",
-/* "Metronone OFF",*/
-};
-
-static int n516_enable_hostfb(bool enable)
-{
- int ret;
- int blank = enable ? FB_BLANK_UNBLANK : FB_BLANK_POWERDOWN;
-
- acquire_console_sem();
- ret = fb_blank(n516_board_info.host_fbinfo, blank);
- release_console_sem();
-
- return ret;
-}
-
-static int n516_init_metronome_gpios(struct metronomefb_par *par)
-{
- int i;
- int ret;
-
- for (i = 0; i < ARRAY_SIZE(metronome_gpios); ++i) {
- ret = gpio_request(metronome_gpios[i], metronome_gpio_names[i]);
- if (ret)
- goto err;
- }
-
- gpio_direction_output(GPIO_DISPLAY_OFF, 0);
- gpio_direction_output(GPIO_DISPLAY_RST_L, 0);
- gpio_direction_output(GPIO_DISPLAY_STBY, 0);
- gpio_direction_input(GPIO_DISPLAY_RDY);
- gpio_direction_input(GPIO_DISPLAY_ERR);
-
- return 0;
-err:
- for (--i; i >= 0; --i)
- gpio_free(metronome_gpios[i]);
-
- return ret;
-}
-
-static int n516_share_video_mem(struct fb_info *info)
-{
- int ret;
-
- dev_dbg(&n516_device->dev, "ENTER %s\n", __func__);
- dev_dbg(&n516_device->dev, "%s, info->var.xres = %u, info->var.yres = %u\n", __func__, info->var.xres, info->var.yres);
- /* rough check if this is our desired fb and not something else */
- if ((info->var.xres != n516_fb_pdata.modes[0].xres)
- || (info->var.yres != n516_fb_pdata.modes[0].yres))
- return 0;
-
- /* we've now been notified that we have our new fb */
- n516_board_info.metromem = info->screen_base;
- n516_board_info.host_fbinfo = info;
-
- n516_enable_hostfb(false);
- /* try to refcount host drv since we are the consumer after this */
- if (!try_module_get(info->fbops->owner))
- return -ENODEV;
-
- /* this _add binds metronomefb to n516. metronomefb refcounts n516 */
- ret = platform_device_add(n516_device);
-
- if (ret) {
- platform_device_put(n516_device);
- return ret;
- }
-
- /* request our platform independent driver */
- request_module("metronomefb");
-
- return 0;
-}
-
-static int n516_unshare_video_mem(struct fb_info *info)
-{
- dev_dbg(&n516_device->dev, "ENTER %s\n", __func__);
-
- if (info != n516_board_info.host_fbinfo)
- return 0;
-
- module_put(n516_board_info.host_fbinfo->fbops->owner);
- return 0;
-}
-
-static int n516_fb_notifier_callback(struct notifier_block *self,
- unsigned long event, void *data)
-{
- struct fb_event *evdata = data;
- struct fb_info *info = evdata->info;
-
- dev_dbg(&n516_device->dev, "ENTER %s\n", __func__);
-
- if (event == FB_EVENT_FB_REGISTERED)
- return n516_share_video_mem(info);
- else if (event == FB_EVENT_FB_UNREGISTERED)
- return n516_unshare_video_mem(info);
-
- return 0;
-}
-
-static struct notifier_block n516_fb_notif = {
- .notifier_call = n516_fb_notifier_callback,
-};
-
-/* this gets called as part of our init. these steps must be done now so
- * that we can use set_pxa_fb_info */
-static void __init n516_presetup_fb(void)
-{
- int padding_size;
- int totalsize;
-
- /* the frame buffer is divided as follows:
- command | CRC | padding
- 16kb waveform data | CRC | padding
- image data | CRC
- */
-
- n516_board_info.fw = 800;
- n516_board_info.fh = 624;
-
- /* waveform must be 16k + 2 for checksum */
- n516_board_info.wfm_size = roundup(16*1024 + 2, n516_board_info.fw);
-
- padding_size = PAGE_SIZE + (4 * n516_board_info.fw);
-
- /* total is 1 cmd , 1 wfm, padding and image */
- totalsize = n516_board_info.fw + n516_board_info.wfm_size;
- totalsize += padding_size + (n516_board_info.fw*n516_board_info.fh);
-
- /* save this off because we're manipulating fw after this and
- * we'll need it when we're ready to setup the framebuffer */
-
- /* the reason we do this adjustment is because we want to acquire
- * more framebuffer memory without imposing custom awareness on the
- * underlying driver */
- n516_fb_pdata.modes[0].yres = DIV_ROUND_UP(totalsize, n516_board_info.fw);
-
- jz4740_framebuffer_device.dev.platform_data = &n516_fb_pdata;
- platform_device_register(&jz4740_framebuffer_device);
-}
-
-/* this gets called by metronomefb as part of its init, in our case, we
- * have already completed initial framebuffer init in presetup_fb so we
- * can just setup the fb access pointers */
-static int n516_setup_fb(struct metronomefb_par *par)
-{
- /* metromem was set up by the notifier in share_video_mem so now
- * we can use its value to calculate the other entries */
- par->metromem_cmd = (struct metromem_cmd *) n516_board_info.metromem;
- par->metromem_wfm = n516_board_info.metromem + n516_board_info.fw;
- par->metromem_img = par->metromem_wfm + n516_board_info.wfm_size;
- par->metromem_img_csum = (u16 *) (par->metromem_img + (n516_board_info.fw * n516_board_info.fh));
- par->metromem_dma = n516_board_info.host_fbinfo->fix.smem_start;
-
- return 0;
-}
-
-static int n516_get_panel_type(void)
-{
- return 5;
-}
-
-static irqreturn_t n516_handle_irq(int irq, void *dev_id)
-{
- struct metronomefb_par *par = dev_id;
-
- dev_dbg(&par->pdev->dev, "Metronome IRQ! RDY=%d\n", gpio_get_value(GPIO_DISPLAY_RDY));
- wake_up_all(&par->waitq);
-
- return IRQ_HANDLED;
-}
-
-static void n516_power_ctl(struct metronomefb_par *par, int cmd)
-{
- switch (cmd) {
- case METRONOME_POWER_OFF:
- gpio_set_value(GPIO_DISPLAY_OFF, 1);
- n516_enable_hostfb(false);
- break;
- case METRONOME_POWER_ON:
- gpio_set_value(GPIO_DISPLAY_OFF, 0);
- n516_enable_hostfb(true);
- break;
- }
-}
-
-static int n516_get_rdy(struct metronomefb_par *par)
-{
- return gpio_get_value(GPIO_DISPLAY_RDY);
-}
-
-static int n516_get_err(struct metronomefb_par *par)
-{
- return gpio_get_value(GPIO_DISPLAY_ERR);
-}
-
-static int n516_setup_irq(struct fb_info *info)
-{
- int ret;
-
- dev_dbg(&n516_device->dev, "ENTER %s\n", __func__);
-
- ret = request_irq(gpio_to_irq(GPIO_DISPLAY_RDY), n516_handle_irq,
- IRQF_TRIGGER_RISING,
- "n516", info->par);
- if (ret)
- dev_err(&n516_device->dev, "request_irq failed: %d\n", ret);
-
- return ret;
-}
-
-static void n516_set_rst(struct metronomefb_par *par, int state)
-{
- dev_dbg(&n516_device->dev, "ENTER %s, RDY=%d\n", __func__, gpio_get_value(GPIO_DISPLAY_RDY));
- if (state)
- gpio_set_value(GPIO_DISPLAY_RST_L, 1);
- else
- gpio_set_value(GPIO_DISPLAY_RST_L, 0);
-}
-
-static void n516_set_stdby(struct metronomefb_par *par, int state)
-{
- dev_dbg(&n516_device->dev, "ENTER %s, RDY=%d\n", __func__, gpio_get_value(GPIO_DISPLAY_RDY));
- if (state)
- gpio_set_value(GPIO_DISPLAY_STBY, 1);
- else
- gpio_set_value(GPIO_DISPLAY_STBY, 0);
-}
-
-static int n516_wait_event(struct metronomefb_par *par)
-{
- unsigned long timeout = jiffies + HZ / 20;
-
- dev_dbg(&n516_device->dev, "ENTER1 %s, RDY=%d\n",
- __func__, gpio_get_value(GPIO_DISPLAY_RDY));
- while (n516_get_rdy(par) && time_before(jiffies, timeout))
- schedule();
-
- dev_dbg(&n516_device->dev, "ENTER2 %s, RDY=%d\n",
- __func__, gpio_get_value(GPIO_DISPLAY_RDY));
- return wait_event_timeout(par->waitq,
- n516_get_rdy(par), HZ * 2) ? 0 : -EIO;
-}
-
-static int n516_wait_event_intr(struct metronomefb_par *par)
-{
- unsigned long timeout = jiffies + HZ/20;
-
- dev_dbg(&n516_device->dev, "ENTER1 %s, RDY=%d\n",
- __func__, gpio_get_value(GPIO_DISPLAY_RDY));
- while (n516_get_rdy(par) && time_before(jiffies, timeout))
- schedule();
-
- dev_dbg(&n516_device->dev, "ENTER2 %s, RDY=%d\n",
- __func__, gpio_get_value(GPIO_DISPLAY_RDY));
- return wait_event_interruptible_timeout(par->waitq,
- n516_get_rdy(par), HZ * 2) ? 0 : -EIO;
-}
-
-static void n516_cleanup(struct metronomefb_par *par)
-{
- int i;
-
- free_irq(gpio_to_irq(GPIO_DISPLAY_RDY), par);
- for (i = 0; i < ARRAY_SIZE(metronome_gpios); ++i)
- gpio_free(metronome_gpios[i]);
-}
-
-static struct metronome_board n516_board __initdata = {
- .owner = THIS_MODULE,
- .power_ctl = n516_power_ctl,
- .setup_irq = n516_setup_irq,
- .setup_io = n516_init_metronome_gpios,
- .setup_fb = n516_setup_fb,
- .set_rst = n516_set_rst,
- .get_err = n516_get_err,
- .get_rdy = n516_get_rdy,
- .set_stdby = n516_set_stdby,
- .met_wait_event = n516_wait_event,
- .met_wait_event_intr = n516_wait_event_intr,
- .get_panel_type = n516_get_panel_type,
- .cleanup = n516_cleanup,
-};
-
-static int __init n516_init(void)
-{
- int ret;
-
- /* Keep the metronome off, until its driver is loaded */
- ret = gpio_request(GPIO_DISPLAY_OFF, "Display off");
- if (ret)
- return ret;
-
- gpio_direction_output(GPIO_DISPLAY_OFF, 1);
-
- /* before anything else, we request notification for any fb
- * creation events */
- fb_register_client(&n516_fb_notif);
-
- n516_device = platform_device_alloc("metronomefb", -1);
- if (!n516_device)
- return -ENOMEM;
-
- /* the n516_board that will be seen by metronomefb is a copy */
- platform_device_add_data(n516_device, &n516_board,
- sizeof(n516_board));
-
- n516_presetup_fb();
-
- return 0;
-}
-module_init(n516_init);
-
-MODULE_DESCRIPTION("board driver for n516 display");
-MODULE_AUTHOR("Yauhen Kharuzhy");
-MODULE_LICENSE("GPL");
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/board-n516.c b/target/linux/xburst/files-2.6.32/arch/mips/jz4740/board-n516.c
deleted file mode 100644
index 0e146ac84..000000000
--- a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/board-n516.c
+++ /dev/null
@@ -1,201 +0,0 @@
-/*
- * linux/arch/mips/jz4740/board-516.c
- *
- * JZ4740 n516 board setup routines.
- *
- * Copyright (c) 2009, Yauhen Kharuzhy <jekhor@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#include <linux/init.h>
-#include <linux/sched.h>
-#include <linux/ioport.h>
-#include <linux/mm.h>
-#include <linux/console.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mmc/jz4740_mmc.h>
-#include <linux/mtd/jz4740_nand.h>
-#include <linux/leds.h>
-
-#include <linux/power_supply.h>
-#include <linux/power/gpio-charger.h>
-
-#include <linux/i2c.h>
-#include <linux/i2c-gpio.h>
-
-#include <asm/mach-jz4740/board-n516.h>
-#include <asm/mach-jz4740/platform.h>
-
-#include "clock.h"
-
-static long n516_panic_blink(long time)
-{
- gpio_set_value(GPIO_LED_ENABLE, 1);
- mdelay(200);
- gpio_set_value(GPIO_LED_ENABLE, 0);
- mdelay(200);
-
- return 400;
-}
-
-static void __init board_gpio_setup(void)
-{
-/* jz_gpio_enable_pullup(JZ_GPIO_PORTD(23));
- jz_gpio_enable_pullup(JZ_GPIO_PORTD(24));*/
-}
-
-static struct i2c_gpio_platform_data n516_i2c_pdata = {
- .sda_pin = JZ_GPIO_PORTD(23),
- .scl_pin = JZ_GPIO_PORTD(24),
- .udelay = 2,
- .timeout = 3 * HZ,
-};
-
-static struct platform_device n516_i2c_device = {
- .name = "i2c-gpio",
- .id = -1,
- .dev = {
- .platform_data = &n516_i2c_pdata,
- },
-};
-
-static const struct i2c_board_info n516_i2c_board_info[] = {
- {
- .type = "LPC524",
- .addr = 0x54,
- },
- {
- .type = "lm75a",
- .addr = 0x48,
- }
-};
-
-static struct jz4740_mmc_platform_data n516_mmc_pdata = {
- .gpio_card_detect = GPIO_SD_CD_N,
- .card_detect_active_low = 1,
- .gpio_read_only = -1,
- .gpio_power = GPIO_SD_VCC_EN_N,
- .power_active_low = 1,
-};
-
-static struct gpio_led n516_leds[] = {
- {
- .name = "n516:blue:power",
- .gpio = GPIO_LED_ENABLE,
- .default_state = LEDS_GPIO_DEFSTATE_ON,
- .default_trigger = "nand-disk",
- }
-};
-
-static struct gpio_led_platform_data n516_leds_pdata = {
- .leds = n516_leds,
- .num_leds = ARRAY_SIZE(n516_leds),
-};
-
-static struct platform_device n516_leds_device = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &n516_leds_pdata,
- },
-};
-
-static struct mtd_partition n516_partitions[] = {
- { .name = "NAND BOOT partition",
- .offset = 0 * 0x100000,
- .size = 4 * 0x100000,
- },
- { .name = "NAND KERNEL partition",
- .offset = 4 * 0x100000,
- .size = 4 * 0x100000,
- },
- { .name = "NAND ROOTFS partition",
- .offset = 8 * 0x100000,
- .size = 504 * 0x100000,
- },
-};
-
-static struct nand_ecclayout n516_ecclayout = {
- .eccbytes = 36,
- .eccpos = {
- 6, 7, 8, 9, 10, 11, 12, 13, 14,
- 15, 16, 17, 18, 19, 20, 21, 22, 23,
- 24, 25, 26, 27, 28, 29, 30, 31, 32,
- 33, 34, 35, 36, 37, 38, 39, 40, 41,
- },
- .oobfree = {
- {.offset = 2,
- .length = 4},
- {.offset = 42,
- .length = 22}}
-};
-
-static struct jz_nand_platform_data n516_nand_pdata = {
- .ecc_layout = &n516_ecclayout,
- .partitions = n516_partitions,
- .num_partitions = ARRAY_SIZE(n516_partitions),
- .busy_gpio = 94,
-};
-
-static char *n516_batteries[] = {
- "n516_battery",
-};
-
-static struct gpio_charger_platform_data n516_charger_pdata = {
- .name = "usb",
- .type = POWER_SUPPLY_TYPE_USB,
- .gpio = GPIO_USB_DETECT,
- .gpio_active_low = 1,
- .batteries = n516_batteries,
- .num_batteries = ARRAY_SIZE(n516_batteries),
-};
-
-static struct platform_device n516_charger_device = {
- .name = "gpio-charger",
- .dev = {
- .platform_data = &n516_charger_pdata,
- },
-};
-
-static struct platform_device *n516_devices[] __initdata = {
- &jz4740_nand_device,
- &n516_leds_device,
- &jz4740_mmc_device,
- &jz4740_i2s_device,
- &jz4740_codec_device,
- &jz4740_rtc_device,
- &jz4740_usb_gdt_device,
- &n516_i2c_device,
- &n516_charger_device,
-};
-
-struct jz4740_clock_board_data jz4740_clock_bdata = {
- .ext_rate = 12000000,
- .rtc_rate = 32768,
-};
-
-extern int jz_gpiolib_init(void);
-
-static int n516_setup_platform(void)
-{
- if (jz_gpiolib_init())
- panic("Failed to initalize jz gpio\n");
-
- jz4740_clock_init();
- board_gpio_setup();
-
- panic_blink = n516_panic_blink;
- i2c_register_board_info(0, n516_i2c_board_info, ARRAY_SIZE(n516_i2c_board_info));
- jz4740_mmc_device.dev.platform_data = &n516_mmc_pdata;
- jz4740_nand_device.dev.platform_data = &n516_nand_pdata;
-
- return platform_add_devices(n516_devices, ARRAY_SIZE(n516_devices));
-}
-arch_initcall(n516_setup_platform);
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/board-n526.c b/target/linux/xburst/files-2.6.32/arch/mips/jz4740/board-n526.c
deleted file mode 100644
index e3e671011..000000000
--- a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/board-n526.c
+++ /dev/null
@@ -1,333 +0,0 @@
-/*
- * Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
- * N526 eBook reader support
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/gpio.h>
-
-#include <asm/mach-jz4740/platform.h>
-
-#include <linux/mtd/jz4740_nand.h>
-#include <linux/jz4740_fb.h>
-#include <linux/power_supply.h>
-#include <linux/mmc/jz4740_mmc.h>
-
-#include <video/broadsheetfb.h>
-#include <linux/delay.h>
-#include <linux/interrupt.h>
-
-#include <linux/input.h>
-#include <linux/gpio_keys.h>
-
-#include <linux/i2c.h>
-#include <linux/i2c-gpio.h>
-
-#include "clock.h"
-
-/* NAND */
-static struct nand_ecclayout n526_ecclayout = {
- .eccbytes = 36,
- .eccpos = {
- 6, 7, 8, 9, 10, 11, 12, 13,
- 14, 15, 16, 17, 18, 19, 20, 21,
- 22, 23, 24, 25, 26, 27, 28, 29,
- 30, 31, 32, 33, 34, 35, 36, 37,
- 38, 39, 40, 41},
- .oobfree = {
- {.offset = 2,
- .length = 4},
- {.offset = 42,
- .length = 22}}
-};
-
-static struct mtd_partition n526_partitions[] = {
- { .name = "NAND BOOT partition",
- .offset = 0 * 0x100000,
- .size = 4 * 0x100000,
- },
- { .name = "NAND KERNEL partition",
- .offset = 4 * 0x100000,
- .size = 4 * 0x100000,
- },
- { .name = "NAND ROOTFS partition",
- .offset = 16 * 0x100000,
- .size = 498 * 0x100000,
- },
-};
-
-static struct jz_nand_platform_data n526_nand_pdata = {
- .ecc_layout = &n526_ecclayout,
- .partitions = n526_partitions,
- .num_partitions = ARRAY_SIZE(n526_partitions),
- .busy_gpio = 94,
-};
-
-static struct jz4740_mmc_platform_data n526_mmc_pdata = {
- .gpio_card_detect = JZ_GPIO_PORTD(7),
- .card_detect_active_low = 1,
- .gpio_read_only = -1,
- .gpio_power = JZ_GPIO_PORTD(17),
- .power_active_low = 1,
-};
-
-static struct gpio_led n526_leds[] = {
- {
- .name = "n526:blue:power",
- .gpio = JZ_GPIO_PORTD(28),
- .default_state = LEDS_GPIO_DEFSTATE_ON,
- }
-};
-
-static struct gpio_led_platform_data n526_leds_pdata = {
- .leds = n526_leds,
- .num_leds = ARRAY_SIZE(n526_leds),
-};
-
-static struct platform_device n526_leds_device = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &n526_leds_pdata,
- },
-};
-
-static void __init board_gpio_setup(void)
-{
- /* We only need to enable/disable pullup here for pins used in generic
- * drivers. Everything else is done by the drivers themselfs. */
- jz_gpio_disable_pullup(JZ_GPIO_PORTD(17));
- jz_gpio_enable_pullup(JZ_GPIO_PORTD(7));
- jz_gpio_disable_pullup(JZ_GPIO_PORTC(19));
- jz_gpio_disable_pullup(JZ_GPIO_PORTC(20));
- jz_gpio_disable_pullup(JZ_GPIO_PORTC(21));
- jz_gpio_disable_pullup(JZ_GPIO_PORTC(23));
-}
-
-
-static const int n526_eink_ctrl_gpios[] = {
- 0,
- JZ_GPIO_PORTC(23),
- JZ_GPIO_PORTC(19),
- JZ_GPIO_PORTC(20),
-};
-
-static void n526_eink_set_ctl(struct broadsheetfb_par * par, unsigned char ctrl, u8
-value)
-{
- gpio_set_value(n526_eink_ctrl_gpios[ctrl], value);
-}
-
-
-static int n526_eink_wait(struct broadsheetfb_par *par)
-{
- wait_event(par->waitq, gpio_get_value(JZ_GPIO_PORTB(17)));
-
- return 0;
-}
-
-static u16 n526_eink_get_hdb(struct broadsheetfb_par *par)
-{
- u16 value = 0;
- jz_gpio_port_direction_input(JZ_GPIO_PORTC(0), 0xffff);
- gpio_set_value(JZ_GPIO_PORTC(21), 0);
- mdelay(100);
-
- value = jz_gpio_port_get_value(JZ_GPIO_PORTC(0), 0xffff);
-
- gpio_set_value(JZ_GPIO_PORTC(21), 1);
- jz_gpio_port_direction_output(JZ_GPIO_PORTC(0), 0xffff);
- return value;
-}
-
-static void n526_eink_set_hdb(struct broadsheetfb_par *par, u16 value)
-{
- jz_gpio_port_set_value(JZ_GPIO_PORTC(0), value, 0xffff);
-}
-
-static int n526_eink_init(struct broadsheetfb_par *par)
-{
- int i;
-
- gpio_request(JZ_GPIO_PORTD(1), "display reset");
- gpio_direction_output(JZ_GPIO_PORTD(1), 1);
- mdelay(10);
- gpio_set_value(JZ_GPIO_PORTD(1), 0);
-
- gpio_request(JZ_GPIO_PORTB(18), "eink enable");
- gpio_direction_output(JZ_GPIO_PORTB(18), 0);
-
- gpio_request(JZ_GPIO_PORTB(29), "foobar");
- gpio_direction_output(JZ_GPIO_PORTB(29), 1);
-
- for(i = 1; i < ARRAY_SIZE(n526_eink_ctrl_gpios); ++i) {
- gpio_request(n526_eink_ctrl_gpios[i], "eink display ctrl");
- gpio_direction_output(n526_eink_ctrl_gpios[i], 0);
- }
-
- gpio_request(JZ_GPIO_PORTC(22), "foobar");
- gpio_direction_input(JZ_GPIO_PORTC(22));
- gpio_request(JZ_GPIO_PORTC(21), "eink nRD");
- gpio_direction_output(JZ_GPIO_PORTC(21), 1);
-
- for(i = 0; i < 16; ++i) {
- gpio_request(JZ_GPIO_PORTC(i), "eink display data");
- }
- jz_gpio_port_direction_output(JZ_GPIO_PORTC(0), 0xffff);
-
- gpio_set_value(JZ_GPIO_PORTB(18), 1);
-
- return 0;
-}
-
-static irqreturn_t n526_eink_busy_irq(int irq, void *devid)
-{
- struct broadsheetfb_par *par = devid;
- wake_up(&par->waitq);
-
- return IRQ_HANDLED;
-}
-
-static int n526_eink_setup_irq(struct fb_info *info)
-{
- int ret;
- struct broadsheetfb_par *par = info->par;
-
- gpio_request(JZ_GPIO_PORTB(17), "eink busy");
- gpio_direction_input(JZ_GPIO_PORTB(17));
-
- ret = request_irq(gpio_to_irq(JZ_GPIO_PORTB(17)), n526_eink_busy_irq,
- IRQF_DISABLED | IRQF_TRIGGER_RISING,
- "eink busyline", par);
- if (ret)
- printk("n526 display: Failed to request busyline irq: %d\n", ret);
- return 0;
-}
-
-static void n526_eink_cleanup(struct broadsheetfb_par *par)
-{
-}
-
-static struct broadsheet_board broadsheet_pdata = {
- .owner = THIS_MODULE,
- .init = n526_eink_init,
- .wait_for_rdy = n526_eink_wait,
- .set_ctl = n526_eink_set_ctl,
- .set_hdb = n526_eink_set_hdb,
- .get_hdb = n526_eink_get_hdb,
- .cleanup = n526_eink_cleanup,
- .setup_irq = n526_eink_setup_irq,
-};
-
-static struct platform_device n526_broadsheet_device = {
- .name = "broadsheetfb",
- .id = -1,
- .dev = {
- .platform_data = &broadsheet_pdata,
- },
-};
-
-static struct gpio_keys_button qi_lb60_gpio_keys_buttons[] = {
- [0] = {
- .code = KEY_ENTER,
- .gpio = 0,
- .active_low = 1,
- .desc = "Power",
- },
-};
-
-static struct gpio_keys_platform_data qi_lb60_gpio_keys_data = {
- .nbuttons = ARRAY_SIZE(qi_lb60_gpio_keys_buttons),
- .buttons = qi_lb60_gpio_keys_buttons,
-};
-
-static struct platform_device qi_lb60_gpio_keys = {
- .name = "gpio-keys",
- .id = -1,
- .dev = {
- .platform_data = &qi_lb60_gpio_keys_data,
- }
-};
-
-static struct i2c_gpio_platform_data n526_i2c_pdata = {
- .sda_pin = JZ_GPIO_PORTD(23),
- .scl_pin = JZ_GPIO_PORTD(24),
- .udelay = 2,
- .timeout = 3 * HZ,
-};
-
-static struct platform_device n526_i2c_device = {
- .name = "i2c-gpio",
- .id = -1,
- .dev = {
- .platform_data = &n526_i2c_pdata,
- },
-};
-
-static struct i2c_board_info n526_i2c_board_info = {
- .type = "n526-lpc",
- .addr = 0x54,
-};
-
-static struct platform_device *jz_platform_devices[] __initdata = {
- &jz4740_usb_ohci_device,
- &jz4740_usb_gdt_device,
- &jz4740_mmc_device,
- &jz4740_nand_device,
- &jz4740_i2s_device,
- &jz4740_codec_device,
- &jz4740_rtc_device,
- &n526_leds_device,
- &n526_broadsheet_device,
- &qi_lb60_gpio_keys,
- &n526_i2c_device,
-};
-
-
-static int __init n526_init_platform_devices(void)
-{
-
- jz4740_nand_device.dev.platform_data = &n526_nand_pdata;
- jz4740_mmc_device.dev.platform_data = &n526_mmc_pdata;
-
- n526_i2c_board_info.irq = gpio_to_irq(JZ_GPIO_PORTD(14)),
- i2c_register_board_info(0, &n526_i2c_board_info, 1);
-
- return platform_add_devices(jz_platform_devices,
- ARRAY_SIZE(jz_platform_devices));
-
-}
-
-struct jz4740_clock_board_data jz4740_clock_bdata = {
- .ext_rate = 12000000,
- .rtc_rate = 32768,
-};
-
-extern int jz_gpiolib_init(void);
-
-static int __init n526_board_setup(void)
-{
- if (jz_gpiolib_init())
- panic("Failed to initalize jz gpio\n");
-
- jz4740_clock_init();
- board_gpio_setup();
-
- if (n526_init_platform_devices())
- panic("Failed to initalize platform devices\n");
-
- return 0;
-}
-
-arch_initcall(n526_board_setup);
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/board-qi_lb60.c b/target/linux/xburst/files-2.6.32/arch/mips/jz4740/board-qi_lb60.c
deleted file mode 100644
index 800441716..000000000
--- a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/board-qi_lb60.c
+++ /dev/null
@@ -1,424 +0,0 @@
-/*
- * linux/arch/mips/jz4740/board-qi_lb60.c
- *
- * QI_LB60 setup routines.
- *
- * Copyright (c) 2009 Qi Hardware inc.,
- * Author: Xiangfu Liu <xiangfu@qi-hardware.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 or later
- * as published by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/gpio.h>
-
-#include <asm/mach-jz4740/board-qi_lb60.h>
-#include <asm/mach-jz4740/platform.h>
-
-#include <linux/input.h>
-#include <linux/gpio_keys.h>
-#include <linux/mtd/jz4740_nand.h>
-#include <linux/jz4740_fb.h>
-#include <linux/input/matrix_keypad.h>
-#include <linux/mtd/jz4740_nand.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/spi_gpio.h>
-#include <linux/power_supply.h>
-#include <linux/power/jz4740-battery.h>
-#include <linux/power/gpio-charger.h>
-#include <linux/mmc/jz4740_mmc.h>
-
-#include "clock.h"
-
-/* NAND */
-static struct nand_ecclayout qi_lb60_ecclayout_1gb = {
- .eccbytes = 36,
- .eccpos = {
- 6, 7, 8, 9, 10, 11, 12, 13,
- 14, 15, 16, 17, 18, 19, 20, 21,
- 22, 23, 24, 25, 26, 27, 28, 29,
- 30, 31, 32, 33, 34, 35, 36, 37,
- 38, 39, 40, 41},
- .oobfree = {
- {.offset = 2,
- .length = 4},
- {.offset = 42,
- .length = 22}}
-};
-
-static struct mtd_partition qi_lb60_partitions_1gb[] = {
- { .name = "NAND BOOT partition",
- .offset = 0 * 0x100000,
- .size = 4 * 0x100000,
- },
- { .name = "NAND KERNEL partition",
- .offset = 4 * 0x100000,
- .size = 4 * 0x100000,
- },
- { .name = "NAND ROOTFS partition",
- .offset = 8 * 0x100000,
- .size = (504 + 512) * 0x100000,
- },
-};
-
-static struct nand_ecclayout qi_lb60_ecclayout_2gb = {
- .eccbytes = 72,
- .eccpos = {
- 12, 13, 14, 15, 16, 17, 18, 19,
- 20, 21, 22, 23, 24, 25, 26, 27,
- 28, 29, 30, 31, 32, 33, 34, 35,
- 36, 37, 38, 39, 40, 41, 42, 43,
- 44, 45, 46, 47, 48, 49, 50, 51,
- 52, 53, 54, 55, 56, 57, 58, 59,
- 60, 61, 62, 63, 64, 65, 66, 67,
- 68, 69, 70, 71, 72, 73, 74, 75,
- 76, 77, 78, 79, 80, 81, 82, 83},
- .oobfree = {
- {.offset = 2,
- .length = 10},
- {.offset = 84,
- .length = 44}}
-};
-
-static struct mtd_partition qi_lb60_partitions_2gb[] = {
- { .name = "NAND BOOT partition",
- .offset = 0 * 0x100000,
- .size = 4 * 0x100000,
- },
- { .name = "NAND KERNEL partition",
- .offset = 4 * 0x100000,
- .size = 4 * 0x100000,
- },
- { .name = "NAND ROOTFS partition",
- .offset = 8 * 0x100000,
- .size = (504 + 512 + 1024) * 0x100000,
- },
-};
-
-static void qi_lb60_nand_ident(struct platform_device *pdev,
- struct nand_chip *chip,
- struct mtd_partition **partitions,
- int *num_partitions)
-{
- if (chip->page_shift == 12) {
- chip->ecc.layout = &qi_lb60_ecclayout_2gb;
- *partitions = qi_lb60_partitions_2gb;
- *num_partitions = ARRAY_SIZE(qi_lb60_partitions_2gb);
- } else {
- chip->ecc.layout = &qi_lb60_ecclayout_1gb;
- *partitions = qi_lb60_partitions_1gb;
- *num_partitions = ARRAY_SIZE(qi_lb60_partitions_1gb);
- }
-}
-
-static struct jz_nand_platform_data qi_lb60_nand_pdata = {
- .ident_callback = qi_lb60_nand_ident,
- .busy_gpio = 94,
-};
-
-/* Keyboard*/
-
-/* #define KEEP_UART_ALIVE
- * don't define this. the keyboard and keyboard both work
- */
-
-#define KEY_QI_QI KEY_F13
-#define KEY_QI_UPRED KEY_RIGHTALT
-#define KEY_QI_VOLUP KEY_VOLUMEUP
-#define KEY_QI_VOLDOWN KEY_VOLUMEDOWN
-#define KEY_QI_FN KEY_LEFTCTRL
-
-static const uint32_t qi_lb60_keymap[] = {
- KEY(0, 0, KEY_F1), /* S2 */
- KEY(0, 1, KEY_F2), /* S3 */
- KEY(0, 2, KEY_F3), /* S4 */
- KEY(0, 3, KEY_F4), /* S5 */
- KEY(0, 4, KEY_F5), /* S6 */
- KEY(0, 5, KEY_F6), /* S7 */
- KEY(0, 6, KEY_F7), /* S8 */
-
- KEY(1, 0, KEY_Q), /* S10 */
- KEY(1, 1, KEY_W), /* S11 */
- KEY(1, 2, KEY_E), /* S12 */
- KEY(1, 3, KEY_R), /* S13 */
- KEY(1, 4, KEY_T), /* S14 */
- KEY(1, 5, KEY_Y), /* S15 */
- KEY(1, 6, KEY_U), /* S16 */
- KEY(1, 7, KEY_I), /* S17 */
- KEY(2, 0, KEY_A), /* S18 */
- KEY(2, 1, KEY_S), /* S19 */
- KEY(2, 2, KEY_D), /* S20 */
- KEY(2, 3, KEY_F), /* S21 */
- KEY(2, 4, KEY_G), /* S22 */
- KEY(2, 5, KEY_H), /* S23 */
- KEY(2, 6, KEY_J), /* S24 */
- KEY(2, 7, KEY_K), /* S25 */
- KEY(3, 0, KEY_ESC), /* S26 */
- KEY(3, 1, KEY_Z), /* S27 */
- KEY(3, 2, KEY_X), /* S28 */
- KEY(3, 3, KEY_C), /* S29 */
- KEY(3, 4, KEY_V), /* S30 */
- KEY(3, 5, KEY_B), /* S31 */
- KEY(3, 6, KEY_N), /* S32 */
- KEY(3, 7, KEY_M), /* S33 */
- KEY(4, 0, KEY_TAB), /* S34 */
- KEY(4, 1, KEY_CAPSLOCK), /* S35 */
- KEY(4, 2, KEY_BACKSLASH), /* S36 */
- KEY(4, 3, KEY_APOSTROPHE), /* S37 */
- KEY(4, 4, KEY_COMMA), /* S38 */
- KEY(4, 5, KEY_DOT), /* S39 */
- KEY(4, 6, KEY_SLASH), /* S40 */
- KEY(4, 7, KEY_UP), /* S41 */
- KEY(5, 0, KEY_O), /* S42 */
- KEY(5, 1, KEY_L), /* S43 */
- KEY(5, 2, KEY_EQUAL), /* S44 */
- KEY(5, 3, KEY_QI_UPRED), /* S45 */
- KEY(5, 4, KEY_SPACE), /* S46 */
- KEY(5, 5, KEY_QI_QI), /* S47 */
- KEY(5, 6, KEY_RIGHTCTRL), /* S48 */
- KEY(5, 7, KEY_LEFT), /* S49 */
- KEY(6, 0, KEY_F8), /* S50 */
- KEY(6, 1, KEY_P), /* S51 */
- KEY(6, 2, KEY_BACKSPACE),/* S52 */
- KEY(6, 3, KEY_ENTER), /* S53 */
- KEY(6, 4, KEY_QI_VOLUP), /* S54 */
- KEY(6, 5, KEY_QI_VOLDOWN), /* S55 */
- KEY(6, 6, KEY_DOWN), /* S56 */
- KEY(6, 7, KEY_RIGHT), /* S57 */
-
-#ifndef KEEP_UART_ALIVE
- KEY(7, 0, KEY_LEFTSHIFT), /* S58 */
- KEY(7, 1, KEY_LEFTALT), /* S59 */
- KEY(7, 2, KEY_QI_FN), /* S60 */
-#endif
-};
-
-static const struct matrix_keymap_data qi_lb60_keymap_data = {
- .keymap = qi_lb60_keymap,
- .keymap_size = ARRAY_SIZE(qi_lb60_keymap),
-};
-
-static const unsigned int qi_lb60_keypad_cols[] = {
- 74, 75, 76, 77, 78, 79, 80, 81,
-};
-
-static const unsigned int qi_lb60_keypad_rows[] = {
- 114, 115, 116, 117, 118, 119, 120,
-#ifndef KEEP_UART_ALIVE
- 122,
-#endif
-};
-
-static struct matrix_keypad_platform_data qi_lb60_pdata = {
- .keymap_data = &qi_lb60_keymap_data,
- .col_gpios = qi_lb60_keypad_cols,
- .row_gpios = qi_lb60_keypad_rows,
- .num_col_gpios = ARRAY_SIZE(qi_lb60_keypad_cols),
- .num_row_gpios = ARRAY_SIZE(qi_lb60_keypad_rows),
- .col_scan_delay_us = 10,
- .debounce_ms = 10,
- .wakeup = 1,
- .active_low = 1,
-};
-
-static struct platform_device qi_lb60_keypad = {
- .name = "matrix-keypad",
- .id = -1,
- .dev = {
- .platform_data = &qi_lb60_pdata,
- },
-};
-
-/* Display */
-static struct fb_videomode qi_lb60_video_modes[] = {
- {
- .name = "320x240",
- .xres = 320,
- .yres = 240,
- .refresh = 30,
- .left_margin = 140,
- .right_margin = 273,
- .upper_margin = 20,
- .lower_margin = 2,
- .hsync_len = 1,
- .vsync_len = 1,
- .sync = 0,
- .vmode = FB_VMODE_NONINTERLACED,
- },
-};
-
-static struct jz4740_fb_platform_data qi_lb60_fb_pdata = {
- .width = 60,
- .height = 45,
- .num_modes = ARRAY_SIZE(qi_lb60_video_modes),
- .modes = qi_lb60_video_modes,
- .bpp = 24,
- .lcd_type = JZ_LCD_TYPE_8BIT_SERIAL,
- .pixclk_falling_edge = 1,
-};
-
-
-struct spi_gpio_platform_data spigpio_platform_data = {
- .sck = JZ_GPIO_PORTC(23),
- .mosi = JZ_GPIO_PORTC(22),
- .miso = JZ_GPIO_PORTC(22),
- .num_chipselect = 1,
-};
-
-static struct platform_device spigpio_device = {
- .name = "spi_gpio",
- .id = 1,
- .dev = {
- .platform_data = &spigpio_platform_data,
- },
-};
-
-static struct spi_board_info qi_lb60_spi_board_info[] = {
- {
- .modalias = "gpm940b0",
- .controller_data = (void*)JZ_GPIO_PORTC(21),
- .chip_select = 0,
- .bus_num = 1,
- .max_speed_hz = 30 * 1000,
- },
-};
-
-/* Battery */
-static struct jz_battery_platform_data qi_lb60_battery_pdata = {
- .gpio_charge = GPIO_CHARG_STAT_N,
- .gpio_charge_active_low = 1,
- .info = {
- .name = "battery",
- .technology = POWER_SUPPLY_TECHNOLOGY_LIPO,
- .voltage_max_design = 4200000,
- .voltage_min_design = 3600000,
- },
-};
-
-static char *qi_lb60_batteries[] = {
- "battery",
-};
-
-static struct gpio_charger_platform_data qi_lb60_charger_pdata = {
- .name = "USB",
- .type = POWER_SUPPLY_TYPE_USB,
- .gpio = GPIO_USB_DETE,
- .gpio_active_low = 1,
- .batteries = qi_lb60_batteries,
- .num_batteries = ARRAY_SIZE(qi_lb60_batteries),
-};
-
-static struct platform_device qi_lb60_charger_device = {
- .name = "gpio-charger",
- .dev = {
- .platform_data = &qi_lb60_charger_pdata,
- },
-};
-
-/* GPIO Key: power */
-static struct gpio_keys_button qi_lb60_gpio_keys_buttons[] = {
- [0] = {
- .code = KEY_POWER,
- .gpio = GPIO_WAKEUP_N,
- .active_low = 1,
- .desc = "Power",
- .wakeup = 1,
- },
-};
-
-static struct gpio_keys_platform_data qi_lb60_gpio_keys_data = {
- .nbuttons = ARRAY_SIZE(qi_lb60_gpio_keys_buttons),
- .buttons = qi_lb60_gpio_keys_buttons,
-};
-
-static struct platform_device qi_lb60_gpio_keys = {
- .name = "gpio-keys",
- .id = -1,
- .dev = {
- .platform_data = &qi_lb60_gpio_keys_data,
- }
-};
-
-static struct jz4740_mmc_platform_data qi_lb60_mmc_pdata = {
- .gpio_card_detect = JZ_GPIO_PORTD(0),
- .gpio_read_only = -1,
- .gpio_power = JZ_GPIO_PORTD(2),
- .power_active_low = 1,
-};
-
-static struct platform_device *jz_platform_devices[] __initdata = {
- &jz4740_usb_ohci_device,
- &jz4740_usb_gdt_device,
- &jz4740_mmc_device,
- &jz4740_nand_device,
- &qi_lb60_keypad,
- &spigpio_device,
- &jz4740_framebuffer_device,
- &jz4740_i2s_device,
- &jz4740_codec_device,
- &jz4740_rtc_device,
- &jz4740_adc_device,
- &jz4740_battery_device,
- &qi_lb60_gpio_keys,
- &qi_lb60_charger_device,
-};
-
-static void __init board_gpio_setup(void)
-{
- /* We only need to enable/disable pullup here for pins used in generic
- * drivers. Everything else is done by the drivers themselfs. */
- jz_gpio_disable_pullup(GPIO_SD_VCC_EN_N);
- jz_gpio_disable_pullup(GPIO_SD_CD_N);
-}
-
-static int __init qi_lb60_init_platform_devices(void)
-{
- jz4740_framebuffer_device.dev.platform_data = &qi_lb60_fb_pdata;
- jz4740_nand_device.dev.platform_data = &qi_lb60_nand_pdata;
- jz4740_battery_device.dev.platform_data = &qi_lb60_battery_pdata;
- jz4740_mmc_device.dev.platform_data = &qi_lb60_mmc_pdata;
-
- spi_register_board_info(qi_lb60_spi_board_info,
- ARRAY_SIZE(qi_lb60_spi_board_info));
-
- return platform_add_devices(jz_platform_devices,
- ARRAY_SIZE(jz_platform_devices));
-
-}
-
-struct jz4740_clock_board_data jz4740_clock_bdata = {
- .ext_rate = 12000000,
- .rtc_rate = 32768,
-};
-
-extern int jz_gpiolib_init(void);
-
-static __init int board_avt2(char *str)
-{
- qi_lb60_mmc_pdata.card_detect_active_low = 1;
- qi_lb60_mmc_pdata.power_active_low = 1;
-
- return 1;
-}
-
-__setup("avt2", board_avt2);
-
-static int __init qi_lb60_board_setup(void)
-{
- printk("Qi Hardware JZ4740 QI_LB60 setup\n");
- if (jz_gpiolib_init())
- panic("Failed to initalize jz gpio\n");
-
- jz4740_clock_init();
- board_gpio_setup();
-
- if (qi_lb60_init_platform_devices())
- panic("Failed to initalize platform devices\n");
-
- return 0;
-}
-
-arch_initcall(qi_lb60_board_setup);
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/clock-debugfs.c b/target/linux/xburst/files-2.6.32/arch/mips/jz4740/clock-debugfs.c
deleted file mode 100644
index 8968f7c67..000000000
--- a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/clock-debugfs.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
- * JZ4740 SoC clock support debugfs entries
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/clk.h>
-#include <linux/err.h>
-
-#include <linux/debugfs.h>
-#include <linux/uaccess.h>
-
-#include <asm/mach-jz4740/clock.h>
-#include "clock.h"
-
-static struct dentry *jz4740_clock_debugfs;
-
-static int jz4740_clock_debugfs_show_enabled(void *data, uint64_t *value)
-{
- struct clk *clk = data;
- *value = clk_is_enabled(clk);
-
- return 0;
-}
-
-static int jz4740_clock_debugfs_set_enabled(void *data, uint64_t value)
-{
- struct clk *clk = data;
-
- if (value)
- return clk_enable(clk);
- else
- clk_disable(clk);
-
- return 0;
-}
-
-DEFINE_SIMPLE_ATTRIBUTE(jz4740_clock_debugfs_ops_enabled,
- jz4740_clock_debugfs_show_enabled,
- jz4740_clock_debugfs_set_enabled,
- "%llu\n");
-
-static int jz4740_clock_debugfs_show_rate(void *data, uint64_t *value)
-{
- struct clk *clk = data;
- *value = clk_get_rate(clk);
-
- return 0;
-}
-
-DEFINE_SIMPLE_ATTRIBUTE(jz4740_clock_debugfs_ops_rate,
- jz4740_clock_debugfs_show_rate,
- NULL,
- "%llu\n");
-
-void jz4740_clock_debugfs_add_clk(struct clk *clk)
-{
- if (!jz4740_clock_debugfs)
- return;
-
- clk->debugfs_entry = debugfs_create_dir(clk->name, jz4740_clock_debugfs);
- debugfs_create_file("rate", S_IWUGO | S_IRUGO, clk->debugfs_entry, clk,
- &jz4740_clock_debugfs_ops_rate);
- debugfs_create_file("enabled", S_IRUGO, clk->debugfs_entry, clk,
- &jz4740_clock_debugfs_ops_enabled);
-
- if (clk->parent) {
- char parent_path[100];
- snprintf(parent_path, 100, "../%s", clk->parent->name);
- clk->debugfs_parent_entry = debugfs_create_symlink("parent",
- clk->debugfs_entry,
- parent_path);
- }
-}
-
-/* TODO: Locking */
-void jz4740_clock_debugfs_update_parent(struct clk *clk)
-{
- if (clk->debugfs_parent_entry)
- debugfs_remove(clk->debugfs_parent_entry);
-
- if (clk->parent) {
- char parent_path[100];
- snprintf(parent_path, 100, "../%s", clk->parent->name);
- clk->debugfs_parent_entry = debugfs_create_symlink("parent",
- clk->debugfs_entry,
- parent_path);
- } else {
- clk->debugfs_parent_entry = NULL;
- }
-}
-
-void jz4740_clock_debugfs_init(void)
-{
- jz4740_clock_debugfs = debugfs_create_dir("jz4740-clock", NULL);
- if (IS_ERR(jz4740_clock_debugfs))
- jz4740_clock_debugfs = NULL;
-}
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/clock.c b/target/linux/xburst/files-2.6.32/arch/mips/jz4740/clock.c
deleted file mode 100644
index a780706be..000000000
--- a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/clock.c
+++ /dev/null
@@ -1,930 +0,0 @@
-/*
- * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
- * JZ4740 SoC clock support
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/clk.h>
-#include <linux/spinlock.h>
-#include <linux/io.h>
-#include <linux/module.h>
-#include <linux/list.h>
-#include <linux/err.h>
-
-#include <asm/mach-jz4740/clock.h>
-#include "clock.h"
-
-#define JZ_REG_CLOCK_CTRL 0x00
-#define JZ_REG_CLOCK_LOW_POWER 0x04
-#define JZ_REG_CLOCK_PLL 0x10
-#define JZ_REG_CLOCK_GATE 0x20
-#define JZ_REG_CLOCK_SLEEP_CTRL 0x24
-#define JZ_REG_CLOCK_I2S 0x60
-#define JZ_REG_CLOCK_LCD 0x64
-#define JZ_REG_CLOCK_MMC 0x68
-#define JZ_REG_CLOCK_UHC 0x6C
-#define JZ_REG_CLOCK_SPI 0x74
-
-#define JZ_CLOCK_CTRL_I2S_SRC_PLL BIT(31)
-#define JZ_CLOCK_CTRL_KO_ENABLE BIT(30)
-#define JZ_CLOCK_CTRL_UDC_SRC_PLL BIT(29)
-#define JZ_CLOCK_CTRL_UDIV_MASK 0x1f800000
-#define JZ_CLOCK_CTRL_CHANGE_ENABLE BIT(22)
-#define JZ_CLOCK_CTRL_PLL_HALF BIT(21)
-#define JZ_CLOCK_CTRL_LDIV_MASK 0x001f0000
-#define JZ_CLOCK_CTRL_UDIV_OFFSET 23
-#define JZ_CLOCK_CTRL_LDIV_OFFSET 16
-#define JZ_CLOCK_CTRL_MDIV_OFFSET 12
-#define JZ_CLOCK_CTRL_PDIV_OFFSET 8
-#define JZ_CLOCK_CTRL_HDIV_OFFSET 4
-#define JZ_CLOCK_CTRL_CDIV_OFFSET 0
-
-#define JZ_CLOCK_GATE_UART0 BIT(0)
-#define JZ_CLOCK_GATE_TCU BIT(1)
-#define JZ_CLOCK_GATE_RTC BIT(2)
-#define JZ_CLOCK_GATE_I2C BIT(3)
-#define JZ_CLOCK_GATE_SPI BIT(4)
-#define JZ_CLOCK_GATE_AIC BIT(5)
-#define JZ_CLOCK_GATE_I2S BIT(6)
-#define JZ_CLOCK_GATE_MMC BIT(7)
-#define JZ_CLOCK_GATE_ADC BIT(8)
-#define JZ_CLOCK_GATE_CIM BIT(9)
-#define JZ_CLOCK_GATE_LCD BIT(10)
-#define JZ_CLOCK_GATE_UDC BIT(11)
-#define JZ_CLOCK_GATE_DMAC BIT(12)
-#define JZ_CLOCK_GATE_IPU BIT(13)
-#define JZ_CLOCK_GATE_UHC BIT(14)
-#define JZ_CLOCK_GATE_UART1 BIT(15)
-
-#define JZ_CLOCK_I2S_DIV_MASK 0x01ff
-
-#define JZ_CLOCK_LCD_DIV_MASK 0x01ff
-
-#define JZ_CLOCK_MMC_DIV_MASK 0x001f
-
-#define JZ_CLOCK_UHC_DIV_MASK 0x000f
-
-#define JZ_CLOCK_SPI_SRC_PLL BIT(31)
-#define JZ_CLOCK_SPI_DIV_MASK 0x000f
-
-#define JZ_CLOCK_PLL_M_MASK 0x01ff
-#define JZ_CLOCK_PLL_N_MASK 0x001f
-#define JZ_CLOCK_PLL_OD_MASK 0x0003
-#define JZ_CLOCK_PLL_STABLE BIT(10)
-#define JZ_CLOCK_PLL_BYPASS BIT(9)
-#define JZ_CLOCK_PLL_ENABLED BIT(8)
-#define JZ_CLOCK_PLL_STABLIZE_MASK 0x000f
-#define JZ_CLOCK_PLL_M_OFFSET 23
-#define JZ_CLOCK_PLL_N_OFFSET 18
-#define JZ_CLOCK_PLL_OD_OFFSET 16
-
-#define JZ_CLOCK_LOW_POWER_MODE_DOZE BIT(2)
-#define JZ_CLOCK_LOW_POWER_MODE_SLEEP BIT(0)
-
-#define JZ_CLOCK_SLEEP_CTRL_SUSPEND_UHC BIT(7)
-#define JZ_CLOCK_SLEEP_CTRL_ENABLE_UDC BIT(6)
-
-static void __iomem *jz_clock_base;
-static spinlock_t jz_clock_lock;
-static LIST_HEAD(jz_clocks);
-
-struct main_clk {
- struct clk clk;
- uint32_t div_offset;
-};
-
-struct divided_clk {
- struct clk clk;
- uint32_t reg;
- uint32_t mask;
-};
-
-struct static_clk {
- struct clk clk;
- unsigned long rate;
-};
-
-static uint32_t jz_clk_reg_read(int reg)
-{
- return readl(jz_clock_base + reg);
-}
-
-static void jz_clk_reg_write_mask(int reg, uint32_t val, uint32_t mask)
-{
- uint32_t val2;
-
- spin_lock(&jz_clock_lock);
- val2 = readl(jz_clock_base + reg);
- val2 &= ~mask;
- val2 |= val;
- writel(val2, jz_clock_base + reg);
- spin_unlock(&jz_clock_lock);
-}
-
-static void jz_clk_reg_set_bits(int reg, uint32_t mask)
-{
- uint32_t val;
-
- spin_lock(&jz_clock_lock);
- val = readl(jz_clock_base + reg);
- val |= mask;
- writel(val, jz_clock_base + reg);
- spin_unlock(&jz_clock_lock);
-}
-
-static void jz_clk_reg_clear_bits(int reg, uint32_t mask)
-{
- uint32_t val;
-
- spin_lock(&jz_clock_lock);
- val = readl(jz_clock_base + reg);
- val &= ~mask;
- writel(val, jz_clock_base + reg);
- spin_unlock(&jz_clock_lock);
-}
-
-static int jz_clk_enable_gating(struct clk *clk)
-{
- if (clk->gate_bit == JZ4740_CLK_NOT_GATED)
- return -EINVAL;
-
- jz_clk_reg_clear_bits(JZ_REG_CLOCK_GATE, clk->gate_bit);
- return 0;
-}
-
-static int jz_clk_disable_gating(struct clk *clk)
-{
- if (clk->gate_bit == JZ4740_CLK_NOT_GATED)
- return -EINVAL;
-
- jz_clk_reg_set_bits(JZ_REG_CLOCK_GATE, clk->gate_bit);
- return 0;
-}
-
-static int jz_clk_is_enabled_gating(struct clk *clk)
-{
- if (clk->gate_bit == JZ4740_CLK_NOT_GATED)
- return 1;
-
- return !(jz_clk_reg_read(JZ_REG_CLOCK_GATE) & clk->gate_bit);
-}
-
-static unsigned long jz_clk_static_get_rate(struct clk *clk)
-{
- return ((struct static_clk*)clk)->rate;
-}
-
-static int jz_clk_ko_enable(struct clk *clk)
-{
- jz_clk_reg_set_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_KO_ENABLE);
- return 0;
-}
-
-static int jz_clk_ko_disable(struct clk *clk)
-{
- jz_clk_reg_clear_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_KO_ENABLE);
- return 0;
-}
-
-static int jz_clk_ko_is_enabled(struct clk *clk)
-{
- return !!(jz_clk_reg_read(JZ_REG_CLOCK_CTRL) & JZ_CLOCK_CTRL_KO_ENABLE);
-}
-
-static const int pllno[] = {1, 2, 2, 4};
-
-static unsigned long jz_clk_pll_get_rate(struct clk *clk)
-{
- uint32_t val;
- int m;
- int n;
- int od;
-
- val = jz_clk_reg_read(JZ_REG_CLOCK_PLL);
-
- if (val & JZ_CLOCK_PLL_BYPASS)
- return clk_get_rate(clk->parent);
-
- m = ((val >> 23) & 0x1ff) + 2;
- n = ((val >> 18) & 0x1f) + 2;
- od = (val >> 16) & 0x3;
-
- return clk_get_rate(clk->parent) * (m / n) / pllno[od];
-}
-
-static unsigned long jz_clk_pll_half_get_rate(struct clk *clk)
-{
- uint32_t reg;
-
- reg = jz_clk_reg_read(JZ_REG_CLOCK_CTRL);
- if (reg & JZ_CLOCK_CTRL_PLL_HALF)
- return jz_clk_pll_get_rate(clk->parent);
- return jz_clk_pll_get_rate(clk->parent) >> 1;
-}
-
-static const int jz_clk_main_divs[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
-
-static unsigned long jz_clk_main_round_rate(struct clk *clk, unsigned long rate)
-{
- unsigned long parent_rate = jz_clk_pll_get_rate(clk->parent);
- int div;
-
- div = parent_rate / rate;
- if (div > 32)
- return parent_rate / 32;
- else if (div < 1)
- return parent_rate;
-
- div &= (0x3 << (ffs(div) - 1));
-
- return parent_rate / div;
-}
-
-static unsigned long jz_clk_main_get_rate(struct clk *clk) {
- struct main_clk *mclk = (struct main_clk*)clk;
- uint32_t div;
-
- div = jz_clk_reg_read(JZ_REG_CLOCK_CTRL);
-
- div >>= mclk->div_offset;
- div &= 0xf;
-
- if (div >= ARRAY_SIZE(jz_clk_main_divs))
- div = ARRAY_SIZE(jz_clk_main_divs) - 1;
-
- return jz_clk_pll_get_rate(clk->parent) / jz_clk_main_divs[div];
-}
-
-static int jz_clk_main_set_rate(struct clk *clk, unsigned long rate)
-{
- struct main_clk *mclk = (struct main_clk*)clk;
- int i;
- int div;
- unsigned long parent_rate = jz_clk_pll_get_rate(clk->parent);
-
- rate = jz_clk_main_round_rate(clk, rate);
-
- div = parent_rate / rate;
-
- i = (ffs(div) - 1) << 1;
- if (i > 0 && !(div & BIT(i-1)))
- i -= 1;
-
- jz_clk_reg_write_mask(JZ_REG_CLOCK_CTRL, i << mclk->div_offset,
- 0xf << mclk->div_offset);
-
- return 0;
-}
-
-static struct clk_ops jz_clk_static_ops = {
- .get_rate = jz_clk_static_get_rate,
- .enable = jz_clk_enable_gating,
- .disable = jz_clk_disable_gating,
- .is_enabled = jz_clk_is_enabled_gating,
-};
-
-static struct static_clk jz_clk_ext = {
- .clk = {
- .name = "ext",
- .gate_bit = JZ4740_CLK_NOT_GATED,
- .ops = &jz_clk_static_ops,
- },
-};
-
-static struct clk_ops jz_clk_pll_ops = {
- .get_rate = jz_clk_static_get_rate,
-};
-
-static struct clk jz_clk_pll = {
- .name = "pll",
- .parent = &jz_clk_ext.clk,
- .ops = &jz_clk_pll_ops,
-};
-
-static struct clk_ops jz_clk_pll_half_ops = {
- .get_rate = jz_clk_pll_half_get_rate,
-};
-
-static struct clk jz_clk_pll_half = {
- .name = "pll half",
- .parent = &jz_clk_pll,
- .ops = &jz_clk_pll_half_ops,
-};
-
-static const struct clk_ops jz_clk_main_ops = {
- .get_rate = jz_clk_main_get_rate,
- .set_rate = jz_clk_main_set_rate,
- .round_rate = jz_clk_main_round_rate,
-};
-
-static struct main_clk jz_clk_cpu = {
- .clk = {
- .name = "cclk",
- .parent = &jz_clk_pll,
- .ops = &jz_clk_main_ops,
- },
- .div_offset = JZ_CLOCK_CTRL_CDIV_OFFSET,
-};
-
-static struct main_clk jz_clk_memory = {
- .clk = {
- .name = "mclk",
- .parent = &jz_clk_pll,
- .ops = &jz_clk_main_ops,
- },
- .div_offset = JZ_CLOCK_CTRL_MDIV_OFFSET,
-};
-
-static struct main_clk jz_clk_high_speed_peripheral = {
- .clk = {
- .name = "hclk",
- .parent = &jz_clk_pll,
- .ops = &jz_clk_main_ops,
- },
- .div_offset = JZ_CLOCK_CTRL_HDIV_OFFSET,
-};
-
-
-static struct main_clk jz_clk_low_speed_peripheral = {
- .clk = {
- .name = "pclk",
- .parent = &jz_clk_pll,
- .ops = &jz_clk_main_ops,
- },
- .div_offset = JZ_CLOCK_CTRL_PDIV_OFFSET,
-};
-
-static const struct clk_ops jz_clk_ko_ops = {
- .enable = jz_clk_ko_enable,
- .disable = jz_clk_ko_disable,
- .is_enabled = jz_clk_ko_is_enabled,
-};
-
-static struct clk jz_clk_ko = {
- .name = "cko",
- .parent = &jz_clk_memory.clk,
- .ops = &jz_clk_ko_ops,
-};
-
-static int jz_clk_spi_set_parent(struct clk *clk, struct clk *parent)
-{
- if (parent == &jz_clk_pll)
- jz_clk_reg_set_bits(JZ_CLOCK_SPI_SRC_PLL, JZ_REG_CLOCK_SPI);
- else if(parent == &jz_clk_ext.clk)
- jz_clk_reg_clear_bits(JZ_CLOCK_SPI_SRC_PLL, JZ_REG_CLOCK_SPI);
- else
- return -EINVAL;
-
- clk->parent = parent;
-
- return 0;
-}
-
-static int jz_clk_i2s_set_parent(struct clk *clk, struct clk *parent)
-{
- if (parent == &jz_clk_pll_half)
- jz_clk_reg_set_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_I2S_SRC_PLL);
- else if(parent == &jz_clk_ext.clk)
- jz_clk_reg_clear_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_I2S_SRC_PLL);
- else
- return -EINVAL;
-
- clk->parent = parent;
-
- return 0;
-}
-
-static int jz_clk_udc_enable(struct clk *clk)
-{
- jz_clk_reg_set_bits(JZ_REG_CLOCK_SLEEP_CTRL,
- JZ_CLOCK_SLEEP_CTRL_ENABLE_UDC);
-
- return 0;
-}
-
-static int jz_clk_udc_disable(struct clk *clk)
-{
- jz_clk_reg_clear_bits(JZ_REG_CLOCK_SLEEP_CTRL,
- JZ_CLOCK_SLEEP_CTRL_ENABLE_UDC);
-
- return 0;
-}
-
-static int jz_clk_udc_is_enabled(struct clk *clk)
-{
- return !!(jz_clk_reg_read(JZ_REG_CLOCK_SLEEP_CTRL) &
- JZ_CLOCK_SLEEP_CTRL_ENABLE_UDC);
-}
-static int jz_clk_udc_set_parent(struct clk *clk, struct clk *parent)
-{
- if (parent == &jz_clk_pll_half)
- jz_clk_reg_set_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_UDC_SRC_PLL);
- else if(parent == &jz_clk_ext.clk)
- jz_clk_reg_clear_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_UDC_SRC_PLL);
- else
- return -EINVAL;
-
- clk->parent = parent;
-
- return 0;
-}
-
-static int jz_clk_udc_set_rate(struct clk *clk, unsigned long rate)
-{
- int div;
-
- if (clk->parent == &jz_clk_ext.clk)
- return -EINVAL;
-
- div = clk_get_rate(clk->parent) / rate - 1;
-
- if (div < 0)
- div = 0;
- else if (div > 63)
- div = 63;
-
- jz_clk_reg_write_mask(JZ_REG_CLOCK_CTRL, div << JZ_CLOCK_CTRL_UDIV_OFFSET,
- JZ_CLOCK_CTRL_UDIV_MASK);
- return 0;
-}
-
-static unsigned long jz_clk_udc_get_rate(struct clk *clk)
-{
- int div;
-
- if (clk->parent == &jz_clk_ext.clk)
- return clk_get_rate(clk->parent);
-
- div = (jz_clk_reg_read(JZ_REG_CLOCK_CTRL) & JZ_CLOCK_CTRL_UDIV_MASK);
- div >>= JZ_CLOCK_CTRL_UDIV_OFFSET;
- div += 1;
-
- return clk_get_rate(clk->parent) / div;
-}
-
-static unsigned long jz_clk_divided_get_rate(struct clk *clk)
-{
- struct divided_clk *dclk = (struct divided_clk*)clk;
- int div;
-
- if (clk->parent == &jz_clk_ext.clk)
- return clk_get_rate(clk->parent);
-
- div = (jz_clk_reg_read(dclk->reg) & dclk->mask) + 1;
-
- return clk_get_rate(clk->parent) / div;
-}
-
-static int jz_clk_divided_set_rate(struct clk *clk, unsigned long rate)
-{
- struct divided_clk *dclk = (struct divided_clk*)clk;
- int div;
-
- if (clk->parent == &jz_clk_ext.clk)
- return -EINVAL;
-
- div = clk_get_rate(clk->parent) / rate - 1;
-
- if (div < 0)
- div = 0;
- else if(div > dclk->mask)
- div = dclk->mask;
-
- jz_clk_reg_write_mask(dclk->reg, div, dclk->mask);
-
- return 0;
-}
-
-static unsigned long jz_clk_ldclk_round_rate(struct clk *clk, unsigned long rate)
-{
- int div;
- unsigned long parent_rate = jz_clk_pll_half_get_rate(clk->parent);
-
- if (rate > 150000000)
- return 150000000;
-
- div = parent_rate / rate;
- if (div < 1)
- div = 1;
- else if(div > 32)
- div = 32;
-
- return parent_rate / div;
-}
-
-static int jz_clk_ldclk_set_rate(struct clk *clk, unsigned long rate)
-{
- int div;
-
- if (rate > 150000000)
- return -EINVAL;
-
- div = jz_clk_pll_half_get_rate(clk->parent) / rate - 1;
- if (div < 0)
- div = 0;
- else if(div > 31)
- div = 31;
-
- jz_clk_reg_write_mask(JZ_REG_CLOCK_CTRL, div << JZ_CLOCK_CTRL_LDIV_OFFSET,
- JZ_CLOCK_CTRL_LDIV_MASK);
-
- return 0;
-}
-
-static unsigned long jz_clk_ldclk_get_rate(struct clk *clk)
-{
- int div;
-
- div = jz_clk_reg_read(JZ_REG_CLOCK_CTRL) & JZ_CLOCK_CTRL_LDIV_MASK;
- div >>= JZ_CLOCK_CTRL_LDIV_OFFSET;
-
- return jz_clk_pll_half_get_rate(clk->parent) / (div + 1);
-}
-
-static const struct clk_ops jz_clk_ops_ld = {
- .set_rate = jz_clk_ldclk_set_rate,
- .get_rate = jz_clk_ldclk_get_rate,
- .round_rate = jz_clk_ldclk_round_rate,
- .enable = jz_clk_enable_gating,
- .disable = jz_clk_disable_gating,
- .is_enabled = jz_clk_is_enabled_gating,
-};
-
-static struct clk jz_clk_ld = {
- .name = "lcd",
- .gate_bit = JZ_CLOCK_GATE_LCD,
- .parent = &jz_clk_pll_half,
- .ops = &jz_clk_ops_ld,
-};
-
-/* TODO: ops!!! */
-static struct clk jz_clk_cim_mclk = {
- .name = "cim_mclk",
- .parent = &jz_clk_high_speed_peripheral.clk,
-};
-
-static struct static_clk jz_clk_cim_pclk = {
- .clk = {
- .name = "cim_pclk",
- .gate_bit = JZ_CLOCK_GATE_CIM,
- .ops = &jz_clk_static_ops,
- },
-};
-
-static const struct clk_ops jz_clk_i2s_ops =
-{
- .set_rate = jz_clk_divided_set_rate,
- .get_rate = jz_clk_divided_get_rate,
- .enable = jz_clk_enable_gating,
- .disable = jz_clk_disable_gating,
- .is_enabled = jz_clk_is_enabled_gating,
- .set_parent = jz_clk_i2s_set_parent,
-};
-
-static const struct clk_ops jz_clk_spi_ops =
-{
- .set_rate = jz_clk_divided_set_rate,
- .get_rate = jz_clk_divided_get_rate,
- .enable = jz_clk_enable_gating,
- .disable = jz_clk_disable_gating,
- .is_enabled = jz_clk_is_enabled_gating,
- .set_parent = jz_clk_spi_set_parent,
-};
-
-static const struct clk_ops jz_clk_divided_ops =
-{
- .set_rate = jz_clk_divided_set_rate,
- .get_rate = jz_clk_divided_get_rate,
- .enable = jz_clk_enable_gating,
- .disable = jz_clk_disable_gating,
- .is_enabled = jz_clk_is_enabled_gating,
-};
-
-static struct divided_clk jz4740_clock_divided_clks[] = {
- {
- .clk = {
- .name = "lcd_pclk",
- .parent = &jz_clk_pll_half,
- .gate_bit = JZ4740_CLK_NOT_GATED,
- .ops = &jz_clk_divided_ops,
- },
- .reg = JZ_REG_CLOCK_LCD,
- .mask = JZ_CLOCK_LCD_DIV_MASK,
- },
- {
- .clk = {
- .name = "i2s",
- .parent = &jz_clk_ext.clk,
- .gate_bit = JZ_CLOCK_GATE_I2S,
- .ops = &jz_clk_i2s_ops,
- },
- .reg = JZ_REG_CLOCK_I2S,
- .mask = JZ_CLOCK_I2S_DIV_MASK,
- },
- {
- .clk = {
- .name = "spi",
- .parent = &jz_clk_ext.clk,
- .gate_bit = JZ_CLOCK_GATE_SPI,
- .ops = &jz_clk_spi_ops,
- },
- .reg = JZ_REG_CLOCK_SPI,
- .mask = JZ_CLOCK_SPI_DIV_MASK,
- },
- {
- .clk = {
- .name = "mmc",
- .parent = &jz_clk_pll_half,
- .gate_bit = JZ_CLOCK_GATE_MMC,
- .ops = &jz_clk_divided_ops,
- },
- .reg = JZ_REG_CLOCK_MMC,
- .mask = JZ_CLOCK_MMC_DIV_MASK,
- },
- {
- .clk = {
- .name = "uhc",
- .parent = &jz_clk_pll_half,
- .gate_bit = JZ_CLOCK_GATE_UHC,
- .ops = &jz_clk_divided_ops,
- },
- .reg = JZ_REG_CLOCK_UHC,
- .mask = JZ_CLOCK_UHC_DIV_MASK,
- },
-};
-
-static const struct clk_ops jz_clk_udc_ops = {
- .set_parent = jz_clk_udc_set_parent,
- .set_rate = jz_clk_udc_set_rate,
- .get_rate = jz_clk_udc_get_rate,
- .enable = jz_clk_udc_enable,
- .disable = jz_clk_udc_disable,
- .is_enabled = jz_clk_udc_is_enabled,
-};
-
-static const struct clk_ops jz_clk_simple_ops = {
- .enable = jz_clk_enable_gating,
- .disable = jz_clk_disable_gating,
- .is_enabled = jz_clk_is_enabled_gating,
-};
-
-static struct clk jz4740_clock_simple_clks[] = {
- {
- .name = "udc",
- .parent = &jz_clk_ext.clk,
- .ops = &jz_clk_udc_ops,
- },
- {
- .name = "uart0",
- .parent = &jz_clk_ext.clk,
- .gate_bit = JZ_CLOCK_GATE_UART0,
- .ops = &jz_clk_simple_ops,
- },
- {
- .name = "uart1",
- .parent = &jz_clk_ext.clk,
- .gate_bit = JZ_CLOCK_GATE_UART1,
- .ops = &jz_clk_simple_ops,
- },
- {
- .name = "dma",
- .parent = &jz_clk_high_speed_peripheral.clk,
- .gate_bit = JZ_CLOCK_GATE_UART0,
- .ops = &jz_clk_simple_ops,
- },
- {
- .name = "ipu",
- .parent = &jz_clk_high_speed_peripheral.clk,
- .gate_bit = JZ_CLOCK_GATE_IPU,
- .ops = &jz_clk_simple_ops,
- },
- {
- .name = "adc",
- .parent = &jz_clk_ext.clk,
- .gate_bit = JZ_CLOCK_GATE_ADC,
- .ops = &jz_clk_simple_ops,
- },
- {
- .name = "i2c",
- .parent = &jz_clk_ext.clk,
- .gate_bit = JZ_CLOCK_GATE_I2C,
- .ops = &jz_clk_simple_ops,
- },
- {
- .name = "aic",
- .parent = &jz_clk_ext.clk,
- .gate_bit = JZ_CLOCK_GATE_AIC,
- .ops = &jz_clk_simple_ops,
- },
-};
-
-static struct static_clk jz_clk_rtc = {
- .clk = {
- .name = "rtc",
- .gate_bit = JZ_CLOCK_GATE_RTC,
- .ops = &jz_clk_static_ops,
- },
- .rate = 32768,
-};
-
-int clk_enable(struct clk *clk)
-{
- if (!clk->ops->enable)
- return -EINVAL;
-
- return clk->ops->enable(clk);
-}
-EXPORT_SYMBOL_GPL(clk_enable);
-
-void clk_disable(struct clk *clk)
-{
- if (clk->ops->disable)
- clk->ops->disable(clk);
-}
-EXPORT_SYMBOL_GPL(clk_disable);
-
-int clk_is_enabled(struct clk *clk)
-{
- if (clk->ops->is_enabled)
- return clk->ops->is_enabled(clk);
-
- return 1;
-}
-
-unsigned long clk_get_rate(struct clk *clk)
-{
- if (clk->ops->get_rate)
- return clk->ops->get_rate(clk);
- if (clk->parent)
- return clk_get_rate(clk->parent);
-
- return -EINVAL;
-}
-EXPORT_SYMBOL_GPL(clk_get_rate);
-
-int clk_set_rate(struct clk *clk, unsigned long rate)
-{
- if (!clk->ops->set_rate)
- return -EINVAL;
- return clk->ops->set_rate(clk, rate);
-}
-EXPORT_SYMBOL_GPL(clk_set_rate);
-
-long clk_round_rate(struct clk *clk, unsigned long rate)
-{
- if (clk->ops->round_rate)
- return clk->ops->round_rate(clk, rate);
-
- return -EINVAL;
-}
-EXPORT_SYMBOL_GPL(clk_round_rate);
-
-int clk_set_parent(struct clk *clk, struct clk *parent)
-{
- int ret;
-
- if (!clk->ops->set_parent)
- return -EINVAL;
-
- clk_disable(clk);
- ret = clk->ops->set_parent(clk, parent);
- clk_enable(clk);
-
- jz4740_clock_debugfs_update_parent(clk);
-
- return ret;
-}
-EXPORT_SYMBOL_GPL(clk_set_parent);
-
-struct clk *clk_get(struct device *dev, const char *name)
-{
- struct clk *clk;
-
- list_for_each_entry(clk, &jz_clocks, list) {
- if (strcmp(clk->name, name) == 0)
- return clk;
- }
- return ERR_PTR(-ENOENT);
-}
-EXPORT_SYMBOL_GPL(clk_get);
-
-void clk_put(struct clk *clk)
-{
-}
-EXPORT_SYMBOL_GPL(clk_put);
-
-
-inline static void clk_add(struct clk *clk)
-{
- list_add_tail(&clk->list, &jz_clocks);
-
- jz4740_clock_debugfs_add_clk(clk);
-}
-
-static void clk_register_clks(void)
-{
- size_t i;
-
- clk_add(&jz_clk_ext.clk);
- clk_add(&jz_clk_pll);
- clk_add(&jz_clk_pll_half);
- clk_add(&jz_clk_cpu.clk);
- clk_add(&jz_clk_high_speed_peripheral.clk);
- clk_add(&jz_clk_low_speed_peripheral.clk);
- clk_add(&jz_clk_ko);
- clk_add(&jz_clk_ld);
- clk_add(&jz_clk_cim_mclk);
- clk_add(&jz_clk_cim_pclk.clk);
- clk_add(&jz_clk_rtc.clk);
-
- for (i = 0; i < ARRAY_SIZE(jz4740_clock_divided_clks); ++i)
- clk_add(&jz4740_clock_divided_clks[i].clk);
-
- for (i = 0; i < ARRAY_SIZE(jz4740_clock_simple_clks); ++i)
- clk_add(&jz4740_clock_simple_clks[i]);
-}
-
-void jz4740_clock_set_wait_mode(enum jz4740_wait_mode mode)
-{
- switch (mode) {
- case JZ4740_WAIT_MODE_IDLE:
- jz_clk_reg_clear_bits(JZ_REG_CLOCK_LOW_POWER, JZ_CLOCK_LOW_POWER_MODE_SLEEP);
- break;
- case JZ4740_WAIT_MODE_SLEEP:
- jz_clk_reg_set_bits(JZ_REG_CLOCK_LOW_POWER, JZ_CLOCK_LOW_POWER_MODE_SLEEP);
- break;
- }
-}
-
-void jz4740_clock_udc_disable_auto_suspend(void)
-{
- jz_clk_reg_clear_bits(JZ_REG_CLOCK_GATE, JZ_CLOCK_GATE_UDC);
-}
-EXPORT_SYMBOL_GPL(jz4740_clock_udc_disable_auto_suspend);
-
-void jz4740_clock_udc_enable_auto_suspend(void)
-{
- jz_clk_reg_set_bits(JZ_REG_CLOCK_GATE, JZ_CLOCK_GATE_UDC);
-}
-EXPORT_SYMBOL_GPL(jz4740_clock_udc_enable_auto_suspend);
-
-void jz4740_clock_suspend(void)
-{
- jz_clk_reg_set_bits(JZ_REG_CLOCK_GATE,
- JZ_CLOCK_GATE_TCU | JZ_CLOCK_GATE_DMAC | JZ_CLOCK_GATE_UART0);
-
- jz_clk_reg_clear_bits(JZ_REG_CLOCK_PLL, JZ_CLOCK_PLL_ENABLED);
-}
-
-void jz4740_clock_resume(void)
-{
- jz_clk_reg_set_bits(JZ_REG_CLOCK_PLL, JZ_CLOCK_PLL_ENABLED);
- while ((jz_clk_reg_read(JZ_REG_CLOCK_PLL) & JZ_CLOCK_PLL_STABLE) == 0);
-
- jz_clk_reg_clear_bits(JZ_REG_CLOCK_GATE,
- JZ_CLOCK_GATE_TCU | JZ_CLOCK_GATE_DMAC | JZ_CLOCK_GATE_UART0);
-}
-
-int jz4740_clock_init(void)
-{
- uint32_t val;
-
- jz_clock_base = ioremap(CPHYSADDR(CPM_BASE), 0x100);
- if (!jz_clock_base)
- return -EBUSY;
-
- spin_lock_init(&jz_clock_lock);
-
- jz_clk_ext.rate = jz4740_clock_bdata.ext_rate;
- jz_clk_rtc.rate = jz4740_clock_bdata.rtc_rate;
-
- val = jz_clk_reg_read(JZ_REG_CLOCK_SPI);
-
- if (val & JZ_CLOCK_SPI_SRC_PLL)
- jz4740_clock_divided_clks[1].clk.parent = &jz_clk_pll_half;
-
- val = jz_clk_reg_read(JZ_REG_CLOCK_CTRL);
-
- if (val & JZ_CLOCK_CTRL_I2S_SRC_PLL)
- jz4740_clock_divided_clks[0].clk.parent = &jz_clk_pll_half;
-
- if (val & JZ_CLOCK_CTRL_UDC_SRC_PLL)
- jz4740_clock_simple_clks[0].parent = &jz_clk_pll_half;
-
- jz4740_clock_debugfs_init();
-
- clk_register_clks();
-
- return 0;
-}
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/clock.h b/target/linux/xburst/files-2.6.32/arch/mips/jz4740/clock.h
deleted file mode 100644
index 9c91f0d94..000000000
--- a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/clock.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
- * JZ4740 SoC clock support
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-
-#ifndef __JZ4740_CLOCK_H__
-#define __JZ4740_CLOCK_H__
-
-struct jz4740_clock_board_data {
- unsigned long ext_rate;
- unsigned long rtc_rate;
-};
-
-extern struct jz4740_clock_board_data jz4740_clock_bdata;
-
-int jz4740_clock_init(void);
-void jz4740_clock_suspend(void);
-void jz4740_clock_resume(void);
-
-struct clk;
-
-struct clk_ops {
- unsigned long (*get_rate)(struct clk* clk);
- unsigned long (*round_rate)(struct clk *clk, unsigned long rate);
- int (*set_rate)(struct clk* clk, unsigned long rate);
- int (*enable)(struct clk* clk);
- int (*disable)(struct clk* clk);
- int (*is_enabled)(struct clk* clk);
-
- int (*set_parent)(struct clk* clk, struct clk *parent);
-
-};
-
-struct clk {
- const char *name;
- struct clk* parent;
-
- uint32_t gate_bit;
-
- const struct clk_ops *ops;
-
- struct list_head list;
-
-#ifdef CONFIG_DEBUG_FS
- struct dentry *debugfs_entry;
- struct dentry *debugfs_parent_entry;
-#endif
-
-};
-
-#define JZ4740_CLK_NOT_GATED ((uint32_t)-1)
-
-int clk_is_enabled(struct clk *clk);
-
-#ifdef CONFIG_DEBUG_FS
-void jz4740_clock_debugfs_init(void);
-void jz4740_clock_debugfs_add_clk(struct clk *clk);
-void jz4740_clock_debugfs_update_parent(struct clk *clk);
-#else
-static inline void jz4740_clock_debugfs_init(void) {};
-static inline void jz4740_clock_debugfs_add_clk(struct clk *clk) {};
-static inline void jz4740_clock_debugfs_update_parent(struct clk *clk) {};
-#endif
-
-#endif
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/dma.c b/target/linux/xburst/files-2.6.32/arch/mips/jz4740/dma.c
deleted file mode 100644
index 43086dd34..000000000
--- a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/dma.c
+++ /dev/null
@@ -1,339 +0,0 @@
-/*
- * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
- * JZ4740 SoC DMA support
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/spinlock.h>
-#include <linux/interrupt.h>
-
-#include <linux/dma-mapping.h>
-#include <asm/mach-jz4740/dma.h>
-#include <asm/mach-jz4740/regs.h>
-
-#define JZ_REG_DMA_SRC_ADDR(x) (0x00 + (x) * 0x20)
-#define JZ_REG_DMA_DST_ADDR(x) (0x04 + (x) * 0x20)
-#define JZ_REG_DMA_TRANSFER_COUNT(x) (0x08 + (x) * 0x20)
-#define JZ_REG_DMA_REQ_TYPE(x) (0x0C + (x) * 0x20)
-#define JZ_REG_DMA_STATUS_CTRL(x) (0x10 + (x) * 0x20)
-#define JZ_REG_DMA_CMD(x) (0x14 + (x) * 0x20)
-#define JZ_REG_DMA_DESC_ADDR(x) (0x18 + (x) * 0x20)
-
-#define JZ_REG_DMA_CTRL 0x300
-#define JZ_REG_DMA_IRQ 0x304
-#define JZ_REG_DMA_DOORBELL 0x308
-#define JZ_REG_DMA_DOORBELL_SET 0x30C
-
-#define JZ_DMA_STATUS_CTRL_NO_DESC BIT(31)
-#define JZ_DMA_STATUS_CTRL_DESC_INV BIT(6)
-#define JZ_DMA_STATUS_CTRL_ADDR_ERR BIT(4)
-#define JZ_DMA_STATUS_CTRL_TRANSFER_DONE BIT(3)
-#define JZ_DMA_STATUS_CTRL_HALT BIT(2)
-#define JZ_DMA_STATUS_CTRL_COUNT_TERMINATE BIT(1)
-#define JZ_DMA_STATUS_CTRL_ENABLE BIT(0)
-
-#define JZ_DMA_CMD_SRC_INC BIT(23)
-#define JZ_DMA_CMD_DST_INC BIT(22)
-#define JZ_DMA_CMD_RDIL_MASK (0xf << 16)
-#define JZ_DMA_CMD_SRC_WIDTH_MASK (0x3 << 14)
-#define JZ_DMA_CMD_DST_WIDTH_MASK (0x3 << 12)
-#define JZ_DMA_CMD_INTERVAL_LENGTH_MASK (0x7 << 8)
-#define JZ_DMA_CMD_BLOCK_MODE BIT(7)
-#define JZ_DMA_CMD_DESC_VALID BIT(4)
-#define JZ_DMA_CMD_DESC_VALID_MODE BIT(3)
-#define JZ_DMA_CMD_VALID_IRQ_ENABLE BIT(2)
-#define JZ_DMA_CMD_TRANSFER_IRQ_ENABLE BIT(1)
-#define JZ_DMA_CMD_LINK_ENABLE BIT(0)
-
-#define JZ_DMA_CMD_FLAGS_OFFSET 22
-#define JZ_DMA_CMD_RDIL_OFFSET 16
-#define JZ_DMA_CMD_SRC_WIDTH_OFFSET 14
-#define JZ_DMA_CMD_DST_WIDTH_OFFSET 12
-#define JZ_DMA_CMD_TRANSFER_SIZE_OFFSET 8
-#define JZ_DMA_CMD_MODE_OFFSET 7
-
-#define JZ_DMA_CTRL_PRIORITY_MASK (0x3 << 8)
-#define JZ_DMA_CTRL_HALT BIT(3)
-#define JZ_DMA_CTRL_ADDRESS_ERROR BIT(2)
-#define JZ_DMA_CTRL_ENABLE BIT(0)
-
-
-static void __iomem *jz4740_dma_base;
-static spinlock_t jz4740_dma_lock;
-
-static inline uint32_t jz4740_dma_read(size_t reg)
-{
- return readl(jz4740_dma_base + reg);
-}
-
-static inline void jz4740_dma_write(size_t reg, uint32_t val)
-{
- writel(val, jz4740_dma_base + reg);
-}
-
-static inline void jz4740_dma_write_mask(size_t reg, uint32_t val, uint32_t mask)
-{
- uint32_t val2;
- val2 = jz4740_dma_read(reg);
- val2 &= ~mask;
- val2 |= val;
- jz4740_dma_write(reg, val2);
-}
-
-struct jz4740_dma_chan {
- unsigned int id;
- void *dev;
- const char *name;
-
- enum jz4740_dma_flags flags;
- uint32_t transfer_shift;
-
- jz4740_dma_complete_callback_t complete_cb;
-
- unsigned used:1;
-};
-
-#define JZ4740_DMA_CHANNEL(_id) { .id = _id }
-
-struct jz4740_dma_chan jz4740_dma_channels[] = {
- JZ4740_DMA_CHANNEL(0),
- JZ4740_DMA_CHANNEL(1),
- JZ4740_DMA_CHANNEL(2),
- JZ4740_DMA_CHANNEL(3),
- JZ4740_DMA_CHANNEL(4),
- JZ4740_DMA_CHANNEL(5),
-};
-
-struct jz4740_dma_chan* jz4740_dma_request(void *dev, const char *name)
-{
- unsigned int i;
- struct jz4740_dma_chan *dma = NULL;
-
- spin_lock(&jz4740_dma_lock);
-
- for (i = 0; i < ARRAY_SIZE(jz4740_dma_channels); ++i) {
- if (!jz4740_dma_channels[i].used) {
- dma = &jz4740_dma_channels[i];
- dma->used = 1;
- break;
- }
- }
-
- spin_unlock(&jz4740_dma_lock);
-
- if (!dma)
- return NULL;
-
- dma->dev = dev;
- dma->name = name;
-
- return dma;
-}
-EXPORT_SYMBOL_GPL(jz4740_dma_request);
-
-void jz4740_dma_configure(struct jz4740_dma_chan *dma,
- const struct jz4740_dma_config *config)
-{
- uint32_t cmd;
- uint32_t ctrl;
-
- switch(config->transfer_size) {
- case JZ4740_DMA_TRANSFER_SIZE_2BYTE:
- dma->transfer_shift = 1;
- break;
- case JZ4740_DMA_TRANSFER_SIZE_4BYTE:
- dma->transfer_shift = 2;
- break;
- case JZ4740_DMA_TRANSFER_SIZE_16BYTE:
- dma->transfer_shift = 4;
- break;
- case JZ4740_DMA_TRANSFER_SIZE_32BYTE:
- dma->transfer_shift = 5;
- break;
- default:
- dma->transfer_shift = 0;
- break;
- }
-
- cmd = config->flags << JZ_DMA_CMD_FLAGS_OFFSET;
- cmd |= config->src_width << JZ_DMA_CMD_SRC_WIDTH_OFFSET;
- cmd |= config->dst_width << JZ_DMA_CMD_DST_WIDTH_OFFSET;
- cmd |= config->transfer_size << JZ_DMA_CMD_TRANSFER_SIZE_OFFSET;
- cmd |= config->mode << JZ_DMA_CMD_MODE_OFFSET;
- cmd |= JZ_DMA_CMD_TRANSFER_IRQ_ENABLE;
-
- ctrl = JZ_DMA_STATUS_CTRL_NO_DESC;
- ctrl |= JZ_DMA_STATUS_CTRL_HALT;
-
- jz4740_dma_write(JZ_REG_DMA_CMD(dma->id), cmd);
- jz4740_dma_write(JZ_REG_DMA_STATUS_CTRL(dma->id), ctrl);
- jz4740_dma_write(JZ_REG_DMA_REQ_TYPE(dma->id), config->request_type);
-}
-EXPORT_SYMBOL_GPL(jz4740_dma_configure);
-
-void jz4740_dma_set_src_addr(struct jz4740_dma_chan *dma, dma_addr_t src)
-{
- jz4740_dma_write(JZ_REG_DMA_SRC_ADDR(dma->id), src);
-}
-EXPORT_SYMBOL_GPL(jz4740_dma_set_src_addr);
-
-void jz4740_dma_set_dst_addr(struct jz4740_dma_chan *dma, dma_addr_t dst)
-{
- jz4740_dma_write(JZ_REG_DMA_DST_ADDR(dma->id), dst);
-}
-EXPORT_SYMBOL_GPL(jz4740_dma_set_dst_addr);
-
-void jz4740_dma_set_transfer_count(struct jz4740_dma_chan *dma, uint32_t count)
-{
- count >>= dma->transfer_shift;
- jz4740_dma_write(JZ_REG_DMA_TRANSFER_COUNT(dma->id), count);
-}
-EXPORT_SYMBOL_GPL(jz4740_dma_set_transfer_count);
-
-void jz4740_dma_set_complete_cb(struct jz4740_dma_chan *dma,
- jz4740_dma_complete_callback_t cb)
-{
- dma->complete_cb = cb;
-}
-EXPORT_SYMBOL_GPL(jz4740_dma_set_complete_cb);
-
-void jz4740_dma_free(struct jz4740_dma_chan *dma)
-{
- dma->dev = NULL;
- dma->complete_cb = NULL;
- dma->used = 0;
-}
-EXPORT_SYMBOL_GPL(jz4740_dma_free);
-
-void jz4740_dma_enable(struct jz4740_dma_chan *dma)
-{
- jz4740_dma_write_mask(JZ_REG_DMA_STATUS_CTRL(dma->id),
- JZ_DMA_STATUS_CTRL_ENABLE,
- JZ_DMA_STATUS_CTRL_ENABLE | JZ_DMA_STATUS_CTRL_HALT);
-
- jz4740_dma_write_mask(JZ_REG_DMA_CTRL,
- JZ_DMA_CTRL_ENABLE,
- JZ_DMA_CTRL_ENABLE | JZ_DMA_CTRL_HALT);
-}
-EXPORT_SYMBOL_GPL(jz4740_dma_enable);
-
-void jz4740_dma_disable(struct jz4740_dma_chan *dma)
-{
- jz4740_dma_write_mask(JZ_REG_DMA_STATUS_CTRL(dma->id), 0,
- JZ_DMA_STATUS_CTRL_ENABLE);
-}
-EXPORT_SYMBOL_GPL(jz4740_dma_disable);
-
-uint32_t jz4740_dma_get_residue(const struct jz4740_dma_chan *dma)
-{
- uint32_t residue;
- residue = jz4740_dma_read(JZ_REG_DMA_TRANSFER_COUNT(dma->id));
- return residue << dma->transfer_shift;
-}
-EXPORT_SYMBOL_GPL(jz4740_dma_get_residue);
-
-static void jz4740_dma_chan_irq(struct jz4740_dma_chan *dma)
-{
- uint32_t status;
-
- status = jz4740_dma_read(JZ_REG_DMA_STATUS_CTRL(dma->id));
-
- jz4740_dma_write_mask(JZ_REG_DMA_STATUS_CTRL(dma->id), 0,
- JZ_DMA_STATUS_CTRL_ENABLE | JZ_DMA_STATUS_CTRL_TRANSFER_DONE);
-
- if (dma->complete_cb)
- dma->complete_cb(dma, 0, dma->dev);
-}
-
-static irqreturn_t jz4740_dma_irq(int irq, void *dev_id)
-{
- uint32_t irq_status;
- unsigned int i;
-
- irq_status = readl(jz4740_dma_base + JZ_REG_DMA_IRQ);
-
- for (i = 0; i < 6; ++i) {
- if (irq_status & (1 << i))
- jz4740_dma_chan_irq(&jz4740_dma_channels[i]);
- }
-
- return IRQ_HANDLED;
-}
-
-#if 0
-static struct jz4740_dma_config dma_test_config = {
- .src_width = JZ4740_DMA_WIDTH_32BIT,
- .dst_width = JZ4740_DMA_WIDTH_32BIT,
- .transfer_size = JZ4740_DMA_TRANSFER_SIZE_4BYTE,
- .request_type = JZ4740_DMA_TYPE_AUTO_REQUEST,
- .flags = JZ4740_DMA_SRC_AUTOINC | JZ4740_DMA_DST_AUTOINC,
- .mode = JZ4740_DMA_MODE_BLOCK,
-};
-
-static void jz4740_dma_test(void)
-{
- uint32_t *buf1, *buf2;
- dma_addr_t addr1, addr2;
- struct jz4740_dma_chan *dma = jz4740_dma_request(NULL, "dma test");
- int i;
-
- printk("STARTING DMA TEST\n");
-
- buf1 = dma_alloc_coherent(NULL,
- 0x1000,
- &addr1, GFP_KERNEL);
- buf2 = dma_alloc_coherent(NULL,
- 0x1000,
- &addr2, GFP_KERNEL);
-
- for (i = 0; i < 0x400; ++i)
- buf1[i] = i;
-
-
- jz4740_dma_configure(dma, &dma_test_config);
- jz4740_dma_set_src_addr(dma, addr1);
- jz4740_dma_set_dst_addr(dma, addr2);
- jz4740_dma_set_transfer_count(dma, 0x1000);
-
- jz4740_dma_enable(dma);
- mdelay(2000);
-
- for (i = 0; i < 0x400; ++i) {
- if (buf2[i] != i)
- printk("OH MY GOD: %x %x\n", i, buf2[i]);
- }
-
- printk("DMA TEST DONE\n");
-}
-#endif
-
-static int jz4740_dma_init(void)
-{
- unsigned int ret;
-
- jz4740_dma_base = ioremap(CPHYSADDR(DMAC_BASE), 0x400);
-
- if (!jz4740_dma_base)
- return -EBUSY;
-
- spin_lock_init(&jz4740_dma_lock);
-
- ret = request_irq(JZ_IRQ_DMAC, jz4740_dma_irq, 0, "DMA", NULL);
-
- if (ret)
- printk("JZ4740 DMA: Failed to request irq: %d\n", ret);
-
- return ret;
-}
-arch_initcall(jz4740_dma_init);
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/gpio.c b/target/linux/xburst/files-2.6.32/arch/mips/jz4740/gpio.c
deleted file mode 100644
index 8a99f4d37..000000000
--- a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/gpio.c
+++ /dev/null
@@ -1,540 +0,0 @@
-/*
- * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
- * JZ4740 platform GPIO support
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/init.h>
-
-#include <linux/spinlock.h>
-#include <linux/sysdev.h>
-#include <linux/io.h>
-#include <linux/gpio.h>
-#include <linux/delay.h>
-#include <linux/interrupt.h>
-#include <linux/bitops.h>
-
-#include <linux/debugfs.h>
-#include <linux/seq_file.h>
-
-#define JZ_GPIO_BASE_A (32*0)
-#define JZ_GPIO_BASE_B (32*1)
-#define JZ_GPIO_BASE_C (32*2)
-#define JZ_GPIO_BASE_D (32*3)
-
-#define JZ_GPIO_NUM_A 32
-#define JZ_GPIO_NUM_B 32
-#define JZ_GPIO_NUM_C 31
-#define JZ_GPIO_NUM_D 32
-
-#define JZ_IRQ_GPIO_BASE_A (JZ_IRQ_GPIO(0) + JZ_GPIO_BASE_A)
-#define JZ_IRQ_GPIO_BASE_B (JZ_IRQ_GPIO(0) + JZ_GPIO_BASE_B)
-#define JZ_IRQ_GPIO_BASE_C (JZ_IRQ_GPIO(0) + JZ_GPIO_BASE_C)
-#define JZ_IRQ_GPIO_BASE_D (JZ_IRQ_GPIO(0) + JZ_GPIO_BASE_D)
-
-#define JZ_IRQ_GPIO_A(num) (JZ_IRQ_GPIO_BASE_A + num)
-#define JZ_IRQ_GPIO_B(num) (JZ_IRQ_GPIO_BASE_B + num)
-#define JZ_IRQ_GPIO_C(num) (JZ_IRQ_GPIO_BASE_C + num)
-#define JZ_IRQ_GPIO_D(num) (JZ_IRQ_GPIO_BASE_D + num)
-
-#define JZ_REG_GPIO_PIN 0x00
-#define JZ_REG_GPIO_DATA 0x10
-#define JZ_REG_GPIO_DATA_SET 0x14
-#define JZ_REG_GPIO_DATA_CLEAR 0x18
-#define JZ_REG_GPIO_MASK 0x20
-#define JZ_REG_GPIO_MASK_SET 0x24
-#define JZ_REG_GPIO_MASK_CLEAR 0x28
-#define JZ_REG_GPIO_PULL 0x30
-#define JZ_REG_GPIO_PULL_SET 0x34
-#define JZ_REG_GPIO_PULL_CLEAR 0x38
-#define JZ_REG_GPIO_FUNC 0x40
-#define JZ_REG_GPIO_FUNC_SET 0x44
-#define JZ_REG_GPIO_FUNC_CLEAR 0x48
-#define JZ_REG_GPIO_SELECT 0x50
-#define JZ_REG_GPIO_SELECT_SET 0x54
-#define JZ_REG_GPIO_SELECT_CLEAR 0x58
-#define JZ_REG_GPIO_DIRECTION 0x60
-#define JZ_REG_GPIO_DIRECTION_SET 0x64
-#define JZ_REG_GPIO_DIRECTION_CLEAR 0x68
-#define JZ_REG_GPIO_TRIGGER 0x70
-#define JZ_REG_GPIO_TRIGGER_SET 0x74
-#define JZ_REG_GPIO_TRIGGER_CLEAR 0x78
-#define JZ_REG_GPIO_FLAG 0x80
-#define JZ_REG_GPIO_FLAG_CLEAR 0x14
-
-#define CHIP_TO_REG(chip, reg) (jz_gpio_base + (((chip)->base) << 3) + reg)
-
-#define GPIO_TO_BIT(gpio) BIT(gpio & 0x1f)
-#define GPIO_TO_REG(gpio, reg) (jz_gpio_base + ((gpio >> 5) << 8) + reg)
-
-static void __iomem *jz_gpio_base;
-
-struct jz_gpio_chip {
- unsigned int irq;
- unsigned int irq_base;
- uint32_t wakeup;
- uint32_t suspend_mask;
- uint32_t edge_trigger_both;
- spinlock_t lock;
- struct gpio_chip gpio_chip;
- struct irq_chip irq_chip;
-};
-
-static struct jz_gpio_chip *jz_irq_to_chip(unsigned int irq)
-{
- return get_irq_chip_data(irq);
-}
-
-static inline void jz_gpio_write_bit(unsigned int gpio, unsigned int reg)
-{
- writel(GPIO_TO_BIT(gpio), GPIO_TO_REG(gpio, reg));
-}
-
-int jz_gpio_set_function(int gpio, enum jz_gpio_function function)
-{
- if (function == JZ_GPIO_FUNC_NONE) {
- jz_gpio_write_bit(gpio, JZ_REG_GPIO_FUNC_CLEAR);
- jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_CLEAR);
- jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_CLEAR);
- } else {
- jz_gpio_write_bit(gpio, JZ_REG_GPIO_FUNC_SET);
- jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_CLEAR);
- switch (function) {
- case JZ_GPIO_FUNC1:
- jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_CLEAR);
- break;
- case JZ_GPIO_FUNC3:
- jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_SET);
- case JZ_GPIO_FUNC2: /* Falltrough */
- jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_SET);
- break;
- default:
- BUG();
- break;
- }
- }
-
- return 0;
-}
-EXPORT_SYMBOL_GPL(jz_gpio_set_function);
-
-int jz_gpio_bulk_request(const struct jz_gpio_bulk_request *request, size_t num)
-{
- size_t i;
- int ret;
-
- for (i = 0; i < num; ++i, ++request) {
- ret = gpio_request(request->gpio, request->name);
- if (ret)
- goto err;
- jz_gpio_set_function(request->gpio, request->function);
- }
-
- return 0;
-err:
- for (--request; i > 0; --i, --request)
- gpio_free(request->gpio);
-
- return ret;
-}
-EXPORT_SYMBOL_GPL(jz_gpio_bulk_request);
-
-void jz_gpio_bulk_free(const struct jz_gpio_bulk_request *request, size_t num)
-{
- size_t i;
-
- for (i = 0; i < num; ++i, ++request) {
- gpio_free(request->gpio);
- jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE);
- }
-
-}
-EXPORT_SYMBOL_GPL(jz_gpio_bulk_free);
-
-void jz_gpio_bulk_suspend(const struct jz_gpio_bulk_request *request, size_t num)
-{
- size_t i;
-
- for (i = 0; i < num; ++i, ++request) {
- jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE);
- jz_gpio_write_bit(request->gpio, JZ_REG_GPIO_DIRECTION_CLEAR);
- jz_gpio_write_bit(request->gpio, JZ_REG_GPIO_PULL_SET);
- }
-}
-EXPORT_SYMBOL_GPL(jz_gpio_bulk_suspend);
-
-void jz_gpio_bulk_resume(const struct jz_gpio_bulk_request *request, size_t num)
-{
- size_t i;
-
- for (i = 0; i < num; ++i, ++request) {
- jz_gpio_set_function(request->gpio, request->function);
- }
-}
-EXPORT_SYMBOL_GPL(jz_gpio_bulk_resume);
-
-void jz_gpio_enable_pullup(unsigned gpio)
-{
- jz_gpio_write_bit(gpio, JZ_REG_GPIO_PULL_CLEAR);
-}
-EXPORT_SYMBOL_GPL(jz_gpio_enable_pullup);
-
-void jz_gpio_disable_pullup(unsigned gpio)
-{
- jz_gpio_write_bit(gpio, JZ_REG_GPIO_PULL_SET);
-}
-EXPORT_SYMBOL_GPL(jz_gpio_disable_pullup);
-
-static int jz_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
-{
- return !!(readl(CHIP_TO_REG(chip, JZ_REG_GPIO_PIN)) & BIT(gpio));
-}
-
-static void jz_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
-{
- uint32_t __iomem *reg = CHIP_TO_REG(chip, JZ_REG_GPIO_DATA_SET);
- reg += !value;
- writel(BIT(gpio), reg);
-}
-
-static int jz_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
-{
- writel(BIT(gpio), CHIP_TO_REG(chip, JZ_REG_GPIO_DIRECTION_SET));
- jz_gpio_set_value(chip, gpio, value);
-
- return 0;
-}
-
-static int jz_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
-{
- writel(BIT(gpio), CHIP_TO_REG(chip, JZ_REG_GPIO_DIRECTION_CLEAR));
-
- return 0;
-}
-
-int jz_gpio_port_direction_input(int port, uint32_t mask)
-{
- writel(mask, GPIO_TO_REG(port, JZ_REG_GPIO_DIRECTION_CLEAR));
-
- return 0;
-}
-EXPORT_SYMBOL(jz_gpio_port_direction_input);
-
-int jz_gpio_port_direction_output(int port, uint32_t mask)
-{
- writel(mask, GPIO_TO_REG(port, JZ_REG_GPIO_DIRECTION_SET));
-
- return 0;
-}
-EXPORT_SYMBOL(jz_gpio_port_direction_output);
-
-void jz_gpio_port_set_value(int port, uint32_t value, uint32_t mask)
-{
- writel((~value) & mask, GPIO_TO_REG(port, JZ_REG_GPIO_DATA_CLEAR));
- writel(value & mask, GPIO_TO_REG(port, JZ_REG_GPIO_DATA_SET));
-}
-EXPORT_SYMBOL(jz_gpio_port_set_value);
-
-uint32_t jz_gpio_port_get_value(int port, uint32_t mask)
-{
- uint32_t value = readl(GPIO_TO_REG(port, JZ_REG_GPIO_PIN));
-
- return value & mask;
-}
-EXPORT_SYMBOL(jz_gpio_port_get_value);
-
-
-#define IRQ_TO_GPIO(irq) (irq - JZ_IRQ_GPIO(0))
-#define IRQ_TO_BIT(irq) BIT(IRQ_TO_GPIO(irq) & 0x1f)
-
-#define IRQ_TO_REG(irq, reg) GPIO_TO_REG(IRQ_TO_GPIO(irq), reg)
-
-static void jz_gpio_irq_demux_handler(unsigned int irq, struct irq_desc *desc)
-{
- uint32_t flag;
- unsigned int gpio_irq;
- unsigned int gpio_bank;
- struct jz_gpio_chip *chip = get_irq_desc_data(desc);
-
- gpio_bank = JZ_IRQ_GPIO0 - irq;
-
- flag = readl(jz_gpio_base + (gpio_bank << 8) + JZ_REG_GPIO_FLAG);
-
- gpio_irq = ffs(flag) - 1;
-
- if (chip->edge_trigger_both & BIT(gpio_irq)) {
- uint32_t value = readl(CHIP_TO_REG(&chip->gpio_chip, JZ_REG_GPIO_PIN));
- if (value & BIT(gpio_irq)) {
- writel(BIT(gpio_irq),
- CHIP_TO_REG(&chip->gpio_chip, JZ_REG_GPIO_DIRECTION_CLEAR));
- } else {
- writel(BIT(gpio_irq),
- CHIP_TO_REG(&chip->gpio_chip, JZ_REG_GPIO_DIRECTION_SET));
- }
- }
-
- gpio_irq += (gpio_bank << 5) + JZ_IRQ_GPIO(0);
-
- generic_handle_irq(gpio_irq);
-};
-
-static inline void jz_gpio_set_irq_bit(unsigned int irq, unsigned int reg)
-{
- writel(IRQ_TO_BIT(irq), IRQ_TO_REG(irq, reg));
-}
-
-static void jz_gpio_irq_mask(unsigned int irq)
-{
- jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_MASK_SET);
-};
-
-static void jz_gpio_irq_unmask(unsigned int irq)
-{
- jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_MASK_CLEAR);
-};
-
-
-/* TODO: Check if function is gpio */
-static unsigned int jz_gpio_irq_startup(unsigned int irq)
-{
- struct irq_desc *desc = irq_to_desc(irq);
-
- jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_SELECT_SET);
-
- desc->status &= ~IRQ_MASKED;
- jz_gpio_irq_unmask(irq);
-
- return 0;
-}
-
-static void jz_gpio_irq_shutdown(unsigned int irq)
-{
- struct irq_desc *desc = irq_to_desc(irq);
-
- jz_gpio_irq_mask(irq);
- desc->status |= IRQ_MASKED;
-
- /* Set direction to input */
- jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_CLEAR);
- jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_SELECT_CLEAR);
-}
-
-static void jz_gpio_irq_ack(unsigned int irq)
-{
- jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_FLAG_CLEAR);
-};
-
-static int jz_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
-{
- struct jz_gpio_chip *chip = jz_irq_to_chip(irq);
- struct irq_desc *desc = irq_to_desc(irq);
-
- jz_gpio_irq_mask(irq);
-
- if (flow_type == IRQ_TYPE_EDGE_BOTH) {
- uint32_t value = readl(IRQ_TO_REG(irq, JZ_REG_GPIO_PIN));
- if (value & IRQ_TO_BIT(irq))
- flow_type = IRQ_TYPE_EDGE_FALLING;
- else
- flow_type = IRQ_TYPE_EDGE_RISING;
- chip->edge_trigger_both |= IRQ_TO_BIT(irq);
- } else {
- chip->edge_trigger_both &= ~IRQ_TO_BIT(irq);
- }
-
- switch(flow_type) {
- case IRQ_TYPE_EDGE_RISING:
- jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_SET);
- jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_SET);
- break;
- case IRQ_TYPE_EDGE_FALLING:
- jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_CLEAR);
- jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_SET);
- break;
- case IRQ_TYPE_LEVEL_HIGH:
- jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_SET);
- jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_CLEAR);
- break;
- case IRQ_TYPE_LEVEL_LOW:
- jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_CLEAR);
- jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_CLEAR);
- break;
- default:
- return -EINVAL;
- }
-
- if (!(desc->status & IRQ_MASKED))
- jz_gpio_irq_unmask(irq);
-
- return 0;
-}
-
-static int jz_gpio_irq_set_wake(unsigned int irq, unsigned int on)
-{
- struct jz_gpio_chip *chip = jz_irq_to_chip(irq);
- spin_lock(&chip->lock);
- if (on)
- chip->wakeup |= IRQ_TO_BIT(irq);
- else
- chip->wakeup &= ~IRQ_TO_BIT(irq);
- spin_unlock(&chip->lock);
-
- set_irq_wake(chip->irq, !!(chip->wakeup));
- return 0;
-}
-
-int gpio_to_irq(unsigned gpio)
-{
- return JZ_IRQ_GPIO(0) + gpio;
-}
-EXPORT_SYMBOL_GPL(gpio_to_irq);
-
-int irq_to_gpio(unsigned gpio)
-{
- return IRQ_TO_GPIO(gpio);
-}
-EXPORT_SYMBOL_GPL(irq_to_gpio);
-
-#define JZ_GPIO_CHIP(_bank) { \
- .irq_base = JZ_IRQ_GPIO_BASE_ ## _bank, \
- .gpio_chip = { \
- .label = "Bank " # _bank, \
- .owner = THIS_MODULE, \
- .set = jz_gpio_set_value, \
- .get = jz_gpio_get_value, \
- .direction_output = jz_gpio_direction_output, \
- .direction_input = jz_gpio_direction_input, \
- .base = JZ_GPIO_BASE_ ## _bank, \
- .ngpio = JZ_GPIO_NUM_ ## _bank, \
- }, \
- .irq_chip = { \
- .name = "GPIO Bank " # _bank, \
- .mask = jz_gpio_irq_mask, \
- .unmask = jz_gpio_irq_unmask, \
- .ack = jz_gpio_irq_ack, \
- .startup = jz_gpio_irq_startup, \
- .shutdown = jz_gpio_irq_shutdown, \
- .set_type = jz_gpio_irq_set_type, \
- .set_wake = jz_gpio_irq_set_wake, \
- }, \
-}
-
-static struct jz_gpio_chip jz_gpio_chips[] = {
- JZ_GPIO_CHIP(A),
- JZ_GPIO_CHIP(B),
- JZ_GPIO_CHIP(C),
- JZ_GPIO_CHIP(D),
-};
-
-int jz_gpio_suspend(void)
-{
- struct jz_gpio_chip *chip = jz_gpio_chips;
- int i, gpio;
-
- for (i = 0; i < ARRAY_SIZE(jz_gpio_chips); ++i, ++chip) {
- gpio = chip->gpio_chip.base;
- chip->suspend_mask = readl(GPIO_TO_REG(gpio, JZ_REG_GPIO_MASK));
- writel(~(chip->wakeup), GPIO_TO_REG(gpio, JZ_REG_GPIO_MASK_SET));
- writel(chip->wakeup, GPIO_TO_REG(gpio, JZ_REG_GPIO_MASK_CLEAR));
- }
-
- chip = jz_gpio_chips;
-
- return 0;
-}
-
-int jz_gpio_resume(void)
-{
- struct jz_gpio_chip *chip = jz_gpio_chips;
- int i;
-
- for (i = 0; i < ARRAY_SIZE(jz_gpio_chips); ++i, ++chip) {
- writel(~(chip->suspend_mask), GPIO_TO_REG(chip->gpio_chip.base,
- JZ_REG_GPIO_MASK_CLEAR));
- writel(chip->suspend_mask, GPIO_TO_REG(chip->gpio_chip.base,
- JZ_REG_GPIO_MASK_SET));
- }
-
- return 0;
-}
-
-int __init jz_gpiolib_init(void)
-{
- struct jz_gpio_chip *chip = jz_gpio_chips;
- int i, irq;
-
- jz_gpio_base = ioremap(0x10010000, 0x400);
-
- for (i = 0; i < ARRAY_SIZE(jz_gpio_chips); ++i, ++chip) {
- gpiochip_add(&chip->gpio_chip);
- spin_lock_init(&chip->lock);
- chip->irq = JZ_IRQ_INTC_GPIO(i);
- set_irq_data(chip->irq, chip);
- set_irq_chained_handler(chip->irq, jz_gpio_irq_demux_handler);
- for (irq = chip->irq_base; irq < chip->irq_base + chip->gpio_chip.ngpio; ++irq) {
- set_irq_chip_and_handler(irq, &chip->irq_chip, handle_level_irq);
- set_irq_chip_data(irq, chip);
- }
- }
-
- printk("JZ GPIO initalized\n");
-
- return 0;
-}
-
-#ifdef CONFIG_DEBUG_FS
-
-static int gpio_regs_show(struct seq_file *s, void *unused)
-{
- struct jz_gpio_chip *chip = jz_gpio_chips;
- int i;
-
- for (i = 0; i < ARRAY_SIZE(jz_gpio_chips); ++i, ++chip) {
- seq_printf(s, "GPIO %d: \n", i);
- seq_printf(s, "\tPin: %.8x\n", readl(CHIP_TO_REG(&chip->gpio_chip, JZ_REG_GPIO_PIN)));
- seq_printf(s, "\tData: %.8x\n", readl(CHIP_TO_REG(&chip->gpio_chip, JZ_REG_GPIO_DATA)));
- seq_printf(s, "\tMask: %.8x\n", readl(CHIP_TO_REG(&chip->gpio_chip, JZ_REG_GPIO_MASK)));
- seq_printf(s, "\tData: %.8x\n", readl(CHIP_TO_REG(&chip->gpio_chip, JZ_REG_GPIO_DATA)));
- seq_printf(s, "\tPull: %.8x\n", readl(CHIP_TO_REG(&chip->gpio_chip, JZ_REG_GPIO_PULL)));
- seq_printf(s, "\tFunc: %.8x\n", readl(CHIP_TO_REG(&chip->gpio_chip, JZ_REG_GPIO_FUNC)));
- seq_printf(s, "\tSelect: %.8x\n", readl(CHIP_TO_REG(&chip->gpio_chip, JZ_REG_GPIO_SELECT)));
- seq_printf(s, "\tDirection: %.8x\n", readl(CHIP_TO_REG(&chip->gpio_chip, JZ_REG_GPIO_DIRECTION)));
- seq_printf(s, "\tTrigger: %.8x\n", readl(CHIP_TO_REG(&chip->gpio_chip, JZ_REG_GPIO_TRIGGER)));
- seq_printf(s, "\tFlag: %.8x\n", readl(CHIP_TO_REG(&chip->gpio_chip, JZ_REG_GPIO_FLAG)));
- }
-
- return 0;
-}
-
-static int gpio_regs_open(struct inode *inode, struct file *file)
-{
- return single_open(file, gpio_regs_show, NULL);
-}
-
-static const struct file_operations gpio_regs_operations = {
- .open = gpio_regs_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = single_release,
-};
-
-static int __init gpio_debugfs_init(void)
-{
- (void) debugfs_create_file("jz_regs_gpio", S_IFREG | S_IRUGO,
- NULL, NULL, &gpio_regs_operations);
- return 0;
-}
-subsys_initcall(gpio_debugfs_init);
-
-#endif
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/irq.c b/target/linux/xburst/files-2.6.32/arch/mips/jz4740/irq.c
deleted file mode 100644
index 5555026d1..000000000
--- a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/irq.c
+++ /dev/null
@@ -1,166 +0,0 @@
-/*
- * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
- * JZ4740 platform IRQ support
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-
-#include <linux/errno.h>
-#include <linux/init.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/timex.h>
-#include <linux/slab.h>
-#include <linux/delay.h>
-
-#include <linux/debugfs.h>
-#include <linux/seq_file.h>
-
-#include <asm/io.h>
-#include <asm/mipsregs.h>
-#include <asm/irq_cpu.h>
-
-static void __iomem *jz_intc_base;
-static uint32_t jz_intc_wakeup;
-static uint32_t jz_intc_saved;
-
-#define JZ_REG_BASE_INTC 0x10001000
-
-#define JZ_REG_INTC_STATUS 0x00
-#define JZ_REG_INTC_MASK 0x04
-#define JZ_REG_INTC_SET_MASK 0x08
-#define JZ_REG_INTC_CLEAR_MASK 0x0c
-#define JZ_REG_INTC_PENDING 0x10
-
-#define IRQ_BIT(x) BIT((x) - JZ_IRQ_BASE)
-
-static void intc_irq_unmask(unsigned int irq)
-{
- writel(IRQ_BIT(irq), jz_intc_base + JZ_REG_INTC_CLEAR_MASK);
-}
-
-static void intc_irq_mask(unsigned int irq)
-{
- writel(IRQ_BIT(irq), jz_intc_base + JZ_REG_INTC_SET_MASK);
-}
-
-static void intc_irq_ack(unsigned int irq)
-{
- writel(IRQ_BIT(irq), jz_intc_base + JZ_REG_INTC_PENDING);
-}
-
-static int intc_irq_set_wake(unsigned int irq, unsigned int on)
-{
- if (on)
- jz_intc_wakeup |= IRQ_BIT(irq);
- else
- jz_intc_wakeup &= ~IRQ_BIT(irq);
-
- return 0;
-}
-
-static struct irq_chip intc_irq_type = {
- .name = "INTC",
- .mask = intc_irq_mask,
- .unmask = intc_irq_unmask,
- .ack = intc_irq_ack,
- .set_wake = intc_irq_set_wake,
-};
-
-static irqreturn_t jz4740_cascade(int irq, void *data)
-{
- uint32_t irq_reg;
-
- irq_reg = readl(jz_intc_base + JZ_REG_INTC_PENDING);
- generic_handle_irq(ffs(irq_reg) - 1 + JZ_IRQ_BASE);
-
- return IRQ_HANDLED;
-}
-
-static struct irqaction jz4740_cascade_action = {
- .handler = jz4740_cascade,
- .name = "JZ4740 cascade interrupt",
- .flags = IRQF_DISABLED,
-};
-
-void __init arch_init_irq(void)
-{
- int i;
- mips_cpu_irq_init();
-
- jz_intc_base = ioremap(JZ_REG_BASE_INTC, 0x14);
-
- for (i = JZ_IRQ_BASE; i < JZ_IRQ_BASE + 32; i++) {
- intc_irq_mask(i);
- set_irq_chip_and_handler(i, &intc_irq_type, handle_level_irq);
- }
-
- setup_irq(2, &jz4740_cascade_action);
-}
-
-asmlinkage void plat_irq_dispatch(void)
-{
- unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
- if (pending & STATUSF_IP2)
- do_IRQ(2);
- else if(pending & STATUSF_IP3)
- do_IRQ(3);
- else
- spurious_interrupt();
-}
-
-/* TODO: Use sysdev */
-void jz4740_intc_suspend(void)
-{
- jz_intc_saved = readl(jz_intc_base + JZ_REG_INTC_MASK);
- writel(~jz_intc_wakeup, jz_intc_base + JZ_REG_INTC_SET_MASK);
- writel(jz_intc_wakeup, jz_intc_base + JZ_REG_INTC_CLEAR_MASK);
-}
-
-void jz4740_intc_resume(void)
-{
- writel(~jz_intc_saved, jz_intc_base + JZ_REG_INTC_CLEAR_MASK);
- writel(jz_intc_saved, jz_intc_base + JZ_REG_INTC_SET_MASK);
-}
-
-#ifdef CONFIG_DEBUG_FS
-
-static int intc_regs_show(struct seq_file *s, void *unused)
-{
- seq_printf(s, "Status:\t\t%08x\n", readl(jz_intc_base + JZ_REG_INTC_STATUS));
- seq_printf(s, "Mask\t\t%08x\n", readl(jz_intc_base + JZ_REG_INTC_MASK));
- seq_printf(s, "Pending:\t%08x\n", readl(jz_intc_base + JZ_REG_INTC_PENDING));
-
- return 0;
-}
-
-static int intc_regs_open(struct inode *inode, struct file *file)
-{
- return single_open(file, intc_regs_show, NULL);
-}
-
-static const struct file_operations intc_regs_operations = {
- .open = intc_regs_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = single_release,
-};
-
-static int __init intc_debugfs_init(void)
-{
- (void) debugfs_create_file("jz_regs_intc", S_IFREG | S_IRUGO,
- NULL, NULL, &intc_regs_operations);
- return 0;
-}
-subsys_initcall(intc_debugfs_init);
-
-#endif
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/platform.c b/target/linux/xburst/files-2.6.32/arch/mips/jz4740/platform.c
deleted file mode 100644
index ec34ea257..000000000
--- a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/platform.c
+++ /dev/null
@@ -1,246 +0,0 @@
-/*
- * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
- * JZ4740 platform devices
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/resource.h>
-
-#include <asm/mach-jz4740/platform.h>
-#include <asm/mach-jz4740/regs.h>
-#include <asm/mach-jz4740/irq.h>
-
-/* OHCI (USB full speed host controller) */
-static struct resource jz4740_usb_ohci_resources[] = {
- [0] = {
- .start = CPHYSADDR(UHC_BASE),
- .end = CPHYSADDR(UHC_BASE) + 0x10000 - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = JZ_IRQ_UHC,
- .end = JZ_IRQ_UHC,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-/* The dmamask must be set for OHCI to work */
-static u64 ohci_dmamask = ~(u32)0;
-
-struct platform_device jz4740_usb_ohci_device = {
- .name = "jz-ohci",
- .id = 0,
- .dev = {
- .dma_mask = &ohci_dmamask,
- .coherent_dma_mask = 0xffffffff,
- },
- .num_resources = ARRAY_SIZE(jz4740_usb_ohci_resources),
- .resource = jz4740_usb_ohci_resources,
-};
-
-/* UDC (USB gadget controller) */
-static struct resource jz4740_usb_gdt_resources[] = {
- [0] = {
- .start = CPHYSADDR(UDC_BASE),
- .end = CPHYSADDR(UDC_BASE) + 0x10000 - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = JZ_IRQ_UDC,
- .end = JZ_IRQ_UDC,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static u64 jz4740_udc_dmamask = ~(u32)0;
-
-struct platform_device jz4740_usb_gdt_device = {
- .name = "jz-udc",
- .id = -1,
- .dev = {
- .dma_mask = &jz4740_udc_dmamask,
- .coherent_dma_mask = 0xffffffff,
- },
- .num_resources = ARRAY_SIZE(jz4740_usb_gdt_resources),
- .resource = jz4740_usb_gdt_resources,
-};
-
-/** MMC/SD controller **/
-static struct resource jz4740_mmc_resources[] = {
- [0] = {
- .start = CPHYSADDR(MSC_BASE),
- .end = CPHYSADDR(MSC_BASE) + 0x10000 - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = JZ_IRQ_MSC,
- .end = JZ_IRQ_MSC,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-static u64 jz4740_mmc_dmamask = ~(u32)0;
-
-struct platform_device jz4740_mmc_device = {
- .name = "jz4740-mmc",
- .id = 0,
- .dev = {
- .dma_mask = &jz4740_mmc_dmamask,
- .coherent_dma_mask = 0xffffffff,
- },
- .num_resources = ARRAY_SIZE(jz4740_mmc_resources),
- .resource = jz4740_mmc_resources,
-};
-
-static struct resource jz4740_rtc_resources[] = {
- [0] = {
- .start = CPHYSADDR(RTC_BASE),
- .end = CPHYSADDR(RTC_BASE) + 0x38 - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = JZ_IRQ_RTC,
- .end = JZ_IRQ_RTC,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-struct platform_device jz4740_rtc_device = {
- .name = "jz4740-rtc",
- .id = -1,
- .num_resources = ARRAY_SIZE(jz4740_rtc_resources),
- .resource = jz4740_rtc_resources,
-};
-
-/** I2C controller **/
-static struct resource jz4740_i2c_resources[] = {
- [0] = {
- .start = CPHYSADDR(I2C_BASE),
- .end = CPHYSADDR(I2C_BASE) + 0x10000 - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = JZ_IRQ_I2C,
- .end = JZ_IRQ_I2C,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-static u64 jz4740_i2c_dmamask = ~(u32)0;
-
-struct platform_device jz4740_i2c_device = {
- .name = "jz_i2c",
- .id = 0,
- .dev = {
- .dma_mask = &jz4740_i2c_dmamask,
- .coherent_dma_mask = 0xffffffff,
- },
- .num_resources = ARRAY_SIZE(jz4740_i2c_resources),
- .resource = jz4740_i2c_resources,
-};
-
-static struct resource jz4740_nand_resources[] = {
- [0] = {
- .start = CPHYSADDR(EMC_BASE),
- .end = CPHYSADDR(EMC_BASE) + 0x10000 - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-struct platform_device jz4740_nand_device = {
- .name = "jz4740-nand",
- .num_resources = ARRAY_SIZE(jz4740_nand_resources),
- .resource = jz4740_nand_resources,
-};
-
-static struct resource jz4740_framebuffer_resources[] = {
- [0] = {
- .start = CPHYSADDR(LCD_BASE),
- .end = CPHYSADDR(LCD_BASE) + 0x10000 - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static u64 jz4740_fb_dmamask = ~(u32)0;
-
-struct platform_device jz4740_framebuffer_device = {
- .name = "jz4740-fb",
- .id = -1,
- .num_resources = ARRAY_SIZE(jz4740_framebuffer_resources),
- .resource = jz4740_framebuffer_resources,
- .dev = {
- .dma_mask = &jz4740_fb_dmamask,
- .coherent_dma_mask = 0xffffffff,
- },
-};
-
-static struct resource jz4740_i2s_resources[] = {
- [0] = {
- .start = CPHYSADDR(AIC_BASE),
- .end = CPHYSADDR(AIC_BASE) + 0x38 - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-struct platform_device jz4740_i2s_device = {
- .name = "jz4740-i2s",
- .id = -1,
- .num_resources = ARRAY_SIZE(jz4740_i2s_resources),
- .resource = jz4740_i2s_resources,
-};
-
-static struct resource jz4740_codec_resources[] = {
- [0] = {
- .start = CPHYSADDR(AIC_BASE) + 0x80,
- .end = CPHYSADDR(AIC_BASE) + 0x88 - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-struct platform_device jz4740_codec_device = {
- .name = "jz4740-codec",
- .id = -1,
- .num_resources = ARRAY_SIZE(jz4740_codec_resources),
- .resource = jz4740_codec_resources,
-};
-
-static struct resource jz4740_adc_resources[] = {
- [0] = {
- .start = CPHYSADDR(SADC_BASE),
- .end = CPHYSADDR(SADC_BASE) + 0x30,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = JZ_IRQ_SADC,
- .end = JZ_IRQ_SADC,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-struct platform_device jz4740_adc_device = {
- .name = "jz4740-adc",
- .id = -1,
- .num_resources = ARRAY_SIZE(jz4740_adc_resources),
- .resource = jz4740_adc_resources,
-};
-
-struct platform_device jz4740_battery_device = {
- .name = "jz4740-battery",
- .id = -1,
- .dev = {
- .parent = &jz4740_adc_device.dev
- },
-};
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/pm.c b/target/linux/xburst/files-2.6.32/arch/mips/jz4740/pm.c
deleted file mode 100644
index e7e463ef3..000000000
--- a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/pm.c
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
- * JZ4740 SoC power management support
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-
-#include <linux/init.h>
-#include <linux/pm.h>
-#include <linux/delay.h>
-#include <linux/suspend.h>
-#include <asm/mach-jz4740/regs.h>
-#include <asm/mach-jz4740/clock.h>
-
-#include "clock.h"
-
-extern void jz4740_intc_suspend(void);
-extern void jz4740_intc_resume(void);
-extern void jz_gpio_suspend(void);
-extern void jz_gpio_resume(void);
-
-static int jz_pm_enter(suspend_state_t state)
-{
- jz_gpio_suspend();
- jz4740_intc_suspend();
- jz4740_clock_suspend();
-
- jz4740_clock_set_wait_mode(JZ4740_WAIT_MODE_SLEEP);
-
- __asm__(".set\tmips3\n\t"
- "wait\n\t"
- ".set\tmips0");
-
- jz4740_clock_set_wait_mode(JZ4740_WAIT_MODE_IDLE);
-
- jz4740_clock_resume();
- jz4740_intc_resume();
- jz_gpio_resume();
-
- return 0;
-}
-
-static struct platform_suspend_ops jz_pm_ops = {
- .valid = suspend_valid_only_mem,
- .enter = jz_pm_enter,
-};
-
-/*
- * Initialize power interface
- */
-int __init jz_pm_init(void)
-{
- suspend_set_ops(&jz_pm_ops);
- return 0;
-
-}
-late_initcall(jz_pm_init);
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/prom.c b/target/linux/xburst/files-2.6.32/arch/mips/jz4740/prom.c
deleted file mode 100644
index e28d8154c..000000000
--- a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/prom.c
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- *
- * BRIEF MODULE DESCRIPTION
- * PROM library initialisation code, supports YAMON and U-Boot.
- *
- * Copyright 2000, 2001, 2006 MontaVista Software Inc.
- * Author: MontaVista Software, Inc.
- * ppopov@mvista.com or source@mvista.com
- *
- * This file was derived from Carsten Langgaard's
- * arch/mips/mips-boards/xx files.
- *
- * Carsten Langgaard, carstenl@mips.com
- * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/string.h>
-
-#include <asm/bootinfo.h>
-#include <asm/mach-jz4740/regs.h>
-
-/* #define DEBUG_CMDLINE */
-
-int prom_argc;
-char **prom_argv, **prom_envp;
-
-char *prom_getcmdline(void)
-{
- return &(arcs_cmdline[0]);
-}
-
-void prom_init_cmdline(void)
-{
- char *cp, *c;
- size_t i = 1;
-
- cp = &(arcs_cmdline[0]);
- while(i < prom_argc) {
- c = prom_argv[i];
- while (*c) {
- *cp++ = *c++;
- }
- *cp++ = ' ';
- i++;
- }
- if (i > 1) {
- *(cp - 1) = '\0';
- }
-
-}
-
-void __init prom_init(void)
-{
- unsigned long memsize;
-
- prom_argc = (int) fw_arg0;
- prom_argv = (char **) fw_arg1;
- prom_envp = (char **) fw_arg2;
-
- mips_machtype = MACH_INGENIC_JZ4740;
-
- prom_init_cmdline();
- memsize = 0x04000000;
- add_memory_region(0, memsize, BOOT_MEM_RAM);
-}
-
-void __init prom_free_prom_memory(void)
-{
-}
-
-/* used by early printk */
-void prom_putchar(char c)
-{
- volatile u8 *uart_lsr = (volatile u8 *)(UART0_BASE + OFF_LSR);
- volatile u8 *uart_tdr = (volatile u8 *)(UART0_BASE + OFF_TDR);
-
- /* Wait for fifo to shift out some bytes */
- while ( !((*uart_lsr & (UARTLSR_TDRQ | UARTLSR_TEMT)) == 0x60) );
-
- *uart_tdr = (u8)c;
-}
-
-const char *get_system_type(void)
-{
- return "JZ4740";
-}
-
-EXPORT_SYMBOL(prom_getcmdline);
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/reset.c b/target/linux/xburst/files-2.6.32/arch/mips/jz4740/reset.c
deleted file mode 100644
index e4fd522b8..000000000
--- a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/reset.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * linux/arch/mips/jz4740/reset.c
- *
- * JZ4740 reset routines.
- *
- * Copyright (c) 2006-2007 Ingenic Semiconductor Inc.
- * Author: <yliu@ingenic.cn>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/sched.h>
-#include <linux/mm.h>
-#include <asm/io.h>
-#include <asm/pgtable.h>
-#include <asm/processor.h>
-#include <asm/reboot.h>
-#include <asm/system.h>
-#include <asm/mach-jz4740/regs.h>
-#include <asm/mach-jz4740/timer.h>
-#include <asm/mach-jz4740/jz4740.h>
-
-#include "clock.h"
-
-void jz_restart(char *command)
-{
- printk(KERN_NOTICE "Restarting after 4 ms\n");
- REG_WDT_TCSR = WDT_TCSR_PRESCALE4 | WDT_TCSR_EXT_EN;
- REG_WDT_TCNT = 0;
- REG_WDT_TDR = jz4740_clock_bdata.ext_rate / 1000; /* reset after 4ms */
- jz4740_timer_enable_watchdog();
- REG_WDT_TCER = WDT_TCER_TCEN; /* wdt start */
- while (1);
-}
-
-void jz_halt(void)
-{
- /* Put CPU to power down mode */
- while (!(REG_RTC_RCR & RTC_RCR_WRDY));
- REG_RTC_HCR = RTC_HCR_PD;
-
- while (1)
- __asm__(".set\tmips3\n\t"
- "wait\n\t"
- ".set\tmips0");
-}
-
-void jz_power_off(void)
-{
- jz_halt();
-}
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/setup.c b/target/linux/xburst/files-2.6.32/arch/mips/jz4740/setup.c
deleted file mode 100644
index f475ff6dd..000000000
--- a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/setup.c
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- * linux/arch/mips/jz4740/common/setup.c
- *
- * JZ4740 common setup routines.
- *
- * Copyright (C) 2006 Ingenic Semiconductor Inc.
- *
- * This program is free software; you can distribute it and/or modify it
- * under the terms of the GNU General Public License (Version 2) as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- * for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- */
-#include <linux/init.h>
-#include <linux/string.h>
-#include <linux/kernel.h>
-#include <linux/io.h>
-#include <linux/ioport.h>
-#include <linux/tty.h>
-#include <linux/serial.h>
-#include <linux/serial_core.h>
-#include <linux/serial_8250.h>
-
-#include <asm/cpu.h>
-#include <asm/bootinfo.h>
-#include <asm/irq.h>
-#include <asm/mipsregs.h>
-#include <asm/reboot.h>
-#include <asm/pgtable.h>
-#include <asm/time.h>
-#include <asm/mach-jz4740/jz4740.h>
-#include <asm/mach-jz4740/regs.h>
-#include <asm/mach-jz4740/clock.h>
-#include <asm/mach-jz4740/serial.h>
-
-#include "clock.h"
-
-extern char *__init prom_getcmdline(void);
-extern void jz_restart(char *);
-extern void jz_halt(void);
-extern void jz_power_off(void);
-
-static void __init jz_serial_setup(void)
-{
-#ifdef CONFIG_SERIAL_8250
- struct uart_port s;
- REG8(UART0_FCR) |= UARTFCR_UUE; /* enable UART module */
- memset(&s, 0, sizeof(s));
- s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
- s.iotype = SERIAL_IO_MEM;
- s.regshift = 2;
- s.uartclk = jz4740_clock_bdata.ext_rate;
-
- s.line = 0;
- s.membase = (u8 *)UART0_BASE;
- s.irq = JZ_IRQ_UART0;
- if (early_serial_setup(&s) != 0) {
- printk(KERN_ERR "Serial ttyS0 setup failed!\n");
- }
-
- s.line = 1;
- s.membase = (u8 *)UART1_BASE;
- s.irq = JZ_IRQ_UART1;
- if (early_serial_setup(&s) != 0) {
- printk(KERN_ERR "Serial ttyS1 setup failed!\n");
- }
-#endif
-}
-
-void __init plat_mem_setup(void)
-{
- char *argptr;
-
- argptr = prom_getcmdline();
-
- /* IO/MEM resources. Which will be the addtion value in `inX' and
- * `outX' macros defined in asm/io.h */
- set_io_port_base(0);
- ioport_resource.start = 0x00000000;
- ioport_resource.end = 0xffffffff;
- iomem_resource.start = 0x00000000;
- iomem_resource.end = 0xffffffff;
-
- _machine_restart = jz_restart;
- _machine_halt = jz_halt;
- pm_power_off = jz_power_off;
- jz_serial_setup();
-}
-
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/time.c b/target/linux/xburst/files-2.6.32/arch/mips/jz4740/time.c
deleted file mode 100644
index 77fc2012e..000000000
--- a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/time.c
+++ /dev/null
@@ -1,256 +0,0 @@
-/*
- * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
- * JZ4740 platform timer support
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/interrupt.h>
-#include <linux/time.h>
-#include <linux/clockchips.h>
-#include <linux/clk.h>
-
-#include <asm/mach-jz4740/irq.h>
-#include <asm/mach-jz4740/jz4740.h>
-#include <asm/time.h>
-#include "clock.h"
-
-#define JZ_REG_TIMER_STOP 0x1C
-#define JZ_REG_TIMER_STOP_SET 0x2C
-#define JZ_REG_TIMER_STOP_CLEAR 0x3C
-#define JZ_REG_TIMER_ENABLE 0x10
-#define JZ_REG_TIMER_ENABLE_SET 0x14
-#define JZ_REG_TIMER_ENABLE_CLEAR 0x18
-#define JZ_REG_TIMER_FLAG 0x20
-#define JZ_REG_TIMER_FLAG_SET 0x24
-#define JZ_REG_TIMER_FLAG_CLEAR 0x28
-#define JZ_REG_TIMER_MASK 0x30
-#define JZ_REG_TIMER_MASK_SET 0x34
-#define JZ_REG_TIMER_MASK_CLEAR 0x38
-
-#define JZ_REG_TIMER_DFR(x) (((x) * 0x10) + 0x40)
-#define JZ_REG_TIMER_DHR(x) (((x) * 0x10) + 0x44)
-#define JZ_REG_TIMER_CNT(x) (((x) * 0x10) + 0x48)
-#define JZ_REG_TIMER_CTRL(x) (((x) * 0x10) + 0x4C)
-
-#define JZ_TIMER_IRQ_HALF(x) BIT((x) + 0x10)
-#define JZ_TIMER_IRQ_FULL(x) BIT(x)
-
-#define JZ_TIMER_CTRL_PWM_ACTIVE_LOW BIT(8)
-#define JZ_TIMER_CTRL_PWM_ENABLE BIT(7)
-#define JZ_TIMER_CTRL_PRESCALE_MASK 0x1c
-#define JZ_TIMER_CTRL_PRESCALE_OFFSET 0x3
-#define JZ_TIMER_CTRL_PRESCALE_1 (0 << 3)
-#define JZ_TIMER_CTRL_PRESCALE_4 (1 << 3)
-#define JZ_TIMER_CTRL_PRESCALE_16 (2 << 3)
-#define JZ_TIMER_CTRL_PRESCALE_64 (3 << 3)
-#define JZ_TIMER_CTRL_PRESCALE_256 (4 << 3)
-#define JZ_TIMER_CTRL_PRESCALE_1024 (5 << 3)
-
-#define JZ_TIMER_CTRL_SRC_EXT BIT(2)
-#define JZ_TIMER_CTRL_SRC_RTC BIT(1)
-#define JZ_TIMER_CTRL_SRC_PCLK BIT(0)
-
-static void __iomem *jz4740_timer_base;
-static uint16_t jz4740_jiffies_per_tick;
-
-void jz4740_timer_enable_watchdog(void)
-{
- writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR);
-}
-
-void jz4740_timer_disable_watchdog(void)
-{
- writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
-}
-
-static inline void jz4740_timer_set_period(unsigned int timer, uint16_t period)
-{
- writew(period, jz4740_timer_base + JZ_REG_TIMER_DFR(timer));
-}
-
-static inline void jz4740_timer_set_duty(unsigned int timer, uint16_t duty)
-{
- writew(duty, jz4740_timer_base + JZ_REG_TIMER_DHR(timer));
-}
-
-static void jz4740_init_timer(void)
-{
- uint16_t val = 0;
- val |= JZ_TIMER_CTRL_PRESCALE_16;
- val |= JZ_TIMER_CTRL_SRC_EXT;
-
- writew(val, jz4740_timer_base + JZ_REG_TIMER_CTRL(0));
- writew(0xffff, jz4740_timer_base + JZ_REG_TIMER_DFR(0));
- writew(val, jz4740_timer_base + JZ_REG_TIMER_CTRL(1));
- writew(0xffff, jz4740_timer_base + JZ_REG_TIMER_DFR(1));
-}
-
-static void jz4740_timer_enable(unsigned int timer)
-{
- writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR);
- writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_SET);
-}
-
-static void jz4740_timer_disable(unsigned int timer)
-{
- writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_CLEAR);
- writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
-}
-
-static void jz4740_timer_irq_full_enable(unsigned int timer)
-{
- writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR);
- writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_CLEAR);
-}
-
-static int jz4740_timer_irq_full_is_enabled(unsigned int timer)
-{
- return !(readl(jz4740_timer_base + JZ_REG_TIMER_MASK) &
- JZ_TIMER_IRQ_FULL(timer));
-}
-
-static void jz4740_timer_irq_full_disable(unsigned int timer)
-{
- writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_SET);
-}
-
-static void jz4740_timer_irq_half_enable(unsigned int timer)
-{
- writel(JZ_TIMER_IRQ_HALF(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR);
- writel(JZ_TIMER_IRQ_HALF(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_CLEAR);
-}
-
-static void jz4740_timer_irq_half_disable(unsigned int timer)
-{
- writel(JZ_TIMER_IRQ_HALF(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_SET);
-}
-
-static cycle_t jz4740_clocksource_read(struct clocksource *cs)
-{
- uint16_t val;
- val = readw(jz4740_timer_base + JZ_REG_TIMER_CNT(1));
- return val;
-}
-
-static struct clocksource jz4740_clocksource = {
- .name = "jz4740-timer",
- .rating = 200,
- .read = jz4740_clocksource_read,
- .mask = CLOCKSOURCE_MASK(16),
- .flags = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-
-static irqreturn_t jz4740_clockevent_irq(int irq, void *devid)
-{
- struct clock_event_device *cd = devid;
-
- writel(JZ_TIMER_IRQ_FULL(0), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR);
-
- if (cd->mode != CLOCK_EVT_MODE_PERIODIC) {
- jz4740_timer_disable(0);
- cd->event_handler(cd);
- } else {
- cd->event_handler(cd);
- }
-
- return IRQ_HANDLED;
-}
-
-static void jz4740_clockevent_set_mode(enum clock_event_mode mode,
- struct clock_event_device *cd)
-{
- switch(mode) {
- case CLOCK_EVT_MODE_PERIODIC:
- writew(0x0, jz4740_timer_base + JZ_REG_TIMER_CNT(0));
- writew(jz4740_jiffies_per_tick, jz4740_timer_base + JZ_REG_TIMER_DFR(0));
- case CLOCK_EVT_MODE_RESUME:
- jz4740_timer_irq_full_enable(0);
- jz4740_timer_enable(0);
- break;
- case CLOCK_EVT_MODE_ONESHOT:
- case CLOCK_EVT_MODE_SHUTDOWN:
- jz4740_timer_disable(0);
- break;
- default:
- break;
- }
-}
-
-static int jz4740_clockevent_set_next(unsigned long evt, struct
-clock_event_device *cd)
-{
- writew(0x0, jz4740_timer_base + JZ_REG_TIMER_CNT(0));
- writew(evt, jz4740_timer_base + JZ_REG_TIMER_DFR(0));
- jz4740_timer_enable(0);
-
- return 0;
-}
-
-static struct clock_event_device jz4740_clockevent = {
- .name = "jz4740-timer",
- .features = CLOCK_EVT_FEAT_PERIODIC,
- .set_next_event = jz4740_clockevent_set_next,
- .set_mode = jz4740_clockevent_set_mode,
- .rating = 200,
- .irq = JZ_IRQ_TCU0,
-};
-
-static struct irqaction jz_irqaction = {
- .handler = jz4740_clockevent_irq,
- .flags = IRQF_PERCPU | IRQF_TIMER | IRQF_DISABLED,
- .name = "jz4740-timerirq",
- .dev_id = &jz4740_clockevent,
-};
-
-
-void __init plat_time_init(void)
-{
- int ret;
- uint32_t clk_rate;
-
- jz4740_timer_base = ioremap(CPHYSADDR(TCU_BASE), 0x100);
-
- if (!jz4740_timer_base) {
- printk(KERN_ERR "Failed to ioremap timer registers");
- return;
- }
-
- clk_rate = jz4740_clock_bdata.ext_rate >> 4;
- jz4740_jiffies_per_tick = DIV_ROUND_CLOSEST(clk_rate, HZ);
-
- clockevent_set_clock(&jz4740_clockevent, clk_rate);
- jz4740_clockevent.min_delta_ns = clockevent_delta2ns(100, &jz4740_clockevent);
- jz4740_clockevent.max_delta_ns = clockevent_delta2ns(0xffff, &jz4740_clockevent);
- jz4740_clockevent.cpumask = cpumask_of(0);
-
- clockevents_register_device(&jz4740_clockevent);
-
- clocksource_set_clock(&jz4740_clocksource, clk_rate);
- ret = clocksource_register(&jz4740_clocksource);
-
- if (ret)
- printk(KERN_ERR "Failed to register clocksource: %d\n", ret);
-
- setup_irq(JZ_IRQ_TCU0, &jz_irqaction);
-
- jz4740_init_timer();
- writew(jz4740_jiffies_per_tick, jz4740_timer_base + JZ_REG_TIMER_DFR(0));
- jz4740_timer_irq_half_disable(0);
- jz4740_timer_irq_full_enable(0);
- jz4740_timer_enable(0);
-
- jz4740_timer_irq_half_disable(1);
- jz4740_timer_irq_full_disable(1);
-
- jz4740_timer_enable(1);
-}