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-rw-r--r--target/linux/ramips/files/arch/mips/include/asm/mach-ralink/ramips_nand_platform.h23
-rw-r--r--target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt3883.h133
-rw-r--r--target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt3883/cpu-feature-overrides.h55
-rw-r--r--target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt3883/ralink_soc.h18
-rw-r--r--target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt3883_ehci_platform.h20
-rw-r--r--target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt3883_ohci_platform.h20
-rw-r--r--target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt3883_regs.h199
-rw-r--r--target/linux/ramips/files/arch/mips/ralink/Kconfig21
-rw-r--r--target/linux/ramips/files/arch/mips/ralink/Platform7
-rw-r--r--target/linux/ramips/files/arch/mips/ralink/rt3883/Kconfig7
-rw-r--r--target/linux/ramips/files/arch/mips/ralink/rt3883/Makefile12
-rw-r--r--target/linux/ramips/files/arch/mips/ralink/rt3883/clock.c103
-rw-r--r--target/linux/ramips/files/arch/mips/ralink/rt3883/common.h16
-rw-r--r--target/linux/ramips/files/arch/mips/ralink/rt3883/devices.c385
-rw-r--r--target/linux/ramips/files/arch/mips/ralink/rt3883/devices.h29
-rw-r--r--target/linux/ramips/files/arch/mips/ralink/rt3883/early_printk.c29
-rw-r--r--target/linux/ramips/files/arch/mips/ralink/rt3883/irq.c84
-rw-r--r--target/linux/ramips/files/arch/mips/ralink/rt3883/rt3883.c211
-rw-r--r--target/linux/ramips/files/arch/mips/ralink/rt3883/setup.c89
19 files changed, 1461 insertions, 0 deletions
diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/ramips_nand_platform.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/ramips_nand_platform.h
new file mode 100644
index 000000000..54203db8e
--- /dev/null
+++ b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/ramips_nand_platform.h
@@ -0,0 +1,23 @@
+/*
+ * Platform data definition for the built-in NAND controller of the
+ * Ralink RT305X/RT3662/RT3883 SoCs
+ *
+ * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#ifndef _RAMIPS_NAND_PLATFORM_H
+#define _RAMIPS_NAND_PLATFORM_H
+
+#define RAMIPS_NAND_DRIVER_NAME "ramips-nand"
+
+struct ramips_nand_platform_data {
+ const char *name;
+ struct mtd_partition *parts;
+ int nr_parts;
+};
+
+#endif /* _RAMIPS_NAND_PLATFORM_H */
diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt3883.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt3883.h
new file mode 100644
index 000000000..004acfb73
--- /dev/null
+++ b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt3883.h
@@ -0,0 +1,133 @@
+/*
+ * Ralink RT3662/RT3883 SoC specific definitions
+ *
+ * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * Parts of this file are based on Ralink's 2.6.21 BSP
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#ifndef _RT3883_H_
+#define _RT3883_H_
+
+#include <linux/init.h>
+#include <linux/io.h>
+
+void rt3883_detect_sys_type(void);
+
+#define RT3883_MEM_SIZE_MIN (2 * 1024 * 1024)
+#define RT3883_MEM_SIZE_MAX (256 * 1024 * 1024)
+
+#define RT3883_CPU_IRQ_BASE 0
+#define RT3883_CPU_IRQ_COUNT 8
+#define RT3883_INTC_IRQ_BASE (RT3883_CPU_IRQ_BASE + RT3883_CPU_IRQ_COUNT)
+#define RT3883_INTC_IRQ_COUNT 32
+#define RT3883_GPIO_IRQ_BASE (RT3883_INTC_IRQ_BASE + RT3883_INTC_IRQ_COUNT)
+
+#define RT3883_CPU_IRQ_INTC (RT3883_CPU_IRQ_BASE + 2)
+#define RT3883_CPU_IRQ_PCI (RT3883_CPU_IRQ_BASE + 4)
+#define RT3883_CPU_IRQ_FE (RT3883_CPU_IRQ_BASE + 5)
+#define RT3883_CPU_IRQ_WLAN (RT3883_CPU_IRQ_BASE + 6)
+#define RT3883_CPU_IRQ_COUNTER (RT3883_CPU_IRQ_BASE + 7)
+
+#define RT3883_INTC_IRQ_SYSCTL (RT3883_INTC_IRQ_BASE + 0)
+#define RT3883_INTC_IRQ_TIMER0 (RT3883_INTC_IRQ_BASE + 1)
+#define RT3883_INTC_IRQ_TIMER1 (RT3883_INTC_IRQ_BASE + 2)
+#define RT3883_INTC_IRQ_IA (RT3883_INTC_IRQ_BASE + 3)
+#define RT3883_INTC_IRQ_PCM (RT3883_INTC_IRQ_BASE + 4)
+#define RT3883_INTC_IRQ_UART0 (RT3883_INTC_IRQ_BASE + 5)
+#define RT3883_INTC_IRQ_PIO (RT3883_INTC_IRQ_BASE + 6)
+#define RT3883_INTC_IRQ_DMA (RT3883_INTC_IRQ_BASE + 7)
+#define RT3883_INTC_IRQ_NAND (RT3883_INTC_IRQ_BASE + 8)
+#define RT3883_INTC_IRQ_PERFC (RT3883_INTC_IRQ_BASE + 9)
+#define RT3883_INTC_IRQ_I2S (RT3883_INTC_IRQ_BASE + 10)
+#define RT3883_INTC_IRQ_UART1 (RT3883_INTC_IRQ_BASE + 12)
+#define RT3883_INTC_IRQ_UHST (RT3883_INTC_IRQ_BASE + 18)
+#define RT3883_INTC_IRQ_UDEV (RT3883_INTC_IRQ_BASE + 19)
+
+extern void __iomem *rt3883_sysc_base;
+extern void __iomem *rt3883_memc_base;
+
+static inline void rt3883_sysc_wr(u32 val, unsigned reg)
+{
+ __raw_writel(val, rt3883_sysc_base + reg);
+}
+
+static inline u32 rt3883_sysc_rr(unsigned reg)
+{
+ return __raw_readl(rt3883_sysc_base + reg);
+}
+
+static inline void rt3883_memc_wr(u32 val, unsigned reg)
+{
+ __raw_writel(val, rt3883_memc_base + reg);
+}
+
+static inline u32 rt3883_memc_rr(unsigned reg)
+{
+ return __raw_readl(rt3883_memc_base + reg);
+}
+
+#define RT3883_GPIO_I2C_SD 1
+#define RT3883_GPIO_I2C_SCLK 2
+#define RT3883_GPIO_SPI_CS0 3
+#define RT3883_GPIO_SPI_CLK 4
+#define RT3883_GPIO_SPI_MOSI 5
+#define RT3883_GPIO_SPI_MISO 6
+/* GPIO 7-14 is shared between UART0, PCM and I2S interfaces */
+#define RT3883_GPIO_7 7
+#define RT3883_GPIO_8 8
+#define RT3883_GPIO_9 9
+#define RT3883_GPIO_10 10
+#define RT3883_GPIO_11 11
+#define RT3883_GPIO_12 12
+#define RT3883_GPIO_13 13
+#define RT3883_GPIO_14 14
+#define RT3883_GPIO_UART1_TXD 15
+#define RT3883_GPIO_UART1_RXD 16
+#define RT3883_GPIO_JTAG_TDO 17
+#define RT3883_GPIO_JTAG_TDI 18
+#define RT3883_GPIO_JTAG_TMS 19
+#define RT3883_GPIO_JTAG_TCLK 20
+#define RT3883_GPIO_JTAG_TRST_N 21
+#define RT3883_GPIO_MDIO_MDC 22
+#define RT3883_GPIO_MDIO_MDIO 23
+#define RT3883_GPIO_LNA_PE_A0 32
+#define RT3883_GPIO_LNA_PE_A1 33
+#define RT3883_GPIO_LNA_PE_A2 34
+#define RT3883_GPIO_LNA_PE_G0 35
+#define RT3883_GPIO_LNA_PE_G1 36
+#define RT3883_GPIO_LNA_PE_G2 37
+#define RT3883_GPIO_PCI_AD0 40
+#define RT3883_GPIO_PCI_AD31 71
+#define RT3883_GPIO_GE2_TXD0 72
+#define RT3883_GPIO_GE2_TXD1 73
+#define RT3883_GPIO_GE2_TXD2 74
+#define RT3883_GPIO_GE2_TXD3 75
+#define RT3883_GPIO_GE2_TXEN 76
+#define RT3883_GPIO_GE2_TXCLK 77
+#define RT3883_GPIO_GE2_RXD0 78
+#define RT3883_GPIO_GE2_RXD1 79
+#define RT3883_GPIO_GE2_RXD2 80
+#define RT3883_GPIO_GE2_RXD3 81
+#define RT3883_GPIO_GE2_RXDV 82
+#define RT3883_GPIO_GE2_RXCLK 83
+#define RT3883_GPIO_GE1_TXD0 84
+#define RT3883_GPIO_GE1_TXD1 85
+#define RT3883_GPIO_GE1_TXD2 86
+#define RT3883_GPIO_GE1_TXD3 87
+#define RT3883_GPIO_GE1_TXEN 88
+#define RT3883_GPIO_GE1_TXCLK 89
+#define RT3883_GPIO_GE1_RXD0 90
+#define RT3883_GPIO_GE1_RXD1 91
+#define RT3883_GPIO_GE1_RXD2 92
+#define RT3883_GPIO_GE1_RXD3 93
+#define RT3883_GPIO_GE1_RXDV 94
+#define RT3883_GPIO_GE1_RXCLK 95
+
+void rt3883_gpio_init(u32 mode);
+
+#endif /* _RT3883_H_ */
diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt3883/cpu-feature-overrides.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt3883/cpu-feature-overrides.h
new file mode 100644
index 000000000..7ff0b358e
--- /dev/null
+++ b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt3883/cpu-feature-overrides.h
@@ -0,0 +1,55 @@
+/*
+ * Ralink RT3662/RT3883 specific CPU feature overrides
+ *
+ * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This file was derived from: include/asm-mips/cpu-features.h
+ * Copyright (C) 2003, 2004 Ralf Baechle
+ * Copyright (C) 2004 Maciej W. Rozycki
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+#ifndef __ASM_MACH_RALINK_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_RALINK_CPU_FEATURE_OVERRIDES_H
+
+#define cpu_has_tlb 1
+#define cpu_has_4kex 1
+#define cpu_has_3k_cache 0
+#define cpu_has_4k_cache 1
+#define cpu_has_tx39_cache 0
+#define cpu_has_sb1_cache 0
+#define cpu_has_fpu 0
+#define cpu_has_32fpr 0
+#define cpu_has_counter 1
+#define cpu_has_watch 1
+#define cpu_has_divec 1
+
+#define cpu_has_prefetch 1
+#define cpu_has_ejtag 1
+#define cpu_has_llsc 1
+
+#define cpu_has_mips16 1
+#define cpu_has_mdmx 0
+#define cpu_has_mips3d 0
+#define cpu_has_smartmips 0
+
+#define cpu_has_mips32r1 1
+#define cpu_has_mips32r2 1
+#define cpu_has_mips64r1 0
+#define cpu_has_mips64r2 0
+
+#define cpu_has_dsp 0
+#define cpu_has_mipsmt 0
+
+#define cpu_has_64bits 0
+#define cpu_has_64bit_zero_reg 0
+#define cpu_has_64bit_gp_regs 0
+#define cpu_has_64bit_addresses 0
+
+#define cpu_dcache_line_size() 32
+#define cpu_icache_line_size() 32
+
+#endif /* __ASM_MACH_RALINK_CPU_FEATURE_OVERRIDES_H */
diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt3883/ralink_soc.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt3883/ralink_soc.h
new file mode 100644
index 000000000..8a080b7d2
--- /dev/null
+++ b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt3883/ralink_soc.h
@@ -0,0 +1,18 @@
+/*
+ * Ralink RT3662/RT3883 specific SOC defines
+ *
+ * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#ifndef _RT3883_RALINK_SOC_H
+#define _RT3883_RALINK_SOC_H
+
+#define RALINK_SOC_SDRAM_BASE 0
+#define RALINK_SOC_MEM_SIZE_MIN (2 * 1024 * 1024)
+#define RALINK_SOC_MEM_SIZE_MAX (256 * 1024 * 1024)
+
+#endif /* _RT3883_RALINK_SOC_H */
diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt3883_ehci_platform.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt3883_ehci_platform.h
new file mode 100644
index 000000000..a83c45850
--- /dev/null
+++ b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt3883_ehci_platform.h
@@ -0,0 +1,20 @@
+/*
+ * Platform data definition for built-in EHCI controller of the
+ * Ralink RT3662/RT3883 SoCs
+ *
+ * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#ifndef _RT3883_EHCI_PLATFORM_H
+#define _RT3883_EHCI_PLATFORM_H
+
+struct rt3883_ehci_platform_data {
+ void (*start_hw)(void);
+ void (*stop_hw)(void);
+};
+
+#endif /* _RT3883_EHCI_PLATFORM_H */
diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt3883_ohci_platform.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt3883_ohci_platform.h
new file mode 100644
index 000000000..cc8383bf3
--- /dev/null
+++ b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt3883_ohci_platform.h
@@ -0,0 +1,20 @@
+/*
+ * Platform data definition for built-in OHCI controller of the
+ * Ralink RT3662/RT3883 SoCs
+ *
+ * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#ifndef _RT3883_OHCI_PLATFORM_H
+#define _RT3883_OHCI_PLATFORM_H
+
+struct rt3883_ohci_platform_data {
+ void (*start_hw)(void);
+ void (*stop_hw)(void);
+};
+
+#endif /* _RT3883_OHCI_PLATFORM_H */
diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt3883_regs.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt3883_regs.h
new file mode 100644
index 000000000..7149e6faf
--- /dev/null
+++ b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt3883_regs.h
@@ -0,0 +1,199 @@
+/*
+ * Ralink RT3662/RT3883 SoC register definitions
+ *
+ * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#ifndef _RT3883_REGS_H_
+#define _RT3883_REGS_H_
+
+#include <linux/bitops.h>
+
+#define RT3883_SDRAM_BASE 0x00000000
+#define RT3883_SYSC_BASE 0x10000000
+#define RT3883_TIMER_BASE 0x10000100
+#define RT3883_INTC_BASE 0x10000200
+#define RT3883_MEMC_BASE 0x10000300
+#define RT3883_UART0_BASE 0x10000500
+#define RT3883_PIO_BASE 0x10000600
+#define RT3883_FSCC_BASE 0x10000700
+#define RT3883_NANDC_BASE 0x10000810
+#define RT3883_I2C_BASE 0x10000900
+#define RT3883_I2S_BASE 0x10000a00
+#define RT3883_SPI_BASE 0x10000b00
+#define RT3883_UART1_BASE 0x10000c00
+#define RT3883_PCM_BASE 0x10002000
+#define RT3883_GDMA_BASE 0x10002800
+#define RT3883_CODEC1_BASE 0x10003000
+#define RT3883_CODEC2_BASE 0x10003800
+#define RT3883_FE_BASE 0x10100000
+#define RT3883_ROM_BASE 0x10118000
+#define RT3883_USBDEV_BASE 0x10112000
+#define RT3883_PCI_BASE 0x10140000
+#define RT3883_WLAN_BASE 0x10180000
+#define RT3883_USBHOST_BASE 0x101c0000
+#define RT3883_BOOT_BASE 0x1c000000
+#define RT3883_SRAM_BASE 0x1e000000
+#define RT3883_PCIMEM_BASE 0x20000000
+
+#define RT3883_EHCI_BASE (RT3883_USBHOST_BASE)
+#define RT3883_OHCI_BASE (RT3883_USBHOST_BASE + 0x1000)
+
+#define RT3883_SYSC_SIZE 0x100
+#define RT3883_TIMER_SIZE 0x100
+#define RT3883_INTC_SIZE 0x100
+#define RT3883_MEMC_SIZE 0x100
+#define RT3883_UART0_SIZE 0x100
+#define RT3883_UART1_SIZE 0x100
+#define RT3883_PIO_SIZE 0x100
+#define RT3883_FSCC_SIZE 0x100
+#define RT3883_NANDC_SIZE 0x0f0
+#define RT3883_I2C_SIZE 0x100
+#define RT3883_I2S_SIZE 0x100
+#define RT3883_SPI_SIZE 0x100
+#define RT3883_PCM_SIZE 0x800
+#define RT3883_GDMA_SIZE 0x800
+#define RT3883_CODEC1_SIZE 0x800
+#define RT3883_CODEC2_SIZE 0x800
+#define RT3883_FE_SIZE 0x10000
+#define RT3883_ROM_SIZE 0x4000
+#define RT3883_USBDEV_SIZE 0x4000
+#define RT3883_PCI_SIZE 0x40000
+#define RT3883_WLAN_SIZE 0x40000
+#define RT3883_USBHOST_SIZE 0x40000
+#define RT3883_BOOT_SIZE (32 * 1024 * 1024)
+#define RT3883_SRAM_SIZE (32 * 1024 * 1024)
+
+/* SYSC registers */
+#define RT3883_SYSC_REG_CHIPID0_3 0x00 /* Chip ID 0 */
+#define RT3883_SYSC_REG_CHIPID4_7 0x04 /* Chip ID 1 */
+#define RT3883_SYSC_REG_REVID 0x0c /* Chip Revision Identification */
+#define RT3883_SYSC_REG_SYSCFG0 0x10 /* System Configuration 0 */
+#define RT3883_SYSC_REG_SYSCFG1 0x14 /* System Configuration 1 */
+#define RT3883_SYSC_REG_CLKCFG0 0x2c /* Clock Configuration 0 */
+#define RT3883_SYSC_REG_CLKCFG1 0x30 /* Clock Configuration 1 */
+#define RT3883_SYSC_REG_RSTCTRL 0x34 /* Reset Control*/
+#define RT3883_SYSC_REG_RSTSTAT 0x38 /* Reset Status*/
+#define RT3883_SYSC_REG_USB_PS 0x5c /* USB Power saving control */
+#define RT3883_SYSC_REG_GPIO_MODE 0x60 /* GPIO Purpose Select */
+#define RT3883_SYSC_REG_PMU 0x88
+#define RT3883_SYSC_REG_PMU1 0x8c
+
+#define RT3883_REVID_VER_ID_MASK 0x0f
+#define RT3883_REVID_VER_ID_SHIFT 8
+#define RT3883_REVID_ECO_ID_MASK 0x0f
+
+#define RT3883_SYSCFG0_DRAM_TYPE_DDR2 BIT(17)
+#define RT3883_SYSCFG0_CPUCLK_SHIFT 8
+#define RT3883_SYSCFG0_CPUCLK_MASK 0x3
+#define RT3883_SYSCFG0_CPUCLK_250 0x0
+#define RT3883_SYSCFG0_CPUCLK_384 0x1
+#define RT3883_SYSCFG0_CPUCLK_480 0x2
+#define RT3883_SYSCFG0_CPUCLK_500 0x3
+
+#define RT3883_SYSCFG1_USB0_HOST_MODE BIT(10)
+#define RT3883_SYSCFG1_GPIO2_AS_WDT_OUT BIT(2)
+
+#define RT3883_CLKCFG1_UPHY1_CLK_EN BIT(20)
+#define RT3883_CLKCFG1_UPHY0_CLK_EN BIT(18)
+
+#define RT3883_GPIO_MODE_I2C BIT(0)
+#define RT3883_GPIO_MODE_SPI BIT(1)
+#define RT3883_GPIO_MODE_UART0_SHIFT 2
+#define RT3883_GPIO_MODE_UART0_MASK 0x7
+#define RT3883_GPIO_MODE_UART0(x) ((x) << RT3883_GPIO_MODE_UART0_SHIFT)
+#define RT3883_GPIO_MODE_UARTF 0x0
+#define RT3883_GPIO_MODE_PCM_UARTF 0x1
+#define RT3883_GPIO_MODE_PCM_I2S 0x2
+#define RT3883_GPIO_MODE_I2S_UARTF 0x3
+#define RT3883_GPIO_MODE_PCM_GPIO 0x4
+#define RT3883_GPIO_MODE_GPIO_UARTF 0x5
+#define RT3883_GPIO_MODE_GPIO_I2S 0x6
+#define RT3883_GPIO_MODE_GPIO 0x7
+#define RT3883_GPIO_MODE_UART1 BIT(5)
+#define RT3883_GPIO_MODE_JTAG BIT(6)
+#define RT3883_GPIO_MODE_MDIO BIT(7)
+#define RT3883_GPIO_MODE_GE1 BIT(9)
+#define RT3883_GPIO_MODE_GE2 BIT(10)
+#define RT3883_GPIO_MODE_PCI_SHIFT 11
+#define RT3883_GPIO_MODE_PCI_MASK 0x7
+#define RT3883_GPIO_MODE_PCI(_x) ((_x) << RT3883_GPIO_MODE_PCI_SHIFT)
+#define RT3883_GPIO_MODE_PCI_DEV 0
+#define RT3883_GPIO_MODE_PCI_HOST2 1
+#define RT3883_GPIO_MODE_PCI_HOST1 2
+#define RT3883_GPIO_MODE_PCI_FNC 3
+#define RT3883_GPIO_MODE_PCI_GPIO 7
+#define RT3883_GPIO_MODE_LNA_A_SHIFT 16
+#define RT3883_GPIO_MODE_LNA_A_MASK 0x3
+#define RT3883_GPIO_MODE_LNA_A(_x) ((_x) << RT3883_GPIO_MODE_LNA_A_SHIFT)
+#define RT3883_GPIO_MODE_LNA_A_GPIO 0x3
+#define RT3883_GPIO_MODE_LNA_G_SHIFT 18
+#define RT3883_GPIO_MODE_LNA_G_MASK 0x3
+#define RT3883_GPIO_MODE_LNA_G(_x) ((_x) << RT3883_GPIO_MODE_LNA_G_SHIFT)
+#define RT3883_GPIO_MODE_LNA_G_GPIO 0x3
+
+#define RT3883_RSTCTRL_PCIE_PCI_PDM BIT(27)
+#define RT3883_RSTCTRL_FLASH BIT(26)
+#define RT3883_RSTCTRL_UDEV BIT(25)
+#define RT3883_RSTCTRL_PCI BIT(24)
+#define RT3883_RSTCTRL_PCIE BIT(23)
+#define RT3883_RSTCTRL_UHST BIT(22)
+#define RT3883_RSTCTRL_FE BIT(21)
+#define RT3883_RSTCTRL_WLAN BIT(20)
+#define RT3883_RSTCTRL_UART1 BIT(29)
+#define RT3883_RSTCTRL_SPI BIT(18)
+#define RT3883_RSTCTRL_I2S BIT(17)
+#define RT3883_RSTCTRL_I2C BIT(16)
+#define RT3883_RSTCTRL_NAND BIT(15)
+#define RT3883_RSTCTRL_DMA BIT(14)
+#define RT3883_RSTCTRL_PIO BIT(13)
+#define RT3883_RSTCTRL_UART BIT(12)
+#define RT3883_RSTCTRL_PCM BIT(11)
+#define RT3883_RSTCTRL_MC BIT(10)
+#define RT3883_RSTCTRL_INTC BIT(9)
+#define RT3883_RSTCTRL_TIMER BIT(8)
+#define RT3883_RSTCTRL_SYS BIT(0)
+
+#define RT3883_INTC_INT_SYSCTL BIT(0)
+#define RT3883_INTC_INT_TIMER0 BIT(1)
+#define RT3883_INTC_INT_TIMER1 BIT(2)
+#define RT3883_INTC_INT_IA BIT(3)
+#define RT3883_INTC_INT_PCM BIT(4)
+#define RT3883_INTC_INT_UART0 BIT(5)
+#define RT3883_INTC_INT_PIO BIT(6)
+#define RT3883_INTC_INT_DMA BIT(7)
+#define RT3883_INTC_INT_NAND BIT(8)
+#define RT3883_INTC_INT_PERFC BIT(9)
+#define RT3883_INTC_INT_I2S BIT(10)
+#define RT3883_INTC_INT_UART1 BIT(12)
+#define RT3883_INTC_INT_UHST BIT(18)
+#define RT3883_INTC_INT_UDEV BIT(19)
+
+/* FLASH/SRAM/Codec Controller registers */
+#define RT3883_FSCC_REG_FLASH_CFG0 0x00
+#define RT3883_FSCC_REG_FLASH_CFG1 0x04
+#define RT3883_FSCC_REG_CODEC_CFG0 0x40
+#define RT3883_FSCC_REG_CODEC_CFG1 0x44
+
+#define RT3883_FLASH_CFG_WIDTH_SHIFT 26
+#define RT3883_FLASH_CFG_WIDTH_MASK 0x3
+#define RT3883_FLASH_CFG_WIDTH_8BIT 0x0
+#define RT3883_FLASH_CFG_WIDTH_16BIT 0x1
+#define RT3883_FLASH_CFG_WIDTH_32BIT 0x2
+
+
+/* UART registers */
+#define RT3883_UART_REG_RX 0
+#define RT3883_UART_REG_TX 1
+#define RT3883_UART_REG_IER 2
+#define RT3883_UART_REG_IIR 3
+#define RT3883_UART_REG_FCR 4
+#define RT3883_UART_REG_LCR 5
+#define RT3883_UART_REG_MCR 6
+#define RT3883_UART_REG_LSR 7
+
+#endif /* _RT3883_REGS_H_ */
diff --git a/target/linux/ramips/files/arch/mips/ralink/Kconfig b/target/linux/ramips/files/arch/mips/ralink/Kconfig
index 1bb6bc3ba..a7e7f21f9 100644
--- a/target/linux/ramips/files/arch/mips/ralink/Kconfig
+++ b/target/linux/ramips/files/arch/mips/ralink/Kconfig
@@ -14,10 +14,15 @@ choice
bool "RT305x"
select SOC_RT305X
+ config RALINK_RT3883
+ bool "RT3883"
+ select SOC_RT3883
+
endchoice
source "arch/mips/ralink/rt288x/Kconfig"
source "arch/mips/ralink/rt305x/Kconfig"
+source "arch/mips/ralink/rt3883/Kconfig"
config SOC_RT288X
bool
@@ -49,6 +54,22 @@ config SOC_RT305X
select MIPS_MACHINE
select USB_ARCH_HAS_HCD
+config SOC_RT3883
+ bool
+ select CEVT_R4K
+ select CSRC_R4K
+ select DMA_NONCOHERENT
+ select IRQ_CPU
+ select ARCH_REQUIRE_GPIOLIB
+ select SYS_HAS_CPU_MIPS32_R1
+ select SYS_HAS_CPU_MIPS32_R2
+ select SYS_SUPPORTS_32BIT_KERNEL
+ select SYS_SUPPORTS_LITTLE_ENDIAN
+ select SYS_HAS_EARLY_PRINTK
+ select MIPS_MACHINE
+ select USB_ARCH_HAS_OHCI
+ select USB_ARCH_HAS_EHCI
+
config RALINK_DEV_GPIO_BUTTONS
def_bool n
diff --git a/target/linux/ramips/files/arch/mips/ralink/Platform b/target/linux/ramips/files/arch/mips/ralink/Platform
index 86871bda3..1b540492c 100644
--- a/target/linux/ramips/files/arch/mips/ralink/Platform
+++ b/target/linux/ramips/files/arch/mips/ralink/Platform
@@ -17,3 +17,10 @@ load-$(CONFIG_RALINK_RT288X) += 0xffffffff88000000
core-$(CONFIG_RALINK_RT305X) += arch/mips/ralink/rt305x/
cflags-$(CONFIG_RALINK_RT305X) += -I$(srctree)/arch/mips/include/asm/mach-ralink/rt305x
load-$(CONFIG_RALINK_RT305X) += 0xffffffff80000000
+
+#
+# Ralink RT3883
+#
+core-$(CONFIG_RALINK_RT3883) += arch/mips/ralink/rt3883/
+cflags-$(CONFIG_RALINK_RT3883) += -I$(srctree)/arch/mips/include/asm/mach-ralink/rt3883
+load-$(CONFIG_RALINK_RT3883) += 0xffffffff80000000
diff --git a/target/linux/ramips/files/arch/mips/ralink/rt3883/Kconfig b/target/linux/ramips/files/arch/mips/ralink/rt3883/Kconfig
new file mode 100644
index 000000000..7b4579adb
--- /dev/null
+++ b/target/linux/ramips/files/arch/mips/ralink/rt3883/Kconfig
@@ -0,0 +1,7 @@
+if RALINK_RT3883
+
+menu "Ralink RT3662/RT3883 machine selection"
+
+endmenu
+
+endif
diff --git a/target/linux/ramips/files/arch/mips/ralink/rt3883/Makefile b/target/linux/ramips/files/arch/mips/ralink/rt3883/Makefile
new file mode 100644
index 000000000..f8098592b
--- /dev/null
+++ b/target/linux/ramips/files/arch/mips/ralink/rt3883/Makefile
@@ -0,0 +1,12 @@
+#
+# Makefile for the Ralink RT3662/RT3883 SoC specific parts of the kernel
+#
+# Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License version 2 as published
+# by the Free Software Foundation.
+
+obj-y := irq.o setup.o devices.o rt3883.o clock.o
+
+obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
diff --git a/target/linux/ramips/files/arch/mips/ralink/rt3883/clock.c b/target/linux/ramips/files/arch/mips/ralink/rt3883/clock.c
new file mode 100644
index 000000000..bf70259ca
--- /dev/null
+++ b/target/linux/ramips/files/arch/mips/ralink/rt3883/clock.c
@@ -0,0 +1,103 @@
+/*
+ * Ralink RT3662/RT3883 clock API
+ *
+ * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+
+#include <asm/mach-ralink/common.h>
+#include <asm/mach-ralink/rt3883.h>
+#include <asm/mach-ralink/rt3883_regs.h>
+#include "common.h"
+
+struct clk {
+ unsigned long rate;
+};
+
+static struct clk rt3883_cpu_clk;
+static struct clk rt3883_sys_clk;
+static struct clk rt3883_wdt_clk;
+static struct clk rt3883_uart_clk;
+
+void __init rt3883_clocks_init(void)
+{
+ u32 syscfg0;
+ u32 clksel;
+ u32 ddr2;
+
+ syscfg0 = rt3883_sysc_rr(RT3883_SYSC_REG_SYSCFG0);
+ clksel = ((syscfg0 >> RT3883_SYSCFG0_CPUCLK_SHIFT) &
+ RT3883_SYSCFG0_CPUCLK_MASK);
+ ddr2 = syscfg0 & RT3883_SYSCFG0_DRAM_TYPE_DDR2;
+
+ switch (clksel) {
+ case RT3883_SYSCFG0_CPUCLK_250:
+ rt3883_cpu_clk.rate = 250000000;
+ rt3883_sys_clk.rate = (ddr2) ? 125000000 : 83000000;
+ break;
+ case RT3883_SYSCFG0_CPUCLK_384:
+ rt3883_cpu_clk.rate = 384000000;
+ rt3883_sys_clk.rate = (ddr2) ? 128000000 : 96000000;
+ break;
+ case RT3883_SYSCFG0_CPUCLK_480:
+ rt3883_cpu_clk.rate = 480000000;
+ rt3883_sys_clk.rate = (ddr2) ? 160000000 : 120000000;
+ break;
+ case RT3883_SYSCFG0_CPUCLK_500:
+ rt3883_cpu_clk.rate = 500000000;
+ rt3883_sys_clk.rate = (ddr2) ? 166000000 : 125000000;
+ break;
+ }
+
+ rt3883_wdt_clk.rate = rt3883_sys_clk.rate;
+ rt3883_uart_clk.rate = 40000000;
+}
+
+struct clk *clk_get(struct device *dev, const char *id)
+{
+ if (!strcmp(id, "sys"))
+ return &rt3883_sys_clk;
+
+ if (!strcmp(id, "cpu"))
+ return &rt3883_cpu_clk;
+
+ if (!strcmp(id, "wdt"))
+ return &rt3883_wdt_clk;
+
+ if (!strcmp(id, "uart"))
+ return &rt3883_uart_clk;
+
+ return ERR_PTR(-ENOENT);
+}
+EXPORT_SYMBOL(clk_get);
+
+int clk_enable(struct clk *clk)
+{
+ return 0;
+}
+EXPORT_SYMBOL(clk_enable);
+
+void clk_disable(struct clk *clk)
+{
+}
+EXPORT_SYMBOL(clk_disable);
+
+unsigned long clk_get_rate(struct clk *clk)
+{
+ return clk->rate;
+}
+EXPORT_SYMBOL(clk_get_rate);
+
+void clk_put(struct clk *clk)
+{
+}
+EXPORT_SYMBOL(clk_put);
diff --git a/target/linux/ramips/files/arch/mips/ralink/rt3883/common.h b/target/linux/ramips/files/arch/mips/ralink/rt3883/common.h
new file mode 100644
index 000000000..a389dccce
--- /dev/null
+++ b/target/linux/ramips/files/arch/mips/ralink/rt3883/common.h
@@ -0,0 +1,16 @@
+/*
+ * Ralink RT3662/RT3883 SoC common defines
+ *
+ * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#ifndef _RT3883_COMMON_H
+#define _RT3883_COMMON_H
+
+void rt3883_clocks_init(void);
+
+#endif /* _RT3883_COMMON_H */ \ No newline at end of file
diff --git a/target/linux/ramips/files/arch/mips/ralink/rt3883/devices.c b/target/linux/ramips/files/arch/mips/ralink/rt3883/devices.c
new file mode 100644
index 000000000..058402a5a
--- /dev/null
+++ b/target/linux/ramips/files/arch/mips/ralink/rt3883/devices.c
@@ -0,0 +1,385 @@
+/*
+ * Ralink RT3662/RT3883 SoC platform device registration
+ *
+ * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mtd/partitions.h>
+#include <linux/dma-mapping.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/rt2x00_platform.h>
+
+#include <asm/addrspace.h>
+
+#include <asm/mach-ralink/rt3883.h>
+#include <asm/mach-ralink/rt3883_regs.h>
+#include <asm/mach-ralink/rt3883_ehci_platform.h>
+#include <asm/mach-ralink/rt3883_ohci_platform.h>
+#include <asm/mach-ralink/ramips_nand_platform.h>
+#include "devices.h"
+
+#include <ramips_eth_platform.h>
+
+static struct resource rt3883_flash0_resources[] = {
+ {
+ .flags = IORESOURCE_MEM,
+ .start = RT3883_BOOT_BASE,
+ .end = RT3883_BOOT_BASE + RT3883_BOOT_SIZE - 1,
+ },
+};
+
+struct physmap_flash_data rt3883_flash0_data;
+static struct platform_device rt3883_flash0_device = {
+ .name = "physmap-flash",
+ .resource = rt3883_flash0_resources,
+ .num_resources = ARRAY_SIZE(rt3883_flash0_resources),
+ .dev = {
+ .platform_data = &rt3883_flash0_data,
+ },
+};
+
+static struct resource rt3883_flash1_resources[] = {
+ {
+ .flags = IORESOURCE_MEM,
+ .start = RT3883_SRAM_BASE,
+ .end = RT3883_SRAM_BASE + RT3883_SRAM_SIZE - 1,
+ },
+};
+
+struct physmap_flash_data rt3883_flash1_data;
+static struct platform_device rt3883_flash1_device = {
+ .name = "physmap-flash",
+ .resource = rt3883_flash1_resources,
+ .num_resources = ARRAY_SIZE(rt3883_flash1_resources),
+ .dev = {
+ .platform_data = &rt3883_flash1_data,
+ },
+};
+
+static int rt3883_flash_instance __initdata;
+void __init rt3883_register_pflash(unsigned int id)
+{
+ struct platform_device *pdev;
+ struct physmap_flash_data *pdata;
+ void __iomem *fscc_base;
+ u32 t;
+ int reg;
+
+ switch (id) {
+ case 0:
+ pdev = &rt3883_flash0_device;
+ reg = RT3883_FSCC_REG_FLASH_CFG0;
+ break;
+ case 1:
+ pdev = &rt3883_flash1_device;
+ reg = RT3883_FSCC_REG_FLASH_CFG1;
+ break;
+ default:
+ return;
+ }
+
+ pdata = pdev->dev.platform_data;
+
+ fscc_base = ioremap(RT3883_FSCC_BASE, RT3883_FSCC_SIZE);
+ if (!fscc_base)
+ panic("RT3883: ioremap failed for FSCC");
+
+ t = __raw_readl(fscc_base + reg);
+ iounmap(fscc_base);
+
+ t = (t >> RT3883_FLASH_CFG_WIDTH_SHIFT) & RT3883_FLASH_CFG_WIDTH_MASK;
+ switch (t) {
+ case RT3883_FLASH_CFG_WIDTH_8BIT:
+ pdata->width = 1;
+ break;
+ case RT3883_FLASH_CFG_WIDTH_16BIT:
+ pdata->width = 2;
+ break;
+ case RT3883_FLASH_CFG_WIDTH_32BIT:
+ if (id == 1) {
+ pdata->width = 4;
+ break;
+ }
+ /* fallthrough */
+ default:
+ pr_warn("RT3883: flash bank%d: invalid width detected\n", id);
+ return;
+ }
+
+ pdev->id = rt3883_flash_instance;
+
+ platform_device_register(pdev);
+ rt3883_flash_instance++;
+}
+
+static atomic_t rt3883_usb_use_count = ATOMIC_INIT(0);
+
+static void rt3883_usb_host_start(void)
+{
+ u32 t;
+
+ if (atomic_inc_return(&rt3883_usb_use_count) != 1)
+ return;
+
+ t = rt3883_sysc_rr(RT3883_SYSC_REG_USB_PS);
+
+#if 0
+ /* put the HOST controller into reset */
+ t = rt3883_sysc_rr(RT3883_SYSC_REG_RSTCTRL);
+ t |= RT3883_RSTCTRL_UHST;
+ rt3883_sysc_wr(t, RT3883_SYSC_REG_RSTCTRL);
+#endif
+
+ /* enable clock for port0's and port1's phys */
+ t = rt3883_sysc_rr(RT3883_SYSC_REG_CLKCFG1);
+ t = t | RT3883_CLKCFG1_UPHY0_CLK_EN | RT3883_CLKCFG1_UPHY1_CLK_EN;
+ rt3883_sysc_wr(t, RT3883_SYSC_REG_CLKCFG1);
+ mdelay(500);
+
+ /* pull USBHOST and USBDEV out from reset */
+ t = rt3883_sysc_rr(RT3883_SYSC_REG_RSTCTRL);
+ t &= ~(RT3883_RSTCTRL_UHST | RT3883_RSTCTRL_UDEV);
+ rt3883_sysc_wr(t, RT3883_SYSC_REG_RSTCTRL);
+ mdelay(500);
+
+ /* enable host mode */
+ t = rt3883_sysc_rr(RT3883_SYSC_REG_SYSCFG1);
+ t |= RT3883_SYSCFG1_USB0_HOST_MODE;
+ rt3883_sysc_wr(t, RT3883_SYSC_REG_SYSCFG1);
+
+ t = rt3883_sysc_rr(RT3883_SYSC_REG_USB_PS);
+}
+
+static void rt3883_usb_host_stop(void)
+{
+ u32 t;
+
+ if (atomic_dec_return(&rt3883_usb_use_count) != 0)
+ return;
+
+ /* put USBHOST and USBDEV into reset */
+ t = rt3883_sysc_rr(RT3883_SYSC_REG_RSTCTRL);
+ t |= RT3883_RSTCTRL_UHST | RT3883_RSTCTRL_UDEV;
+ rt3883_sysc_wr(t, RT3883_SYSC_REG_RSTCTRL);
+ udelay(10000);
+
+ /* disable clock for port0's and port1's phys*/
+ t = rt3883_sysc_rr(RT3883_SYSC_REG_CLKCFG1);
+ t &= ~(RT3883_CLKCFG1_UPHY0_CLK_EN | RT3883_CLKCFG1_UPHY1_CLK_EN);
+ rt3883_sysc_wr(t, RT3883_SYSC_REG_CLKCFG1);
+ udelay(10000);
+}
+
+static struct rt3883_ehci_platform_data rt3883_ehci_data = {
+ .start_hw = rt3883_usb_host_start,
+ .stop_hw = rt3883_usb_host_stop,
+};
+
+static struct resource rt3883_ehci_resources[] = {
+ {
+ .start = RT3883_EHCI_BASE,
+ .end = RT3883_EHCI_BASE + PAGE_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = RT3883_INTC_IRQ_UHST,
+ .end = RT3883_INTC_IRQ_UHST,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static u64 rt3883_ehci_dmamask = DMA_BIT_MASK(32);
+static struct platform_device rt3883_ehci_device = {
+ .name = "rt3883-ehci",
+ .id = -1,
+ .resource = rt3883_ehci_resources,
+ .num_resources = ARRAY_SIZE(rt3883_ehci_resources),
+ .dev = {
+ .dma_mask = &rt3883_ehci_dmamask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ .platform_data = &rt3883_ehci_data,
+ },
+};
+
+static struct resource rt3883_ohci_resources[] = {
+ {
+ .start = RT3883_OHCI_BASE,
+ .end = RT3883_OHCI_BASE + PAGE_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = RT3883_INTC_IRQ_UHST,
+ .end = RT3883_INTC_IRQ_UHST,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct rt3883_ohci_platform_data rt3883_ohci_data = {
+ .start_hw = rt3883_usb_host_start,
+ .stop_hw = rt3883_usb_host_stop,
+};
+
+static u64 rt3883_ohci_dmamask = DMA_BIT_MASK(32);
+static struct platform_device rt3883_ohci_device = {
+ .name = "rt3883-ohci",
+ .id = -1,
+ .resource = rt3883_ohci_resources,
+ .num_resources = ARRAY_SIZE(rt3883_ohci_resources),
+ .dev = {
+ .dma_mask = &rt3883_ohci_dmamask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ .platform_data = &rt3883_ohci_data,
+ },
+};
+
+void __init rt3883_register_usbhost(void)
+{
+ platform_device_register(&rt3883_ehci_device);
+ platform_device_register(&rt3883_ohci_device);
+}
+
+static void rt3883_fe_reset(void)
+{
+ u32 t;
+
+ t = rt3883_sysc_rr(RT3883_SYSC_REG_RSTCTRL);
+ t |= RT3883_RSTCTRL_FE;
+ rt3883_sysc_wr(t , RT3883_SYSC_REG_RSTCTRL);
+
+ t &= ~RT3883_RSTCTRL_FE;
+ rt3883_sysc_wr(t, RT3883_SYSC_REG_RSTCTRL);
+}
+
+static struct resource rt3883_eth_resources[] = {
+ {
+ .start = RT3883_FE_BASE,
+ .end = RT3883_FE_BASE + PAGE_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = RT3883_CPU_IRQ_FE,
+ .end = RT3883_CPU_IRQ_FE,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct ramips_eth_platform_data rt3883_eth_data = {
+ .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
+ .reset_fe = rt3883_fe_reset,
+ .min_pkt_len = 64,
+};
+
+static struct platform_device rt3883_eth_device = {
+ .name = "ramips_eth",
+ .resource = rt3883_eth_resources,
+ .num_resources = ARRAY_SIZE(rt3883_eth_resources),
+ .dev = {
+ .platform_data = &rt3883_eth_data,
+ }
+};
+
+void __init rt3883_register_ethernet(void)
+{
+ struct clk *clk;
+
+ clk = clk_get(NULL, "sys");
+ if (IS_ERR(clk))
+ panic("unable to get SYS clock, err=%ld", PTR_ERR(clk));
+
+ rt3883_eth_data.sys_freq = clk_get_rate(clk);
+
+ platform_device_register(&rt3883_eth_device);
+}
+
+static struct resource rt3883_wlan_resources[] = {
+ {
+ .start = RT3883_WLAN_BASE,
+ .end = RT3883_WLAN_BASE + 0x3FFFF,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = RT3883_CPU_IRQ_WLAN,
+ .end = RT3883_CPU_IRQ_WLAN,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct rt2x00_platform_data rt3883_wlan_data = {
+ .eeprom_file_name = "rt3883.eeprom",
+};
+
+static struct platform_device rt3883_wlan_device = {
+ .name = "rt2800_wmac",
+ .resource = rt3883_wlan_resources,
+ .num_resources = ARRAY_SIZE(rt3883_wlan_resources),
+ .dev = {
+ .platform_data = &rt3883_wlan_data,
+ }
+};
+
+void __init rt3883_register_wlan(void)
+{
+ platform_device_register(&rt3883_wlan_device);
+}
+
+static struct resource rt3883_wdt_resources[] = {
+ {
+ .start = RT3883_TIMER_BASE,
+ .end = RT3883_TIMER_BASE + RT3883_TIMER_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device rt3883_wdt_device = {
+ .name = "ramips-wdt",
+ .id = -1,
+ .resource = rt3883_wdt_resources,
+ .num_resources = ARRAY_SIZE(rt3883_wdt_resources),
+};
+
+void __init rt3883_register_wdt(bool enable_reset)
+{
+ if (enable_reset) {
+ u32 t;
+
+ /* enable WDT reset output on GPIO 2 */
+ t = rt3883_sysc_rr(RT3883_SYSC_REG_SYSCFG1);
+ t |= RT3883_SYSCFG1_GPIO2_AS_WDT_OUT;
+ rt3883_sysc_wr(t, RT3883_SYSC_REG_SYSCFG1);
+ }
+
+ platform_device_register(&rt3883_wdt_device);
+}
+
+static struct resource rt3883_nand_resources[] = {
+ {
+ .flags = IORESOURCE_MEM,
+ .start = RT3883_NANDC_BASE,
+ .end = RT3883_NANDC_BASE + RT3883_NANDC_SIZE - 1,
+ },
+};
+
+static struct ramips_nand_platform_data rt3883_nand_data;
+
+static struct platform_device rt3883_nand_device = {
+ .name = RAMIPS_NAND_DRIVER_NAME,
+ .id = -1,
+ .resource = rt3883_nand_resources,
+ .num_resources = ARRAY_SIZE(rt3883_nand_resources),
+ .dev = {
+ .platform_data = &rt3883_nand_data,
+ },
+};
+
+void __init rt3883_register_nand(struct mtd_partition *parts, int nr_parts)
+{
+ rt3883_nand_data.parts = parts;
+ rt3883_nand_data.nr_parts = nr_parts;
+ platform_device_register(&rt3883_nand_device);
+}
diff --git a/target/linux/ramips/files/arch/mips/ralink/rt3883/devices.h b/target/linux/ramips/files/arch/mips/ralink/rt3883/devices.h
new file mode 100644
index 000000000..4b460e355
--- /dev/null
+++ b/target/linux/ramips/files/arch/mips/ralink/rt3883/devices.h
@@ -0,0 +1,29 @@
+/*
+ * Ralink RT3662/3883 SoC specific platform device definitions
+ *
+ * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#ifndef _RT3883_DEVICES_H
+#define _RT3883_DEVICES_H
+
+struct physmap_flash_data;
+
+extern struct physmap_flash_data rt3883_flash0_data;
+extern struct physmap_flash_data rt3883_flash1_data;
+void rt3883_register_pflash(unsigned int id);
+
+struct mtd_partition;
+void rt3883_register_nand(struct mtd_partition *parts, int nr_parts);
+
+extern struct ramips_eth_platform_data rt3883_eth_data;
+void rt3883_register_ethernet(void);
+void rt3883_register_usbhost(void);
+void rt3883_register_wlan(void);
+void rt3883_register_wdt(bool enable_reset);
+
+#endif /* _RT3883_DEVICES_H */
diff --git a/target/linux/ramips/files/arch/mips/ralink/rt3883/early_printk.c b/target/linux/ramips/files/arch/mips/ralink/rt3883/early_printk.c
new file mode 100644
index 000000000..e3bf7ba33
--- /dev/null
+++ b/target/linux/ramips/files/arch/mips/ralink/rt3883/early_printk.c
@@ -0,0 +1,29 @@
+/*
+ * Ralink RT3662/RT3883 SoC early printk support
+ *
+ * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/io.h>
+#include <linux/serial_reg.h>
+
+#include <asm/addrspace.h>
+
+#include <asm/mach-ralink/rt3883_regs.h>
+
+#define UART_READ(r) \
+ __raw_readl((void __iomem *)(KSEG1ADDR(RT3883_UART1_BASE) + 4 * (r)))
+
+#define UART_WRITE(r, v) \
+ __raw_writel((v), (void __iomem *)(KSEG1ADDR(RT3883_UART1_BASE) + 4 * (r)))
+
+void prom_putchar(unsigned char ch)
+{
+ while (((UART_READ(RT3883_UART_REG_LSR)) & UART_LSR_THRE) == 0);
+ UART_WRITE(RT3883_UART_REG_TX, ch);
+ while (((UART_READ(RT3883_UART_REG_LSR)) & UART_LSR_THRE) == 0);
+}
diff --git a/target/linux/ramips/files/arch/mips/ralink/rt3883/irq.c b/target/linux/ramips/files/arch/mips/ralink/rt3883/irq.c
new file mode 100644
index 000000000..b561fd38c
--- /dev/null
+++ b/target/linux/ramips/files/arch/mips/ralink/rt3883/irq.c
@@ -0,0 +1,84 @@
+/*
+ * Ralink RT3662/RT3883 SoC specific interrupt handling
+ *
+ * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+
+#include <asm/irq_cpu.h>
+#include <asm/mipsregs.h>
+
+#include <asm/mach-ralink/common.h>
+#include <asm/mach-ralink/rt3883.h>
+#include <asm/mach-ralink/rt3883_regs.h>
+
+static void rt3883_intc_irq_dispatch(void)
+{
+ u32 pending;
+
+ pending = ramips_intc_get_status();
+
+ if (pending & RT3883_INTC_INT_TIMER0)
+ do_IRQ(RT3883_INTC_IRQ_TIMER0);
+
+ else if (pending & RT3883_INTC_INT_TIMER1)
+ do_IRQ(RT3883_INTC_IRQ_TIMER1);
+
+ else if (pending & RT3883_INTC_INT_UART0)
+ do_IRQ(RT3883_INTC_IRQ_UART0);
+
+ else if (pending & RT3883_INTC_INT_UART1)
+ do_IRQ(RT3883_INTC_IRQ_UART1);
+
+ else if (pending & RT3883_INTC_INT_PERFC)
+ do_IRQ(RT3883_INTC_IRQ_PERFC);
+
+ else if (pending & RT3883_INTC_INT_UHST)
+ do_IRQ(RT3883_INTC_IRQ_UHST);
+
+ /* TODO: handle PIO interrupts as well */
+
+ else
+ spurious_interrupt();
+}
+
+asmlinkage void plat_irq_dispatch(void)
+{
+ unsigned long pending;
+
+ pending = read_c0_status() & read_c0_cause() & ST0_IM;
+
+ if (pending & STATUSF_IP7)
+ do_IRQ(RT3883_CPU_IRQ_COUNTER);
+
+ else if (pending & STATUSF_IP5)
+ do_IRQ(RT3883_CPU_IRQ_FE);
+
+ else if (pending & STATUSF_IP6)
+ do_IRQ(RT3883_CPU_IRQ_WLAN);
+
+ else if (pending & STATUSF_IP4)
+ do_IRQ(RT3883_CPU_IRQ_PCI);
+
+ else if (pending & STATUSF_IP2)
+ rt3883_intc_irq_dispatch();
+
+ else
+ spurious_interrupt();
+}
+
+void __init arch_init_irq(void)
+{
+ mips_cpu_irq_init();
+ ramips_intc_irq_init(RT3883_INTC_BASE, RT3883_CPU_IRQ_INTC,
+ RT3883_INTC_IRQ_BASE);
+ cp0_perfcount_irq = RT3883_INTC_IRQ_PERFC;
+}
diff --git a/target/linux/ramips/files/arch/mips/ralink/rt3883/rt3883.c b/target/linux/ramips/files/arch/mips/ralink/rt3883/rt3883.c
new file mode 100644
index 000000000..6e75b390f
--- /dev/null
+++ b/target/linux/ramips/files/arch/mips/ralink/rt3883/rt3883.c
@@ -0,0 +1,211 @@
+/*
+ * Ralink RT3662/RT3883 SoC specific setup
+ *
+ * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * Parts of this file are based on Ralink's 2.6.21 BSP
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/module.h>
+
+#include <asm/mach-ralink/common.h>
+#include <asm/mach-ralink/ramips_gpio.h>
+#include <asm/mach-ralink/rt3883.h>
+#include <asm/mach-ralink/rt3883_regs.h>
+
+void __iomem * rt3883_sysc_base;
+void __iomem * rt3883_memc_base;
+
+void __init rt3883_detect_sys_type(void)
+{
+ u32 n0;
+ u32 n1;
+ u32 id;
+
+ n0 = rt3883_sysc_rr(RT3883_SYSC_REG_CHIPID0_3);
+ n1 = rt3883_sysc_rr(RT3883_SYSC_REG_CHIPID4_7);
+ id = rt3883_sysc_rr(RT3883_SYSC_REG_REVID);
+
+ snprintf(ramips_sys_type, RAMIPS_SYS_TYPE_LEN,
+ "Ralink %c%c%c%c%c%c%c%c ver:%u eco:%u",
+ (char) (n0 & 0xff), (char) ((n0 >> 8) & 0xff),
+ (char) ((n0 >> 16) & 0xff), (char) ((n0 >> 24) & 0xff),
+ (char) (n1 & 0xff), (char) ((n1 >> 8) & 0xff),
+ (char) ((n1 >> 16) & 0xff), (char) ((n1 >> 24) & 0xff),
+ (id >> RT3883_REVID_VER_ID_SHIFT) & RT3883_REVID_VER_ID_MASK,
+ (id & RT3883_REVID_ECO_ID_MASK));
+}
+
+static struct ramips_gpio_chip rt3883_gpio_chips[] = {
+ {
+ .chip = {
+ .label = "RT3883-GPIO0",
+ .base = 0,
+ .ngpio = 24,
+ },
+ .regs = {
+ [RAMIPS_GPIO_REG_INT] = 0x00,
+ [RAMIPS_GPIO_REG_EDGE] = 0x04,
+ [RAMIPS_GPIO_REG_RENA] = 0x08,
+ [RAMIPS_GPIO_REG_FENA] = 0x0c,
+ [RAMIPS_GPIO_REG_DATA] = 0x20,
+ [RAMIPS_GPIO_REG_DIR] = 0x24,
+ [RAMIPS_GPIO_REG_POL] = 0x28,
+ [RAMIPS_GPIO_REG_SET] = 0x2c,
+ [RAMIPS_GPIO_REG_RESET] = 0x30,
+ [RAMIPS_GPIO_REG_TOGGLE] = 0x34,
+ },
+ .map_base = RT3883_PIO_BASE,
+ .map_size = RT3883_PIO_SIZE,
+ },
+ {
+ .chip = {
+ .label = "RT3883-GPIO1",
+ .base = 24,
+ .ngpio = 16,
+ },
+ .regs = {
+ [RAMIPS_GPIO_REG_INT] = 0x38,
+ [RAMIPS_GPIO_REG_EDGE] = 0x3c,
+ [RAMIPS_GPIO_REG_RENA] = 0x40,
+ [RAMIPS_GPIO_REG_FENA] = 0x44,
+ [RAMIPS_GPIO_REG_DATA] = 0x48,
+ [RAMIPS_GPIO_REG_DIR] = 0x4c,
+ [RAMIPS_GPIO_REG_POL] = 0x50,
+ [RAMIPS_GPIO_REG_SET] = 0x54,
+ [RAMIPS_GPIO_REG_RESET] = 0x58,
+ [RAMIPS_GPIO_REG_TOGGLE] = 0x5c,
+ },
+ .map_base = RT3883_PIO_BASE,
+ .map_size = RT3883_PIO_SIZE,
+ },
+ {
+ .chip = {
+ .label = "RT3883-GPIO2",
+ .base = 40,
+ .ngpio = 32,
+ },
+ .regs = {
+ [RAMIPS_GPIO_REG_INT] = 0x60,
+ [RAMIPS_GPIO_REG_EDGE] = 0x64,
+ [RAMIPS_GPIO_REG_RENA] = 0x68,
+ [RAMIPS_GPIO_REG_FENA] = 0x6c,
+ [RAMIPS_GPIO_REG_DATA] = 0x70,
+ [RAMIPS_GPIO_REG_DIR] = 0x74,
+ [RAMIPS_GPIO_REG_POL] = 0x78,
+ [RAMIPS_GPIO_REG_SET] = 0x7c,
+ [RAMIPS_GPIO_REG_RESET] = 0x80,
+ [RAMIPS_GPIO_REG_TOGGLE] = 0x84,
+ },
+ .map_base = RT3883_PIO_BASE,
+ .map_size = RT3883_PIO_SIZE,
+ },
+ {
+ .chip = {
+ .label = "RT3883-GPIO3",
+ .base = 72,
+ .ngpio = 24,
+ },
+ .regs = {
+ [RAMIPS_GPIO_REG_INT] = 0x88,
+ [RAMIPS_GPIO_REG_EDGE] = 0x8c,
+ [RAMIPS_GPIO_REG_RENA] = 0x90,
+ [RAMIPS_GPIO_REG_FENA] = 0x94,
+ [RAMIPS_GPIO_REG_DATA] = 0x98,
+ [RAMIPS_GPIO_REG_DIR] = 0x9c,
+ [RAMIPS_GPIO_REG_POL] = 0xa0,
+ [RAMIPS_GPIO_REG_SET] = 0xa4,
+ [RAMIPS_GPIO_REG_RESET] = 0xa8,
+ [RAMIPS_GPIO_REG_TOGGLE] = 0xac,
+ },
+ .map_base = RT3883_PIO_BASE,
+ .map_size = RT3883_PIO_SIZE,
+ },
+};
+
+static struct ramips_gpio_data rt3883_gpio_data = {
+ .chips = rt3883_gpio_chips,
+ .num_chips = ARRAY_SIZE(rt3883_gpio_chips),
+};
+
+static void rt3883_gpio_reserve(int first, int last)
+{
+ for (; first <= last; first++)
+ gpio_request(first, "reserved");
+}
+
+void __init rt3883_gpio_init(u32 mode)
+{
+ u32 t;
+
+ rt3883_sysc_wr(mode, RT3883_SYSC_REG_GPIO_MODE);
+
+ ramips_gpio_init(&rt3883_gpio_data);
+ if ((mode & RT3883_GPIO_MODE_I2C) == 0)
+ rt3883_gpio_reserve(RT3883_GPIO_I2C_SD, RT3883_GPIO_I2C_SCLK);
+
+ if ((mode & RT3883_GPIO_MODE_SPI) == 0)
+ rt3883_gpio_reserve(RT3883_GPIO_SPI_CS0, RT3883_GPIO_SPI_CLK);
+
+ t = mode >> RT3883_GPIO_MODE_UART0_SHIFT;
+ t &= RT3883_GPIO_MODE_UART0_MASK;
+ switch (t) {
+ case RT3883_GPIO_MODE_UARTF:
+ case RT3883_GPIO_MODE_PCM_UARTF:
+ case RT3883_GPIO_MODE_PCM_I2S:
+ case RT3883_GPIO_MODE_I2S_UARTF:
+ rt3883_gpio_reserve(RT3883_GPIO_7, RT3883_GPIO_14);
+ break;
+ case RT3883_GPIO_MODE_PCM_GPIO:
+ rt3883_gpio_reserve(RT3883_GPIO_11, RT3883_GPIO_14);
+ break;
+ case RT3883_GPIO_MODE_GPIO_UARTF:
+ case RT3883_GPIO_MODE_GPIO_I2S:
+ rt3883_gpio_reserve(RT3883_GPIO_7, RT3883_GPIO_10);
+ break;
+ }
+
+ if ((mode & RT3883_GPIO_MODE_UART1) == 0)
+ rt3883_gpio_reserve(RT3883_GPIO_UART1_TXD,
+ RT3883_GPIO_UART1_RXD);
+
+ if ((mode & RT3883_GPIO_MODE_JTAG) == 0)
+ rt3883_gpio_reserve(RT3883_GPIO_JTAG_TDO,
+ RT3883_GPIO_JTAG_TCLK);
+
+ if ((mode & RT3883_GPIO_MODE_MDIO) == 0)
+ rt3883_gpio_reserve(RT3883_GPIO_MDIO_MDC,
+ RT3883_GPIO_MDIO_MDIO);
+
+ if ((mode & RT3883_GPIO_MODE_GE1) == 0)
+ rt3883_gpio_reserve(RT3883_GPIO_GE1_TXD0,
+ RT3883_GPIO_GE1_RXCLK);
+
+ if ((mode & RT3883_GPIO_MODE_GE2) == 0)
+ rt3883_gpio_reserve(RT3883_GPIO_GE2_TXD0,
+ RT3883_GPIO_GE2_RXCLK);
+
+ t = mode >> RT3883_GPIO_MODE_PCI_SHIFT;
+ t &= RT3883_GPIO_MODE_PCI_MASK;
+ if (t != RT3883_GPIO_MODE_PCI_GPIO)
+ rt3883_gpio_reserve(RT3883_GPIO_PCI_AD0,
+ RT3883_GPIO_PCI_AD31);
+
+ t = mode >> RT3883_GPIO_MODE_LNA_A_SHIFT;
+ t &= RT3883_GPIO_MODE_LNA_A_MASK;
+ if (t != RT3883_GPIO_MODE_LNA_A_GPIO)
+ rt3883_gpio_reserve(RT3883_GPIO_LNA_PE_A0,
+ RT3883_GPIO_LNA_PE_A2);
+
+ t = mode >> RT3883_GPIO_MODE_LNA_G_SHIFT;
+ t &= RT3883_GPIO_MODE_LNA_G_MASK;
+ if (t != RT3883_GPIO_MODE_LNA_G_GPIO)
+ rt3883_gpio_reserve(RT3883_GPIO_LNA_PE_G0,
+ RT3883_GPIO_LNA_PE_G2);
+}
diff --git a/target/linux/ramips/files/arch/mips/ralink/rt3883/setup.c b/target/linux/ramips/files/arch/mips/ralink/rt3883/setup.c
new file mode 100644
index 000000000..f4c7296fa
--- /dev/null
+++ b/target/linux/ramips/files/arch/mips/ralink/rt3883/setup.c
@@ -0,0 +1,89 @@
+/*
+ * Ralink RT3662/RT3883 SoC specific setup
+ *
+ * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * Parts of this file are based on Ralink's 2.6.21 BSP
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+
+#include <asm/mips_machine.h>
+#include <asm/reboot.h>
+#include <asm/time.h>
+
+#include <asm/mach-ralink/common.h>
+#include <asm/mach-ralink/rt3883.h>
+#include <asm/mach-ralink/rt3883_regs.h>
+#include "common.h"
+
+static void rt3883_restart(char *command)
+{
+ rt3883_sysc_wr(RT3883_RSTCTRL_SYS, RT3883_SYSC_REG_RSTCTRL);
+ while (1)
+ if (cpu_wait)
+ cpu_wait();
+}
+
+static void rt3883_halt(void)
+{
+ while (1)
+ if (cpu_wait)
+ cpu_wait();
+}
+
+unsigned int __cpuinit get_c0_compare_irq(void)
+{
+ return CP0_LEGACY_COMPARE_IRQ;
+}
+
+void __init ramips_soc_setup(void)
+{
+ struct clk *clk;
+
+ rt3883_sysc_base = ioremap_nocache(RT3883_SYSC_BASE, PAGE_SIZE);
+ rt3883_memc_base = ioremap_nocache(RT3883_MEMC_BASE, PAGE_SIZE);
+
+ rt3883_detect_sys_type();
+ rt3883_clocks_init();
+
+ clk = clk_get(NULL, "cpu");
+ if (IS_ERR(clk))
+ panic("unable to get CPU clock, err=%ld", PTR_ERR(clk));
+
+ printk(KERN_INFO "%s running at %lu.%02lu MHz\n", ramips_sys_type,
+ clk_get_rate(clk) / 1000000,
+ (clk_get_rate(clk) % 1000000) * 100 / 1000000);
+
+ _machine_restart = rt3883_restart;
+ _machine_halt = rt3883_halt;
+ pm_power_off = rt3883_halt;
+
+ clk = clk_get(NULL, "uart");
+ if (IS_ERR(clk))
+ panic("unable to get UART clock, err=%ld", PTR_ERR(clk));
+
+ ramips_early_serial_setup(0, RT3883_UART0_BASE, clk_get_rate(clk),
+ RT3883_INTC_IRQ_UART0);
+ ramips_early_serial_setup(1, RT3883_UART1_BASE, clk_get_rate(clk),
+ RT3883_INTC_IRQ_UART1);
+}
+
+void __init plat_time_init(void)
+{
+ struct clk *clk;
+
+ clk = clk_get(NULL, "cpu");
+ if (IS_ERR(clk))
+ panic("unable to get CPU clock, err=%ld", PTR_ERR(clk));
+
+ mips_hpt_frequency = clk_get_rate(clk) / 2;
+}