1 files changed, 65 insertions, 0 deletions
diff --git a/target/linux/lantiq/patches/860-falcon-fix-version.patch b/target/linux/lantiq/patches/860-falcon-fix-version.patch
new file mode 100644
index 000000000..e934d2efe
--- /dev/null
+++ b/target/linux/lantiq/patches/860-falcon-fix-version.patch
@@ -0,0 +1,65 @@
+--- a/arch/mips/lantiq/falcon/prom.c
++++ b/arch/mips/lantiq/falcon/prom.c
+@@ -14,6 +14,9 @@
+ #include "../prom.h"
+ 
+ #define SOC_FALCON		"Falcon"
++#define SOC_FALCON_D		"Falcon-D"
++#define SOC_FALCON_V		"Falcon-V"
++#define SOC_FALCON_M		"Falcon-M"
+ 
+ #define PART_SHIFT	12
+ #define PART_MASK	0x0FFFF000
+@@ -21,6 +24,8 @@
+ #define REV_MASK	0xF0000000
+ #define SREV_SHIFT	22
+ #define SREV_MASK	0x03C00000
++#define TYPE_SHIFT	26
++#define TYPE_MASK	0x3C000000
+ 
+ #define MUXC_SIF_RX_PIN		112
+ #define MUXC_SIF_TX_PIN		113
+@@ -54,14 +59,30 @@ ltq_soc_setup(void)
+ void __init
+ ltq_soc_detect(struct ltq_soc_info *i)
+ {
++	u32 type;
+ 	i->partnum = (ltq_r32(LTQ_FALCON_CHIPID) & PART_MASK) >> PART_SHIFT;
+ 	i->rev = (ltq_r32(LTQ_FALCON_CHIPID) & REV_MASK) >> REV_SHIFT;
+-	i->srev = (ltq_r32(LTQ_FALCON_CHIPCONF) & SREV_MASK) >> SREV_SHIFT;
++	i->srev = ((ltq_r32(LTQ_FALCON_CHIPCONF) & SREV_MASK) >> SREV_SHIFT);
+ 	sprintf(i->rev_type, "%c%d%d", (i->srev & 0x4) ? ('B') : ('A'),
+-		i->rev & 0x7, i->srev & 0x3);
++		i->rev & 0x7, (i->srev & 0x3) + 1);
++
+ 	switch (i->partnum) {
+ 	case SOC_ID_FALCON:
+-		i->name = SOC_FALCON;
++		type = (ltq_r32(LTQ_FALCON_CHIPTYPE) & TYPE_MASK) >> TYPE_SHIFT;
++		switch (type) {
++		case 0:
++			i->name = SOC_FALCON_D;
++			break;
++		case 1:
++			i->name = SOC_FALCON_V;
++			break;
++		case 2:
++			i->name = SOC_FALCON_M;
++			break;
++		default:
++			i->name = SOC_FALCON;
++			break;
++		}
+ 		i->type = SOC_TYPE_FALCON;
+ 		break;
+ 
+--- a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
++++ b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
+@@ -78,6 +78,7 @@
+ #define LTQ_STATUS_BASE_ADDR	0x1E802000
+ 
+ #define LTQ_FALCON_CHIPID	((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x0c))
++#define LTQ_FALCON_CHIPTYPE	((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x38))
+ #define LTQ_FALCON_CHIPCONF	((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x40))
+ 
+ /* SYSCTL - start/stop/restart/configure/... different parts of the Soc */