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Diffstat (limited to 'target/linux/lantiq/patches-3.3/0011-MIPS-lantiq-fix-pull-gpio-up-resistors-usage.patch')
-rw-r--r--target/linux/lantiq/patches-3.3/0011-MIPS-lantiq-fix-pull-gpio-up-resistors-usage.patch48
1 files changed, 48 insertions, 0 deletions
diff --git a/target/linux/lantiq/patches-3.3/0011-MIPS-lantiq-fix-pull-gpio-up-resistors-usage.patch b/target/linux/lantiq/patches-3.3/0011-MIPS-lantiq-fix-pull-gpio-up-resistors-usage.patch
new file mode 100644
index 000000000..c89134df8
--- /dev/null
+++ b/target/linux/lantiq/patches-3.3/0011-MIPS-lantiq-fix-pull-gpio-up-resistors-usage.patch
@@ -0,0 +1,48 @@
+From 784e85cf7ce5032c9e5de35505fcc209f2a7891e Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Thu, 27 Oct 2011 20:06:30 +0200
+Subject: [PATCH 11/70] MIPS: lantiq: fix pull gpio up resistors usage
+
+The register that enables a gpios internal pullups was not used. This patch
+makes sure the pullups are activated correctly.
+
+Signed-off-by: Matti Laakso <malaakso@elisanet.fi>
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/lantiq/xway/gpio.c | 6 ++++++
+ 1 files changed, 6 insertions(+), 0 deletions(-)
+
+diff --git a/arch/mips/lantiq/xway/gpio.c b/arch/mips/lantiq/xway/gpio.c
+index f204f6c..14ff7c7 100644
+--- a/arch/mips/lantiq/xway/gpio.c
++++ b/arch/mips/lantiq/xway/gpio.c
+@@ -21,6 +21,8 @@
+ #define LTQ_GPIO_ALTSEL0 0x0C
+ #define LTQ_GPIO_ALTSEL1 0x10
+ #define LTQ_GPIO_OD 0x14
++#define LTQ_GPIO_PUDSEL 0x1C
++#define LTQ_GPIO_PUDEN 0x20
+
+ #define PINS_PER_PORT 16
+ #define MAX_PORTS 3
+@@ -106,6 +108,8 @@ static int ltq_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
+
+ ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_OD, offset);
+ ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_DIR, offset);
++ ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_PUDSEL, offset);
++ ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_PUDEN, offset);
+
+ return 0;
+ }
+@@ -117,6 +121,8 @@ static int ltq_gpio_direction_output(struct gpio_chip *chip,
+
+ ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_OD, offset);
+ ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_DIR, offset);
++ ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_PUDSEL, offset);
++ ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_PUDEN, offset);
+ ltq_gpio_set(chip, offset, value);
+
+ return 0;
+--
+1.7.9.1
+