diff options
Diffstat (limited to 'target/linux/lantiq/files-3.3/arch/mips/lantiq')
56 files changed, 10440 insertions, 0 deletions
diff --git a/target/linux/lantiq/files-3.3/arch/mips/lantiq/dev-gpio-buttons.c b/target/linux/lantiq/files-3.3/arch/mips/lantiq/dev-gpio-buttons.c new file mode 100644 index 000000000..ad25cac79 --- /dev/null +++ b/target/linux/lantiq/files-3.3/arch/mips/lantiq/dev-gpio-buttons.c @@ -0,0 +1,58 @@ +/* + * Lantiq GPIO button support + * + * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/init.h> +#include <linux/slab.h> +#include <linux/platform_device.h> + +#include <dev-gpio-buttons.h> + +void __init ltq_register_gpio_keys_polled(int id, + unsigned poll_interval, + unsigned nbuttons, + struct gpio_keys_button *buttons) +{ + struct platform_device *pdev; + struct gpio_keys_platform_data pdata; + struct gpio_keys_button *p; + int err; + + p = kmalloc(nbuttons * sizeof(*p), GFP_KERNEL); + if (!p) + return; + + memcpy(p, buttons, nbuttons * sizeof(*p)); + + pdev = platform_device_alloc("gpio-keys-polled", id); + if (!pdev) + goto err_free_buttons; + + memset(&pdata, 0, sizeof(pdata)); + pdata.poll_interval = poll_interval; + pdata.nbuttons = nbuttons; + pdata.buttons = p; + + err = platform_device_add_data(pdev, &pdata, sizeof(pdata)); + if (err) + goto err_put_pdev; + + err = platform_device_add(pdev); + if (err) + goto err_put_pdev; + + return; + +err_put_pdev: + platform_device_put(pdev); + +err_free_buttons: + kfree(p); +} diff --git a/target/linux/lantiq/files-3.3/arch/mips/lantiq/dev-gpio-leds.c b/target/linux/lantiq/files-3.3/arch/mips/lantiq/dev-gpio-leds.c new file mode 100644 index 000000000..89dc79de6 --- /dev/null +++ b/target/linux/lantiq/files-3.3/arch/mips/lantiq/dev-gpio-leds.c @@ -0,0 +1,57 @@ +/* + * Lantiq GPIO LED device support + * + * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * Parts of this file are based on Atheros' 2.6.15 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/init.h> +#include <linux/slab.h> +#include <linux/platform_device.h> + +#include <dev-gpio-leds.h> + +void __init ltq_add_device_gpio_leds(int id, unsigned num_leds, + struct gpio_led *leds) +{ + struct platform_device *pdev; + struct gpio_led_platform_data pdata; + struct gpio_led *p; + int err; + + p = kmalloc(num_leds * sizeof(*p), GFP_KERNEL); + if (!p) + return; + + memcpy(p, leds, num_leds * sizeof(*p)); + + pdev = platform_device_alloc("leds-gpio", id); + if (!pdev) + goto err_free_leds; + + memset(&pdata, 0, sizeof(pdata)); + pdata.num_leds = num_leds; + pdata.leds = p; + + err = platform_device_add_data(pdev, &pdata, sizeof(pdata)); + if (err) + goto err_put_pdev; + + err = platform_device_add(pdev); + if (err) + goto err_put_pdev; + + return; + +err_put_pdev: + platform_device_put(pdev); + +err_free_leds: + kfree(p); +} diff --git a/target/linux/lantiq/files-3.3/arch/mips/lantiq/falcon/Kconfig b/target/linux/lantiq/files-3.3/arch/mips/lantiq/falcon/Kconfig new file mode 100644 index 000000000..03e999d92 --- /dev/null +++ b/target/linux/lantiq/files-3.3/arch/mips/lantiq/falcon/Kconfig @@ -0,0 +1,11 @@ +if SOC_FALCON + +menu "MIPS Machine" + +config LANTIQ_MACH_EASY98000 + bool "Easy98000" + default y + +endmenu + +endif diff --git a/target/linux/lantiq/files-3.3/arch/mips/lantiq/falcon/Makefile b/target/linux/lantiq/files-3.3/arch/mips/lantiq/falcon/Makefile new file mode 100644 index 000000000..3634154fb --- /dev/null +++ b/target/linux/lantiq/files-3.3/arch/mips/lantiq/falcon/Makefile @@ -0,0 +1,2 @@ +obj-y := prom.o reset.o sysctrl.o devices.o gpio.o +obj-$(CONFIG_LANTIQ_MACH_EASY98000) += mach-easy98000.o diff --git a/target/linux/lantiq/files-3.3/arch/mips/lantiq/falcon/addon-easy98000.c b/target/linux/lantiq/files-3.3/arch/mips/lantiq/falcon/addon-easy98000.c new file mode 100644 index 000000000..317ee4001 --- /dev/null +++ b/target/linux/lantiq/files-3.3/arch/mips/lantiq/falcon/addon-easy98000.c @@ -0,0 +1,213 @@ +/* + * EASY98000 CPLD Addon driver + * + * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/version.h> +#include <linux/types.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/errno.h> +#include <linux/slab.h> +#include <linux/proc_fs.h> +#include <linux/seq_file.h> + +struct easy98000_reg_cpld { + u16 cmdreg1; /* 0x1 */ + u16 cmdreg0; /* 0x0 */ + u16 idreg0; /* 0x3 */ + u16 resreg; /* 0x2 */ + u16 intreg; /* 0x5 */ + u16 idreg1; /* 0x4 */ + u16 ledreg; /* 0x7 */ + u16 pcmconconfig; /* 0x6 */ + u16 res0; /* 0x9 */ + u16 ethledreg; /* 0x8 */ + u16 res1[4]; /* 0xa-0xd */ + u16 cpld1v; /* 0xf */ + u16 cpld2v; /* 0xe */ +}; +static struct easy98000_reg_cpld * const cpld = + (struct easy98000_reg_cpld *)(KSEG1 | 0x17c00000); +#define cpld_r8(reg) (__raw_readw(&cpld->reg) & 0xFF) +#define cpld_w8(val, reg) __raw_writew((val) & 0xFF, &cpld->reg) + +int easy98000_addon_has_dm9000(void) +{ + if ((cpld_r8(idreg0) & 0xF) == 1) + return 1; + return 0; +} + +#if defined(CONFIG_PROC_FS) +typedef void (*cpld_dump) (struct seq_file *s); +struct proc_entry { + char *name; + void *callback; +}; + +static int cpld_proc_show ( struct seq_file *s, void *p ) +{ + cpld_dump dump = s->private; + + if ( dump != NULL ) + dump(s); + + return 0; +} + +static int cpld_proc_open ( struct inode *inode, struct file *file ) +{ + return single_open ( file, cpld_proc_show, PDE(inode)->data ); +} + +static void cpld_versions_get ( struct seq_file *s ) +{ + seq_printf(s, "CPLD1: V%d\n", cpld_r8(cpld1v)); + seq_printf(s, "CPLD2: V%d\n", cpld_r8(cpld2v)); +} + +static void cpld_ebu_module_get ( struct seq_file *s ) +{ + u8 addon_id; + + addon_id = cpld_r8(idreg0) & 0xF; + switch (addon_id) { + case 0xF: /* nothing connected */ + break; + case 1: + seq_printf(s, "Ethernet Controller module (dm9000)\n"); + break; + default: + seq_printf(s, "Unknown EBU module (EBU_ID=0x%02X)\n", addon_id); + break; + } +} + +static void cpld_xmii_module_get ( struct seq_file *s ) +{ + u8 addon_id; + char *mod = NULL; + + addon_id = cpld_r8(idreg1) & 0xF; + switch (addon_id) { + case 0xF: + mod = "no module"; + break; + case 0x1: + mod = "RGMII module"; + break; + case 0x4: + mod = "GMII MAC Mode (XWAY TANTOS-3G)"; + break; + case 0x6: + mod = "TMII MAC Mode (XWAY TANTOS-3G)"; + break; + case 0x8: + mod = "GMII PHY module"; + break; + case 0x9: + mod = "MII PHY module"; + break; + case 0xA: + mod = "RMII PHY module"; + break; + default: + break; + } + if (mod) + seq_printf(s, "%s\n", mod); + else + seq_printf(s, "unknown xMII module (xMII_ID=0x%02X)\n", addon_id); +} + +static struct proc_entry proc_entries[] = { + {"versions", cpld_versions_get}, + {"ebu", cpld_ebu_module_get}, + {"xmii", cpld_xmii_module_get}, +}; + +static struct file_operations ops = { + .owner = THIS_MODULE, + .open = cpld_proc_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static void cpld_proc_entry_create(struct proc_dir_entry *parent_node, + struct proc_entry *proc_entry) +{ + proc_create_data ( proc_entry->name, (S_IFREG | S_IRUGO), parent_node, + &ops, proc_entry->callback); +} + +static int cpld_proc_install(void) +{ + struct proc_dir_entry *driver_proc_node; + + driver_proc_node = proc_mkdir("cpld", NULL); + if (driver_proc_node != NULL) { + int i; + for (i = 0; i < ARRAY_SIZE(proc_entries); i++) + cpld_proc_entry_create(driver_proc_node, + &proc_entries[i]); + } else { + printk("cannot create proc entry"); + return -1; + } + return 0; +} +#else +static inline int cpld_proc_install(void) {} +#endif + +static int easy98000_addon_probe(struct platform_device *pdev) +{ + return cpld_proc_install(); +} + +static int easy98000_addon_remove(struct platform_device *pdev) +{ +#if defined(CONFIG_PROC_FS) + char buf[64]; + int i; + + for (i = 0; i < sizeof(proc_entries) / sizeof(proc_entries[0]); i++) { + sprintf(buf, "cpld/%s", proc_entries[i].name); + remove_proc_entry(buf, 0); + } + remove_proc_entry("cpld", 0); +#endif + return 0; +} + +static struct platform_driver easy98000_addon_driver = { + .probe = easy98000_addon_probe, + .remove = __devexit_p(easy98000_addon_remove), + .driver = { + .name = "easy98000_addon", + .owner = THIS_MODULE, + }, +}; + +int __init easy98000_addon_init(void) +{ + return platform_driver_register(&easy98000_addon_driver); +} + +void __exit easy98000_addon_exit(void) +{ + platform_driver_unregister(&easy98000_addon_driver); +} + +module_init(easy98000_addon_init); +module_exit(easy98000_addon_exit); diff --git a/target/linux/lantiq/files-3.3/arch/mips/lantiq/falcon/dev-leds-easy98000-cpld.c b/target/linux/lantiq/files-3.3/arch/mips/lantiq/falcon/dev-leds-easy98000-cpld.c new file mode 100644 index 000000000..94622cfda --- /dev/null +++ b/target/linux/lantiq/files-3.3/arch/mips/lantiq/falcon/dev-leds-easy98000-cpld.c @@ -0,0 +1,161 @@ +/* + * EASY98000 CPLD LED driver + * + * Copyright (C) 2010 Ralph Hempel <ralph.hempel@lantiq.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include <linux/kernel.h> +#include <linux/version.h> +#include <linux/types.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/module.h> +#include <linux/errno.h> +#include <linux/leds.h> +#include <linux/slab.h> + +#include "dev-leds-easy98000-cpld.h" + +const char *led_name[8] = { + "ge0_act", + "ge0_link", + "ge1_act", + "ge1_link", + "fe2_act", + "fe2_link", + "fe3_act", + "fe3_link" +}; + +#define cpld_base7 ((u16 *)(KSEG1 | 0x17c0000c)) +#define cpld_base8 ((u16 *)(KSEG1 | 0x17c00012)) + +#define ltq_r16(reg) __raw_readw(reg) +#define ltq_w16(val, reg) __raw_writew(val, reg) + +struct cpld_led_dev { + struct led_classdev cdev; + u8 mask; + u16 *base; +}; + +struct cpld_led_drvdata { + struct cpld_led_dev *led_devs; + int num_leds; +}; + +void led_set(u8 mask, u16 *base) +{ + ltq_w16(ltq_r16(base) | mask, base); +} + +void led_clear(u8 mask, u16 *base) +{ + ltq_w16(ltq_r16(base) & (~mask), base); +} + +void led_blink_clear(u8 mask, u16 *base) +{ + led_clear(mask, base); +} + +static void led_brightness(struct led_classdev *led_cdev, + enum led_brightness value) +{ + struct cpld_led_dev *led_dev = + container_of(led_cdev, struct cpld_led_dev, cdev); + + if (value) + led_set(led_dev->mask, led_dev->base); + else + led_clear(led_dev->mask, led_dev->base); +} + +static int led_probe(struct platform_device *pdev) +{ + int i; + char name[32]; + struct cpld_led_drvdata *drvdata; + int ret = 0; + + drvdata = kzalloc(sizeof(struct cpld_led_drvdata) + + sizeof(struct cpld_led_dev) * MAX_LED, + GFP_KERNEL); + if (!drvdata) + return -ENOMEM; + + drvdata->led_devs = (struct cpld_led_dev *) &drvdata[1]; + + for (i = 0; i < MAX_LED; i++) { + struct cpld_led_dev *led_dev = &drvdata->led_devs[i]; + led_dev->cdev.brightness_set = led_brightness; + led_dev->cdev.default_trigger = NULL; + led_dev->mask = 1 << (i % 8); + if(i < 8) { + sprintf(name, "easy98000-cpld:%s", led_name[i]); + led_dev->base = cpld_base8; + } else { + sprintf(name, "easy98000-cpld:red:%d", i-8); + led_dev->base = cpld_base7; + } + led_dev->cdev.name = name; + ret = led_classdev_register(&pdev->dev, &led_dev->cdev); + if (ret) + goto err; + } + platform_set_drvdata(pdev, drvdata); + return 0; + +err: + printk("led_probe: 3\n"); + for (i = i - 1; i >= 0; i--) + led_classdev_unregister(&drvdata->led_devs[i].cdev); + + kfree(drvdata); + return ret; +} + +static int led_remove(struct platform_device *pdev) +{ + int i; + struct cpld_led_drvdata *drvdata = platform_get_drvdata(pdev); + for (i = 0; i < MAX_LED; i++) + led_classdev_unregister(&drvdata->led_devs[i].cdev); + kfree(drvdata); + return 0; +} + +static struct platform_driver led_driver = { + .probe = led_probe, + .remove = __devexit_p(led_remove), + .driver = { + .name = LED_NAME, + .owner = THIS_MODULE, + }, +}; + +int __init easy98000_cpld_led_init(void) +{ + pr_info(LED_DESC ", Version " LED_VERSION + " (c) Copyright 2011, Lantiq Deutschland GmbH\n"); + return platform_driver_register(&led_driver); +} + +void __exit easy98000_cpld_led_exit(void) +{ + platform_driver_unregister(&led_driver); +} + +module_init(easy98000_cpld_led_init); +module_exit(easy98000_cpld_led_exit); + +MODULE_DESCRIPTION(LED_NAME); +MODULE_DESCRIPTION(LED_DESC); +MODULE_AUTHOR("Ralph Hempel <ralph.hempel@lantiq.com>"); +MODULE_LICENSE("GPL v2"); + diff --git a/target/linux/lantiq/files-3.3/arch/mips/lantiq/falcon/dev-leds-easy98000-cpld.h b/target/linux/lantiq/files-3.3/arch/mips/lantiq/falcon/dev-leds-easy98000-cpld.h new file mode 100644 index 000000000..3160189fe --- /dev/null +++ b/target/linux/lantiq/files-3.3/arch/mips/lantiq/falcon/dev-leds-easy98000-cpld.h @@ -0,0 +1,20 @@ +/* + * EASY98000 CPLD LED driver + * + * Copyright (C) 2010 Ralph Hempel <ralph.hempel@lantiq.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ +#ifndef _INCLUDE_EASY98000_CPLD_LED_H_ +#define _INCLUDE_EASY98000_CPLD_LED_H_ + +#define LED_NAME "easy98000_cpld_led" +#define LED_DESC "EASY98000 LED driver" +#define LED_VERSION "1.0.0" + +#define MAX_LED 16 + +#endif /* _INCLUDE_EASY98000_CPLD_LED_H_ */ diff --git a/target/linux/lantiq/files-3.3/arch/mips/lantiq/falcon/devices.c b/target/linux/lantiq/files-3.3/arch/mips/lantiq/falcon/devices.c new file mode 100644 index 000000000..e684ed470 --- /dev/null +++ b/target/linux/lantiq/files-3.3/arch/mips/lantiq/falcon/devices.c @@ -0,0 +1,152 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com> + * Copyright (C) 2011 John Crispin <blogic@openwrt.org> + */ + +#include <linux/platform_device.h> +#include <linux/mtd/nand.h> +#include <linux/gpio.h> + +#include <lantiq_soc.h> + +#include "devices.h" + +/* nand flash */ +/* address lines used for NAND control signals */ +#define NAND_ADDR_ALE 0x10000 +#define NAND_ADDR_CLE 0x20000 +/* Ready/Busy Status */ +#define MODCON_STS 0x0002 +/* Ready/Busy Status Edge */ +#define MODCON_STSEDGE 0x0004 + +static const char *part_probes[] = { "cmdlinepart", NULL }; + +static int +falcon_nand_ready(struct mtd_info *mtd) +{ + u32 modcon = ltq_ebu_r32(LTQ_EBU_MODCON); + + return (((modcon & (MODCON_STS | MODCON_STSEDGE)) == + (MODCON_STS | MODCON_STSEDGE))); +} + +static void +falcon_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) +{ + struct nand_chip *this = mtd->priv; + unsigned long nandaddr = (unsigned long) this->IO_ADDR_W; + + if (ctrl & NAND_CTRL_CHANGE) { + nandaddr &= ~(NAND_ADDR_ALE | NAND_ADDR_CLE); + + if (ctrl & NAND_CLE) + nandaddr |= NAND_ADDR_CLE; + if (ctrl & NAND_ALE) + nandaddr |= NAND_ADDR_ALE; + + this->IO_ADDR_W = (void __iomem *) nandaddr; + } + + if (cmd != NAND_CMD_NONE) + writeb(cmd, this->IO_ADDR_W); +} + +static struct platform_nand_data falcon_flash_nand_data = { + .chip = { + .nr_chips = 1, + .chip_delay = 25, + .part_probe_types = part_probes, + }, + .ctrl = { + .cmd_ctrl = falcon_hwcontrol, + .dev_ready = falcon_nand_ready, + } +}; + +static struct resource ltq_nand_res = + MEM_RES("nand", LTQ_FLASH_START, LTQ_FLASH_MAX); + +static struct platform_device ltq_flash_nand = { + .name = "gen_nand", + .id = -1, + .num_resources = 1, + .resource = <q_nand_res, + .dev = { + .platform_data = &falcon_flash_nand_data, + }, +}; + +void __init +falcon_register_nand(void) +{ + platform_device_register(<q_flash_nand); +} + +/* gpio */ +#define DECLARE_GPIO_RES(port) \ +static struct resource falcon_gpio ## port ## _res[] = { \ + MEM_RES("gpio"#port, LTQ_GPIO ## port ## _BASE_ADDR, \ + LTQ_GPIO ## port ## _SIZE), \ + MEM_RES("padctrl"#port, LTQ_PADCTRL ## port ## _BASE_ADDR, \ + LTQ_PADCTRL ## port ## _SIZE), \ + IRQ_RES("gpio_mux"#port, FALCON_IRQ_GPIO_P ## port) \ +} +DECLARE_GPIO_RES(0); +DECLARE_GPIO_RES(1); +DECLARE_GPIO_RES(2); +DECLARE_GPIO_RES(3); +DECLARE_GPIO_RES(4); + +void __init +falcon_register_gpio(void) +{ + platform_device_register_simple("falcon_gpio", 0, + falcon_gpio0_res, ARRAY_SIZE(falcon_gpio0_res)); + platform_device_register_simple("falcon_gpio", 1, + falcon_gpio1_res, ARRAY_SIZE(falcon_gpio1_res)); + platform_device_register_simple("falcon_gpio", 2, + falcon_gpio2_res, ARRAY_SIZE(falcon_gpio2_res)); +} + +void __init +falcon_register_gpio_extra(void) +{ + platform_device_register_simple("falcon_gpio", 3, + falcon_gpio3_res, ARRAY_SIZE(falcon_gpio3_res)); + platform_device_register_simple("falcon_gpio", 4, + falcon_gpio4_res, ARRAY_SIZE(falcon_gpio4_res)); +} + +/* spi flash */ +static struct platform_device ltq_spi = { + .name = "falcon_spi", + .num_resources = 0, +}; + +void __init +falcon_register_spi_flash(struct spi_board_info *data) +{ + spi_register_board_info(data, 1); + platform_device_register(<q_spi); +} + +/* i2c */ +static struct resource falcon_i2c_resources[] = { + MEM_RES("i2c", GPON_I2C_BASE, GPON_I2C_SIZE), + IRQ_RES(i2c_lb, FALCON_IRQ_I2C_LBREQ), + IRQ_RES(i2c_b, FALCON_IRQ_I2C_BREQ), + IRQ_RES(i2c_err, FALCON_IRQ_I2C_I2C_ERR), + IRQ_RES(i2c_p, FALCON_IRQ_I2C_I2C_P), +}; + +void __init +falcon_register_i2c(void) +{ + platform_device_register_simple("i2c-falcon", 0, + falcon_i2c_resources, ARRAY_SIZE(falcon_i2c_resources)); +} diff --git a/target/linux/lantiq/files-3.3/arch/mips/lantiq/falcon/devices.h b/target/linux/lantiq/files-3.3/arch/mips/lantiq/falcon/devices.h new file mode 100644 index 000000000..d81edbe74 --- /dev/null +++ b/target/linux/lantiq/files-3.3/arch/mips/lantiq/falcon/devices.h @@ -0,0 +1,25 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com> + * Copyright (C) 2011 John Crispin <blogic@openwrt.org> + */ + +#ifndef _FALCON_DEVICES_H__ +#define _FALCON_DEVICES_H__ + +#include <linux/spi/spi.h> +#include <linux/spi/flash.h> + +#include "../devices.h" + +extern void falcon_register_nand(void); +extern void falcon_register_gpio(void); +extern void falcon_register_gpio_extra(void); +extern void falcon_register_spi_flash(struct spi_board_info *data); +extern void falcon_register_i2c(void); + +#endif diff --git a/target/linux/lantiq/files-3.3/arch/mips/lantiq/falcon/gpio.c b/target/linux/lantiq/files-3.3/arch/mips/lantiq/falcon/gpio.c new file mode 100644 index 000000000..4147d61c7 --- /dev/null +++ b/target/linux/lantiq/files-3.3/arch/mips/lantiq/falcon/gpio.c @@ -0,0 +1,409 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com> + * Copyright (C) 2011 John Crispin <blogic@openwrt.org> + */ + +#include <linux/gpio.h> +#include <linux/interrupt.h> +#include <linux/slab.h> +#include <linux/export.h> +#include <linux/err.h> +#include <linux/platform_device.h> + +#include <lantiq_soc.h> + +/* Multiplexer Control Register */ +#define LTQ_PADC_MUX(x) (x * 0x4) +/* Pad Control Availability Register */ +#define LTQ_PADC_AVAIL 0x000000F0 + +/* Data Output Register */ +#define LTQ_GPIO_OUT 0x00000000 +/* Data Input Register */ +#define LTQ_GPIO_IN 0x00000004 +/* Direction Register */ +#define LTQ_GPIO_DIR 0x00000008 +/* External Interrupt Control Register 0 */ +#define LTQ_GPIO_EXINTCR0 0x00000018 +/* External Interrupt Control Register 1 */ +#define LTQ_GPIO_EXINTCR1 0x0000001C +/* IRN Capture Register */ +#define LTQ_GPIO_IRNCR 0x00000020 +/* IRN Interrupt Configuration Register */ +#define LTQ_GPIO_IRNCFG 0x0000002C +/* IRN Interrupt Enable Set Register */ +#define LTQ_GPIO_IRNRNSET 0x00000030 +/* IRN Interrupt Enable Clear Register */ +#define LTQ_GPIO_IRNENCLR 0x00000034 +/* Output Set Register */ +#define LTQ_GPIO_OUTSET 0x00000040 +/* Output Cler Register */ +#define LTQ_GPIO_OUTCLR 0x00000044 +/* Direction Clear Register */ +#define LTQ_GPIO_DIRSET 0x00000048 +/* Direction Set Register */ +#define LTQ_GPIO_DIRCLR 0x0000004C + +/* turn a gpio_chip into a falcon_gpio_port */ +#define ctop(c) container_of(c, struct falcon_gpio_port, gpio_chip) +/* turn a irq_data into a falcon_gpio_port */ +#define itop(i) ((struct falcon_gpio_port *) irq_get_chip_data(i->irq)) + +#define ltq_pad_r32(p, reg) ltq_r32(p->pad + reg) +#define ltq_pad_w32(p, val, reg) ltq_w32(val, p->pad + reg) +#define ltq_pad_w32_mask(c, clear, set, reg) \ + ltq_pad_w32(c, (ltq_pad_r32(c, reg) & ~(clear)) | (set), reg) + +#define ltq_port_r32(p, reg) ltq_r32(p->port + reg) +#define ltq_port_w32(p, val, reg) ltq_w32(val, p->port + reg) +#define ltq_port_w32_mask(p, clear, set, reg) \ + ltq_port_w32(p, (ltq_port_r32(p, reg) & ~(clear)) | (set), reg) + +#define MAX_PORTS 5 +#define PINS_PER_PORT 32 + +struct falcon_gpio_port { + struct gpio_chip gpio_chip; + void __iomem *pad; + void __iomem *port; + unsigned int irq_base; + unsigned int chained_irq; + struct clk *clk; +}; + +static struct falcon_gpio_port ltq_gpio_port[MAX_PORTS]; + +int gpio_to_irq(unsigned int gpio) +{ + return __gpio_to_irq(gpio); +} +EXPORT_SYMBOL(gpio_to_irq); + +int ltq_gpio_mux_set(unsigned int pin, unsigned int mux) +{ + int port = pin / 100; + int offset = pin % 100; + struct falcon_gpio_port *gpio_port; + + if ((offset >= PINS_PER_PORT) || (port >= MAX_PORTS)) + return -EINVAL; + + gpio_port = <q_gpio_port[port]; + ltq_pad_w32(gpio_port, mux & 0x3, LTQ_PADC_MUX(offset)); + + return 0; +} +EXPORT_SYMBOL(ltq_gpio_mux_set); + +int ltq_gpio_request(struct device *dev, unsigned int pin, unsigned int mux, + unsigned int dir, const char *name) +{ + int port = pin / 100; + int offset = pin % 100; + + if (offset >= PINS_PER_PORT || port >= MAX_PORTS) + return -EINVAL; + + if (devm_gpio_request(dev, pin, name)) { + pr_err("failed to setup lantiq gpio: %s\n", name); + return -EBUSY; + } + + if (dir) + gpio_direction_output(pin, 1); + else + gpio_direction_input(pin); + + return ltq_gpio_mux_set(pin, mux); +} +EXPORT_SYMBOL(ltq_gpio_request); + +static int +falcon_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) +{ + ltq_port_w32(ctop(chip), 1 << offset, LTQ_GPIO_DIRCLR); + + return 0; +} + +static void +falcon_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) +{ + if (value) + ltq_port_w32(ctop(chip), 1 << offset, LTQ_GPIO_OUTSET); + else + ltq_port_w32(ctop(chip), 1 << offset, LTQ_GPIO_OUTCLR); +} + +static int +falcon_gpio_direction_output(struct gpio_chip *chip, + unsigned int offset, int value) +{ + falcon_gpio_set(chip, offset, value); + ltq_port_w32(ctop(chip), 1 << offset, LTQ_GPIO_DIRSET); + + return 0; +} + +static int +falcon_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + if ((ltq_port_r32(ctop(chip), LTQ_GPIO_DIR) >> offset) & 1) + return (ltq_port_r32(ctop(chip), LTQ_GPIO_OUT) >> offset) & 1; + else + return (ltq_port_r32(ctop(chip), LTQ_GPIO_IN) >> offset) & 1; +} + +static int +falcon_gpio_request(struct gpio_chip *chip, unsigned offset) +{ + if ((ltq_pad_r32(ctop(chip), LTQ_PADC_AVAIL) >> offset) & 1) { + if (ltq_pad_r32(ctop(chip), LTQ_PADC_MUX(offset)) > 1) + return -EBUSY; + /* switch on gpio function */ + ltq_pad_w32(ctop(chip), 1, LTQ_PADC_MUX(offset)); + return 0; + } + + return -ENODEV; +} + +static void +falcon_gpio_free(struct gpio_chip *chip, unsigned offset) +{ + if ((ltq_pad_r32(ctop(chip), LTQ_PADC_AVAIL) >> offset) & 1) { + if (ltq_pad_r32(ctop(chip), LTQ_PADC_MUX(offset)) > 1) + return; + /* switch off gpio function */ + ltq_pad_w32(ctop(chip), 0, LTQ_PADC_MUX(offset)); + } +} + +static int +falcon_gpio_to_irq(struct gpio_chip *chip, unsigned offset) +{ + return ctop(chip)->irq_base + offset; +} + +static void +falcon_gpio_disable_irq(struct irq_data *d) +{ + unsigned int offset = d->irq - itop(d)->irq_base; + + ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNENCLR); +} + +static void +falcon_gpio_enable_irq(struct irq_data *d) +{ + unsigned int offset = d->irq - itop(d)->irq_base; + + if (!ltq_pad_r32(itop(d), LTQ_PADC_MUX(offset)) < 1) + /* switch on gpio function */ + ltq_pad_w32(itop(d), 1, LTQ_PADC_MUX(offset)); + + ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNRNSET); +} + +static void +falcon_gpio_ack_irq(struct irq_data *d) +{ + unsigned int offset = d->irq - itop(d)->irq_base; + + ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNCR); +} + +static void +falcon_gpio_mask_and_ack_irq(struct irq_data *d) +{ + unsigned int offset = d->irq - itop(d)->irq_base; + + ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNENCLR); + ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNCR); +} + +static struct irq_chip falcon_gpio_irq_chip; +static int +falcon_gpio_irq_type(struct irq_data *d, unsigned int type) +{ + unsigned int offset = d->irq - itop(d)->irq_base; + unsigned int mask = 1 << offset; + + if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_NONE) + return 0; + + if ((type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) != 0) { + /* level triggered */ + ltq_port_w32_mask(itop(d), 0, mask, LTQ_GPIO_IRNCFG); + irq_set_chip_and_handler_name(d->irq, + &falcon_gpio_irq_chip, handle_level_irq, "mux"); + } else { + /* edge triggered */ + ltq_port_w32_mask(itop(d), mask, 0, LTQ_GPIO_IRNCFG); + irq_set_chip_and_handler_name(d->irq, + &falcon_gpio_irq_chip, handle_simple_irq, "mux"); + } + + if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { + ltq_port_w32_mask(itop(d), mask, 0, LTQ_GPIO_EXINTCR0); + ltq_port_w32_mask(itop(d), 0, mask, LTQ_GPIO_EXINTCR1); + } else { + if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH)) != 0) + /* positive logic: rising edge, high level */ + ltq_port_w32_mask(itop(d), mask, 0, LTQ_GPIO_EXINTCR0); + else + /* negative logic: falling edge, low level */ + ltq_port_w32_mask(itop(d), 0, mask, LTQ_GPIO_EXINTCR0); + ltq_port_w32_mask(itop(d), mask, 0, LTQ_GPIO_EXINTCR1); + } + + return gpio_direction_input(itop(d)->gpio_chip.base + offset); +} + +static void +falcon_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) +{ + struct falcon_gpio_port *gpio_port = irq_desc_get_handler_data(desc); + unsigned long irncr; + int offset; + + /* acknowledge interrupt */ + irncr = ltq_port_r32(gpio_port, LTQ_GPIO_IRNCR); + ltq_port_w32(gpio_port, irncr, LTQ_GPIO_IRNCR); + + desc->irq_data.chip->irq_ack(&desc->irq_data); + + for_each_set_bit(offset, &irncr, gpio_port->gpio_chip.ngpio) + generic_handle_irq(gpio_port->irq_base + offset); +} + +static struct irq_chip falcon_gpio_irq_chip = { + .name = "gpio_irq_mux", + .irq_mask = falcon_gpio_disable_irq, + .irq_unmask = falcon_gpio_enable_irq, + .irq_ack = falcon_gpio_ack_irq, + .irq_mask_ack = falcon_gpio_mask_and_ack_irq, + .irq_set_type = falcon_gpio_irq_type, +}; + +static struct irqaction gpio_cascade = { + .handler = no_action, + .flags = IRQF_DISABLED, + .name = "gpio_cascade", +}; + +static int +falcon_gpio_probe(struct platform_device *pdev) +{ + struct falcon_gpio_port *gpio_port; + int ret, i; + struct resource *gpiores, *padres; + int irq; + + if (pdev->id >= MAX_PORTS) + return -ENODEV; + + gpiores = platform_get_resource(pdev, IORESOURCE_MEM, 0); + padres = platform_get_resource(pdev, IORESOURCE_MEM, 1); + irq = platform_get_irq(pdev, 0); + if (!gpiores || !padres) + return -ENODEV; + + gpio_port = <q_gpio_port[pdev->id]; + gpio_port->gpio_chip.label = "falcon-gpio"; + gpio_port->gpio_chip.direction_input = falcon_gpio_direction_input; + gpio_port->gpio_chip.direction_output = falcon_gpio_direction_output; + gpio_port->gpio_chip.get = falcon_gpio_get; + gpio_port->gpio_chip.set = falcon_gpio_set; + gpio_port->gpio_chip.request = falcon_gpio_request; + gpio_port->gpio_chip.free = falcon_gpio_free; + gpio_port->gpio_chip.base = 100 * pdev->id; + gpio_port->gpio_chip.ngpio = 32; + gpio_port->gpio_chip.dev = &pdev->dev; + + gpio_port->port = ltq_remap_resource(gpiores); + gpio_port->pad = ltq_remap_resource(padres); + + if (!gpio_port->port || !gpio_port->pad) { + dev_err(&pdev->dev, "Could not map io ranges\n"); + ret = -ENOMEM; + goto err; + } + + gpio_port->clk = clk_get(&pdev->dev, NULL); + if (IS_ERR(gpio_port->clk)) { + dev_err(&pdev->dev, "Could not get clock\n"); + ret = PTR_ERR(gpio_port->clk);; + goto err; + } + clk_enable(gpio_port->clk); + + if (irq > 0) { + /* irq_chip support */ + gpio_port->gpio_chip.to_irq = falcon_gpio_to_irq; + gpio_port->irq_base = INT_NUM_EXTRA_START + (32 * pdev->id); + + for (i = 0; i < 32; i++) { + irq_set_chip_and_handler_name(gpio_port->irq_base + i, + &falcon_gpio_irq_chip, handle_simple_irq, + "mux"); + irq_set_chip_data(gpio_port->irq_base + i, gpio_port); + /* set to negative logic (falling edge, low level) */ + ltq_port_w32_mask(gpio_port, 0, 1 << i, + LTQ_GPIO_EXINTCR0); + } + + gpio_port->chained_irq = irq; + setup_irq(irq, &gpio_cascade); + irq_set_handler_data(irq, gpio_port); + irq_set_chained_handler(irq, falcon_gpio_irq_handler); + } + + ret = gpiochip_add(&gpio_port->gpio_chip); + if (ret < 0) { + dev_err(&pdev->dev, "Could not register gpiochip %d, %d\n", + pdev->id, ret); + goto err; + } + platform_set_drvdata(pdev, gpio_port); + return ret; + +err: + dev_err(&pdev->dev, "Error in gpio_probe %d, %d\n", pdev->id, ret); + if (gpiores) + release_resource(gpiores); + if (padres) + release_resource(padres); + + if (gpio_port->port) + iounmap(gpio_port->port); + if (gpio_port->pad) + iounmap(gpio_port->pad); + return ret; +} + +static struct platform_driver falcon_gpio_driver = { + .probe = falcon_gpio_probe, + .driver = { + .name = "falcon_gpio", + .owner = THIS_MODULE, + }, +}; + +int __init +falcon_gpio_init(void) +{ + int ret; + + pr_info("FALC(tm) ON GPIO Driver, (C) 2011 Lantiq Deutschland Gmbh\n"); + ret = platform_driver_register(&falcon_gpio_driver); + if (ret) + pr_err("falcon_gpio: Error registering platform driver!"); + return ret; +} + +postcore_initcall(falcon_gpio_init); diff --git a/target/linux/lantiq/files-3.3/arch/mips/lantiq/falcon/mach-95C3AM1.c b/target/linux/lantiq/files-3.3/arch/mips/lantiq/falcon/mach-95C3AM1.c new file mode 100644 index 000000000..42a3344ae --- /dev/null +++ b/target/linux/lantiq/files-3.3/arch/mips/lantiq/falcon/mach-95C3AM1.c @@ -0,0 +1,94 @@ +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/i2c-gpio.h> + +#include <dev-gpio-leds.h> + +#include "../machtypes.h" +#include "devices.h" + +#define BOARD_95C3AM1_GPIO_LED_0 10 +#define BOARD_95C3AM1_GPIO_LED_1 11 +#define BOARD_95C3AM1_GPIO_LED_2 12 +#define BOARD_95C3AM1_GPIO_LED_3 13 + +static struct mtd_partition board_95C3AM1_partitions[] = +{ + { + .name = "uboot", + .offset = 0x0, + .size = 0x40000, + }, + { + .name = "uboot_env", + .offset = 0x40000, + .size = 0x40000, /* 2 sectors for redundant env. */ + }, + { + .name = "linux", + .offset = 0x80000, + .size = 0xF80000, /* map only 16 MiB */ + }, +}; + +static struct flash_platform_data board_95C3AM1_flash_platform_data = { + .name = "sflash", + .parts = board_95C3AM1_partitions, + .nr_parts = ARRAY_SIZE(board_95C3AM1_partitions) +}; + +static struct spi_board_info board_95C3AM1_flash_data __initdata = { + .modalias = "m25p80", + .bus_num = 0, + .chip_select = 0, + .max_speed_hz = 10 * 1000 * 1000, + .mode = SPI_MODE_3, + .platform_data = &board_95C3AM1_flash_platform_data +}; + +static struct gpio_led board_95C3AM1_gpio_leds[] __initdata = { + { + .name = "power", + .gpio = BOARD_95C3AM1_GPIO_LED_0, + .active_low = 0, + }, { + .name = "optical", + .gpio = BOARD_95C3AM1_GPIO_LED_1, + .active_low = 0, + }, { + .name = "lan", + .gpio = BOARD_95C3AM1_GPIO_LED_2, + .active_low = 0, + }, { + .name = "update", + .gpio = BOARD_95C3AM1_GPIO_LED_3, + .active_low = 0, + } +}; + +static struct i2c_gpio_platform_data board_95C3AM1_i2c_gpio_data = { + .sda_pin = 107, + .scl_pin = 108, +}; + +static struct platform_device board_95C3AM1_i2c_gpio_device = { + .name = "i2c-gpio", + .id = 0, + .dev = { + .platform_data = &board_95C3AM1_i2c_gpio_data, + } +}; + +static void __init board_95C3AM1_init(void) +{ + falcon_register_i2c(); + falcon_register_spi_flash(&board_95C3AM1_flash_data); + platform_device_register(&board_95C3AM1_i2c_gpio_device); + ltq_add_device_gpio_leds(-1, ARRAY_SIZE(board_95C3AM1_gpio_leds), + board_95C3AM1_gpio_leds); +} + +MIPS_MACHINE(LANTIQ_MACH_95C3AM1, + "95C3AM1", + "95C3AM1 Board", + board_95C3AM1_init); diff --git a/target/linux/lantiq/files-3.3/arch/mips/lantiq/falcon/mach-easy98000.c b/target/linux/lantiq/files-3.3/arch/mips/lantiq/falcon/mach-easy98000.c new file mode 100644 index 000000000..fc5720d4e --- /dev/null +++ b/target/linux/lantiq/files-3.3/arch/mips/lantiq/falcon/mach-easy98000.c @@ -0,0 +1,138 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com> + * Copyright (C) 2011 John Crispin <blogic@openwrt.org> + */ + +#include <linux/platform_device.h> +#include <linux/mtd/partitions.h> +#include <linux/spi/spi.h> +#include <linux/spi/spi_gpio.h> +#include <linux/spi/eeprom.h> + +#include "../machtypes.h" + +#include "devices.h" + +static struct mtd_partition easy98000_nor_partitions[] = { + { + .name = "uboot", + .offset = 0x0, + .size = 0x40000, + }, + { + .name = "uboot_env", + .offset = 0x40000, + .size = 0x40000, /* 2 sectors for redundant env. */ + }, + { + .name = "linux", + .offset = 0x80000, + .size = 0xF80000, /* map only 16 MiB */ + }, +}; + +struct physmap_flash_data easy98000_nor_flash_data = { + .nr_parts = ARRAY_SIZE(easy98000_nor_partitions), + .parts = easy98000_nor_partitions, +}; + +static struct flash_platform_data easy98000_spi_flash_platform_data = { + .name = "sflash", + .parts = easy98000_nor_partitions, + .nr_parts = ARRAY_SIZE(easy98000_nor_partitions) +}; + +static struct spi_board_info easy98000_spi_flash_data __initdata = { + .modalias = "m25p80", + .bus_num = 0, + .chip_select = 0, + .max_speed_hz = 10 * 1000 * 1000, + .mode = SPI_MODE_3, + .platform_data = &easy98000_spi_flash_platform_data +}; + +/* setup gpio based spi bus/device for access to the eeprom on the board */ +#define SPI_GPIO_MRST 102 +#define SPI_GPIO_MTSR 103 +#define SPI_GPIO_CLK 104 +#define SPI_GPIO_CS0 105 +#define SPI_GPIO_CS1 106 +#define SPI_GPIO_BUS_NUM 1 + +static struct spi_gpio_platform_data easy98000_spi_gpio_data = { + .sck = SPI_GPIO_CLK, + .mosi = SPI_GPIO_MTSR, + .miso = SPI_GPIO_MRST, + .num_chipselect = 2, +}; + +static struct platform_device easy98000_spi_gpio_device = { + .name = "spi_gpio", + .id = SPI_GPIO_BUS_NUM, + .dev.platform_data = &easy98000_spi_gpio_data, +}; + +static struct spi_eeprom at25160n = { + .byte_len = 16 * 1024 / 8, + .name = "at25160n", + .page_size = 32, + .flags = EE_ADDR2, +}; + +static struct spi_board_info easy98000_spi_gpio_devices __initdata = { + .modalias = "at25", + .bus_num = SPI_GPIO_BUS_NUM, + .max_speed_hz = 1000 * 1000, + .mode = SPI_MODE_3, + .chip_select = 1, + .controller_data = (void *) SPI_GPIO_CS1, + .platform_data = &at25160n, +}; + +static void __init +easy98000_init_common(void) +{ + spi_register_board_info(&easy98000_spi_gpio_devices, 1); + platform_device_register(&easy98000_spi_gpio_device); + falcon_register_i2c(); +} + +static void __init +easy98000_init(void) +{ + easy98000_init_common(); + ltq_register_nor(&easy98000_nor_flash_data); +} + +static void __init +easy98000sf_init(void) +{ + easy98000_init_common(); + falcon_register_spi_flash(&easy98000_spi_flash_data); +} + +static void __init +easy98000nand_init(void) +{ + easy98000_init_common(); + falcon_register_nand(); +} + +MIPS_MACHINE(LANTIQ_MACH_EASY98000, + "EASY98000", + "EASY98000 Eval Board", + easy98000_init); + +MIPS_MACHINE(LANTIQ_MACH_EASY98000SF, + "EASY98000SF", + "EASY98000 Eval Board (Serial Flash)", + easy98000sf_init); + +MIPS_MACHINE(LANTIQ_MACH_EASY98000NAND, + "EASY98000NAND", + "EASY98000 Eval Board (NAND Flash)", + easy98000nand_init); diff --git a/target/linux/lantiq/files-3.3/arch/mips/lantiq/falcon/mach-easy98020.c b/target/linux/lantiq/files-3.3/arch/mips/lantiq/falcon/mach-easy98020.c new file mode 100644 index 000000000..4cdfc199d --- /dev/null +++ b/target/linux/lantiq/files-3.3/arch/mips/lantiq/falcon/mach-easy98020.c @@ -0,0 +1,118 @@ +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/leds.h> +#include <linux/gpio.h> +#include <linux/gpio_buttons.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> +#include <linux/input.h> +#include <linux/interrupt.h> +#include <linux/spi/spi.h> +#include <linux/spi/flash.h> + +#include <dev-gpio-leds.h> + +#include "../machtypes.h" +#include "devices.h" + +#define EASY98020_GPIO_LED_0 9 +#define EASY98020_GPIO_LED_1 10 +#define EASY98020_GPIO_LED_2 11 +#define EASY98020_GPIO_LED_3 12 +#define EASY98020_GPIO_LED_GE0_ACT 110 +#define EASY98020_GPIO_LED_GE0_LINK 109 +#define EASY98020_GPIO_LED_GE1_ACT 106 +#define EASY98020_GPIO_LED_GE1_LINK 105 + +static struct mtd_partition easy98020_spi_partitions[] = +{ + { + .name = "uboot", + .offset = 0x0, + .size = 0x40000, + }, + { + .name = "uboot_env", + .offset = 0x40000, + .size = 0x40000, /* 2 sectors for redundant env. */ + }, + { + .name = "linux", + .offset = 0x80000, + .size = 0xF80000, /* map only 16 MiB */ + }, +}; + +static struct flash_platform_data easy98020_spi_flash_platform_data = { + .name = "sflash", + .parts = easy98020_spi_partitions, + .nr_parts = ARRAY_SIZE(easy98020_spi_partitions) +}; + +static struct spi_board_info easy98020_spi_flash_data __initdata = { + .modalias = "m25p80", + .bus_num = 0, + .chip_select = 0, + .max_speed_hz = 10 * 1000 * 1000, + .mode = SPI_MODE_3, + .platform_data = &easy98020_spi_flash_platform_data +}; + +static struct gpio_led easy98020_gpio_leds[] __initdata = { + { + .name = "easy98020:green:0", + .gpio = EASY98020_GPIO_LED_0, + .active_low = 0, + }, { + .name = "easy98020:green:1", + .gpio = EASY98020_GPIO_LED_1, + .active_low = 0, + }, { + .name = "easy98020:green:2", + .gpio = EASY98020_GPIO_LED_2, + .active_low = 0, + }, { + .name = "easy98020:green:3", + .gpio = EASY98020_GPIO_LED_3, + .active_low = 0, + }, { + .name = "easy98020:ge0_act", + .gpio = EASY98020_GPIO_LED_GE0_ACT, + .active_low = 0, + }, { + .name = "easy98020:ge0_link", + .gpio = EASY98020_GPIO_LED_GE0_LINK, + .active_low = 0, + }, { + .name = "easy98020:ge1_act", + .gpio = EASY98020_GPIO_LED_GE1_ACT, + .active_low = 0, + }, { + .name = "easy98020:ge1_link", + .gpio = EASY98020_GPIO_LED_GE1_LINK, + .active_low = 0, + } +}; + +static void __init easy98020_init(void) +{ + falcon_register_i2c(); + falcon_register_spi_flash(&easy98020_spi_flash_data); + ltq_add_device_gpio_leds(-1, ARRAY_SIZE(easy98020_gpio_leds), + easy98020_gpio_leds); +} + +MIPS_MACHINE(LANTIQ_MACH_EASY98020, + "EASY98020", + "EASY98020 Eval Board", + easy98020_init); + +MIPS_MACHINE(LANTIQ_MACH_EASY98020_1LAN, + "EASY98020_1LAN", + "EASY98020 Eval Board (1 LAN port)", + easy98020_init); + +MIPS_MACHINE(LANTIQ_MACH_EASY98020_2LAN, + "EASY98020_2LAN", + "EASY98020 Eval Board (2 LAN ports)", + easy98020_init); diff --git a/target/linux/lantiq/files-3.3/arch/mips/lantiq/falcon/prom.c b/target/linux/lantiq/files-3.3/arch/mips/lantiq/falcon/prom.c new file mode 100644 index 000000000..2a4eea178 --- /dev/null +++ b/target/linux/lantiq/files-3.3/arch/mips/lantiq/falcon/prom.c @@ -0,0 +1,84 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com> + * Copyright (C) 2011 John Crispin <blogic@openwrt.org> + */ + +#include <lantiq_soc.h> + +#include "devices.h" + +#include "../prom.h" + +#define SOC_FALCON "Falcon" +#define SOC_FALCON_D "Falcon-D" +#define SOC_FALCON_V "Falcon-V" +#define SOC_FALCON_M "Falcon-M" + +#define PART_SHIFT 12 +#define PART_MASK 0x0FFFF000 +#define REV_SHIFT 28 +#define REV_MASK 0xF0000000 +#define SREV_SHIFT 22 +#define SREV_MASK 0x03C00000 +#define TYPE_SHIFT 26 +#define TYPE_MASK 0x3C000000 + +/* this parameter allows us enable/disable asc1 via commandline */ +static int register_asc1; +static int __init +ltq_parse_asc1(char *p) +{ + register_asc1 = 1; + return 0; +} +__setup("use_asc1", ltq_parse_asc1); + +void __init +ltq_soc_setup(void) +{ + ltq_register_asc(0); + ltq_register_wdt(); + falcon_register_gpio(); + if (register_asc1) + ltq_register_asc(1); +} + +void __init +ltq_soc_detect(struct ltq_soc_info *i) +{ + u32 type; + i->partnum = (ltq_r32(LTQ_FALCON_CHIPID) & PART_MASK) >> PART_SHIFT; + i->rev = (ltq_r32(LTQ_FALCON_CHIPID) & REV_MASK) >> REV_SHIFT; + i->srev = ((ltq_r32(LTQ_FALCON_CHIPCONF) & SREV_MASK) >> SREV_SHIFT); + sprintf(i->rev_type, "%c%d%d", (i->srev & 0x4) ? ('B') : ('A'), + i->rev & 0x7, (i->srev & 0x3) + 1); + + switch (i->partnum) { + case SOC_ID_FALCON: + type = (ltq_r32(LTQ_FALCON_CHIPTYPE) & TYPE_MASK) >> TYPE_SHIFT; + switch (type) { + case 0: + i->name = SOC_FALCON_D; + break; + case 1: + i->name = SOC_FALCON_V; + break; + case 2: + i->name = SOC_FALCON_M; + break; + default: + i->name = SOC_FALCON; + break; + } + i->type = SOC_TYPE_FALCON; + break; + + default: + unreachable(); + break; + } +} diff --git a/target/linux/lantiq/files-3.3/arch/mips/lantiq/falcon/reset.c b/target/linux/lantiq/files-3.3/arch/mips/lantiq/falcon/reset.c new file mode 100644 index 000000000..cbcadc5c4 --- /dev/null +++ b/target/linux/lantiq/files-3.3/arch/mips/lantiq/falcon/reset.c @@ -0,0 +1,87 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com> + * Copyright (C) 2011 John Crispin <blogic@openwrt.org> + */ + +#include <linux/init.h> +#include <linux/io.h> +#include <linux/pm.h> +#include <asm/reboot.h> +#include <linux/export.h> + +#include <lantiq_soc.h> + +/* CPU0 Reset Source Register */ +#define LTQ_SYS1_CPU0RS 0x0040 +/* reset cause mask */ +#define LTQ_CPU0RS_MASK 0x0003 + +int +ltq_reset_cause(void) +{ + return ltq_sys1_r32(LTQ_SYS1_CPU0RS) & LTQ_CPU0RS_MASK; +} +EXPORT_SYMBOL_GPL(ltq_reset_cause); + +#define BOOT_REG_BASE (KSEG1 | 0x1F200000) +#define BOOT_PW1_REG (BOOT_REG_BASE | 0x20) +#define BOOT_PW2_REG (BOOT_REG_BASE | 0x24) +#define BOOT_PW1 0x4C545100 +#define BOOT_PW2 0x0051544C + +#define WDT_REG_BASE (KSEG1 | 0x1F8803F0) +#define WDT_PW1 0x00BE0000 +#define WDT_PW2 0x00DC0000 + +static void +ltq_machine_restart(char *command) +{ + pr_notice("System restart\n"); + local_irq_disable(); + + /* reboot magic */ + ltq_w32(BOOT_PW1, (void *)BOOT_PW1_REG); /* 'LTQ\0' */ + ltq_w32(BOOT_PW2, (void *)BOOT_PW2_REG); /* '\0QTL' */ + ltq_w32(0, (void *)BOOT_REG_BASE); /* reset Bootreg RVEC */ + + /* watchdog magic */ + ltq_w32(WDT_PW1, (void *)WDT_REG_BASE); + ltq_w32(WDT_PW2 | + (0x3 << 26) | /* PWL */ + (0x2 << 24) | /* CLKDIV */ + (0x1 << 31) | /* enable */ + (1), /* reload */ + (void *)WDT_REG_BASE); + unreachable(); +} + +static void +ltq_machine_halt(void) +{ + pr_notice("System halted.\n"); + local_irq_disable(); + unreachable(); +} + +static void +ltq_machine_power_off(void) +{ + pr_notice("Please turn off the power now.\n"); + local_irq_disable(); + unreachable(); +} + +static int __init +mips_reboot_setup(void) +{ + _machine_restart = ltq_machine_restart; + _machine_halt = ltq_machine_halt; + pm_power_off = ltq_machine_power_off; + return 0; +} + +arch_initcall(mips_reboot_setup); diff --git a/target/linux/lantiq/files-3.3/arch/mips/lantiq/falcon/sysctrl.c b/target/linux/lantiq/files-3.3/arch/mips/lantiq/falcon/sysctrl.c new file mode 100644 index 000000000..f27d69482 --- /dev/null +++ b/target/linux/lantiq/files-3.3/arch/mips/lantiq/falcon/sysctrl.c @@ -0,0 +1,211 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com> + * Copyright (C) 2011 John Crispin <blogic@openwrt.org> + */ + +#include <linux/ioport.h> +#include <linux/export.h> +#include <linux/clkdev.h> +#include <asm/delay.h> + +#include <lantiq_soc.h> + +#include "devices.h" +#include "../clk.h" + +/* infrastructure control register */ +#define SYS1_INFRAC 0x00bc +/* Configuration fuses for drivers and pll */ +#define STATUS_CONFIG 0x0040 + +/* GPE frequency selection */ +#define GPPC_OFFSET 24 +#define GPEFREQ_MASK 0x00000C0 +#define GPEFREQ_OFFSET 10 +/* Clock status register */ +#define LTQ_SYSCTL_CLKS 0x0000 +/* Clock enable register */ +#define LTQ_SYSCTL_CLKEN 0x0004 +/* Clock clear register */ +#define LTQ_SYSCTL_CLKCLR 0x0008 +/* Activation Status Register */ +#define LTQ_SYSCTL_ACTS 0x0020 +/* Activation Register */ +#define LTQ_SYSCTL_ACT 0x0024 +/* Deactivation Register */ +#define LTQ_SYSCTL_DEACT 0x0028 +/* reboot Register */ +#define LTQ_SYSCTL_RBT 0x002c +/* CPU0 Clock Control Register */ +#define LTQ_SYS1_CPU0CC 0x0040 +/* clock divider bit */ +#define LTQ_CPU0CC_CPUDIV 0x0001 + +static struct resource ltq_sysctl_res[] = { + MEM_RES("sys1", LTQ_SYS1_BASE_ADDR, LTQ_SYS1_SIZE), + MEM_RES("syseth", LTQ_SYS_ETH_BASE_ADDR, LTQ_SYS_ETH_SIZE), + MEM_RES("sysgpe", LTQ_SYS_GPE_BASE_ADDR, LTQ_SYS_GPE_SIZE), +}; + +static struct resource ltq_status_res = + MEM_RES("status", LTQ_STATUS_BASE_ADDR, LTQ_STATUS_SIZE); +static struct resource ltq_ebu_res = + MEM_RES("ebu", LTQ_EBU_BASE_ADDR, LTQ_EBU_SIZE); + +static void __iomem *ltq_sysctl[3]; +static void __iomem *ltq_status_membase; +void __iomem *ltq_sys1_membase; +void __iomem *ltq_ebu_membase; + +#define ltq_reg_w32(m, x, y) ltq_w32((x), ltq_sysctl[m] + (y)) +#define ltq_reg_r32(m, x) ltq_r32(ltq_sysctl[m] + (x)) +#define ltq_reg_w32_mask(m, clear, set, reg) \ + ltq_reg_w32(m, (ltq_reg_r32(m, reg) & ~(clear)) | (set), reg) + +#define ltq_status_w32(x, y) ltq_w32((x), ltq_status_membase + (y)) +#define ltq_status_r32(x) ltq_r32(ltq_status_membase + (x)) + +static inline void +ltq_sysctl_wait(struct clk *clk, + unsigned int test, unsigned int reg) +{ + int err = 1000000; + + do {} while (--err && ((ltq_reg_r32(clk->module, reg) + & clk->bits) != test)); + if (!err) + pr_err("module de/activation failed %d %08X %08X %08X\n", + clk->module, clk->bits, test, + ltq_reg_r32(clk->module, reg) & clk->bits); +} + +static int +ltq_sysctl_activate(struct clk *clk) +{ + ltq_reg_w32(clk->module, clk->bits, LTQ_SYSCTL_CLKEN); + ltq_reg_w32(clk->module, clk->bits, LTQ_SYSCTL_ACT); + ltq_sysctl_wait(clk, clk->bits, LTQ_SYSCTL_ACTS); + return 0; +} + +static void +ltq_sysctl_deactivate(struct clk *clk) +{ + ltq_reg_w32(clk->module, clk->bits, LTQ_SYSCTL_CLKCLR); + ltq_reg_w32(clk->module, clk->bits, LTQ_SYSCTL_DEACT); + ltq_sysctl_wait(clk, 0, LTQ_SYSCTL_ACTS); +} + +static int +ltq_sysctl_clken(struct clk *clk) +{ + ltq_reg_w32(clk->module, clk->bits, LTQ_SYSCTL_CLKEN); + ltq_sysctl_wait(clk, clk->bits, LTQ_SYSCTL_CLKS); + return 0; +} + +static void +ltq_sysctl_clkdis(struct clk *clk) +{ + ltq_reg_w32(clk->module, clk->bits, LTQ_SYSCTL_CLKCLR); + ltq_sysctl_wait(clk, 0, LTQ_SYSCTL_CLKS); +} + +static void +ltq_sysctl_reboot(struct clk *clk) +{ + unsigned int act; + unsigned int bits; + + act = ltq_reg_r32(clk->module, LTQ_SYSCTL_ACT); + bits = ~act & clk->bits; + if (bits != 0) { + ltq_reg_w32(clk->module, bits, LTQ_SYSCTL_CLKEN); + ltq_reg_w32(clk->module, bits, LTQ_SYSCTL_ACT); + ltq_sysctl_wait(clk, bits, LTQ_SYSCTL_ACTS); + } + ltq_reg_w32(clk->module, act & clk->bits, LTQ_SYSCTL_RBT); + ltq_sysctl_wait(clk, clk->bits, LTQ_SYSCTL_ACTS); +} + +/* enable the ONU core */ +static void +ltq_gpe_enable(void) +{ + unsigned int freq; + unsigned int status; + + /* if if the clock is already enabled */ + status = ltq_reg_r32(SYSCTL_SYS1, SYS1_INFRAC); + if (status & (1 << (GPPC_OFFSET + 1))) + return; + + if (ltq_status_r32(STATUS_CONFIG) == 0) + freq = 1; /* use 625MHz on unfused chip */ + else + freq = (ltq_status_r32(STATUS_CONFIG) & + GPEFREQ_MASK) >> + GPEFREQ_OFFSET; + + /* apply new frequency */ + ltq_reg_w32_mask(SYSCTL_SYS1, 7 << (GPPC_OFFSET + 1), + freq << (GPPC_OFFSET + 2) , SYS1_INFRAC); + udelay(1); + + /* enable new frequency */ + ltq_reg_w32_mask(SYSCTL_SYS1, 0, 1 << (GPPC_OFFSET + 1), SYS1_INFRAC); + udelay(1); +} + +static inline void +clkdev_add_sys(const char *dev, unsigned int module, + unsigned int bits) +{ + struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); + + clk->cl.dev_id = dev; + clk->cl.con_id = NULL; + clk->cl.clk = clk; + clk->module = module; + clk->bits = bits; + clk->activate = ltq_sysctl_activate; + clk->deactivate = ltq_sysctl_deactivate; + clk->enable = ltq_sysctl_clken; + clk->disable = ltq_sysctl_clkdis; + clk->reboot = ltq_sysctl_reboot; + clkdev_add(&clk->cl); +} + +void __init +ltq_soc_init(void) +{ + int i; + + for (i = 0; i < 3; i++) + ltq_sysctl[i] = ltq_remap_resource(<q_sysctl_res[i]); + + ltq_sys1_membase = ltq_sysctl[0]; + ltq_status_membase = ltq_remap_resource(<q_status_res); + ltq_ebu_membase = ltq_remap_resource(<q_ebu_res); + + ltq_gpe_enable(); + + /* get our 3 static rates for cpu, fpi and io clocks */ + if (ltq_sys1_r32(LTQ_SYS1_CPU0CC) & LTQ_CPU0CC_CPUDIV) + clkdev_add_static(CLOCK_200M, CLOCK_100M, CLOCK_200M); + else + clkdev_add_static(CLOCK_400M, CLOCK_100M, CLOCK_200M); + + /* add our clock domains */ + clkdev_add_sys("falcon_gpio.0", SYSCTL_SYSETH, ACTS_PADCTRL0 | ACTS_P0); + clkdev_add_sys("falcon_gpio.1", SYSCTL_SYS1, ACTS_PADCTRL1 | ACTS_P1); + clkdev_add_sys("falcon_gpio.2", SYSCTL_SYSETH, ACTS_PADCTRL2 | ACTS_P2); + clkdev_add_sys("falcon_gpio.3", SYSCTL_SYS1, ACTS_PADCTRL3 | ACTS_P3); + clkdev_add_sys("falcon_gpio.4", SYSCTL_SYS1, ACTS_PADCTRL4 | ACTS_P4); + clkdev_add_sys("ltq_asc.1", SYSCTL_SYS1, ACTS_ASC1_ACT); + clkdev_add_sys("i2c-falcon.0", SYSCTL_SYS1, ACTS_I2C_ACT); +} diff --git a/target/linux/lantiq/files-3.3/arch/mips/lantiq/svip/Kconfig b/target/linux/lantiq/files-3.3/arch/mips/lantiq/svip/Kconfig new file mode 100644 index 000000000..f351a189a --- /dev/null +++ b/target/linux/lantiq/files-3.3/arch/mips/lantiq/svip/Kconfig @@ -0,0 +1,16 @@ +if SOC_SVIP + +menu "Mips Machine" + +config LANTIQ_MACH_EASY33016 + bool "Easy33016" + default y + +config LANTIQ_MACH_EASY336 + select SYS_SUPPORTS_LITTLE_ENDIAN + bool "Easy336" + default y + +endmenu + +endif diff --git a/target/linux/lantiq/files-3.3/arch/mips/lantiq/svip/Makefile b/target/linux/lantiq/files-3.3/arch/mips/lantiq/svip/Makefile new file mode 100644 index 000000000..405d65219 --- /dev/null +++ b/target/linux/lantiq/files-3.3/arch/mips/lantiq/svip/Makefile @@ -0,0 +1,3 @@ +obj-y := devices.o prom.o reset.o clk-svip.o gpio.o dma.o switchip_setup.o pms.o mux.o +obj-$(CONFIG_LANTIQ_MACH_EASY33016) += mach-easy33016.o +obj-$(CONFIG_LANTIQ_MACH_EASY336) += mach-easy336.o diff --git a/target/linux/lantiq/files-3.3/arch/mips/lantiq/svip/clk-svip.c b/target/linux/lantiq/files-3.3/arch/mips/lantiq/svip/clk-svip.c new file mode 100644 index 000000000..4a14df509 --- /dev/null +++ b/target/linux/lantiq/files-3.3/arch/mips/lantiq/svip/clk-svip.c @@ -0,0 +1,100 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * Copyright (C) 2010 John Crispin <blogic@openwrt.org> + */ + +#include <linux/io.h> +#include <linux/module.h> +#include <linux/init.h> +#include <linux/time.h> + +#include <asm/irq.h> +#include <asm/div64.h> + +#include <lantiq_soc.h> +#include <base_reg.h> +#include <sys0_reg.h> +#include <sys1_reg.h> +#include <status_reg.h> + +static struct svip_reg_status *const status = +(struct svip_reg_status *)LTQ_STATUS_BASE; +static struct svip_reg_sys0 *const sys0 = (struct svip_reg_sys0 *)LTQ_SYS0_BASE; +static struct svip_reg_sys1 *const sys1 = (struct svip_reg_sys1 *)LTQ_SYS1_BASE; + +unsigned int ltq_svip_io_region_clock(void) +{ + return 200000000; /* 200 MHz */ +} +EXPORT_SYMBOL(ltq_svip_io_region_clock); + +unsigned int ltq_svip_cpu_hz(void) +{ + /* Magic BootROM speed location... */ + if ((*(u32 *)0x9fc07ff0) == 1) + return *(u32 *)0x9fc07ff4; + + if (STATUS_CONFIG_CLK_MODE_GET(status_r32(config)) == 1) { + /* xT16 */ + return 393216000; + } else { + switch (SYS0_PLL1CR_PLLDIV_GET(sys0_r32(pll1cr))) { + case 3: + return 475000000; + case 2: + return 450000000; + case 1: + return 425000000; + default: + return 400000000; + } + } +} +EXPORT_SYMBOL(ltq_svip_cpu_hz); + +unsigned int ltq_svip_fpi_hz(void) +{ + u32 fbs0_div[2] = {4, 8}; + u32 div; + + div = SYS1_FPICR_FPIDIV_GET(sys1_r32(fpicr)); + return ltq_svip_cpu_hz()/fbs0_div[div]; +} +EXPORT_SYMBOL(ltq_svip_fpi_hz); + +unsigned int ltq_get_ppl_hz(void) +{ + /* Magic BootROM speed location... */ + if ((*(u32 *)0x9fc07ff0) == 1) + return *(u32 *)0x9fc07ff4; + + if (STATUS_CONFIG_CLK_MODE_GET(status_r32(config)) == 1) { + /* xT16 */ + return 393216000; + } else { + switch (SYS0_PLL1CR_PLLDIV_GET(sys0_r32(pll1cr))) { + case 3: + return 475000000; + case 2: + return 450000000; + case 1: + return 425000000; + default: + return 400000000; + } + } +} + +unsigned int ltq_get_fbs0_hz(void) +{ + u32 fbs0_div[2] = {4, 8}; + u32 div; + + div = SYS1_FPICR_FPIDIV_GET(sys1_r32(fpicr)); + return ltq_get_ppl_hz()/fbs0_div[div]; +} +EXPORT_SYMBOL(ltq_get_fbs0_hz); diff --git a/target/linux/lantiq/files-3.3/arch/mips/lantiq/svip/devices.c b/target/linux/lantiq/files-3.3/arch/mips/lantiq/svip/devices.c new file mode 100644 index 000000000..735b9419f --- /dev/null +++ b/target/linux/lantiq/files-3.3/arch/mips/lantiq/svip/devices.c @@ -0,0 +1,380 @@ +#include <linux/init.h> +#include <linux/module.h> +#include <linux/types.h> +#include <linux/string.h> +#include <linux/mtd/physmap.h> +#include <linux/kernel.h> +#include <linux/reboot.h> +#include <linux/platform_device.h> +#include <linux/leds.h> +#include <linux/etherdevice.h> +#include <linux/reboot.h> +#include <linux/time.h> +#include <linux/io.h> +#include <linux/gpio.h> +#include <linux/leds.h> +#include <linux/spi/spi.h> +#include <linux/mtd/nand.h> + +#include <asm/bootinfo.h> +#include <asm/irq.h> + +#include <lantiq.h> + +#include <base_reg.h> +#include <sys1_reg.h> +#include <sys2_reg.h> +#include <ebu_reg.h> + +#include "devices.h" + +#include <lantiq_soc.h> +#include <svip_mux.h> +#include <svip_pms.h> + +/* ASC */ +void __init svip_register_asc(int port) +{ + switch (port) { + case 0: + ltq_register_asc(0); + svip_sys1_clk_enable(SYS1_CLKENR_ASC0); + break; + case 1: + ltq_register_asc(1); + svip_sys1_clk_enable(SYS1_CLKENR_ASC1); + break; + default: + break; + }; +} + +/* Ethernet */ +static unsigned char svip_ethaddr[6] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; + +static struct platform_device ltq_mii = { + .name = "ifxmips_mii0", + .dev = { + .platform_data = svip_ethaddr, + }, +}; + +static int __init svip_set_ethaddr(char *str) +{ + sscanf(str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx", + &svip_ethaddr[0], &svip_ethaddr[1], &svip_ethaddr[2], + &svip_ethaddr[3], &svip_ethaddr[4], &svip_ethaddr[5]); + return 0; +} +__setup("ethaddr=", svip_set_ethaddr); + +void __init svip_register_eth(void) +{ + if (!is_valid_ether_addr(svip_ethaddr)) + random_ether_addr(svip_ethaddr); + + platform_device_register(<q_mii); + svip_sys1_clk_enable(SYS1_CLKENR_ETHSW); +} + +/* Virtual Ethernet */ +static struct platform_device ltq_ve = { + .name = "ifxmips_svip_ve", +}; + +void __init svip_register_virtual_eth(void) +{ + platform_device_register(<q_ve); +} + +/* SPI */ +static void __init ltq_register_ssc(int bus_num, unsigned long base, int irq_rx, + int irq_tx, int irq_err, int irq_frm) +{ + struct resource res[] = { + { + .name = "regs", + .start = base, + .end = base + 0x20 - 1, + .flags = IORESOURCE_MEM, + }, { + .name = "rx", + .start = irq_rx, + .flags = IORESOURCE_IRQ, + }, { + .name = "tx", + .start = irq_tx, + .flags = IORESOURCE_IRQ, + }, { + .name = "err", + .start = irq_err, + .flags = IORESOURCE_IRQ, + }, { + .name = "frm", + .start = irq_frm, + .flags = IORESOURCE_IRQ, + }, + }; + + platform_device_register_simple("ifx_ssc", bus_num, res, + ARRAY_SIZE(res)); +} + +static struct spi_board_info bdinfo[] __initdata = { + { + .modalias = "xt16", + .mode = SPI_MODE_3, + .irq = INT_NUM_IM5_IRL0 + 28, + .max_speed_hz = 1000000, + .bus_num = 0, + .chip_select = 1, + }, + { + .modalias = "xt16", + .mode = SPI_MODE_3, + .irq = INT_NUM_IM5_IRL0 + 19, + .max_speed_hz = 1000000, + .bus_num = 0, + .chip_select = 2, + }, + { + .modalias = "loop", + .mode = SPI_MODE_0 | SPI_LOOP, + .irq = -1, + .max_speed_hz = 10000000, + .bus_num = 0, + .chip_select = 3, + }, +}; + +void __init svip_register_spi(void) +{ + + ltq_register_ssc(0, LTQ_SSC0_BASE, INT_NUM_IM1_IRL0 + 6, + INT_NUM_IM1_IRL0 + 7, INT_NUM_IM1_IRL0 + 8, + INT_NUM_IM1_IRL0 + 9); + + ltq_register_ssc(1, LTQ_SSC1_BASE, INT_NUM_IM1_IRL0 + 10, + INT_NUM_IM1_IRL0 + 11, INT_NUM_IM1_IRL0 + 12, + INT_NUM_IM1_IRL0 + 13); + + spi_register_board_info(bdinfo, ARRAY_SIZE(bdinfo)); + + svip_sys1_clk_enable(SYS1_CLKENR_SSC0 | SYS1_CLKENR_SSC1); +} + +void __init svip_register_spi_flash(struct spi_board_info *bdinfo) +{ + spi_register_board_info(bdinfo, 1); +} + +/* GPIO */ +static struct platform_device ltq_gpio = { + .name = "ifxmips_gpio", +}; + +void __init svip_register_gpio(void) +{ + platform_device_register(<q_gpio); +} + +/* MUX */ +static struct ltq_mux_settings ltq_mux_settings; + +static struct platform_device ltq_mux = { + .name = "ltq_mux", + .dev = { + .platform_data = <q_mux_settings, + } +}; + +void __init svip_register_mux(const struct ltq_mux_pin mux_p0[LTQ_MUX_P0_PINS], + const struct ltq_mux_pin mux_p1[LTQ_MUX_P1_PINS], + const struct ltq_mux_pin mux_p2[LTQ_MUX_P2_PINS], + const struct ltq_mux_pin mux_p3[LTQ_MUX_P3_PINS], + const struct ltq_mux_pin mux_p4[LTQ_MUX_P4_PINS]) +{ + ltq_mux_settings.mux_p0 = mux_p0; + ltq_mux_settings.mux_p1 = mux_p1; + ltq_mux_settings.mux_p2 = mux_p2; + ltq_mux_settings.mux_p3 = mux_p3; + ltq_mux_settings.mux_p4 = mux_p4; + + if (mux_p0) + svip_sys1_clk_enable(SYS1_CLKENR_PORT0); + + if (mux_p1) + svip_sys1_clk_enable(SYS1_CLKENR_PORT1); + + if (mux_p2) + svip_sys1_clk_enable(SYS1_CLKENR_PORT2); + + if (mux_p3) + svip_sys1_clk_enable(SYS1_CLKENR_PORT3); + + if (mux_p4) + svip_sys2_clk_enable(SYS2_CLKENR_PORT4); + + platform_device_register(<q_mux); +} + +/* NAND */ +#define NAND_ADDR_REGION_BASE (LTQ_EBU_SEG1_BASE) +#define NAND_CLE_BIT (1 << 3) +#define NAND_ALE_BIT (1 << 2) + +static struct svip_reg_ebu *const ebu = (struct svip_reg_ebu *)LTQ_EBU_BASE; + +static int svip_nand_probe(struct platform_device *pdev) +{ + ebu_w32(LTQ_EBU_ADDR_SEL_0_BASE_VAL(CPHYSADDR(NAND_ADDR_REGION_BASE) + >> 12) + | LTQ_EBU_ADDR_SEL_0_MASK_VAL(15) + | LTQ_EBU_ADDR_SEL_0_MRME_VAL(0) + | LTQ_EBU_ADDR_SEL_0_REGEN_VAL(1), + addr_sel_0); + + ebu_w32(LTQ_EBU_CON_0_WRDIS_VAL(0) + | LTQ_EBU_CON_0_ADSWP_VAL(1) + | LTQ_EBU_CON_0_AGEN_VAL(0x00) + | LTQ_EBU_CON_0_SETUP_VAL(1) + | LTQ_EBU_CON_0_WAIT_VAL(0x00) + | LTQ_EBU_CON_0_WINV_VAL(0) + | LTQ_EBU_CON_0_PW_VAL(0x00) + | LTQ_EBU_CON_0_ALEC_VAL(0) + | LTQ_EBU_CON_0_BCGEN_VAL(0x01) + | LTQ_EBU_CON_0_WAITWRC_VAL(1) + | LTQ_EBU_CON_0_WAITRDC_VAL(1) + | LTQ_EBU_CON_0_HOLDC_VAL(1) + | LTQ_EBU_CON_0_RECOVC_VAL(0) + | LTQ_EBU_CON_0_CMULT_VAL(0x01), + con_0); + + /* + * ECC disabled + * CLE, ALE and CS are pulse, all other signal are latches based + * CLE and ALE are active high, PRE, WP, SE and CS/CE are active low + * OUT_CS_S is disabled + * NAND mode is disabled + */ + ebu_w32(LTQ_EBU_NAND_CON_ECC_ON_VAL(0) + | LTQ_EBU_NAND_CON_LAT_EN_VAL(0x38) + | LTQ_EBU_NAND_CON_OUT_CS_S_VAL(0) + | LTQ_EBU_NAND_CON_IN_CS_S_VAL(0) + | LTQ_EBU_NAND_CON_PRE_P_VAL(1) + | LTQ_EBU_NAND_CON_WP_P_VAL(1) + | LTQ_EBU_NAND_CON_SE_P_VAL(1) + | LTQ_EBU_NAND_CON_CS_P_VAL(1) + | LTQ_EBU_NAND_CON_CLE_P_VAL(0) + | LTQ_EBU_NAND_CON_ALE_P_VAL(0) + | LTQ_EBU_NAND_CON_CSMUX_E_VAL(0) + | LTQ_EBU_NAND_CON_NANDMODE_VAL(0), + nand_con); + + return 0; +} + +static void svip_nand_hwcontrol(struct mtd_info *mtd, int cmd, + unsigned int ctrl) +{ + struct nand_chip *this = mtd->priv; + + if (ctrl & NAND_CTRL_CHANGE) { + unsigned long adr; + /* Coming here means to change either the enable state or + * the address for controlling ALE or CLE */ + + /* NAND_NCE: Select the chip by setting nCE to low. + * This is done in CON register */ + if (ctrl & NAND_NCE) + ebu_w32_mask(0, LTQ_EBU_NAND_CON_NANDMODE_VAL(1), + nand_con); + else + ebu_w32_mask(LTQ_EBU_NAND_CON_NANDMODE_VAL(1), + 0, nand_con); + + /* The addressing of CLE or ALE is done via different addresses. + We are now changing the address depending on the given action + SVIPs NAND_CLE_BIT = (1 << 3), NAND_CLE = 0x02 + NAND_ALE_BIT = (1 << 2) = NAND_ALE (0x04) */ + adr = (unsigned long)this->IO_ADDR_W; + adr &= ~(NAND_CLE_BIT | NAND_ALE_BIT); + adr |= (ctrl & NAND_CLE) << 2 | (ctrl & NAND_ALE); + this->IO_ADDR_W = (void __iomem *)adr; + } + + if (cmd != NAND_CMD_NONE) + writeb(cmd, this->IO_ADDR_W); +} + +static int svip_nand_ready(struct mtd_info *mtd) +{ + return (ebu_r32(nand_wait) & 0x01) == 0x01; +} + +static inline void svip_nand_wait(void) +{ + static const int nops = 150; + int i; + + for (i = 0; i < nops; i++) + asm("nop"); +} + +static void svip_nand_write_buf(struct mtd_info *mtd, + const u_char *buf, int len) +{ + int i; + struct nand_chip *this = mtd->priv; + + for (i = 0; i < len; i++) { + writeb(buf[i], this->IO_ADDR_W); + svip_nand_wait(); + } +} + +static void svip_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) +{ + int i; + struct nand_chip *this = mtd->priv; + + for (i = 0; i < len; i++) { + buf[i] = readb(this->IO_ADDR_R); + svip_nand_wait(); + } +} + +static const char *part_probes[] = { "cmdlinepart", NULL }; + +static struct platform_nand_data svip_flash_nand_data = { + .chip = { + .nr_chips = 1, + .part_probe_types = part_probes, + }, + .ctrl = { + .probe = svip_nand_probe, + .cmd_ctrl = svip_nand_hwcontrol, + .dev_ready = svip_nand_ready, + .write_buf = svip_nand_write_buf, + .read_buf = svip_nand_read_buf, + } +}; + +static struct resource svip_nand_resources[] = { + MEM_RES("nand", LTQ_FLASH_START, LTQ_FLASH_MAX), +}; + +static struct platform_device svip_flash_nand = { + .name = "gen_nand", + .id = -1, + .num_resources = ARRAY_SIZE(svip_nand_resources), + .resource = svip_nand_resources, + .dev = { + .platform_data = &svip_flash_nand_data, + }, +}; + +void __init svip_register_nand(void) +{ + platform_device_register(&svip_flash_nand); +} diff --git a/target/linux/lantiq/files-3.3/arch/mips/lantiq/svip/devices.h b/target/linux/lantiq/files-3.3/arch/mips/lantiq/svip/devices.h new file mode 100644 index 000000000..a064e67ec --- /dev/null +++ b/target/linux/lantiq/files-3.3/arch/mips/lantiq/svip/devices.h @@ -0,0 +1,23 @@ +#ifndef _SVIP_DEVICES_H__ +#define _SVIP_DEVICES_H__ + +#include <linux/mtd/physmap.h> +#include <linux/spi/spi.h> +#include <linux/spi/flash.h> +#include <svip_mux.h> +#include "../devices.h" + +extern void __init svip_register_asc(int port); +extern void __init svip_register_eth(void); +extern void __init svip_register_virtual_eth(void); +extern void __init svip_register_spi(void); +extern void __init svip_register_spi_flash(struct spi_board_info *bdinfo); +extern void __init svip_register_gpio(void); +extern void __init svip_register_mux(const struct ltq_mux_pin mux_p0[LTQ_MUX_P0_PINS], + const struct ltq_mux_pin mux_p1[LTQ_MUX_P1_PINS], + const struct ltq_mux_pin mux_p2[LTQ_MUX_P2_PINS], + const struct ltq_mux_pin mux_p3[LTQ_MUX_P3_PINS], + const struct ltq_mux_pin mux_p4[LTQ_MUX_P4_PINS]); +extern void __init svip_register_nand(void); + +#endif diff --git a/target/linux/lantiq/files-3.3/arch/mips/lantiq/svip/dma.c b/target/linux/lantiq/files-3.3/arch/mips/lantiq/svip/dma.c new file mode 100644 index 000000000..7464be1bd --- /dev/null +++ b/target/linux/lantiq/files-3.3/arch/mips/lantiq/svip/dma.c @@ -0,0 +1,1206 @@ +/* + ** Copyright (C) 2005 Wu Qi Ming <Qi-Ming.Wu@infineon.com> + ** + ** This program is free software; you can redistribute it and/or modify + ** it under the terms of the GNU General Public License as published by + ** the Free Software Foundation; either version 2 of the License, or + ** (at your option) any later version. + ** + ** This program is distributed in the hope that it will be useful, + ** but WITHOUT ANY WARRANTY; without even the implied warranty of + ** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + ** GNU General Public License for more details. + ** + ** You should have received a copy of the GNU General Public License + ** along with this program; if not, write to the Free Software + ** Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ +/* + * Description: + * Driver for SVIP DMA + * Author: Wu Qi Ming[Qi-Ming.Wu@infineon.com] + * Created: 26-September-2005 + */ + +#include <linux/module.h> +#include <linux/init.h> +#include <linux/sched.h> +#include <linux/kernel.h> +#include <linux/slab.h> +#include <linux/string.h> +#include <linux/timer.h> +#include <linux/fs.h> +#include <linux/errno.h> +#include <linux/proc_fs.h> +#include <linux/stat.h> +#include <linux/mm.h> +#include <linux/tty.h> +#include <linux/selection.h> +#include <linux/kmod.h> +#include <linux/vmalloc.h> +#include <linux/interrupt.h> +#include <linux/delay.h> +#include <linux/errno.h> +#include <linux/uaccess.h> +#include <linux/io.h> +#include <linux/semaphore.h> + +#include <base_reg.h> +#include <mps_reg.h> +#include <dma_reg.h> +#include <svip_dma.h> +#include <lantiq_soc.h> +#include <irq.h> +#include <sys1_reg.h> + +static struct svip_reg_sys1 *const sys1 = (struct svip_reg_sys1 *)LTQ_SYS1_BASE; +static struct svip_reg_dma *const dma = (struct svip_reg_dma *)LTQ_DMA_BASE; +static struct svip_reg_mbs *const mbs = (struct svip_reg_mbs *)LTQ_MBS_BASE; + +#define DRV_NAME "ltq_dma" +extern void ltq_mask_and_ack_irq(struct irq_data *data); +extern void ltq_enable_irq(struct irq_data *data); + +static inline void mask_and_ack_irq(unsigned int irq_nr) +{ + static int i = 0; + struct irq_data data; + data.irq = irq_nr; + if ((i < 2) && (irq_nr == 137)) { + printk("eth delay hack\n"); + i++; + } + ltq_mask_and_ack_irq(&data); +} + +static inline void svip_enable_irq(unsigned int irq_nr) +{ + struct irq_data data; + data.irq = irq_nr; + ltq_enable_irq(&data); +} + +#define DMA_EMSG(fmt, args...) \ + printk(KERN_ERR "%s: " fmt, __func__, ## args) + +static inline void mbs_grab(void) +{ + while (mbs_r32(mbsr0) != 0); +} + +static inline void mbs_release(void) +{ + mbs_w32(0, mbsr0); + asm("sync"); +} + +/* max ports connecting to dma */ +#define LTQ_MAX_DMA_DEVICE_NUM ARRAY_SIZE(dma_devices) +/* max dma channels */ +#define LTQ_MAX_DMA_CHANNEL_NUM ARRAY_SIZE(dma_chan) + +/* bytes per descriptor */ +#define DMA_DESCR_SIZE 8 + +#define DMA_DESCR_CH_SIZE (DMA_DESCR_NUM * DMA_DESCR_SIZE) +#define DMA_DESCR_TOTAL_SIZE (LTQ_MAX_DMA_CHANNEL_NUM * DMA_DESCR_CH_SIZE) +#define DMA_DESCR_MEM_PAGES ((DMA_DESCR_TOTAL_SIZE / PAGE_SIZE) + \ + (((DMA_DESCR_TOTAL_SIZE % PAGE_SIZE) > 0))) + +/* budget for interrupt handling */ +#define DMA_INT_BUDGET 100 +/* set the correct counter value here! */ +#define DMA_POLL_COUNTER 32 + +struct proc_dir_entry *g_dma_dir; + +/* device_name | max_rx_chan_num | max_tx_chan_num | drop_enable */ +struct dma_device_info dma_devices[] = { + { "SW", 4, 4, 0 }, + { "DEU", 1, 1, 0 }, + { "SSC0", 1, 1, 0 }, + { "SSC1", 1, 1, 0 }, + { "MCTRL", 1, 1, 0 }, + { "PCM0", 1, 1, 0 }, + { "PCM1", 1, 1, 0 }, + { "PCM2", 1, 1, 0 }, + { "PCM3", 1, 1, 0 } +}; + +/* *dma_dev | dir | pri | irq | rel_chan_no */ +struct dma_channel_info dma_chan[] = { + { &dma_devices[0], DIR_RX, 0, INT_NUM_IM4_IRL0 + 0, 0 }, + { &dma_devices[0], DIR_TX, 0, INT_NUM_IM4_IRL0 + 1, 0 }, + { &dma_devices[0], DIR_RX, 1, INT_NUM_IM4_IRL0 + 2, 1 }, + { &dma_devices[0], DIR_TX, 1, INT_NUM_IM4_IRL0 + 3, 1 }, + { &dma_devices[0], DIR_RX, 2, INT_NUM_IM4_IRL0 + 4, 2 }, + { &dma_devices[0], DIR_TX, 2, INT_NUM_IM4_IRL0 + 5, 2 }, + { &dma_devices[0], DIR_RX, 3, INT_NUM_IM4_IRL0 + 6, 3 }, + { &dma_devices[0], DIR_TX, 3, INT_NUM_IM4_IRL0 + 7, 3 }, + { &dma_devices[1], DIR_RX, 0, INT_NUM_IM4_IRL0 + 8, 0 }, + { &dma_devices[1], DIR_TX, 0, INT_NUM_IM4_IRL0 + 9, 0 }, + { &dma_devices[2], DIR_RX, 0, INT_NUM_IM4_IRL0 + 10, 0 }, + { &dma_devices[2], DIR_TX, 0, INT_NUM_IM4_IRL0 + 11, 0 }, + { &dma_devices[3], DIR_RX, 0, INT_NUM_IM4_IRL0 + 12, 0 }, + { &dma_devices[3], DIR_TX, 0, INT_NUM_IM4_IRL0 + 13, 0 }, + { &dma_devices[4], DIR_RX, 0, INT_NUM_IM4_IRL0 + 14, 0 }, + { &dma_devices[4], DIR_TX, 0, INT_NUM_IM4_IRL0 + 15, 0 }, + { &dma_devices[5], DIR_RX, 0, INT_NUM_IM4_IRL0 + 16, 0 }, + { &dma_devices[5], DIR_TX, 0, INT_NUM_IM4_IRL0 + 17, 0 }, + { &dma_devices[6], DIR_RX, 1, INT_NUM_IM3_IRL0 + 18, 0 }, + { &dma_devices[6], DIR_TX, 1, INT_NUM_IM3_IRL0 + 19, 0 }, + { &dma_devices[7], DIR_RX, 2, INT_NUM_IM4_IRL0 + 20, 0 }, + { &dma_devices[7], DIR_TX, 2, INT_NUM_IM4_IRL0 + 21, 0 }, + { &dma_devices[8], DIR_RX, 3, INT_NUM_IM4_IRL0 + 22, 0 }, + { &dma_devices[8], DIR_TX, 3, INT_NUM_IM4_IRL0 + 23, 0 } +}; + +u64 *g_desc_list[DMA_DESCR_MEM_PAGES]; + +volatile u32 g_dma_int_status = 0; + +/* 0 - not in process, 1 - in process */ +volatile int g_dma_in_process; + +int ltq_dma_init(void); +void do_dma_tasklet(unsigned long); +DECLARE_TASKLET(dma_tasklet, do_dma_tasklet, 0); +irqreturn_t dma_interrupt(int irq, void *dev_id); + +u8 *common_buffer_alloc(int len, int *byte_offset, void **opt) +{ + u8 *buffer = kmalloc(len * sizeof(u8), GFP_KERNEL); + *byte_offset = 0; + return buffer; +} + +void common_buffer_free(u8 *dataptr, void *opt) +{ + kfree(dataptr); +} + +void enable_ch_irq(struct dma_channel_info *ch) +{ + int chan_no = (int)(ch - dma_chan); + unsigned long flag; + u32 val; + + if (ch->dir == DIR_RX) + val = DMA_CIE_DESCPT | DMA_CIE_DUR; + else + val = DMA_CIE_DESCPT; + + local_irq_save(flag); + mbs_grab(); + dma_w32(chan_no, cs); + dma_w32(val, cie); + dma_w32_mask(0, 1 << chan_no, irnen); + mbs_release(); + local_irq_restore(flag); + + svip_enable_irq(ch->irq); +} + +void disable_ch_irq(struct dma_channel_info *ch) +{ + unsigned long flag; + int chan_no = (int)(ch - dma_chan); + + local_irq_save(flag); + g_dma_int_status &= ~(1 << chan_no); + mbs_grab(); + dma_w32(chan_no, cs); + dma_w32(0, cie); + mbs_release(); + dma_w32_mask(1 << chan_no, 0, irnen); + local_irq_restore(flag); + + mask_and_ack_irq(ch->irq); +} + +int open_chan(struct dma_channel_info *ch) +{ + unsigned long flag; + int j; + int chan_no = (int)(ch - dma_chan); + u8 *buffer; + int byte_offset; + struct rx_desc *rx_desc_p; + struct tx_desc *tx_desc_p; + + if (ch->control == LTQ_DMA_CH_ON) + return -1; + + if (ch->dir == DIR_RX) { + for (j = 0; j < ch->desc_len; j++) { + rx_desc_p = (struct rx_desc *)ch->desc_base+j; + buffer = ch->dma_dev->buffer_alloc(ch->packet_size, + &byte_offset, + (void *)&ch->opt[j]); + if (!buffer) + return -ENOBUFS; + + rx_desc_p->data_pointer = (u32)CPHYSADDR((u32)buffer); + rx_desc_p->status.word = 0; + rx_desc_p->status.field.byte_offset = byte_offset; + rx_desc_p->status.field.data_length = ch->packet_size; + rx_desc_p->status.field.own = DMA_OWN; + } + } else { + for (j = 0; j < ch->desc_len; j++) { + tx_desc_p = (struct tx_desc *)ch->desc_base + j; + tx_desc_p->data_pointer = 0; + tx_desc_p->status.word = 0; + } + } + ch->xfer_cnt = 0; + + local_irq_save(flag); + mbs_grab(); + dma_w32(chan_no, cs); + dma_w32(ch->desc_len, cdlen); + dma_w32(0x7e, cis); + dma_w32(DMA_CCTRL_TXWGT_VAL(ch->tx_weight) + | DMA_CCTRL_CLASS_VAL(ch->pri) + | (ch->dir == DIR_RX ? DMA_CCTRL_ON_OFF : 0), cctrl); + mbs_release(); + ch->control = LTQ_DMA_CH_ON; + local_irq_restore(flag); + + if (request_irq(ch->irq, dma_interrupt, + IRQF_DISABLED, "dma-core", (void *)ch) != 0) { + printk(KERN_ERR "error, cannot get dma_irq!\n"); + return -EFAULT; + } + + enable_ch_irq(ch); + return 0; +} + +int close_chan(struct dma_channel_info *ch) +{ + unsigned long flag; + int j; + int chan_no = (int)(ch - dma_chan); + struct rx_desc *desc_p; + + if (ch->control == LTQ_DMA_CH_OFF) + return -1; + + local_irq_save(flag); + mbs_grab(); + dma_w32(chan_no, cs); + dma_w32_mask(DMA_CCTRL_ON_OFF, 0, cctrl); + mbs_release(); + disable_ch_irq(ch); + free_irq(ch->irq, (void *)ch); + ch->control = LTQ_DMA_CH_OFF; + local_irq_restore(flag); + + /* free descriptors in use */ + for (j = 0; j < ch->desc_len; j++) { + desc_p = (struct rx_desc *)ch->desc_base+j; + if ((desc_p->status.field.own == CPU_OWN && + desc_p->status.field.c) || + (desc_p->status.field.own == DMA_OWN)) { + if (desc_p->data_pointer) { + ch->dma_dev->buffer_free((u8 *)__va(desc_p->data_pointer), + (void *)ch->opt[j]); + desc_p->data_pointer = (u32)NULL; + } + } + } + + return 0; +} + +int reset_chan(struct dma_channel_info *ch) +{ + unsigned long flag; + int val; + int chan_no = (int)(ch - dma_chan); + + close_chan(ch); + + local_irq_save(flag); + mbs_grab(); + dma_w32(chan_no, cs); + dma_w32_mask(0, DMA_CCTRL_RST, cctrl); + mbs_release(); + local_irq_restore(flag); + + do { + local_irq_save(flag); + mbs_grab(); + dma_w32(chan_no, cs); + val = dma_r32(cctrl); + mbs_release(); + local_irq_restore(flag); + } while (val & DMA_CCTRL_RST); + + return 0; +} + +static inline void rx_chan_intr_handler(int chan_no) +{ + struct dma_device_info *dma_dev = (struct dma_device_info *) + dma_chan[chan_no].dma_dev; + struct dma_channel_info *ch = &dma_chan[chan_no]; + struct rx_desc *rx_desc_p; + unsigned long flag; + u32 val; + + local_irq_save(flag); + mbs_grab(); + dma_w32(chan_no, cs); + val = dma_r32(cis); + dma_w32(DMA_CIS_DESCPT, cis); + mbs_release(); + + /* handle command complete interrupt */ + rx_desc_p = (struct rx_desc *)ch->desc_base + ch->curr_desc; + if ((rx_desc_p->status.word & (DMA_DESC_OWN_DMA | DMA_DESC_CPT_SET)) == + DMA_DESC_CPT_SET) { + local_irq_restore(flag); + /* Every thing is correct, then we inform the upper layer */ + dma_dev->current_rx_chan = ch->rel_chan_no; + if (dma_dev->intr_handler) + dma_dev->intr_handler(dma_dev, RCV_INT); + ch->weight--; + } else { + g_dma_int_status &= ~(1 << chan_no); + local_irq_restore(flag); + svip_enable_irq(dma_chan[chan_no].irq); + } +} + +static inline void tx_chan_intr_handler(int chan_no) +{ + struct dma_device_info *dma_dev = (struct dma_device_info *) + dma_chan[chan_no].dma_dev; + struct dma_channel_info *ch = &dma_chan[chan_no]; + struct tx_desc *tx_desc_p; + unsigned long flag; + + local_irq_save(flag); + mbs_grab(); + dma_w32(chan_no, cs); + dma_w32(DMA_CIS_DESCPT, cis); + mbs_release(); + + tx_desc_p = (struct tx_desc *)ch->desc_base+ch->prev_desc; + if ((tx_desc_p->status.word & (DMA_DESC_OWN_DMA | DMA_DESC_CPT_SET)) == + DMA_DESC_CPT_SET) { + local_irq_restore(flag); + + dma_dev->buffer_free((u8 *)__va(tx_desc_p->data_pointer), + ch->opt[ch->prev_desc]); + memset(tx_desc_p, 0, sizeof(struct tx_desc)); + dma_dev->current_tx_chan = ch->rel_chan_no; + if (dma_dev->intr_handler) + dma_dev->intr_handler(dma_dev, TRANSMIT_CPT_INT); + ch->weight--; + + ch->prev_desc = (ch->prev_desc + 1) % (ch->desc_len); + } else { + g_dma_int_status &= ~(1 << chan_no); + local_irq_restore(flag); + svip_enable_irq(dma_chan[chan_no].irq); + } +} + +void do_dma_tasklet(unsigned long unused) +{ + int i; + int chan_no = 0; + int budget = DMA_INT_BUDGET; + int weight = 0; + unsigned long flag; + + while (g_dma_int_status) { + if (budget-- < 0) { + tasklet_schedule(&dma_tasklet); + return; + } + chan_no = -1; + weight = 0; + /* WFQ algorithm to select the channel */ + for (i = 0; i < LTQ_MAX_DMA_CHANNEL_NUM; i++) { + if (g_dma_int_status & (1 << i) && + dma_chan[i].weight > 0) { + if (dma_chan[i].weight > weight) { + chan_no = i; + weight = dma_chan[chan_no].weight; + } + } + } + if (chan_no >= 0) { + if (dma_chan[chan_no].dir == DIR_RX) + rx_chan_intr_handler(chan_no); + else + tx_chan_intr_handler(chan_no); + } else { + /* reset all the channels */ + for (i = 0; i < LTQ_MAX_DMA_CHANNEL_NUM; i++) + dma_chan[i].weight = dma_chan[i].default_weight; + } + } + + local_irq_save(flag); + g_dma_in_process = 0; + if (g_dma_int_status) { + g_dma_in_process = 1; + tasklet_schedule(&dma_tasklet); + } + local_irq_restore(flag); +} + +irqreturn_t dma_interrupt(int irq, void *dev_id) +{ + struct dma_channel_info *ch; + int chan_no = 0; + + ch = (struct dma_channel_info *)dev_id; + chan_no = (int)(ch - dma_chan); + + if ((unsigned)chan_no >= LTQ_MAX_DMA_CHANNEL_NUM) { + printk(KERN_ERR "error: dma_interrupt irq=%d chan_no=%d\n", + irq, chan_no); + } + + g_dma_int_status |= 1 << chan_no; + dma_w32(1 << chan_no, irncr); + mask_and_ack_irq(irq); + + if (!g_dma_in_process) { + g_dma_in_process = 1; + tasklet_schedule(&dma_tasklet); + } + + return IRQ_RETVAL(1); +} + +struct dma_device_info *dma_device_reserve(char *dev_name) +{ + int i; + + ltq_dma_init(); + for (i = 0; i < LTQ_MAX_DMA_DEVICE_NUM; i++) { + if (strcmp(dev_name, dma_devices[i].device_name) == 0) { + if (dma_devices[i].reserved) + return NULL; + dma_devices[i].reserved = 1; + break; + } + } + + if (i == LTQ_MAX_DMA_DEVICE_NUM) + return NULL; + + return &dma_devices[i]; +} +EXPORT_SYMBOL(dma_device_reserve); + +int dma_device_release(struct dma_device_info *dma_dev) +{ + dma_dev->reserved = 0; + + return 0; +} +EXPORT_SYMBOL(dma_device_release); + +int dma_device_register(struct dma_device_info *dma_dev) +{ + int port_no = (int)(dma_dev - dma_devices); + int txbl, rxbl; + unsigned long flag; + + switch (dma_dev->tx_burst_len) { + case 8: + txbl = 3; + break; + case 4: + txbl = 2; + break; + default: + txbl = 1; + break; + } + + switch (dma_dev->rx_burst_len) { + case 8: + rxbl = 3; + break; + case 4: + rxbl = 2; + break; + default: + rxbl = 1; + } + + local_irq_save(flag); + mbs_grab(); + dma_w32(port_no, ps); + dma_w32(DMA_PCTRL_TXWGT_VAL(dma_dev->tx_weight) + | DMA_PCTRL_TXENDI_VAL(dma_dev->tx_endianness_mode) + | DMA_PCTRL_RXENDI_VAL(dma_dev->rx_endianness_mode) + | DMA_PCTRL_PDEN_VAL(dma_dev->drop_enable) + | DMA_PCTRL_TXBL_VAL(txbl) + | DMA_PCTRL_RXBL_VAL(rxbl), pctrl); + mbs_release(); + local_irq_restore(flag); + + return 0; +} +EXPORT_SYMBOL(dma_device_register); + +int dma_device_unregister(struct dma_device_info *dma_dev) +{ + int i; + int port_no = (int)(dma_dev - dma_devices); + unsigned long flag; + + /* flush memcopy module; has no effect for other ports */ + local_irq_save(flag); + mbs_grab(); + dma_w32(port_no, ps); + dma_w32_mask(0, DMA_PCTRL_GPC, pctrl); + mbs_release(); + local_irq_restore(flag); + + for (i = 0; i < dma_dev->max_tx_chan_num; i++) + reset_chan(dma_dev->tx_chan[i]); + + for (i = 0; i < dma_dev->max_rx_chan_num; i++) + reset_chan(dma_dev->rx_chan[i]); + + return 0; +} +EXPORT_SYMBOL(dma_device_unregister); + +/** + * Read Packet from DMA Rx channel. + * The function gets the data from the current rx descriptor assigned + * to the passed DMA device and passes it back to the caller. + * The function is called in the context of DMA interrupt. + * In detail the following actions are done: + * - get current receive descriptor + * - allocate memory via allocation callback function + * - pass data from descriptor to allocated memory + * - update channel weight + * - release descriptor + * - update current descriptor position + * + * \param *dma_dev - pointer to DMA device structure + * \param **dataptr - pointer to received data + * \param **opt + * \return packet length - length of received data + * \ingroup Internal + */ +int dma_device_read(struct dma_device_info *dma_dev, u8 **dataptr, void **opt) +{ + u8 *buf; + int len; + int byte_offset = 0; + void *p = NULL; + + struct dma_channel_info *ch = + dma_dev->rx_chan[dma_dev->current_rx_chan]; + + struct rx_desc *rx_desc_p; + + /* get the rx data first */ + rx_desc_p = (struct rx_desc *)ch->desc_base+ch->curr_desc; + buf = (u8 *)__va(rx_desc_p->data_pointer); + *(u32 *)dataptr = (u32)buf; + len = rx_desc_p->status.field.data_length; +#ifndef CONFIG_MIPS_UNCACHED + dma_cache_inv((unsigned long)buf, len); +#endif + if (opt) + *(int *)opt = (int)ch->opt[ch->curr_desc]; + + /* replace with a new allocated buffer */ + buf = dma_dev->buffer_alloc(ch->packet_size, &byte_offset, &p); + if (buf) { + ch->opt[ch->curr_desc] = p; + + wmb(); + rx_desc_p->data_pointer = (u32)CPHYSADDR((u32)buf); + rx_desc_p->status.word = (DMA_OWN << 31) \ + |(byte_offset << 23) \ + | ch->packet_size; + + wmb(); + } else { + *(u32 *)dataptr = 0; + if (opt) + *(int *)opt = 0; + } + + ch->xfer_cnt++; + /* increase the curr_desc pointer */ + ch->curr_desc++; + if (ch->curr_desc == ch->desc_len) + ch->curr_desc = 0; + /* return the length of the received packet */ + return len; +} +EXPORT_SYMBOL(dma_device_read); + +/** + * Write Packet through DMA Tx channel to peripheral. + * + * \param *dma_dev - pointer to DMA device structure + * \param *dataptr - pointer to data to be sent + * \param len - amount of data bytes to be sent + * \param *opt + * \return len - length of transmitted data + * \ingroup Internal + */ +int dma_device_write(struct dma_device_info *dma_dev, u8 *dataptr, int len, + void *opt) +{ + unsigned long flag; + u32 byte_offset; + struct dma_channel_info *ch; + int chan_no; + struct tx_desc *tx_desc_p; + local_irq_save(flag); + + ch = dma_dev->tx_chan[dma_dev->current_tx_chan]; + chan_no = (int)(ch - dma_chan); + + if (ch->control == LTQ_DMA_CH_OFF) { + local_irq_restore(flag); + printk(KERN_ERR "%s: dma channel %d not enabled!\n", + __func__, chan_no); + return 0; + } + + tx_desc_p = (struct tx_desc *)ch->desc_base+ch->curr_desc; + /* Check whether this descriptor is available */ + if (tx_desc_p->status.word & (DMA_DESC_OWN_DMA | DMA_DESC_CPT_SET)) { + /* if not , the tell the upper layer device */ + dma_dev->intr_handler(dma_dev, TX_BUF_FULL_INT); + local_irq_restore(flag); + return 0; + } + ch->opt[ch->curr_desc] = opt; + /* byte offset----to adjust the starting address of the data buffer, + * should be multiple of the burst length.*/ + byte_offset = ((u32)CPHYSADDR((u32)dataptr)) % + (dma_dev->tx_burst_len * 4); +#ifndef CONFIG_MIPS_UNCACHED + dma_cache_wback((unsigned long)dataptr, len); + wmb(); +#endif + tx_desc_p->data_pointer = (u32)CPHYSADDR((u32)dataptr) - byte_offset; + wmb(); + tx_desc_p->status.word = (DMA_OWN << 31) + | DMA_DESC_SOP_SET + | DMA_DESC_EOP_SET + | (byte_offset << 23) + | len; + wmb(); + + if (ch->xfer_cnt == 0) { + mbs_grab(); + dma_w32(chan_no, cs); + dma_w32_mask(0, DMA_CCTRL_ON_OFF, cctrl); + mbs_release(); + } + + ch->xfer_cnt++; + ch->curr_desc++; + if (ch->curr_desc == ch->desc_len) + ch->curr_desc = 0; + + local_irq_restore(flag); + return len; +} +EXPORT_SYMBOL(dma_device_write); + +/** + * Display descriptor list via proc file + * + * \param chan_no - logical channel number + * \ingroup Internal + */ +int desc_list_proc_read(char *buf, char **start, off_t offset, + int count, int *eof, void *data) +{ + int len = 0; + int i; + static int chan_no; + u32 *p; + + if ((chan_no == 0) && (offset > count)) { + *eof = 1; + return 0; + } + + if (chan_no != 0) { + *start = buf; + } else { + buf = buf + offset; + *start = buf; + } + + p = (u32 *)dma_chan[chan_no].desc_base; + + if (dma_chan[chan_no].dir == DIR_RX) + len += sprintf(buf + len, + "channel %d %s Rx descriptor list:\n", + chan_no, dma_chan[chan_no].dma_dev->device_name); + else + len += sprintf(buf + len, + "channel %d %s Tx descriptor list:\n", + chan_no, dma_chan[chan_no].dma_dev->device_name); + len += sprintf(buf + len, + " no address data pointer command bits " + "(Own, Complete, SoP, EoP, Offset) \n"); + len += sprintf(buf + len, + "----------------------------------------------" + "-----------------------------------\n"); + for (i = 0; i < dma_chan[chan_no].desc_len; i++) { + len += sprintf(buf + len, "%3d ", i); + len += sprintf(buf + len, "0x%08x ", (u32)(p + (i * 2))); + len += sprintf(buf + len, "%08x ", *(p + (i * 2 + 1))); + len += sprintf(buf + len, "%08x ", *(p + (i * 2))); + + if (*(p + (i * 2)) & 0x80000000) + len += sprintf(buf + len, "D "); + else + len += sprintf(buf + len, "C "); + if (*(p + (i * 2)) & 0x40000000) + len += sprintf(buf + len, "C "); + else + len += sprintf(buf + len, "c "); + if (*(p + (i * 2)) & 0x20000000) + len += sprintf(buf + len, "S "); + else + len += sprintf(buf + len, "s "); + if (*(p + (i * 2)) & 0x10000000) + len += sprintf(buf + len, "E "); + else + len += sprintf(buf + len, "e "); + + /* byte offset is different for rx and tx descriptors*/ + if (dma_chan[chan_no].dir == DIR_RX) { + len += sprintf(buf + len, "%01x ", + (*(p + (i * 2)) & 0x01800000) >> 23); + } else { + len += sprintf(buf + len, "%02x ", + (*(p + (i * 2)) & 0x0F800000) >> 23); + } + + if (dma_chan[chan_no].curr_desc == i) + len += sprintf(buf + len, "<- CURR"); + + if (dma_chan[chan_no].prev_desc == i) + len += sprintf(buf + len, "<- PREV"); + + len += sprintf(buf + len, "\n"); + + } + + len += sprintf(buf + len, "\n"); + chan_no++; + if (chan_no > LTQ_MAX_DMA_CHANNEL_NUM - 1) + chan_no = 0; + + *eof = 1; + return len; +} + +/** + * Displays the weight of all DMA channels via proc file + * + * + * + * \param *buf + * \param **start + * \param offset + * \param count + * \param *eof + * \param *data + * \return len - amount of bytes written to file + */ +int channel_weight_proc_read(char *buf, char **start, off_t offset, + int count, int *eof, void *data) +{ + int i; + int len = 0; + len += sprintf(buf + len, "Qos dma channel weight list\n"); + len += sprintf(buf + len, "channel_num default_weight " + "current_weight device Tx/Rx\n"); + len += sprintf(buf + len, "---------------------------" + "---------------------------------\n"); + for (i = 0; i < LTQ_MAX_DMA_CHANNEL_NUM; i++) { + struct dma_channel_info *ch = &dma_chan[i]; + + if (ch->dir == DIR_RX) { + len += sprintf(buf + len, + " %2d %08x " + "%08x %10s Rx\n", + i, ch->default_weight, ch->weight, + ch->dma_dev->device_name); + } else { + len += sprintf(buf + len, + " %2d %08x " + "%08x %10s Tx\n", + i, ch->default_weight, ch->weight, + ch->dma_dev->device_name); + } + } + + return len; +} + +/** + * Provides DMA Register Content to proc file + * This function reads the content of general DMA Registers, DMA Channel + * Registers and DMA Port Registers and performs a structures output to the + * DMA proc file + * + * \param *buf + * \param **start + * \param offset + * \param count + * \param *eof + * \param *data + * \return len - amount of bytes written to file + */ +int dma_register_proc_read(char *buf, char **start, off_t offset, + int count, int *eof, void *data) +{ + int len = 0; + int i; + int limit = count; + unsigned long flags; + static int blockcount; + static int channel_no; + + if ((blockcount == 0) && (offset > count)) { + *eof = 1; + return 0; + } + + switch (blockcount) { + case 0: + len += sprintf(buf + len, "\nGeneral DMA Registers\n"); + len += sprintf(buf + len, "-------------------------" + "----------------\n"); + len += sprintf(buf + len, "CLC= %08x\n", dma_r32(clc)); + len += sprintf(buf + len, "ID= %08x\n", dma_r32(id)); + len += sprintf(buf + len, "DMA_CPOLL= %08x\n", dma_r32(cpoll)); + len += sprintf(buf + len, "DMA_CS= %08x\n", dma_r32(cs)); + len += sprintf(buf + len, "DMA_PS= %08x\n", dma_r32(ps)); + len += sprintf(buf + len, "DMA_IRNEN= %08x\n", dma_r32(irnen)); + len += sprintf(buf + len, "DMA_IRNCR= %08x\n", dma_r32(irncr)); + len += sprintf(buf + len, "DMA_IRNICR= %08x\n", + dma_r32(irnicr)); + len += sprintf(buf + len, "\nDMA Channel Registers\n"); + blockcount = 1; + return len; + break; + case 1: + /* If we had an overflow start at beginning of buffer + * otherwise use offset */ + if (channel_no != 0) { + *start = buf; + } else { + buf = buf + offset; + *start = buf; + } + + local_irq_save(flags); + for (i = channel_no; i < LTQ_MAX_DMA_CHANNEL_NUM; i++) { + struct dma_channel_info *ch = &dma_chan[i]; + + if (len + 300 > limit) { + local_irq_restore(flags); + channel_no = i; + blockcount = 1; + return len; + } + len += sprintf(buf + len, "----------------------" + "-------------------\n"); + if (ch->dir == DIR_RX) { + len += sprintf(buf + len, + "Channel %d - Device %s Rx\n", + i, ch->dma_dev->device_name); + } else { + len += sprintf(buf + len, + "Channel %d - Device %s Tx\n", + i, ch->dma_dev->device_name); + } + dma_w32(i, cs); + len += sprintf(buf + len, "DMA_CCTRL= %08x\n", + dma_r32(cctrl)); + len += sprintf(buf + len, "DMA_CDBA= %08x\n", + dma_r32(cdba)); + len += sprintf(buf + len, "DMA_CIE= %08x\n", + dma_r32(cie)); + len += sprintf(buf + len, "DMA_CIS= %08x\n", + dma_r32(cis)); + len += sprintf(buf + len, "DMA_CDLEN= %08x\n", + dma_r32(cdlen)); + } + local_irq_restore(flags); + blockcount = 2; + channel_no = 0; + return len; + break; + case 2: + *start = buf; + /* + * display port dependent registers + */ + len += sprintf(buf + len, "\nDMA Port Registers\n"); + len += sprintf(buf + len, + "-----------------------------------------\n"); + local_irq_save(flags); + for (i = 0; i < LTQ_MAX_DMA_DEVICE_NUM; i++) { + dma_w32(i, ps); + len += sprintf(buf + len, + "Port %d DMA_PCTRL= %08x\n", + i, dma_r32(pctrl)); + } + local_irq_restore(flags); + blockcount = 0; + *eof = 1; + return len; + break; + } + + blockcount = 0; + *eof = 1; + return 0; +} + +/** + * Open Method of DMA Device Driver + * This function increments the device driver's use counter. + * + * + * \param + * \return + */ +static int dma_open(struct inode *inode, struct file *file) +{ + return 0; +} + +/** + * Release Method of DMA Device driver. + * This function decrements the device driver's use counter. + * + * + * \param + * \return + */ +static int dma_release(struct inode *inode, struct file *file) +{ + /* release the resources */ + return 0; +} + +/** + * Ioctl Interface to DMA Module + * + * \param None + * \return 0 - initialization successful + * <0 - failed initialization + */ +static long dma_ioctl(struct file *file, + unsigned int cmd, unsigned long arg) +{ + int result = 0; + /* TODO: add some user controled functions here */ + return result; +} + +const static struct file_operations dma_fops = { + .owner = THIS_MODULE, + .open = dma_open, + .release = dma_release, + .unlocked_ioctl = dma_ioctl, +}; + +void map_dma_chan(struct dma_channel_info *map) +{ + int i; + + /* assign default values for channel settings */ + for (i = 0; i < LTQ_MAX_DMA_CHANNEL_NUM; i++) { + dma_chan[i].byte_offset = 0; + dma_chan[i].open = &open_chan; + dma_chan[i].close = &close_chan; + dma_chan[i].reset = &reset_chan; + dma_chan[i].enable_irq = enable_ch_irq; + dma_chan[i].disable_irq = disable_ch_irq; + dma_chan[i].tx_weight = 1; + dma_chan[i].control = 0; + dma_chan[i].default_weight = LTQ_DMA_CH_DEFAULT_WEIGHT; + dma_chan[i].weight = dma_chan[i].default_weight; + dma_chan[i].curr_desc = 0; + dma_chan[i].prev_desc = 0; + } + + /* assign default values for port settings */ + for (i = 0; i < LTQ_MAX_DMA_DEVICE_NUM; i++) { + /*set default tx channel number to be one*/ + dma_devices[i].num_tx_chan = 1; + /*set default rx channel number to be one*/ + dma_devices[i].num_rx_chan = 1; + dma_devices[i].buffer_alloc = common_buffer_alloc; + dma_devices[i].buffer_free = common_buffer_free; + dma_devices[i].intr_handler = NULL; + dma_devices[i].tx_burst_len = 4; + dma_devices[i].rx_burst_len = 4; +#ifdef CONFIG_CPU_LITTLE_ENDIAN + dma_devices[i].tx_endianness_mode = 0; + dma_devices[i].rx_endianness_mode = 0; +#else + dma_devices[i].tx_endianness_mode = 3; + dma_devices[i].rx_endianness_mode = 3; +#endif + } +} + +void dma_chip_init(void) +{ + int i; + + sys1_w32(SYS1_CLKENR_DMA, clkenr); + wmb(); + /* reset DMA */ + dma_w32(DMA_CTRL_RST, ctrl); + wmb(); + /* disable all the interrupts first */ + dma_w32(0, irnen); + + /* enable polling for all channels */ + dma_w32(DMA_CPOLL_EN | DMA_CPOLL_CNT_VAL(DMA_POLL_COUNTER), cpoll); + + /****************************************************/ + for (i = 0; i < LTQ_MAX_DMA_CHANNEL_NUM; i++) + disable_ch_irq(&dma_chan[i]); +} + +int ltq_dma_init(void) +{ + int result = 0; + int i; + unsigned long flag; + static int dma_initialized; + + if (dma_initialized == 1) + return 0; + dma_initialized = 1; + + result = register_chrdev(DMA_MAJOR, "dma-core", &dma_fops); + if (result) { + DMA_EMSG("cannot register device dma-core!\n"); + return result; + } + + dma_chip_init(); + map_dma_chan(dma_chan); + + /* allocate DMA memory for buffer descriptors */ + for (i = 0; i < DMA_DESCR_MEM_PAGES; i++) { + g_desc_list[i] = (u64 *)__get_free_page(GFP_DMA); + if (g_desc_list[i] == NULL) { + DMA_EMSG("no memory for desriptor\n"); + return -ENOMEM; + } + g_desc_list[i] = (u64 *)KSEG1ADDR(g_desc_list[i]); + memset(g_desc_list[i], 0, PAGE_SIZE); + } + + for (i = 0; i < LTQ_MAX_DMA_CHANNEL_NUM; i++) { + int page_index, ch_per_page; + /* cross-link relative channels of a port to + * corresponding absolute channels */ + if (dma_chan[i].dir == DIR_RX) { + ((struct dma_device_info *)(dma_chan[i].dma_dev))-> + rx_chan[dma_chan[i].rel_chan_no] = &dma_chan[i]; + } else { + ((struct dma_device_info *)(dma_chan[i].dma_dev))-> + tx_chan[dma_chan[i].rel_chan_no] = &dma_chan[i]; + } + dma_chan[i].abs_chan_no = i; + + page_index = i * DMA_DESCR_CH_SIZE / PAGE_SIZE; + ch_per_page = PAGE_SIZE / DMA_DESCR_CH_SIZE + + ((PAGE_SIZE % DMA_DESCR_CH_SIZE) > 0); + dma_chan[i].desc_base = + (u32)g_desc_list[page_index] + + (i - page_index*ch_per_page) * DMA_DESCR_NUM*8; + dma_chan[i].curr_desc = 0; + dma_chan[i].desc_len = DMA_DESCR_NUM; + + local_irq_save(flag); + mbs_grab(); + dma_w32(i, cs); + dma_w32((u32)CPHYSADDR(dma_chan[i].desc_base), cdba); + mbs_release(); + local_irq_restore(flag); + } + + g_dma_dir = proc_mkdir("driver/" DRV_NAME, NULL); + + create_proc_read_entry("dma_register", + 0, + g_dma_dir, + dma_register_proc_read, + NULL); + + create_proc_read_entry("g_desc_list", + 0, + g_dma_dir, + desc_list_proc_read, + NULL); + + create_proc_read_entry("channel_weight", + 0, + g_dma_dir, + channel_weight_proc_read, + NULL); + + printk(KERN_NOTICE "SVIP DMA engine initialized\n"); + + return 0; +} + +/** + * Cleanup DMA device + * This function releases all resources used by the DMA device driver on + * module removal. + * + * + * \param None + * \return Nothing + */ +void dma_cleanup(void) +{ + int i; + unregister_chrdev(DMA_MAJOR, "dma-core"); + + for (i = 0; i < DMA_DESCR_MEM_PAGES; i++) + free_page(KSEG0ADDR((unsigned long)g_desc_list[i])); + remove_proc_entry("channel_weight", g_dma_dir); + remove_proc_entry("g_desc_list", g_dma_dir); + remove_proc_entry("dma_register", g_dma_dir); + remove_proc_entry("driver/" DRV_NAME, NULL); + /* release the resources */ + for (i = 0; i < LTQ_MAX_DMA_CHANNEL_NUM; i++) + free_irq(dma_chan[i].irq, (void *)&dma_chan[i]); +} + +arch_initcall(ltq_dma_init); + +MODULE_LICENSE("GPL"); diff --git a/target/linux/lantiq/files-3.3/arch/mips/lantiq/svip/gpio.c b/target/linux/lantiq/files-3.3/arch/mips/lantiq/svip/gpio.c new file mode 100644 index 000000000..398339201 --- /dev/null +++ b/target/linux/lantiq/files-3.3/arch/mips/lantiq/svip/gpio.c @@ -0,0 +1,553 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin <blogic@openwrt.org> + */ + +#include <linux/module.h> +#include <linux/slab.h> +#include <linux/gpio.h> +#include <linux/ioport.h> +#include <linux/io.h> +#include <linux/types.h> +#include <linux/errno.h> +#include <linux/proc_fs.h> +#include <linux/init.h> +#include <linux/ioctl.h> +#include <linux/timer.h> +#include <linux/interrupt.h> +#include <linux/kobject.h> +#include <linux/workqueue.h> +#include <linux/skbuff.h> +#include <linux/netlink.h> +#include <linux/platform_device.h> +#include <net/sock.h> +#include <linux/uaccess.h> +#include <linux/version.h> +#include <linux/semaphore.h> + +#include <lantiq_soc.h> +#include <svip_mux.h> +#include <base_reg.h> +#include <port_reg.h> + +#define DRV_NAME "ifxmips_gpio" + +int gpio_to_irq(unsigned int gpio) +{ + return -EINVAL; +} +EXPORT_SYMBOL(gpio_to_irq); + +int irq_to_gpio(unsigned int gpio) +{ + return -EINVAL; +} +EXPORT_SYMBOL(irq_to_gpio); + +struct ltq_port_base { + struct svip_reg_port *base; + u32 pins; +}; + +/* Base addresses for ports */ +static const struct ltq_port_base ltq_port_base[] = { + { (struct svip_reg_port *)LTQ_PORT_P0_BASE, 20 }, + { (struct svip_reg_port *)LTQ_PORT_P1_BASE, 20 }, + { (struct svip_reg_port *)LTQ_PORT_P2_BASE, 19 }, + { (struct svip_reg_port *)LTQ_PORT_P3_BASE, 20 }, + { (struct svip_reg_port *)LTQ_PORT_P4_BASE, 24 } +}; + +#define MAX_PORTS ARRAY_SIZE(ltq_port_base) +#define PINS_PER_PORT(port) (ltq_port_base[port].pins) + +static inline +void ltq_port_set_exintcr0(unsigned int port, unsigned int pin) +{ + if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) + return; + + port_w32(port_r32(ltq_port_base[port].base->exintcr0) | (1 << pin), + ltq_port_base[port].base->exintcr0); +} + +static inline +void ltq_port_clear_exintcr0(unsigned int port, unsigned int pin) +{ + if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) + return; + + port_w32(port_r32(ltq_port_base[port].base->exintcr0) & ~(1 << pin), + ltq_port_base[port].base->exintcr0); +} + +static inline +void ltq_port_set_exintcr1(unsigned int port, unsigned int pin) +{ + if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) + return; + + port_w32(port_r32(ltq_port_base[port].base->exintcr1) | (1 << pin), + ltq_port_base[port].base->exintcr1); +} + +static inline +void ltq_port_clear_exintcr1(unsigned int port, unsigned int pin) +{ + if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) + return; + + port_w32(port_r32(ltq_port_base[port].base->exintcr1) & ~(1 << pin), + ltq_port_base[port].base->exintcr1); +} + +static inline +void ltq_port_set_irncfg(unsigned int port, unsigned int pin) +{ + if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) + return; + + port_w32(port_r32(ltq_port_base[port].base->irncfg) | (1 << pin), + ltq_port_base[port].base->irncfg); +} + +static inline +void ltq_port_clear_irncfg(unsigned int port, unsigned int pin) +{ + if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) + return; + + port_w32(port_r32(ltq_port_base[port].base->irncfg) & ~(1 << pin), + ltq_port_base[port].base->irncfg); +} + +static inline +void ltq_port_set_irnen(unsigned int port, unsigned int pin) +{ + if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) + return; + + port_w32(1 << pin, ltq_port_base[port].base->irnenset); +} + +static inline +void ltq_port_clear_irnen(unsigned int port, unsigned int pin) +{ + if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) + return; + + port_w32(1 << pin, ltq_port_base[port].base->irnenclr); +} + +static inline +void ltq_port_set_dir_out(unsigned int port, unsigned int pin) +{ + if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) + return; + + port_w32(port_r32(ltq_port_base[port].base->dir) | (1 << pin), + ltq_port_base[port].base->dir); +} + +static inline +void ltq_port_set_dir_in(unsigned int port, unsigned int pin) +{ + if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) + return; + + port_w32(port_r32(ltq_port_base[port].base->dir) & ~(1 << pin), + ltq_port_base[port].base->dir); +} + +static inline +void ltq_port_set_output(unsigned int port, unsigned int pin) +{ + if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) + return; + + port_w32(port_r32(ltq_port_base[port].base->out) | (1 << pin), + ltq_port_base[port].base->out); +} + +static inline +void ltq_port_clear_output(unsigned int port, unsigned int pin) +{ + if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) + return; + + port_w32(port_r32(ltq_port_base[port].base->out) & ~(1 << pin), + ltq_port_base[port].base->out); +} + +static inline +int ltq_port_get_input(unsigned int port, unsigned int pin) +{ + if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) + return -EINVAL; + + return (port_r32(ltq_port_base[port].base->in) & (1 << pin)) == 0; +} + +static inline +void ltq_port_set_puen(unsigned int port, unsigned int pin) +{ + if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) + return; + + port_w32(port_r32(ltq_port_base[port].base->puen) | (1 << pin), + ltq_port_base[port].base->puen); +} + +static inline +void ltq_port_clear_puen(unsigned int port, unsigned int pin) +{ + if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) + return; + + port_w32(port_r32(ltq_port_base[port].base->puen) & ~(1 << pin), + ltq_port_base[port].base->puen); +} + +static inline +void ltq_port_set_altsel0(unsigned int port, unsigned int pin) +{ + if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) + return; + + port_w32(port_r32(ltq_port_base[port].base->altsel0) | (1 << pin), + ltq_port_base[port].base->altsel0); +} + +static inline +void ltq_port_clear_altsel0(unsigned int port, unsigned int pin) +{ + if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) + return; + + port_w32(port_r32(ltq_port_base[port].base->altsel0) & ~(1 << pin), + ltq_port_base[port].base->altsel0); +} + +static inline +void ltq_port_set_altsel1(unsigned int port, unsigned int pin) +{ + if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) + return; + + port_w32(port_r32(ltq_port_base[port].base->altsel1) | (1 << pin), + ltq_port_base[port].base->altsel1); +} + +static inline +void ltq_port_clear_altsel1(unsigned int port, unsigned int pin) +{ + if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) + return; + + port_w32(port_r32(ltq_port_base[port].base->altsel1) & ~(1 << pin), + ltq_port_base[port].base->altsel1); +} + +void ltq_gpio_configure(int port, int pin, bool dirin, bool puen, + bool altsel0, bool altsel1) +{ + if (dirin) + ltq_port_set_dir_in(port, pin); + else + ltq_port_set_dir_out(port, pin); + + if (puen) + ltq_port_set_puen(port, pin); + else + ltq_port_clear_puen(port, pin); + + if (altsel0) + ltq_port_set_altsel0(port, pin); + else + ltq_port_clear_altsel0(port, pin); + + if (altsel1) + ltq_port_set_altsel1(port, pin); + else + ltq_port_clear_altsel1(port, pin); +} + +int ltq_port_get_dir(unsigned int port, unsigned int pin) +{ + if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) + return -EINVAL; + + return (port_r32(ltq_port_base[port].base->dir) & (1 << pin)) != 0; +} + +int ltq_port_get_puden(unsigned int port, unsigned int pin) +{ + if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) + return -EINVAL; + + return (port_r32(ltq_port_base[port].base->puen) & (1 << pin)) != 0; +} + +int ltq_port_get_altsel0(unsigned int port, unsigned int pin) +{ + if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) + return -EINVAL; + + return (port_r32(ltq_port_base[port].base->altsel0) & (1 << pin)) != 0; +} + +int ltq_port_get_altsel1(unsigned int port, unsigned int pin) +{ + if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) + return -EINVAL; + + return (port_r32(ltq_port_base[port].base->altsel1) & (1 << pin)) != 0; +} + +struct ltq_gpio_port { + struct gpio_chip gpio_chip; + unsigned int irq_base; + unsigned int chained_irq; +}; + +static struct ltq_gpio_port ltq_gpio_port[MAX_PORTS]; + +static int gpio_exported; +static int __init gpio_export_setup(char *str) +{ + get_option(&str, &gpio_exported); + return 1; +} +__setup("gpio_exported=", gpio_export_setup); + +static inline unsigned int offset2port(unsigned int offset) +{ + unsigned int i; + unsigned int prev = 0; + + for (i = 0; i < ARRAY_SIZE(ltq_port_base); i++) { + if (offset >= prev && + offset < prev + ltq_port_base[i].pins) + return i; + + prev = ltq_port_base[i].pins; + } + + return 0; +} + +static inline unsigned int offset2pin(unsigned int offset) +{ + unsigned int i; + unsigned int prev = 0; + + for (i = 0; i < ARRAY_SIZE(ltq_port_base); i++) { + if (offset >= prev && + offset < prev + ltq_port_base[i].pins) + return offset - prev; + + prev = ltq_port_base[i].pins; + } + + return 0; +} + +static int ltq_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) +{ + ltq_port_set_dir_in(offset2port(offset), offset2pin(offset)); + return 0; +} + +static int ltq_gpio_direction_output(struct gpio_chip *chip, + unsigned int offset, int value) +{ + ltq_port_set_dir_out(offset2port(offset), offset2pin(offset)); + return 0; +} + +static int ltq_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + return ltq_port_get_input(offset2port(offset), offset2pin(offset)); +} + +static void ltq_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) +{ + if (value) + ltq_port_set_output(offset2port(offset), offset2pin(offset)); + else + ltq_port_clear_output(offset2port(offset), offset2pin(offset)); +} + +static int svip_gpio_request(struct gpio_chip *chip, unsigned offset) +{ + return 0; +} + +static void ltq_gpio_free(struct gpio_chip *chip, unsigned offset) +{ +} + +static int ltq_gpio_probe(struct platform_device *pdev) +{ + int ret = 0; + struct ltq_gpio_port *gpio_port; + + if (pdev->id >= MAX_PORTS) + return -ENODEV; + + gpio_port = <q_gpio_port[pdev->id]; + gpio_port->gpio_chip.label = "ltq-gpio"; + + gpio_port->gpio_chip.direction_input = ltq_gpio_direction_input; + gpio_port->gpio_chip.direction_output = ltq_gpio_direction_output; + gpio_port->gpio_chip.get = ltq_gpio_get; + gpio_port->gpio_chip.set = ltq_gpio_set; + gpio_port->gpio_chip.request = svip_gpio_request; + gpio_port->gpio_chip.free = ltq_gpio_free; + gpio_port->gpio_chip.base = 100 * pdev->id; + gpio_port->gpio_chip.ngpio = 32; + gpio_port->gpio_chip.dev = &pdev->dev; + gpio_port->gpio_chip.exported = gpio_exported; + + ret = gpiochip_add(&gpio_port->gpio_chip); + if (ret < 0) { + dev_err(&pdev->dev, "Could not register gpiochip %d, %d\n", + pdev->id, ret); + goto err; + } + platform_set_drvdata(pdev, gpio_port); + + return 0; + +err: + return ret; +} + +static int ltq_gpio_remove(struct platform_device *pdev) +{ + struct ltq_gpio_port *gpio_port = platform_get_drvdata(pdev); + int ret; + + ret = gpiochip_remove(&gpio_port->gpio_chip); + + return ret; +} + +static struct platform_driver ltq_gpio_driver = { + .probe = ltq_gpio_probe, + .remove = __devexit_p(ltq_gpio_remove), + .driver = { + .name = DRV_NAME, + .owner = THIS_MODULE, + }, +}; + +int __init ltq_gpio_init(void) +{ + int ret = platform_driver_register(<q_gpio_driver); + if (ret) + printk(KERN_INFO DRV_NAME + ": Error registering platform driver!"); + return ret; +} + +postcore_initcall(ltq_gpio_init); + +/** + * Convert interrupt number to corresponding port/pin pair + * Returns the port/pin pair serving the selected external interrupt; + * needed since mapping not linear. + * + * \param exint External interrupt number + * \param port Pointer for resulting port + * \param pin Pointer for resutling pin + * \return -EINVAL Invalid exint + * \return 0 port/pin updated + * \ingroup API + */ +static int ltq_exint2port(u32 exint, int *port, int *pin) +{ + if ((exint >= 0) && (exint <= 10)) { + *port = 0; + *pin = exint + 7; + } else if ((exint >= 11) && (exint <= 14)) { + *port = 1; + *pin = 18 - (exint - 11) ; + } else if (exint == 15) { + *port = 1; + *pin = 19; + } else if (exint == 16) { + *port = 0; + *pin = 19; + } else { + return -EINVAL; + } + return 0; +} + +/** + * Enable external interrupt. + * This function enables an external interrupt and sets the given mode. + * valid values for mode are: + * - 0 = Interrupt generation disabled + * - 1 = Interrupt on rising edge + * - 2 = Interrupt on falling edge + * - 3 = Interrupt on rising and falling edge + * - 5 = Interrupt on high level detection + * - 6 = Interrupt on low level detection + * + * \param exint - Number of external interrupt + * \param mode - Trigger mode + * \return 0 on success + * \ingroup API + */ +int ifx_enable_external_int(u32 exint, u32 mode) +{ + int port; + int pin; + + if ((mode < 0) || (mode > 6)) + return -EINVAL; + + if (ltq_exint2port(exint, &port, &pin)) + return -EINVAL; + + ltq_port_clear_exintcr0(port, pin); + ltq_port_clear_exintcr1(port, pin); + ltq_port_clear_irncfg(port, pin); + + if (mode & 0x1) + ltq_port_set_exintcr0(port, pin); + if (mode & 0x2) + ltq_port_set_exintcr1(port, pin); + if (mode & 0x4) + ltq_port_set_irncfg(port, pin); + + ltq_port_set_irnen(port, pin); + return 0; +} +EXPORT_SYMBOL(ifx_enable_external_int); + +/** + * Disable external interrupt. + * This function disables an external interrupt and sets mode to 0x00. + * + * \param exint - Number of external interrupt + * \return 0 on success + * \ingroup API + */ +int ifx_disable_external_int(u32 exint) +{ + int port; + int pin; + + if (ltq_exint2port(exint, &port, &pin)) + return -EINVAL; + + ltq_port_clear_irnen(port, pin); + return 0; +} +EXPORT_SYMBOL(ifx_disable_external_int); diff --git a/target/linux/lantiq/files-3.3/arch/mips/lantiq/svip/mach-easy33016.c b/target/linux/lantiq/files-3.3/arch/mips/lantiq/svip/mach-easy33016.c new file mode 100644 index 000000000..c5993efd6 --- /dev/null +++ b/target/linux/lantiq/files-3.3/arch/mips/lantiq/svip/mach-easy33016.c @@ -0,0 +1,73 @@ +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/leds.h> +#include <linux/gpio.h> +#include <linux/gpio_buttons.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> +#include <linux/input.h> +#include <linux/interrupt.h> +#include <linux/spi/spi.h> +#include <linux/spi/flash.h> +#include "../machtypes.h" + +#include <sys1_reg.h> +#include <sys2_reg.h> +#include <svip_pms.h> + +#include "devices.h" + +static const struct ltq_mux_pin mux_p0[LTQ_MUX_P0_PINS] = { + LTQ_MUX_P0_0_SSC0_MTSR, + LTQ_MUX_P0_1_SSC0_MRST, + LTQ_MUX_P0_2_SSC0_SCLK, + LTQ_MUX_P0_3_SSC1_MTSR, + LTQ_MUX_P0_4_SSC1_MRST, + LTQ_MUX_P0_5_SSC1_SCLK, + LTQ_MUX_P0_6_SSC0_CS0, + LTQ_MUX_P0_7_SSC0_CS1, + LTQ_MUX_P0_8_SSC0_CS2, + LTQ_MUX_P0_9, + LTQ_MUX_P0_10, + LTQ_MUX_P0_11_EXINT4, + LTQ_MUX_P0_12, + LTQ_MUX_P0_13, + LTQ_MUX_P0_14_ASC0_TXD, + LTQ_MUX_P0_15_ASC0_RXD, + LTQ_MUX_P0_16_EXINT9, + LTQ_MUX_P0_17_EXINT10, + LTQ_MUX_P0_18_EJ_BRKIN, + LTQ_MUX_P0_19_EXINT16 +}; + +static void __init easy33016_init(void) +{ + svip_sys1_clk_enable(SYS1_CLKENR_L2C | + SYS1_CLKENR_DDR2 | + SYS1_CLKENR_SMI2 | + SYS1_CLKENR_SMI1 | + SYS1_CLKENR_SMI0 | + SYS1_CLKENR_FMI0 | + SYS1_CLKENR_DMA | + SYS1_CLKENR_SSC0 | + SYS1_CLKENR_SSC1 | + SYS1_CLKENR_EBU); + + svip_sys2_clk_enable(SYS2_CLKENR_HWSYNC | + SYS2_CLKENR_MBS | + SYS2_CLKENR_SWINT); + + svip_register_mux(mux_p0, NULL, NULL, NULL, NULL); + svip_register_asc(0); + svip_register_eth(); + svip_register_virtual_eth(); + ltq_register_wdt(); + svip_register_gpio(); + svip_register_spi(); + svip_register_nand(); +} + +MIPS_MACHINE(LANTIQ_MACH_EASY33016, + "EASY33016", + "EASY33016", + easy33016_init); diff --git a/target/linux/lantiq/files-3.3/arch/mips/lantiq/svip/mach-easy336.c b/target/linux/lantiq/files-3.3/arch/mips/lantiq/svip/mach-easy336.c new file mode 100644 index 000000000..460bb7d85 --- /dev/null +++ b/target/linux/lantiq/files-3.3/arch/mips/lantiq/svip/mach-easy336.c @@ -0,0 +1,221 @@ +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/leds.h> +#include <linux/gpio.h> +#include <linux/gpio_buttons.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> +#include <linux/input.h> +#include <linux/interrupt.h> +#include <linux/spi/spi.h> +#include <linux/spi/flash.h> +#include "../machtypes.h" + +#include <sys1_reg.h> +#include <sys2_reg.h> +#include <svip_pms.h> + +#include "devices.h" + +static struct mtd_partition easy336_sflash_partitions[] = { + { + .name = "SPI flash", + .size = MTDPART_SIZ_FULL, + .offset = 0, + }, +}; + +static struct flash_platform_data easy336_sflash_data = { + .name = "m25p32", + .parts = (void *)&easy336_sflash_partitions, + .nr_parts = ARRAY_SIZE(easy336_sflash_partitions), + .type = "m25p32", +}; + +static struct spi_board_info bdinfo[] __initdata = { + { + .modalias = "m25p80", + .platform_data = &easy336_sflash_data, + .mode = SPI_MODE_0, + .irq = -1, + .max_speed_hz = 25000000, + .bus_num = 0, + .chip_select = 0, + } +}; + +static struct mtd_partition easy336_partitions[] = { + { + .name = "uboot", + .offset = 0x0, + .size = 0x40000, + }, + { + .name = "uboot_env", + .offset = 0x40000, + .size = 0x20000, + }, + { + .name = "linux", + .offset = 0x60000, + .size = 0x1a0000, + }, + { + .name = "rootfs", + .offset = 0x200000, + .size = 0x500000, + }, +}; + +static struct physmap_flash_data easy336_flash_data = { + .nr_parts = ARRAY_SIZE(easy336_partitions), + .parts = easy336_partitions, +}; + +static const struct ltq_mux_pin mux_p0[LTQ_MUX_P0_PINS] = { + LTQ_MUX_P0_0_SSC0_MTSR, + LTQ_MUX_P0_1_SSC0_MRST, + LTQ_MUX_P0_2_SSC0_SCLK, + LTQ_MUX_P0_3_SSC1_MTSR, + LTQ_MUX_P0_4_SSC1_MRST, + LTQ_MUX_P0_5_SSC1_SCLK, + LTQ_MUX_P0_6_SSC0_CS0, + LTQ_MUX_P0_7_SSC0_CS1, + LTQ_MUX_P0_8_SSC0_CS2, + LTQ_MUX_P0_9_SSC0_CS3, + LTQ_MUX_P0_10_SSC0_CS4, + LTQ_MUX_P0_11_SSC0_CS5, + LTQ_MUX_P0_12_EXINT5, + LTQ_MUX_P0_13_EXINT6, + LTQ_MUX_P0_14_ASC0_TXD, + LTQ_MUX_P0_15_ASC0_RXD, + LTQ_MUX_P0_16_EXINT9, + LTQ_MUX_P0_17_EXINT10, + LTQ_MUX_P0_18_EJ_BRKIN, + LTQ_MUX_P0_19_EXINT16 +}; + +static const struct ltq_mux_pin mux_p2[LTQ_MUX_P2_PINS] = { + LTQ_MUX_P2_0_EBU_A0, + LTQ_MUX_P2_1_EBU_A1, + LTQ_MUX_P2_2_EBU_A2, + LTQ_MUX_P2_3_EBU_A3, + LTQ_MUX_P2_4_EBU_A4, + LTQ_MUX_P2_5_EBU_A5, + LTQ_MUX_P2_6_EBU_A6, + LTQ_MUX_P2_7_EBU_A7, + LTQ_MUX_P2_8_EBU_A8, + LTQ_MUX_P2_9_EBU_A9, + LTQ_MUX_P2_10_EBU_A10, + LTQ_MUX_P2_11_EBU_A11, + LTQ_MUX_P2_12_EBU_RD, + LTQ_MUX_P2_13_EBU_WR, + LTQ_MUX_P2_14_EBU_ALE, + LTQ_MUX_P2_15_EBU_WAIT, + LTQ_MUX_P2_16_EBU_RDBY, + LTQ_MUX_P2_17_EBU_BC0, + LTQ_MUX_P2_18_EBU_BC1 +}; + +static const struct ltq_mux_pin mux_p3[LTQ_MUX_P3_PINS] = { + LTQ_MUX_P3_0_EBU_AD0, + LTQ_MUX_P3_1_EBU_AD1, + LTQ_MUX_P3_2_EBU_AD2, + LTQ_MUX_P3_3_EBU_AD3, + LTQ_MUX_P3_4_EBU_AD4, + LTQ_MUX_P3_5_EBU_AD5, + LTQ_MUX_P3_6_EBU_AD6, + LTQ_MUX_P3_7_EBU_AD7, + LTQ_MUX_P3_8_EBU_AD8, + LTQ_MUX_P3_9_EBU_AD9, + LTQ_MUX_P3_10_EBU_AD10, + LTQ_MUX_P3_11_EBU_AD11, + LTQ_MUX_P3_12_EBU_AD12, + LTQ_MUX_P3_13_EBU_AD13, + LTQ_MUX_P3_14_EBU_AD14, + LTQ_MUX_P3_15_EBU_AD15, + LTQ_MUX_P3_16_EBU_CS0, + LTQ_MUX_P3_17_EBU_CS1, + LTQ_MUX_P3_18_EBU_CS2, + LTQ_MUX_P3_19_EBU_CS3 +}; + +static void __init easy336_init_common(void) +{ + svip_sys1_clk_enable(SYS1_CLKENR_L2C | + SYS1_CLKENR_DDR2 | + SYS1_CLKENR_SMI2 | + SYS1_CLKENR_SMI1 | + SYS1_CLKENR_SMI0 | + SYS1_CLKENR_FMI0 | + SYS1_CLKENR_DMA | + SYS1_CLKENR_GPTC | + SYS1_CLKENR_EBU); + + svip_sys2_clk_enable(SYS2_CLKENR_HWSYNC | + SYS2_CLKENR_MBS | + SYS2_CLKENR_SWINT | + SYS2_CLKENR_HWACC3 | + SYS2_CLKENR_HWACC2 | + SYS2_CLKENR_HWACC1 | + SYS2_CLKENR_HWACC0 | + SYS2_CLKENR_SIF7 | + SYS2_CLKENR_SIF6 | + SYS2_CLKENR_SIF5 | + SYS2_CLKENR_SIF4 | + SYS2_CLKENR_SIF3 | + SYS2_CLKENR_SIF2 | + SYS2_CLKENR_SIF1 | + SYS2_CLKENR_SIF0 | + SYS2_CLKENR_DFEV7 | + SYS2_CLKENR_DFEV6 | + SYS2_CLKENR_DFEV5 | + SYS2_CLKENR_DFEV4 | + SYS2_CLKENR_DFEV3 | + SYS2_CLKENR_DFEV2 | + SYS2_CLKENR_DFEV1 | + SYS2_CLKENR_DFEV0); + + svip_register_mux(mux_p0, NULL, mux_p2, mux_p3, NULL); + svip_register_asc(0); + svip_register_eth(); + svip_register_virtual_eth(); + /* ltq_register_wdt(); - conflicts with lq_switch */ + svip_register_gpio(); + svip_register_spi(); + ltq_register_tapi(); +} + +static void __init easy336_init(void) +{ + easy336_init_common(); + ltq_register_nor(&easy336_flash_data); +} + +static void __init easy336sf_init(void) +{ + easy336_init_common(); + svip_register_spi_flash(bdinfo); +} + +static void __init easy336nand_init(void) +{ + easy336_init_common(); + svip_register_nand(); +} + +MIPS_MACHINE(LANTIQ_MACH_EASY336, + "EASY336", + "EASY336", + easy336_init); + +MIPS_MACHINE(LANTIQ_MACH_EASY336SF, + "EASY336SF", + "EASY336 (Serial Flash)", + easy336sf_init); + +MIPS_MACHINE(LANTIQ_MACH_EASY336NAND, + "EASY336NAND", + "EASY336 (NAND Flash)", + easy336nand_init); + diff --git a/target/linux/lantiq/files-3.3/arch/mips/lantiq/svip/mux.c b/target/linux/lantiq/files-3.3/arch/mips/lantiq/svip/mux.c new file mode 100644 index 000000000..56805e55b --- /dev/null +++ b/target/linux/lantiq/files-3.3/arch/mips/lantiq/svip/mux.c @@ -0,0 +1,187 @@ +/************************************************************************ + * + * Copyright (c) 2007 + * Infineon Technologies AG + * St. Martin Strasse 53; 81669 Muenchen; Germany + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + ************************************************************************/ + +#include <linux/module.h> +#include <linux/types.h> +#include <linux/kernel.h> +#include <linux/proc_fs.h> +#include <linux/init.h> +#include <asm/addrspace.h> +#include <linux/platform_device.h> + +#include <lantiq_soc.h> +#include <svip_mux.h> +#include <sys1_reg.h> +#include <sys2_reg.h> +#include <svip_pms.h> + +#define DRV_NAME "ltq_mux" + +static void ltq_mux_port_init(const int port, + const struct ltq_mux_pin *pins, + const int pin_max) +{ + unsigned int i; + + for (i = 0; i < pin_max; i++) + ltq_gpio_configure(port, + i, + pins[i].dirin, + pins[i].puen, + pins[i].altsel0, + pins[i].altsel1); +} + +static int ltq_mux_probe(struct platform_device *pdev) +{ + struct ltq_mux_settings *mux_settings = dev_get_platdata(&pdev->dev); + + if (mux_settings->mux_p0) + ltq_mux_port_init(0, + mux_settings->mux_p0, + LTQ_MUX_P0_PINS); + + if (mux_settings->mux_p1) + ltq_mux_port_init(1, + mux_settings->mux_p1, + LTQ_MUX_P1_PINS); + + if (mux_settings->mux_p2) + ltq_mux_port_init(2, + mux_settings->mux_p2, + LTQ_MUX_P2_PINS); + + if (mux_settings->mux_p3) + ltq_mux_port_init(3, + mux_settings->mux_p3, + LTQ_MUX_P3_PINS); + + if (mux_settings->mux_p4) + ltq_mux_port_init(4, + mux_settings->mux_p4, + LTQ_MUX_P4_PINS); + + return 0; +} + +int ltq_mux_read_procmem(char *buf, char **start, off_t offset, + int count, int *eof, void *data) +{ + int len = 0; + int t = 0, i = 0; + u32 port_clk[5] = { + SYS1_CLKENR_PORT0, + SYS1_CLKENR_PORT1, + SYS1_CLKENR_PORT2, + SYS1_CLKENR_PORT3, + SYS2_CLKENR_PORT4, + }; + +#define PROC_PRINT(fmt, args...) \ + do { \ + int c_len = 0; \ + c_len = snprintf(buf + len, count - len, fmt, ## args); \ + if (c_len <= 0) \ + goto out; \ + if (c_len >= (count - len)) { \ + len += (count - len); \ + goto out; \ + } \ + len += c_len; \ + if (offset > 0) { \ + if (len > offset) { \ + len -= offset; \ + memmove(buf, buf + offset, len); \ + offset = 0; \ + } else { \ + offset -= len; \ + len = 0; \ + } \ + } \ + } while (0) + + PROC_PRINT("\nVINETIC-SVIP Multiplex Settings\n"); + PROC_PRINT(" 3 2 1 0\n"); + PROC_PRINT(" 10987654321098765432109876543210\n"); + PROC_PRINT(" --------------------------------\n"); + + for (i = 0; i < ARRAY_SIZE(port_clk); i++) { + if (i < 4) { + if (!svip_sys1_clk_is_enabled(port_clk[i])) + continue; + } else { + if (!svip_sys2_clk_is_enabled(port_clk[i])) + continue; + } + + PROC_PRINT("P%d.%-10s", i, "DIR:"); + + for (t = 31; t != -1; t--) + PROC_PRINT("%d", ltq_port_get_dir(i, t) == 1 ? 1 : 0); + PROC_PRINT("\n"); + + PROC_PRINT("P%d.%-10s", i, "PUEN:"); + for (t = 31; t != -1; t--) + PROC_PRINT("%d", ltq_port_get_puden(i, t) == 1 ? 1 : 0); + PROC_PRINT("\n"); + + PROC_PRINT("P%d.%-10s", i, "ALTSEL0:"); + for (t = 31; t != -1; t--) + PROC_PRINT("%d", + ltq_port_get_altsel0(i, t) == 1 ? 1 : 0); + PROC_PRINT("\n"); + + PROC_PRINT("P%d.%-10s", i, "ALTSEL1:"); + for (t = 31; t != -1; t--) + PROC_PRINT("%d", + ltq_port_get_altsel1(i, t) == 1 ? 1 : 0); + PROC_PRINT("\n\n"); + } + +out: + if (len < 0) { + len = 0; + *eof = 1; + } else if (len < count) { + *eof = 1; + } else { + len = count; + } + + *start = buf; + + return len; +} + +static struct platform_driver ltq_mux_driver = { + .probe = ltq_mux_probe, + .driver = { + .name = DRV_NAME, + .owner = THIS_MODULE, + }, +}; + +int __init ltq_mux_init(void) +{ + int ret = platform_driver_register(<q_mux_driver); + if (ret) { + printk(KERN_INFO DRV_NAME + ": Error registering platform driver!"); + return ret; + } + + return create_proc_read_entry("driver/ltq_mux", 0, NULL, + ltq_mux_read_procmem, NULL) == NULL; +} + +module_init(ltq_mux_init); diff --git a/target/linux/lantiq/files-3.3/arch/mips/lantiq/svip/pms.c b/target/linux/lantiq/files-3.3/arch/mips/lantiq/svip/pms.c new file mode 100644 index 000000000..5c0c808a0 --- /dev/null +++ b/target/linux/lantiq/files-3.3/arch/mips/lantiq/svip/pms.c @@ -0,0 +1,101 @@ +/************************************************************************ + * + * Copyright (c) 2007 + * Infineon Technologies AG + * St. Martin Strasse 53; 81669 Muenchen; Germany + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + ************************************************************************/ + +#include <linux/module.h> +#include <linux/types.h> +#include <linux/kernel.h> +#include <linux/proc_fs.h> +#include <linux/init.h> +#include <asm/addrspace.h> + +#include <base_reg.h> +#include <sys1_reg.h> +#include <sys2_reg.h> +#include <lantiq_soc.h> + +static struct svip_reg_sys1 *const sys1 = (struct svip_reg_sys1 *)LTQ_SYS1_BASE; +static struct svip_reg_sys2 *const sys2 = (struct svip_reg_sys2 *)LTQ_SYS2_BASE; + +void svip_sys1_clk_enable(u32 mask) +{ + sys1_w32(sys1_r32(clksr) | mask, clkenr); + asm("sync;"); +} +EXPORT_SYMBOL(svip_sys1_clk_enable); + +int svip_sys1_clk_is_enabled(u32 mask) +{ + return (sys1_r32(clksr) & mask) != 0; +} +EXPORT_SYMBOL(svip_sys1_clk_is_enabled); + +void svip_sys2_clk_enable(u32 mask) +{ + sys2_w32(sys2_r32(clksr) | mask, clkenr); + asm("sync;"); +} +EXPORT_SYMBOL(svip_sys2_clk_enable); + +int svip_sys2_clk_is_enabled(u32 mask) +{ + return (sys2_r32(clksr) & mask) != 0; +} +EXPORT_SYMBOL(svip_sys2_clk_is_enabled); + +int ltq_pms_read_procmem(char *buf, char **start, off_t offset, + int count, int *eof, void *data) +{ + long len = 0; + int t = 0; + u32 bit = 0; + u32 reg_tmp, bits_tmp; + + len = sprintf(buf, "\nSVIP PMS Settings\n"); + len = len + sprintf(buf + len, + " 3 2 1 0\n"); + len = len + sprintf(buf + len, + " 210987654321098765432109876543210\n"); + len = len + sprintf(buf + len, + "---------------------------------------------\n"); + len = len + sprintf(buf + len, + "SYS1_CLKSR: "); + reg_tmp = sys1_r32(clksr); + bit = 0x80000000; + for (t = 31; t != -1; t--) { + bits_tmp = (reg_tmp & bit) >> t; + len = len + sprintf(buf + len, "%d", bits_tmp); + bit = bit >> 1; + } + len = len + sprintf(buf + len, "\n\n"); + len = len + sprintf(buf + len, "SYS2_CLKSR: "); + reg_tmp = sys2_r32(clksr); + bit = 0x80000000; + for (t = 31; t != -1; t--) { + bits_tmp = (reg_tmp & bit) >> t; + len = len + sprintf(buf + len, "%d", bits_tmp); + bit = bit >> 1; + } + len = len + sprintf(buf + len, "\n\n"); + + *eof = 1; + + return len; +} + +int __init ltq_pms_init_proc(void) +{ + return create_proc_read_entry("driver/ltq_pms", 0, NULL, + ltq_pms_read_procmem, NULL) == NULL; +} + +module_init(ltq_pms_init_proc); diff --git a/target/linux/lantiq/files-3.3/arch/mips/lantiq/svip/prom.c b/target/linux/lantiq/files-3.3/arch/mips/lantiq/svip/prom.c new file mode 100644 index 000000000..1c1753160 --- /dev/null +++ b/target/linux/lantiq/files-3.3/arch/mips/lantiq/svip/prom.c @@ -0,0 +1,73 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * Copyright (C) 2010 John Crispin <blogic@openwrt.org> + */ + +#include <linux/module.h> +#include <linux/clk.h> +#include <linux/time.h> +#include <asm/bootinfo.h> + +#include <lantiq_soc.h> + +#include "../prom.h" +#include "../clk.h" +#include "../machtypes.h" + +#include <base_reg.h> +#include <ebu_reg.h> + +#define SOC_SVIP "SVIP" + +#define PART_SHIFT 12 +#define PART_MASK 0x0FFFF000 +#define REV_SHIFT 28 +#define REV_MASK 0xF0000000 + +static struct svip_reg_ebu *const ebu = (struct svip_reg_ebu *)LTQ_EBU_BASE; + +void __init ltq_soc_init(void) +{ + clkdev_add_static(ltq_svip_cpu_hz(), ltq_svip_fpi_hz(), + ltq_svip_io_region_clock()); +} + +void __init +ltq_soc_setup(void) +{ + if (mips_machtype == LANTIQ_MACH_EASY33016 || + mips_machtype == LANTIQ_MACH_EASY336) { + ebu_w32(0x120000f1, addr_sel_2); + ebu_w32(LTQ_EBU_CON_0_ADSWP | + LTQ_EBU_CON_0_SETUP | + LTQ_EBU_CON_0_BCGEN_VAL(0x02) | + LTQ_EBU_CON_0_WAITWRC_VAL(7) | + LTQ_EBU_CON_0_WAITRDC_VAL(3) | + LTQ_EBU_CON_0_HOLDC_VAL(3) | + LTQ_EBU_CON_0_RECOVC_VAL(3) | + LTQ_EBU_CON_0_CMULT_VAL(3), con_2); + } +} + +void __init +ltq_soc_detect(struct ltq_soc_info *i) +{ + i->partnum = (ltq_r32(LTQ_STATUS_CHIPID) & PART_MASK) >> PART_SHIFT; + i->rev = (ltq_r32(LTQ_STATUS_CHIPID) & REV_MASK) >> REV_SHIFT; + sprintf(i->rev_type, "1.%d", i->rev); + switch (i->partnum) { + case SOC_ID_SVIP: + i->name = SOC_SVIP; + i->type = SOC_TYPE_SVIP; + break; + + default: + printk(KERN_ERR "unknown partnum : 0x%08X\n", i->partnum); + while (1); + break; + } +} diff --git a/target/linux/lantiq/files-3.3/arch/mips/lantiq/svip/reset.c b/target/linux/lantiq/files-3.3/arch/mips/lantiq/svip/reset.c new file mode 100644 index 000000000..5551875da --- /dev/null +++ b/target/linux/lantiq/files-3.3/arch/mips/lantiq/svip/reset.c @@ -0,0 +1,95 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin <blogic@openwrt.org> + */ + +#include <linux/init.h> +#include <linux/io.h> +#include <linux/ioport.h> +#include <linux/pm.h> +#include <linux/module.h> +#include <asm/reboot.h> + +#include <lantiq_soc.h> +#include "../machtypes.h" +#include <base_reg.h> +#include <sys1_reg.h> +#include <boot_reg.h> +#include <ebu_reg.h> + +static struct svip_reg_sys1 *const sys1 = (struct svip_reg_sys1 *)LTQ_SYS1_BASE; +static struct svip_reg_ebu *const ebu = (struct svip_reg_ebu *)LTQ_EBU_BASE; + +#define CPLD_CMDREG3 ((volatile unsigned char*)(KSEG1 + 0x120000f3)) +extern void switchip_reset(void); + +static void ltq_machine_restart(char *command) +{ + printk(KERN_NOTICE "System restart\n"); + local_irq_disable(); + + if (mips_machtype == LANTIQ_MACH_EASY33016 || + mips_machtype == LANTIQ_MACH_EASY336) { + /* We just use the CPLD function to reset the entire system as a + workaround for the switch reset problem */ + local_irq_disable(); + ebu_w32(0x120000f1, addr_sel_2); + ebu_w32(0x404027ff, con_2); + + if (mips_machtype == LANTIQ_MACH_EASY336) + /* set bit 0 to reset SVIP */ + *CPLD_CMDREG3 = (1<<0); + else + /* set bit 7 to reset SVIP, set bit 3 to reset xT */ + *CPLD_CMDREG3 = (1<<7) | (1<<3); + } else { + *LTQ_BOOT_RVEC(0) = 0; + /* reset all except PER, SUBSYS and CPU0 */ + sys1_w32(0x00043F3E, rreqr); + /* release WDT0 reset */ + sys1_w32(0x00000100, rrlsr); + /* restore reset value for clock enables */ + sys1_w32(~0x0c000040, clkclr); + /* reset SUBSYS (incl. DDR2) and CPU0 */ + sys1_w32(0x00030001, rbtr); + } + + for (;;) + ; +} + +static void ltq_machine_halt(void) +{ + printk(KERN_NOTICE "System halted.\n"); + local_irq_disable(); + for (;;) + ; +} + +static void ltq_machine_power_off(void) +{ + printk(KERN_NOTICE "Please turn off the power now.\n"); + local_irq_disable(); + for (;;) + ; +} + +/* This function is used by the watchdog driver */ +int ltq_reset_cause(void) +{ + return 0; +} +EXPORT_SYMBOL_GPL(ltq_reset_cause); + +static int __init mips_reboot_setup(void) +{ + _machine_restart = ltq_machine_restart; + _machine_halt = ltq_machine_halt; + pm_power_off = ltq_machine_power_off; + return 0; +} + +arch_initcall(mips_reboot_setup); diff --git a/target/linux/lantiq/files-3.3/arch/mips/lantiq/svip/switchip_setup.c b/target/linux/lantiq/files-3.3/arch/mips/lantiq/svip/switchip_setup.c new file mode 100644 index 000000000..5da15327e --- /dev/null +++ b/target/linux/lantiq/files-3.3/arch/mips/lantiq/svip/switchip_setup.c @@ -0,0 +1,666 @@ +/****************************************************************************** + Copyright (c) 2007, Infineon Technologies. All rights reserved. + + No Warranty + Because the program is licensed free of charge, there is no warranty for + the program, to the extent permitted by applicable law. Except when + otherwise stated in writing the copyright holders and/or other parties + provide the program "as is" without warranty of any kind, either + expressed or implied, including, but not limited to, the implied + warranties of merchantability and fitness for a particular purpose. The + entire risk as to the quality and performance of the program is with + you. should the program prove defective, you assume the cost of all + necessary servicing, repair or correction. + + In no event unless required by applicable law or agreed to in writing + will any copyright holder, or any other party who may modify and/or + redistribute the program as permitted above, be liable to you for + damages, including any general, special, incidental or consequential + damages arising out of the use or inability to use the program + (including but not limited to loss of data or data being rendered + inaccurate or losses sustained by you or third parties or a failure of + the program to operate with any other programs), even if such holder or + other party has been advised of the possibility of such damages. + ****************************************************************************** + Module : switchip_setup.c + Date : 2007-11-09 + Description : Basic setup of embedded ethernet switch "SwitchIP" + Remarks: andreas.schmidt@infineon.com + + *****************************************************************************/ + +/* TODO: get rid of #ifdef CONFIG_LANTIQ_MACH_EASY336 */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/version.h> +#include <linux/init.h> +#include <linux/delay.h> +#include <linux/workqueue.h> +#include <linux/time.h> + +#include <base_reg.h> +#include <es_reg.h> +#include <sys1_reg.h> +#include <dma_reg.h> +#include <lantiq_soc.h> + +static struct svip_reg_sys1 *const sys1 = (struct svip_reg_sys1 *)LTQ_SYS1_BASE; +static struct svip_reg_es *const es = (struct svip_reg_es *)LTQ_ES_BASE; + +/* PHY Organizationally Unique Identifier (OUI) */ +#define PHY_OUI_PMC 0x00E004 +#define PHY_OUI_VITESSE 0x008083 +#define PHY_OUI_DEFAULT 0xFFFFFF + +unsigned short switchip_phy_read(unsigned int phyaddr, unsigned int regaddr); +void switchip_phy_write(unsigned int phyaddr, unsigned int regaddr, + unsigned short data); + +static int phy_address[2] = {0, 1}; +static u32 phy_oui; +static void switchip_mdio_poll_init(void); +static void _switchip_mdio_poll(struct work_struct *work); + +/* struct workqueue_struct mdio_poll_task; */ +static struct workqueue_struct *mdio_poll_workqueue; +DECLARE_DELAYED_WORK(mdio_poll_work, _switchip_mdio_poll); +static int old_link_status[2] = {-1, -1}; + +/** + * Autonegotiation check. + * This funtion checks for link changes. If a link change has occured it will + * update certain switch registers. + */ +static void _switchip_check_phy_status(int port) +{ + int new_link_status; + unsigned short reg1; + + reg1 = switchip_phy_read(phy_address[port], 1); + if ((reg1 == 0xFFFF) || (reg1 == 0x0000)) + return; /* no PHY connected */ + + new_link_status = reg1 & 4; + if (old_link_status[port] ^ new_link_status) { + /* link status change */ + if (!new_link_status) { + if (port == 0) + es_w32_mask(LTQ_ES_P0_CTL_REG_FLP, 0, p0_ctl); + else + es_w32_mask(LTQ_ES_P0_CTL_REG_FLP, 0, p1_ctl); + + /* read again; link bit is latched low! */ + reg1 = switchip_phy_read(phy_address[port], 1); + new_link_status = reg1 & 4; + } + + if (new_link_status) { + unsigned short reg0, reg4, reg5, reg9, reg10; + int phy_pause, phy_speed, phy_duplex; + int aneg_enable, aneg_cmpt; + + reg0 = switchip_phy_read(phy_address[port], 0); + reg4 = switchip_phy_read(phy_address[port], 4); + aneg_enable = reg0 & 0x1000; + aneg_cmpt = reg1 & 0x20; + + if (aneg_enable && aneg_cmpt) { + reg5 = switchip_phy_read(phy_address[port], 5); + switch (phy_oui) { +#ifdef CONFIG_LANTIQ_MACH_EASY336 + case PHY_OUI_PMC: + /* PMC Sierra supports 1Gigabit FD, + * only. On successful + * auto-negotiation, we are sure this + * is what the LP can. */ + phy_pause = ((reg4 & reg5) & 0x0080) >> 7; + phy_speed = 2; + phy_duplex = 1; + break; +#endif + case PHY_OUI_VITESSE: + case PHY_OUI_DEFAULT: + reg9 = switchip_phy_read(phy_address[port], 9); + reg10 = switchip_phy_read(phy_address[port], 10); + + /* Check if advertise and partner + * agree on pause */ + phy_pause = ((reg4 & reg5) & 0x0400) >> 10; + + /* Find the best mode both partners + * support + * Priority: 1GB-FD, 1GB-HD, 100MB-FD, + * 100MB-HD, 10MB-FD, 10MB-HD */ + phy_speed = ((((reg9<<2) & reg10) + & 0x0c00) >> 6) | + (((reg4 & reg5) & 0x01e0) >> 5); + + if (phy_speed >= 0x0020) { + phy_speed = 2; + phy_duplex = 1; + } else if (phy_speed >= 0x0010) { + phy_speed = 2; + phy_duplex = 0; + } else if (phy_speed >= 0x0008) { + phy_speed = 1; + phy_duplex = 1; + } else if (phy_speed >= 0x0004) { + phy_speed = 1; + phy_duplex = 0; + } else if (phy_speed >= 0x0002) { + phy_speed = 0; + phy_duplex = 1; + } else { + phy_speed = 0; + phy_duplex = 0; + } + break; + default: + phy_pause = (reg4 & 0x0400) >> 10; + phy_speed = (reg0 & 0x40 ? 2 : (reg0 >> 13)&1); + phy_duplex = (reg0 >> 8)&1; + break; + } + } else { + /* parallel detection or fixed speed */ + phy_pause = (reg4 & 0x0400) >> 10; + phy_speed = (reg0 & 0x40 ? 2 : (reg0 >> 13)&1); + phy_duplex = (reg0 >> 8)&1; + } + + if (port == 0) { + es_w32_mask(LTQ_ES_RGMII_CTL_REG_P0SPD, + LTQ_ES_RGMII_CTL_REG_P0SPD_VAL(phy_speed), + rgmii_ctl); + es_w32_mask(LTQ_ES_RGMII_CTL_REG_P0DUP, + LTQ_ES_RGMII_CTL_REG_P0DUP_VAL(phy_duplex), + rgmii_ctl); + es_w32_mask(LTQ_ES_RGMII_CTL_REG_P0FCE, + LTQ_ES_RGMII_CTL_REG_P0FCE_VAL(phy_pause), + rgmii_ctl); + + es_w32_mask(0, LTQ_ES_P0_CTL_REG_FLP, p0_ctl); + } else { + es_w32_mask(LTQ_ES_RGMII_CTL_REG_P1SPD, + LTQ_ES_RGMII_CTL_REG_P1SPD_VAL(phy_speed), + rgmii_ctl); + es_w32_mask(LTQ_ES_RGMII_CTL_REG_P1DUP, + LTQ_ES_RGMII_CTL_REG_P1DUP_VAL(phy_duplex), + rgmii_ctl); + es_w32_mask(LTQ_ES_RGMII_CTL_REG_P1FCE, + LTQ_ES_RGMII_CTL_REG_P0FCE_VAL(phy_pause), + rgmii_ctl); + + es_w32_mask(1, LTQ_ES_P0_CTL_REG_FLP, p1_ctl); + } + } + } + old_link_status[port] = new_link_status; +} + +static void _switchip_mdio_poll(struct work_struct *work) +{ + if (es_r32(sw_gctl0) & LTQ_ES_SW_GCTL0_REG_SE) { + _switchip_check_phy_status(0); + _switchip_check_phy_status(1); + } + + queue_delayed_work(mdio_poll_workqueue, &mdio_poll_work, HZ/2); +} + +static void switchip_mdio_poll_init(void) +{ + mdio_poll_workqueue = create_workqueue("SVIP MDIP poll"); + INIT_DELAYED_WORK(&mdio_poll_work, _switchip_mdio_poll); + + queue_delayed_work(mdio_poll_workqueue, &mdio_poll_work, HZ/2); + +} + +unsigned short switchip_phy_read(unsigned int phyaddr, unsigned int regaddr) +{ + /* TODO: protect MDIO access with semaphore */ + es_w32(LTQ_ES_MDIO_CTL_REG_MBUSY + | LTQ_ES_MDIO_CTL_REG_OP_VAL(2) /* read operation */ + | LTQ_ES_MDIO_CTL_REG_PHYAD_VAL(phyaddr) + | LTQ_ES_MDIO_CTL_REG_REGAD_VAL(regaddr), mdio_ctl); + while (es_r32(mdio_ctl) & LTQ_ES_MDIO_CTL_REG_MBUSY); + + return es_r32(mdio_data) & 0xFFFF; +} +EXPORT_SYMBOL(switchip_phy_read); + +void switchip_phy_write(unsigned int phyaddr, unsigned int regaddr, + unsigned short data) +{ + /* TODO: protect MDIO access with semaphore */ + es_w32(LTQ_ES_MDIO_CTL_REG_WD_VAL(data) + | LTQ_ES_MDIO_CTL_REG_MBUSY + | LTQ_ES_MDIO_CTL_REG_OP_VAL(1) /* write operation */ + | LTQ_ES_MDIO_CTL_REG_PHYAD_VAL(phyaddr) + | LTQ_ES_MDIO_CTL_REG_REGAD_VAL(regaddr), mdio_ctl); + while (es_r32(mdio_ctl) & LTQ_ES_MDIO_CTL_REG_MBUSY); + + return; +} +EXPORT_SYMBOL(switchip_phy_write); + +const static u32 switch_reset_offset_000[] = { + /*b8000000:*/ 0xffffffff, 0x00000001, 0x00000001, 0x00000003, + /*b8000010:*/ 0x04070001, 0x04070001, 0x04070001, 0xffffffff, + /*b8000020:*/ 0x00001be8, 0x00001be8, 0x00001be8, 0xffffffff, + /*b8000030:*/ 0x00000000, 0x00000000, 0x00080004, 0x00020001, + /*b8000040:*/ 0x00000000, 0x00000000, 0x00080004, 0x00020001, + /*b8000050:*/ 0x00000000, 0x00000000, 0x00080004, 0x00020001, + /*b8000060:*/ 0x00000000, 0x00000000, 0x00081000, 0x001f7777, + /*b8000070:*/ 0x00000000, 0x00000000, 0x0c00ac2b, 0x0000fa50, + /*b8000080:*/ 0x00001000, 0x00001800, 0x00000000, 0x00000000, + /*b8000090:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /*b80000a0:*/ 0x00000000, 0x00000050, 0x00000010, 0x00000000, + /*b80000b0:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /*b80000c0:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /*b80000d0:*/ 0xffffffff, 0x00000000, 0x00000000 +}; +const static u32 switch_reset_offset_100[] = { + /*b8000100:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /*b8000110:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /*b8000120:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /*b8000130:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /*b8000140:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /*b8000150:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /*b8000160:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /*b8000170:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /*b8000180:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /*b8000190:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /*b80001a0:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /*b80001b0:*/ 0x00000000, 0x00000000 +}; + +/* + * Switch Reset. + */ +void switchip_reset(void) +{ + volatile unsigned int *reg; + volatile unsigned int rdreg; + int i; + + sys1_w32(SYS1_CLKENR_ETHSW, clkenr); + asm("sync"); + + /* disable P0 */ + es_w32_mask(0, LTQ_ES_P0_CTL_REG_SPS_VAL(1), p0_ctl); + /* disable P1 */ + es_w32_mask(0, LTQ_ES_P0_CTL_REG_SPS_VAL(1), p1_ctl); + /* disable P2 */ + es_w32_mask(0, LTQ_ES_P0_CTL_REG_SPS_VAL(1), p2_ctl); + + /************************************** + * BEGIN: Procedure to clear MAC table + **************************************/ + for (i = 0; i < 3; i++) { + int result; + + /* check if access engine is available */ + while (es_r32(adr_tb_st2) & LTQ_ES_ADR_TB_ST2_REG_BUSY); + + /* initialise to first address */ + es_w32(LTQ_ES_ADR_TB_CTL2_REG_CMD_VAL(3) + | LTQ_ES_ADR_TB_CTL2_REG_AC_VAL(0), adr_tb_ctl2); + + /* wait while busy */ + while (es_r32(adr_tb_st2) & LTQ_ES_ADR_TB_ST2_REG_BUSY); + + /* setup the portmap */ + es_w32_mask(0, LTQ_ES_ADR_TB_CTL1_REG_PMAP_VAL(1 << i), + adr_tb_ctl1); + + do { + /* search for addresses by port */ + es_w32(LTQ_ES_ADR_TB_CTL2_REG_CMD_VAL(2) + | LTQ_ES_ADR_TB_CTL2_REG_AC_VAL(9), adr_tb_ctl2); + + /* wait while busy */ + while (es_r32(adr_tb_st2) & LTQ_ES_ADR_TB_ST2_REG_BUSY); + + result = LTQ_ES_ADR_TB_ST2_REG_RSLT_GET(es_r32(adr_tb_st2)); + if (result == 0x101) { + printk(KERN_ERR "%s, cmd error\n", __func__); + return; + } + /* if Command OK, address found... */ + if (result == 0) { + unsigned char mac[6]; + + mac[5] = (es_r32(adr_tb_st0) >> 0) & 0xff; + mac[4] = (es_r32(adr_tb_st0) >> 8) & 0xff; + mac[3] = (es_r32(adr_tb_st0) >> 16) & 0xff; + mac[2] = (es_r32(adr_tb_st0) >> 24) & 0xff; + mac[1] = (es_r32(adr_tb_st1) >> 0) & 0xff; + mac[0] = (es_r32(adr_tb_st1) >> 8) & 0xff; + + /* setup address */ + es_w32((mac[5] << 0) | + (mac[4] << 8) | + (mac[3] << 16) | + (mac[2] << 24), adr_tb_ctl0); + es_w32(LTQ_ES_ADR_TB_CTL1_REG_PMAP_VAL(1<<i) | + LTQ_ES_ADR_TB_CTL1_REG_FID_VAL(0) | + (mac[0] << 8) | + (mac[1] << 0), adr_tb_ctl1); + /* erase address */ + + es_w32(LTQ_ES_ADR_TB_CTL2_REG_CMD_VAL(1) | + LTQ_ES_ADR_TB_CTL2_REG_AC_VAL(15), + adr_tb_ctl2); + + /* wait, while busy */ + while (es_r32(adr_tb_st2) & + LTQ_ES_ADR_TB_ST2_REG_BUSY); + } + } while (result == 0); + } + /************************************** + * END: Procedure to clear MAC table + **************************************/ + + /* reset RMON counters */ + es_w32(LTQ_ES_RMON_CTL_REG_BAS | LTQ_ES_RMON_CTL_REG_CAC_VAL(3), + rmon_ctl); + + /* bring all registers to reset state */ + reg = LTQ_ES_PS_REG; + for (i = 0; i < ARRAY_SIZE(switch_reset_offset_000); i++) { + if ((reg == LTQ_ES_PS_REG) || + (reg >= LTQ_ES_ADR_TB_CTL0_REG && + reg <= LTQ_ES_ADR_TB_ST2_REG)) + continue; + + if (switch_reset_offset_000[i] != 0xFFFFFFFF) { + /* write reset value to register */ + *reg = switch_reset_offset_000[i]; + /* read register value back */ + rdreg = *reg; + if (reg == LTQ_ES_SW_GCTL1_REG) + rdreg &= ~LTQ_ES_SW_GCTL1_REG_BISTDN; + /* compare read value with written one */ + if (rdreg != switch_reset_offset_000[i]) { + printk(KERN_ERR "%s,%d: reg %08x mismatch " + "[has:%08x, expect:%08x]\n", + __func__, __LINE__, + (unsigned int)reg, rdreg, + switch_reset_offset_000[i]); + } + } + reg++; + } + + reg = LTQ_ES_VLAN_FLT0_REG; + for (i = 0; i < ARRAY_SIZE(switch_reset_offset_100); i++) { + *reg = switch_reset_offset_100[i]; + rdreg = *reg; + if (rdreg != switch_reset_offset_100[i]) { + printk(KERN_ERR "%s,%d: reg %08x mismatch " + "[has:%08x, expect:%08x]\n", __func__, __LINE__, + (unsigned int)reg, rdreg, + switch_reset_offset_100[i]); + } + reg++; + } +} +EXPORT_SYMBOL(switchip_reset); + +static u32 get_phy_oui(unsigned char phy_addr) +{ + u32 oui; + int i, bit, byte, shift, w; + u16 reg_id[2]; + + /* read PHY identifier registers 1 and 2 */ + reg_id[0] = switchip_phy_read(phy_addr, 2); + reg_id[1] = switchip_phy_read(phy_addr, 3); + + oui = 0; + w = 1; + shift = 7; + byte = 1; + for (i = 0, bit = 10; i <= 21; i++, bit++) { + oui |= ((reg_id[w] & (1<<bit)) ? 1 : 0) << shift; + if (!(shift % 8)) { + byte++; + if (byte == 2) + shift = 15; + else + shift = 21; + } else { + shift--; + } + if (w == 1 && bit == 15) { + bit = -1; + w = 0; + } + } + return oui; +} + +/* + * Switch Initialization. + */ +int switchip_init(void) +{ + int eth_port, phy_present = 0; + u16 reg, mode; + + sys1_w32(SYS1_CLKENR_ETHSW, clkenr); + asm("sync"); + + /* Enable Switch, if not already done so */ + if ((es_r32(sw_gctl0) & LTQ_ES_SW_GCTL0_REG_SE) == 0) + es_w32_mask(0, LTQ_ES_SW_GCTL0_REG_SE, sw_gctl0); + /* Wait for completion of MBIST */ + while (LTQ_ES_SW_GCTL1_REG_BISTDN_GET(es_r32(sw_gctl1)) == 0); + + switchip_reset(); + + mode = LTQ_ES_RGMII_CTL_REG_IS_GET(es_r32(rgmii_ctl)); + eth_port = (mode == 2 ? 1 : 0); + + /* Set the primary port(port toward backplane) as sniffer port, + changing from P2 which is the reset setting */ + es_w32_mask(LTQ_ES_SW_GCTL0_REG_SNIFFPN, + LTQ_ES_SW_GCTL0_REG_SNIFFPN_VAL(eth_port), + sw_gctl0); + + /* Point MDIO state machine to invalid PHY addresses 8 and 9 */ + es_w32_mask(0, LTQ_ES_SW_GCTL0_REG_PHYBA, sw_gctl0); + + /* Add CRC for packets from DMA to PMAC. + Remove CRC for packets from PMAC to DMA. */ + es_w32(LTQ_ES_PMAC_HD_CTL_RC | LTQ_ES_PMAC_HD_CTL_AC, pmac_hd_ctl); + + phy_oui = get_phy_oui(0); + switch (phy_oui) { +#ifdef CONFIG_LANTIQ_MACH_EASY336 + case PHY_OUI_PMC: + phy_address[0] = (mode == 2 ? -1 : 2); + phy_address[1] = (mode == 2 ? 2 : -1); + break; +#endif + case PHY_OUI_VITESSE: + default: + phy_oui = PHY_OUI_DEFAULT; + phy_address[0] = (mode == 2 ? 1 : 0); + phy_address[1] = (mode == 2 ? 0 : 1); + break; + } + + /****** PORT 0 *****/ + reg = switchip_phy_read(phy_address[0], 1); + if ((reg != 0x0000) && (reg != 0xffff)) { + /* PHY connected? */ + phy_present |= 1; + /* Set Rx- and TxDelay in case of RGMII */ + switch (mode) { + case 0: /* *RGMII,RGMII */ + case 2: /* RGMII,*GMII */ + /* program clock delay in PHY, not in SVIP */ + + es_w32_mask(LTQ_ES_RGMII_CTL_REG_P0RDLY, 0, rgmii_ctl); + es_w32_mask(LTQ_ES_RGMII_CTL_REG_P0TDLY, 0, rgmii_ctl); + if (phy_oui == PHY_OUI_VITESSE || + phy_oui == PHY_OUI_DEFAULT) { + switchip_phy_write(phy_address[0], 31, 0x0001); + switchip_phy_write(phy_address[0], 28, 0xA000); + switchip_phy_write(phy_address[0], 31, 0x0000); + } + default: + break; + } + if (phy_oui == PHY_OUI_VITESSE || + phy_oui == PHY_OUI_DEFAULT) { + /* Program PHY advertisements and + * restart auto-negotiation */ + switchip_phy_write(phy_address[0], 4, 0x05E1); + switchip_phy_write(phy_address[0], 9, 0x0300); + switchip_phy_write(phy_address[0], 0, 0x3300); + } else { + reg = switchip_phy_read(phy_address[1], 0); + reg |= 0x1000; /* auto-negotiation enable */ + switchip_phy_write(phy_address[1], 0, reg); + reg |= 0x0200; /* auto-negotiation restart */ + switchip_phy_write(phy_address[1], 0, reg); + } + } else { + /* Force SWITCH link with highest capability: + * 100M FD for MII + * 1G FD for GMII/RGMII + */ + switch (mode) { + case 1: /* *MII,MII */ + case 3: /* *MII,RGMII */ + es_w32_mask(0, LTQ_ES_RGMII_CTL_REG_P0SPD_VAL(1), + rgmii_ctl); + es_w32_mask(0, LTQ_ES_RGMII_CTL_REG_P0DUP_VAL(1), + rgmii_ctl); + break; + case 0: /* *RGMII,RGMII */ + case 2: /* RGMII,*GMII */ + es_w32_mask(0, LTQ_ES_RGMII_CTL_REG_P0SPD_VAL(2), + rgmii_ctl); + es_w32_mask(0, LTQ_ES_RGMII_CTL_REG_P0DUP_VAL(1), + rgmii_ctl); + + es_w32_mask(LTQ_ES_RGMII_CTL_REG_P0RDLY, 0, rgmii_ctl); + es_w32_mask(0, LTQ_ES_RGMII_CTL_REG_P0TDLY_VAL(2), + rgmii_ctl); + break; + } + + es_w32_mask(0, LTQ_ES_P0_CTL_REG_FLP, p0_ctl); + } + + /****** PORT 1 *****/ + reg = switchip_phy_read(phy_address[1], 1); + if ((reg != 0x0000) && (reg != 0xffff)) { + /* PHY connected? */ + phy_present |= 2; + /* Set Rx- and TxDelay in case of RGMII */ + switch (mode) { + case 0: /* *RGMII,RGMII */ + case 3: /* *MII,RGMII */ + /* program clock delay in PHY, not in SVIP */ + + es_w32_mask(LTQ_ES_RGMII_CTL_REG_P1RDLY, 0, rgmii_ctl); + es_w32_mask(LTQ_ES_RGMII_CTL_REG_P1TDLY, 0, rgmii_ctl); + if (phy_oui == PHY_OUI_VITESSE || + phy_oui == PHY_OUI_DEFAULT) { + switchip_phy_write(phy_address[1], 31, 0x0001); + switchip_phy_write(phy_address[1], 28, 0xA000); + switchip_phy_write(phy_address[1], 31, 0x0000); + } + break; + case 2: /* RGMII,*GMII */ + + es_w32_mask(0, LTQ_ES_RGMII_CTL_REG_P1SPD_VAL(2), + rgmii_ctl); + es_w32_mask(0, LTQ_ES_RGMII_CTL_REG_P1DUP, rgmii_ctl); +#ifdef CONFIG_LANTIQ_MACH_EASY336 + if (phy_oui == PHY_OUI_PMC) { + switchip_phy_write(phy_address[1], 24, 0x0510); + switchip_phy_write(phy_address[1], 17, 0xA38C); + switchip_phy_write(phy_address[1], 17, 0xA384); + } +#endif + break; + default: + break; + } + /* Program PHY advertisements and restart auto-negotiation */ + if (phy_oui == PHY_OUI_VITESSE || + phy_oui == PHY_OUI_DEFAULT) { + switchip_phy_write(phy_address[1], 4, 0x05E1); + switchip_phy_write(phy_address[1], 9, 0x0300); + switchip_phy_write(phy_address[1], 0, 0x3300); + } else { + reg = switchip_phy_read(phy_address[1], 0); + reg |= 0x1000; /* auto-negotiation enable */ + switchip_phy_write(phy_address[1], 0, reg); + reg |= 0x0200; /* auto-negotiation restart */ + switchip_phy_write(phy_address[1], 0, reg); + } + } else { + /* Force SWITCH link with highest capability: + * 100M FD for MII + * 1G FD for GMII/RGMII + */ + switch (mode) { + case 1: /* *MII,MII */ + es_w32_mask(0, LTQ_ES_RGMII_CTL_REG_P1SPD_VAL(1), + rgmii_ctl); + es_w32_mask(0, LTQ_ES_RGMII_CTL_REG_P1DUP, rgmii_ctl); + break; + case 0: /* *RGMII,RGMII */ + case 3: /* *MII,RGMII */ + es_w32_mask(0, LTQ_ES_RGMII_CTL_REG_P1SPD_VAL(2), + rgmii_ctl); + es_w32_mask(0, LTQ_ES_RGMII_CTL_REG_P1DUP, rgmii_ctl); + es_w32_mask(LTQ_ES_RGMII_CTL_REG_P1RDLY, 0, rgmii_ctl); + es_w32_mask(0, LTQ_ES_RGMII_CTL_REG_P1TDLY_VAL(2), + rgmii_ctl); + break; + case 2: /* RGMII,*GMII */ + es_w32_mask(0, LTQ_ES_RGMII_CTL_REG_P1SPD_VAL(2), + rgmii_ctl); + es_w32_mask(0, LTQ_ES_RGMII_CTL_REG_P1DUP, rgmii_ctl); + break; + } + es_w32_mask(0, LTQ_ES_P0_CTL_REG_FLP, p0_ctl); + } + + /* + * Allow unknown unicast/multicast and broadcasts + * on all ports. + */ + + es_w32_mask(0, LTQ_ES_SW_GCTL1_REG_UP_VAL(7), sw_gctl1); + es_w32_mask(0, LTQ_ES_SW_GCTL1_REG_BP_VAL(7), sw_gctl1); + es_w32_mask(0, LTQ_ES_SW_GCTL1_REG_MP_VAL(7), sw_gctl1); + es_w32_mask(0, LTQ_ES_SW_GCTL1_REG_RP_VAL(7), sw_gctl1); + + /* Enable LAN port(s) */ + if (eth_port == 0) + es_w32_mask(LTQ_ES_P0_CTL_REG_SPS, 0, p0_ctl); + else + es_w32_mask(LTQ_ES_P0_CTL_REG_SPS, 0, p1_ctl); + /* Enable CPU Port (Forwarding State) */ + es_w32_mask(LTQ_ES_P0_CTL_REG_SPS, 0, p2_ctl); + + if (phy_present) + switchip_mdio_poll_init(); + + return 0; +} +EXPORT_SYMBOL(switchip_init); + +device_initcall(switchip_init); diff --git a/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/clk.c b/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/clk.c new file mode 100644 index 000000000..5d850dc7b --- /dev/null +++ b/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/clk.c @@ -0,0 +1,329 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin <blogic@openwrt.org> + */ + +#include <linux/io.h> +#include <linux/export.h> +#include <linux/init.h> +#include <linux/clk.h> + +#include <asm/time.h> +#include <asm/irq.h> +#include <asm/div64.h> + +#include <lantiq_soc.h> + +#include "../clk.h" + +static unsigned int ltq_ram_clocks[] = { + CLOCK_167M, CLOCK_133M, CLOCK_111M, CLOCK_83M }; +#define DDR_HZ ltq_ram_clocks[ltq_cgu_r32(LTQ_CGU_SYS) & 0x3] + +#define BASIC_FREQUENCY_1 35328000 +#define BASIC_FREQUENCY_2 36000000 +#define BASIS_REQUENCY_USB 12000000 + +#define GET_BITS(x, msb, lsb) \ + (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb)) + +/* legacy xway clock */ +#define LTQ_CGU_PLL0_CFG 0x0004 +#define LTQ_CGU_PLL1_CFG 0x0008 +#define LTQ_CGU_PLL2_CFG 0x000C +#define LTQ_CGU_SYS 0x0010 +#define LTQ_CGU_UPDATE 0x0014 +#define LTQ_CGU_IF_CLK 0x0018 +#define LTQ_CGU_OSC_CON 0x001C +#define LTQ_CGU_SMD 0x0020 +#define LTQ_CGU_CT1SR 0x0028 +#define LTQ_CGU_CT2SR 0x002C +#define LTQ_CGU_PCMCR 0x0030 +#define LTQ_CGU_PCI_CR 0x0034 +#define LTQ_CGU_PD_PC 0x0038 +#define LTQ_CGU_FMR 0x003C + +#define CGU_PLL0_PHASE_DIVIDER_ENABLE \ + (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 31)) +#define CGU_PLL0_BYPASS \ + (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 30)) +#define CGU_PLL0_CFG_DSMSEL \ + (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 28)) +#define CGU_PLL0_CFG_FRAC_EN \ + (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 27)) +#define CGU_PLL1_SRC \ + (ltq_cgu_r32(LTQ_CGU_PLL1_CFG) & (1 << 31)) +#define CGU_PLL2_PHASE_DIVIDER_ENABLE \ + (ltq_cgu_r32(LTQ_CGU_PLL2_CFG) & (1 << 20)) +#define CGU_SYS_FPI_SEL (1 << 6) +#define CGU_SYS_DDR_SEL 0x3 +#define CGU_PLL0_SRC (1 << 29) + +#define CGU_PLL0_CFG_PLLK GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 26, 17) +#define CGU_PLL0_CFG_PLLN GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 12, 6) +#define CGU_PLL0_CFG_PLLM GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 5, 2) +#define CGU_PLL2_SRC GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL2_CFG), 18, 17) +#define CGU_PLL2_CFG_INPUT_DIV GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL2_CFG), 16, 13) + +/* vr9 clock */ +#define LTQ_CGU_SYS_VR9 0x0c +#define LTQ_CGU_IF_CLK_VR9 0x24 + + +static unsigned int ltq_get_pll0_fdiv(void); + +static inline unsigned int get_input_clock(int pll) +{ + switch (pll) { + case 0: + if (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & CGU_PLL0_SRC) + return BASIS_REQUENCY_USB; + else if (CGU_PLL0_PHASE_DIVIDER_ENABLE) + return BASIC_FREQUENCY_1; + else + return BASIC_FREQUENCY_2; + case 1: + if (CGU_PLL1_SRC) + return BASIS_REQUENCY_USB; + else if (CGU_PLL0_PHASE_DIVIDER_ENABLE) + return BASIC_FREQUENCY_1; + else + return BASIC_FREQUENCY_2; + case 2: + switch (CGU_PLL2_SRC) { + case 0: + return ltq_get_pll0_fdiv(); + case 1: + return CGU_PLL2_PHASE_DIVIDER_ENABLE ? + BASIC_FREQUENCY_1 : + BASIC_FREQUENCY_2; + case 2: + return BASIS_REQUENCY_USB; + } + default: + return 0; + } +} + +static inline unsigned int cal_dsm(int pll, unsigned int num, unsigned int den) +{ + u64 res, clock = get_input_clock(pll); + + res = num * clock; + do_div(res, den); + return res; +} + +static inline unsigned int mash_dsm(int pll, unsigned int M, unsigned int N, + unsigned int K) +{ + unsigned int num = ((N + 1) << 10) + K; + unsigned int den = (M + 1) << 10; + + return cal_dsm(pll, num, den); +} + +static inline unsigned int ssff_dsm_1(int pll, unsigned int M, unsigned int N, + unsigned int K) +{ + unsigned int num = ((N + 1) << 11) + K + 512; + unsigned int den = (M + 1) << 11; + + return cal_dsm(pll, num, den); +} + +static inline unsigned int ssff_dsm_2(int pll, unsigned int M, unsigned int N, + unsigned int K) +{ + unsigned int num = K >= 512 ? + ((N + 1) << 12) + K - 512 : ((N + 1) << 12) + K + 3584; + unsigned int den = (M + 1) << 12; + + return cal_dsm(pll, num, den); +} + +static inline unsigned int dsm(int pll, unsigned int M, unsigned int N, + unsigned int K, unsigned int dsmsel, unsigned int phase_div_en) +{ + if (!dsmsel) + return mash_dsm(pll, M, N, K); + else if (!phase_div_en) + return mash_dsm(pll, M, N, K); + else + return ssff_dsm_2(pll, M, N, K); +} + +static inline unsigned int ltq_get_pll0_fosc(void) +{ + if (CGU_PLL0_BYPASS) + return get_input_clock(0); + else + return !CGU_PLL0_CFG_FRAC_EN + ? dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, 0, + CGU_PLL0_CFG_DSMSEL, + CGU_PLL0_PHASE_DIVIDER_ENABLE) + : dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, + CGU_PLL0_CFG_PLLK, CGU_PLL0_CFG_DSMSEL, + CGU_PLL0_PHASE_DIVIDER_ENABLE); +} + +static unsigned int ltq_get_pll0_fdiv(void) +{ + unsigned int div = CGU_PLL2_CFG_INPUT_DIV + 1; + + return (ltq_get_pll0_fosc() + (div >> 1)) / div; +} + +unsigned long ltq_danube_io_region_clock(void) +{ + unsigned int ret = ltq_get_pll0_fosc(); + + switch (ltq_cgu_r32(LTQ_CGU_SYS) & 0x3) { + default: + case 0: + return (ret + 1) / 2; + case 1: + return (ret * 2 + 2) / 5; + case 2: + return (ret + 1) / 3; + case 3: + return (ret + 2) / 4; + } +} + +unsigned long ltq_danube_fpi_bus_clock(int fpi) +{ + unsigned long ret = ltq_danube_io_region_clock(); + + if ((fpi == 2) && (ltq_cgu_r32(LTQ_CGU_SYS) & CGU_SYS_FPI_SEL)) + ret >>= 1; + return ret; +} + +unsigned long ltq_danube_fpi_hz(void) +{ + unsigned long ddr_clock = DDR_HZ; + + if (ltq_cgu_r32(LTQ_CGU_SYS) & 0x40) + return ddr_clock >> 1; + return ddr_clock; +} + +unsigned long ltq_danube_cpu_hz(void) +{ + switch (ltq_cgu_r32(LTQ_CGU_SYS) & 0xc) { + case 0: + return CLOCK_333M; + case 4: + return DDR_HZ; + case 8: + return DDR_HZ << 1; + default: + return DDR_HZ >> 1; + } +} + +unsigned long ltq_ar9_sys_hz(void) +{ + if (((ltq_cgu_r32(LTQ_CGU_SYS) >> 3) & 0x3) == 0x2) + return CLOCK_393M; + return CLOCK_333M; +} + +unsigned long ltq_ar9_fpi_hz(void) +{ + unsigned long sys = ltq_ar9_sys_hz(); + + if (ltq_cgu_r32(LTQ_CGU_SYS) & BIT(0)) + return sys; + return sys >> 1; +} + +unsigned long ltq_ar9_cpu_hz(void) +{ + if (ltq_cgu_r32(LTQ_CGU_SYS) & BIT(2)) + return ltq_ar9_fpi_hz(); + else + return ltq_ar9_sys_hz(); +} + +unsigned long ltq_vr9_cpu_hz(void) +{ + unsigned int cpu_sel; + unsigned long clk; + + cpu_sel = (ltq_cgu_r32(LTQ_CGU_SYS_VR9) >> 4) & 0xf; + + switch (cpu_sel) { + case 0: + clk = CLOCK_600M; + break; + case 1: + clk = CLOCK_500M; + break; + case 2: + clk = CLOCK_393M; + break; + case 3: + clk = CLOCK_333M; + break; + case 5: + case 6: + clk = CLOCK_196_608M; + break; + case 7: + clk = CLOCK_167M; + break; + case 4: + case 8: + case 9: + clk = CLOCK_125M; + break; + default: + clk = 0; + break; + } + + return clk; +} + +unsigned long ltq_vr9_fpi_hz(void) +{ + unsigned int ocp_sel, cpu_clk; + unsigned long clk; + + cpu_clk = ltq_vr9_cpu_hz(); + ocp_sel = ltq_cgu_r32(LTQ_CGU_SYS_VR9) & 0x3; + + switch (ocp_sel) { + case 0: + /* OCP ratio 1 */ + clk = cpu_clk; + break; + case 2: + /* OCP ratio 2 */ + clk = cpu_clk / 2; + break; + case 3: + /* OCP ratio 2.5 */ + clk = (cpu_clk * 2) / 5; + break; + case 4: + /* OCP ratio 3 */ + clk = cpu_clk / 3; + break; + default: + clk = 0; + break; + } + + return clk; +} + +unsigned long ltq_vr9_fpi_bus_clock(int fpi) +{ + return ltq_vr9_fpi_hz(); +} diff --git a/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/dev-dwc_otg.c b/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/dev-dwc_otg.c new file mode 100644 index 000000000..56086fa13 --- /dev/null +++ b/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/dev-dwc_otg.c @@ -0,0 +1,70 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * Copyright (C) 2010 John Crispin <blogic@openwrt.org> + */ + +#include <linux/init.h> +#include <linux/module.h> +#include <linux/types.h> +#include <linux/string.h> +#include <linux/mtd/physmap.h> +#include <linux/kernel.h> +#include <linux/reboot.h> +#include <linux/platform_device.h> +#include <linux/leds.h> +#include <linux/etherdevice.h> +#include <linux/reboot.h> +#include <linux/time.h> +#include <linux/io.h> +#include <linux/gpio.h> +#include <linux/leds.h> + +#include <asm/bootinfo.h> +#include <asm/irq.h> + +#include <lantiq_soc.h> +#include <lantiq_irq.h> +#include <lantiq_platform.h> + +#define LTQ_USB_IOMEM_BASE 0x1e101000 +#define LTQ_USB_IOMEM_SIZE 0x00001000 + +static struct resource resources[] = +{ + [0] = { + .name = "dwc_otg_membase", + .start = LTQ_USB_IOMEM_BASE, + .end = LTQ_USB_IOMEM_BASE + LTQ_USB_IOMEM_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .name = "dwc_otg_irq", + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 dwc_dmamask = (u32)0x1fffffff; + +static struct platform_device platform_dev = { + .name = "dwc_otg", + .dev = { + .dma_mask = &dwc_dmamask, + }, + .resource = resources, + .num_resources = ARRAY_SIZE(resources), +}; + +int __init +xway_register_dwc(int pin) +{ + struct irq_data d; + d.irq = resources[1].start; + ltq_enable_irq(&d); + resources[1].start = ltq_is_ase() ? LTQ_USB_ASE_INT : LTQ_USB_INT; + platform_dev.dev.platform_data = (void*) pin; + return platform_device_register(&platform_dev); +} diff --git a/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/dev-dwc_otg.h b/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/dev-dwc_otg.h new file mode 100644 index 000000000..521fad05e --- /dev/null +++ b/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/dev-dwc_otg.h @@ -0,0 +1,17 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * Copyright (C) 2010 John Crispin <blogic@openwrt.org> + */ + +#ifndef _LTQ_DEV_DWC_H__ +#define _LTQ_DEV_DWC_H__ + +#include <lantiq_platform.h> + +extern void __init xway_register_dwc(int pin); + +#endif diff --git a/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/dev-ifxhcd.c b/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/dev-ifxhcd.c new file mode 100644 index 000000000..ea08a359f --- /dev/null +++ b/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/dev-ifxhcd.c @@ -0,0 +1,45 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * Copyright (C) 2012 John Crispin <blogic@openwrt.org> + */ + +#include <linux/init.h> +#include <linux/module.h> +#include <linux/types.h> +#include <linux/string.h> +#include <linux/mtd/physmap.h> +#include <linux/kernel.h> +#include <linux/reboot.h> +#include <linux/platform_device.h> +#include <linux/leds.h> +#include <linux/etherdevice.h> +#include <linux/reboot.h> +#include <linux/time.h> +#include <linux/io.h> +#include <linux/gpio.h> +#include <linux/leds.h> + +#include <asm/bootinfo.h> +#include <asm/irq.h> + +#include <lantiq_soc.h> +#include <lantiq_irq.h> +#include <lantiq_platform.h> + +static u64 dmamask = (u32)0x1fffffff; + +static struct platform_device platform_dev = { + .name = "ifxusb_hcd", + .dev.dma_mask = &dmamask, +}; + +int __init +xway_register_hcd(int *pins) +{ + platform_dev.dev.platform_data = pins; + return platform_device_register(&platform_dev); +} diff --git a/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/dev-ifxhcd.h b/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/dev-ifxhcd.h new file mode 100644 index 000000000..18b3d2dae --- /dev/null +++ b/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/dev-ifxhcd.h @@ -0,0 +1,17 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * Copyright (C) 2012 John Crispin <blogic@openwrt.org> + */ + +#ifndef _LTQ_DEV_HCD_H__ +#define _LTQ_DEV_HCD_H__ + +#include <lantiq_platform.h> + +extern void __init xway_register_hcd(int *pin); + +#endif diff --git a/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/dev-wifi-athxk.c b/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/dev-wifi-athxk.c new file mode 100644 index 000000000..a75abe3e0 --- /dev/null +++ b/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/dev-wifi-athxk.c @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2011 John Crispin <blogic@openwrt.org> + * Copyright (C) 2011 Andrej VlaÅ¡ić <andrej.vlasic0@gmail.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/ath5k_platform.h> +#include <linux/ath9k_platform.h> +#include <linux/pci.h> + +#include "dev-wifi-athxk.h" + +extern int (*ltqpci_plat_dev_init)(struct pci_dev *dev); +struct ath5k_platform_data ath5k_pdata; +struct ath9k_platform_data ath9k_pdata = { + .led_pin = -1, + .endian_check = true, +}; + +static int +ath5k_pci_plat_dev_init(struct pci_dev *dev) +{ + dev->dev.platform_data = &ath5k_pdata; + return 0; +} + +static int +ath9k_pci_plat_dev_init(struct pci_dev *dev) +{ + dev->dev.platform_data = &ath9k_pdata; + return 0; +} + +void __init +ltq_register_ath5k(u16 *eeprom_data, u8 *macaddr) +{ + ath5k_pdata.eeprom_data = eeprom_data; + ath5k_pdata.macaddr = macaddr; + ltqpci_plat_dev_init = ath5k_pci_plat_dev_init; +} + +void __init +ltq_register_ath9k(u16 *eeprom_data, u8 *macaddr) +{ + memcpy(ath9k_pdata.eeprom_data, eeprom_data, sizeof(ath9k_pdata.eeprom_data)); + ath9k_pdata.macaddr = macaddr; + ltqpci_plat_dev_init = ath9k_pci_plat_dev_init; +} diff --git a/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/dev-wifi-athxk.h b/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/dev-wifi-athxk.h new file mode 100644 index 000000000..5fdb46b61 --- /dev/null +++ b/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/dev-wifi-athxk.h @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2011 John Crispin <blogic@openwrt.org> + * Copyright (C) 2011 Andrej VlaÅ¡ić <andrej.vlasic0@gmail.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _DEV_WIFI_ATHXK_H__ +#define _DEV_WIFI_ATHXK_H__ + +extern void ltq_register_ath5k(u16 *eeprom_data, u8 *macaddr); +extern void ltq_register_ath9k(u16 *eeprom_data, u8 *macaddr); + +#endif diff --git a/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/dev-wifi-rt2x00.c b/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/dev-wifi-rt2x00.c new file mode 100644 index 000000000..8e271f06e --- /dev/null +++ b/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/dev-wifi-rt2x00.c @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2011 John Crispin <blogic@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/rt2x00_platform.h> +#include <linux/pci.h> + +#include "dev-wifi-rt2x00.h" + +extern int (*ltqpci_plat_dev_init)(struct pci_dev *dev); +struct rt2x00_platform_data rt2x00_pdata; + +static int +rt2x00_pci_plat_dev_init(struct pci_dev *dev) +{ + dev->dev.platform_data = &rt2x00_pdata; + return 0; +} + +void __init +ltq_register_rt2x00(const char *firmware, const u8 *mac) +{ + rt2x00_pdata.eeprom_file_name = kstrdup(firmware, GFP_KERNEL); + rt2x00_pdata.mac_address = mac; + ltqpci_plat_dev_init = rt2x00_pci_plat_dev_init; +} diff --git a/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/dev-wifi-rt2x00.h b/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/dev-wifi-rt2x00.h new file mode 100644 index 000000000..941c26535 --- /dev/null +++ b/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/dev-wifi-rt2x00.h @@ -0,0 +1,14 @@ +/* + * Copyright (C) 2011 John Crispin <blogic@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _DEV_WIFI_RT2X00_H__ +#define _DEV_WIFI_RT2X00_H__ + +extern void ltq_register_rt2x00(const char *firmware, const u8 *mac); + +#endif diff --git a/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/gptu.c b/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/gptu.c new file mode 100644 index 000000000..ac82c37eb --- /dev/null +++ b/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/gptu.c @@ -0,0 +1,176 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2012 John Crispin <blogic@openwrt.org> + */ + +#include <linux/init.h> +#include <linux/io.h> +#include <linux/ioport.h> +#include <linux/pm.h> +#include <linux/export.h> +#include <linux/delay.h> +#include <linux/interrupt.h> +#include <asm/reboot.h> + +#include <lantiq_soc.h> +#include "../clk.h" + +#include "../devices.h" + +#define ltq_gptu_w32(x, y) ltq_w32((x), ltq_gptu_membase + (y)) +#define ltq_gptu_r32(x) ltq_r32(ltq_gptu_membase + (x)) + + +/* the magic ID byte of the core */ +#define GPTU_MAGIC 0x59 +/* clock control register */ +#define GPTU_CLC 0x00 +/* id register */ +#define GPTU_ID 0x08 +/* interrupt node enable */ +#define GPTU_IRNEN 0xf4 +/* interrupt control register */ +#define GPTU_IRCR 0xf8 +/* interrupt capture register */ +#define GPTU_IRNCR 0xfc +/* there are 3 identical blocks of 2 timers. calculate register offsets */ +#define GPTU_SHIFT(x) (x % 2 ? 4 : 0) +#define GPTU_BASE(x) (((x >> 1) * 0x20) + 0x10) +/* timer control register */ +#define GPTU_CON(x) (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x00) +/* timer auto reload register */ +#define GPTU_RUN(x) (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x08) +/* timer manual reload register */ +#define GPTU_RLD(x) (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x10) +/* timer count register */ +#define GPTU_CNT(x) (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x18) + +/* GPTU_CON(x) */ +#define CON_CNT BIT(2) +#define CON_EDGE_FALL BIT(7) +#define CON_SYNC BIT(8) +#define CON_CLK_INT BIT(10) + +/* GPTU_RUN(x) */ +#define RUN_SEN BIT(0) +#define RUN_RL BIT(2) + +/* set clock to runmode */ +#define CLC_RMC BIT(8) +/* bring core out of suspend */ +#define CLC_SUSPEND BIT(4) +/* the disable bit */ +#define CLC_DISABLE BIT(0) + +#define TIMER_INTERRUPT (INT_NUM_IM3_IRL0 + 22) + +enum gptu_timer { + TIMER1A = 0, + TIMER1B, + TIMER2A, + TIMER2B, + TIMER3A, + TIMER3B +}; + +static struct resource ltq_gptu_resource = + MEM_RES("GPTU", LTQ_GPTU_BASE_ADDR, LTQ_GPTU_SIZE); + +static void __iomem *ltq_gptu_membase; + +static irqreturn_t timer_irq_handler(int irq, void *priv) +{ + int timer = irq - TIMER_INTERRUPT; + ltq_gptu_w32(1 << timer, GPTU_IRNCR); + return IRQ_HANDLED; +} + +static void gptu_hwinit(void) +{ + struct clk *clk = clk_get_sys("ltq_gptu", NULL); + clk_enable(clk); + ltq_gptu_w32(0x00, GPTU_IRNEN); + ltq_gptu_w32(0xff, GPTU_IRNCR); + ltq_gptu_w32(CLC_RMC | CLC_SUSPEND, GPTU_CLC); +} + +static void gptu_hwexit(void) +{ + ltq_gptu_w32(0x00, GPTU_IRNEN); + ltq_gptu_w32(0xff, GPTU_IRNCR); + ltq_gptu_w32(CLC_DISABLE, GPTU_CLC); +} + +static int ltq_gptu_enable(struct clk *clk) +{ + int ret = request_irq(TIMER_INTERRUPT + clk->bits, timer_irq_handler, + IRQF_TIMER, "timer", NULL); + if (ret) { + pr_err("gptu: failed to request irq\n"); + return ret; + } + + ltq_gptu_w32(CON_CNT | CON_EDGE_FALL | CON_SYNC | CON_CLK_INT, + GPTU_CON(clk->bits)); + ltq_gptu_w32(1, GPTU_RLD(clk->bits)); + ltq_gptu_w32(ltq_gptu_r32(GPTU_IRNEN) | clk->bits, GPTU_IRNEN); + ltq_gptu_w32(RUN_SEN | RUN_RL, GPTU_RUN(clk->bits)); + return 0; +} + +static void ltq_gptu_disable(struct clk *clk) +{ + ltq_gptu_w32(0, GPTU_RUN(clk->bits)); + ltq_gptu_w32(0, GPTU_CON(clk->bits)); + ltq_gptu_w32(0, GPTU_RLD(clk->bits)); + ltq_gptu_w32(ltq_gptu_r32(GPTU_IRNEN) & ~clk->bits, GPTU_IRNEN); + free_irq(TIMER_INTERRUPT + clk->bits, NULL); +} + +static inline void clkdev_add_gptu(const char *con, unsigned int timer) +{ + struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); + + clk->cl.dev_id = "ltq_gptu"; + clk->cl.con_id = con; + clk->cl.clk = clk; + clk->enable = ltq_gptu_enable; + clk->disable = ltq_gptu_disable; + clk->bits = timer; + clkdev_add(&clk->cl); +} + +static int __init gptu_setup(void) +{ + /* remap gptu register range */ + ltq_gptu_membase = ltq_remap_resource(<q_gptu_resource); + if (!ltq_gptu_membase) + panic("Failed to remap gptu memory"); + + /* power up the core */ + gptu_hwinit(); + + /* the gptu has a ID register */ + if (((ltq_gptu_r32(GPTU_ID) >> 8) & 0xff) != GPTU_MAGIC) { + pr_err("gptu: failed to find magic\n"); + gptu_hwexit(); + return -ENAVAIL; + } + + /* register the clocks */ + clkdev_add_gptu("timer1a", TIMER1A); + clkdev_add_gptu("timer1b", TIMER1B); + clkdev_add_gptu("timer2a", TIMER2A); + clkdev_add_gptu("timer2b", TIMER2B); + clkdev_add_gptu("timer3a", TIMER3A); + clkdev_add_gptu("timer3b", TIMER3B); + + pr_info("gptu: 6 timers loaded\n"); + + return 0; +} + +arch_initcall(gptu_setup); diff --git a/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/mach-arv.c b/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/mach-arv.c new file mode 100644 index 000000000..6857e993d --- /dev/null +++ b/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/mach-arv.c @@ -0,0 +1,793 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin <blogic@openwrt.org> + */ + +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/leds.h> +#include <linux/gpio.h> +#include <linux/gpio_buttons.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> +#include <linux/mtd/physmap.h> +#include <linux/input.h> +#include <linux/etherdevice.h> +#include <linux/ath5k_platform.h> +#include <linux/ath9k_platform.h> +#include <linux/pci.h> + +#include <lantiq_soc.h> +#include <lantiq_platform.h> +#include <dev-gpio-leds.h> +#include <dev-gpio-buttons.h> + +#include "../machtypes.h" +#include "dev-wifi-rt2x00.h" +#include "dev-wifi-athxk.h" +#include "devices.h" +#include "dev-dwc_otg.h" +#include "pci-ath-fixup.h" + +static struct mtd_partition arv45xx_brnboot_partitions[] = +{ + { + .name = "brn-boot", + .offset = 0x0, + .size = 0x20000, + }, + { + .name = "config", + .offset = 0x20000, + .size = 0x30000, + }, + { + .name = "linux", + .offset = 0x50000, + .size = 0x390000, + }, + { + .name = "reserved", /* 12-byte signature at 0x3efff4 :/ */ + .offset = 0x3e0000, + .size = 0x010000, + }, + { + .name = "eeprom", + .offset = 0x3f0000, + .size = 0x10000, + }, +}; + +static struct mtd_partition arv75xx_brnboot_partitions[] = +{ + { + .name = "brn-boot", + .offset = 0x0, + .size = 0x20000, + }, + { + .name = "config", + .offset = 0x20000, + .size = 0x40000, + }, + { + .name = "linux", + .offset = 0x440000, + .size = 0x3a0000, + }, + { + .name = "reserved", /* 12-byte signature at 0x7efff4 :/ */ + .offset = 0x7e0000, + .size = 0x010000, + }, + { + .name = "board_config", + .offset = 0x7f0000, + .size = 0x10000, + }, +}; + +/* + * this is generic configuration for all arv based boards, note that it can be + * rewriten in arv_load_nor() + */ +static struct mtd_partition arv_partitions[] = +{ + { + .name = "uboot", + .offset = 0x0, + .size = 0x20000, + }, + { + .name = "uboot_env", + .offset = 0x20000, + .size = 0x10000, + }, + { + .name = "linux", + .offset = 0x30000, + .size = 0x3c0000, + }, + { + .name = "board_config", + .offset = 0x3f0000, + .size = 0x10000, + }, +}; + +static struct physmap_flash_data arv45xx_brnboot_flash_data = { + .nr_parts = ARRAY_SIZE(arv45xx_brnboot_partitions), + .parts = arv45xx_brnboot_partitions, +}; + +static struct physmap_flash_data arv75xx_brnboot_flash_data = { + .nr_parts = ARRAY_SIZE(arv75xx_brnboot_partitions), + .parts = arv75xx_brnboot_partitions, +}; + +static struct physmap_flash_data arv_flash_data = { + .nr_parts = ARRAY_SIZE(arv_partitions), + .parts = arv_partitions, +}; + +static struct ltq_pci_data ltq_pci_data = { + .clock = PCI_CLOCK_EXT, + .gpio = PCI_GNT1 | PCI_REQ1, + .irq = { + [14] = INT_NUM_IM0_IRL0 + 22, + }, +}; + +static struct ltq_eth_data ltq_eth_data = { + .mii_mode = PHY_INTERFACE_MODE_RMII, +}; + +static struct gpio_led +arv4510pw_gpio_leds[] __initdata = { + { .name = "soc:green:foo", .gpio = 4, .active_low = 1, }, +}; + +static struct gpio_led +arv4518pw_gpio_leds[] __initdata = { + { .name = "soc:green:power", .gpio = 3, .active_low = 1, .default_trigger = "default-on" }, + { .name = "soc:green:adsl", .gpio = 4, .active_low = 1, .default_trigger = "default-on" }, + { .name = "soc:green:internet", .gpio = 5, .active_low = 1, .default_trigger = "default-on" }, + { .name = "soc:green:wifi", .gpio = 6, .active_low = 1, .default_trigger = "default-on" }, + { .name = "soc:yellow:wps", .gpio = 7, .active_low = 1, .default_trigger = "default-on" }, + { .name = "soc:red:fail", .gpio = 8, .active_low = 1, .default_trigger = "default-on" }, + { .name = "soc:green:usb", .gpio = 19, .active_low = 1, .default_trigger = "default-on" }, + { .name = "soc:green:voip", .gpio = 100, .active_low = 1, .default_trigger = "default-on" }, + { .name = "soc:green:fxs1", .gpio = 101, .active_low = 1, .default_trigger = "default-on" }, + { .name = "soc:green:fxs2", .gpio = 102, .active_low = 1, .default_trigger = "default-on" }, + { .name = "soc:green:fxo", .gpio = 103, .active_low = 1, .default_trigger = "default-on" }, +}; + +static struct gpio_keys_button +arv4518pw_gpio_keys[] __initdata = { + { + .desc = "wifi", + .type = EV_KEY, + .code = BTN_0, + .debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL, + .gpio = 28, + .active_low = 1, + }, + { + .desc = "reset", + .type = EV_KEY, + .code = BTN_1, + .debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL, + .gpio = 30, + .active_low = 1, + }, + { + .desc = "wps", + .type = EV_KEY, + .code = BTN_2, + .debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL, + .gpio = 29, + .active_low = 1, + }, +}; + +static struct gpio_led +arv4519pw_gpio_leds[] __initdata = { + { .name = "soc:red:power", .gpio = 7, .active_low = 1, }, + { .name = "soc:green:power", .gpio = 2, .active_low = 1, .default_trigger = "default-on" }, + { .name = "soc:green:wifi", .gpio = 6, .active_low = 1, }, + { .name = "soc:green:adsl", .gpio = 4, .active_low = 1, }, + { .name = "soc:green:internet", .gpio = 5, .active_low = 1, }, + { .name = "soc:red:internet", .gpio = 8, .active_low = 1, }, + { .name = "soc:green:voip", .gpio = 100, .active_low = 1, }, + { .name = "soc:green:phone1", .gpio = 101, .active_low = 1, }, + { .name = "soc:green:phone2", .gpio = 102, .active_low = 1, }, + { .name = "soc:green:fxo", .gpio = 103, .active_low = 1, }, + { .name = "soc:green:usb", .gpio = 19, .active_low = 1, }, + { .name = "soc:orange:wps", .gpio = 104, .active_low = 1, }, + { .name = "soc:green:wps", .gpio = 105, .active_low = 1, }, + { .name = "soc:red:wps", .gpio = 106, .active_low = 1, }, + +}; + +static struct gpio_keys_button +arv4519pw_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = BTN_1, + .debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL, + .gpio = 30, + .active_low = 1, + }, + { + .desc = "wlan", + .type = EV_KEY, + .code = BTN_2, + .debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL, + .gpio = 28, + .active_low = 1, + }, +}; + +static struct gpio_led +arv4520pw_gpio_leds[] __initdata = { + { .name = "soc:blue:power", .gpio = 3, .active_low = 1, }, + { .name = "soc:blue:adsl", .gpio = 4, .active_low = 1, }, + { .name = "soc:blue:internet", .gpio = 5, .active_low = 1, }, + { .name = "soc:red:power", .gpio = 6, .active_low = 1, }, + { .name = "soc:yellow:wps", .gpio = 7, .active_low = 1, }, + { .name = "soc:red:wps", .gpio = 9, .active_low = 1, }, + { .name = "soc:blue:voip", .gpio = 100, .active_low = 1, }, + { .name = "soc:blue:fxs1", .gpio = 101, .active_low = 1, }, + { .name = "soc:blue:fxs2", .gpio = 102, .active_low = 1, }, + { .name = "soc:blue:fxo", .gpio = 103, .active_low = 1, }, + { .name = "soc:blue:voice", .gpio = 104, .active_low = 1, }, + { .name = "soc:blue:usb", .gpio = 105, .active_low = 1, }, + { .name = "soc:blue:wifi", .gpio = 106, .active_low = 1, }, +}; + +static struct gpio_led +arv452cpw_gpio_leds[] __initdata = { + { .name = "soc:blue:power", .gpio = 3, .active_low = 1, .default_trigger = "default-on" }, + { .name = "soc:blue:adsl", .gpio = 4, .active_low = 1, .default_trigger = "default-on" }, + { .name = "soc:blue:isdn", .gpio = 5, .active_low = 1, .default_trigger = "default-on" }, + { .name = "soc:red:power", .gpio = 6, .active_low = 1, .default_trigger = "default-on" }, + { .name = "soc:yellow:wps", .gpio = 7, .active_low = 1, .default_trigger = "default-on" }, + { .name = "soc:red:wps", .gpio = 9, .active_low = 1, .default_trigger = "default-on" }, + { .name = "soc:blue:fxs1", .gpio = 100, .active_low = 1, .default_trigger = "default-on" }, + { .name = "soc:blue:fxs2", .gpio = 101, .active_low = 1, .default_trigger = "default-on" }, + { .name = "soc:blue:wps", .gpio = 102, .active_low = 1, .default_trigger = "default-on" }, + { .name = "soc:blue:fxo", .gpio = 103, .active_low = 1, .default_trigger = "default-on" }, + { .name = "soc:blue:voice", .gpio = 104, .active_low = 1, .default_trigger = "default-on" }, + { .name = "soc:blue:usb", .gpio = 105, .active_low = 1, .default_trigger = "default-on" }, + { .name = "soc:blue:wifi", .gpio = 106, .active_low = 1, .default_trigger = "default-on" }, + { .name = "soc:blue:internet", .gpio = 108, .active_low = 1, .default_trigger = "default-on" }, + { .name = "soc:red:internet", .gpio = 109, .active_low = 1, .default_trigger = "default-on" }, +}; + +static struct gpio_led +arv4525pw_gpio_leds[] __initdata = { + { .name = "soc:green:dsl", .gpio = 6, .active_low = 1, .default_trigger = "default-on" }, + { .name = "soc:green:wifi", .gpio = 8, .active_low = 1, .default_trigger = "default-on" }, + { .name = "soc:green:online", .gpio = 9, .active_low = 1, .default_trigger = "default-on" }, + { .name = "soc:green:fxs-internet", .gpio = 5, .active_low = 1, .default_trigger = "default-on" }, + { .name = "soc:green:fxs-festnetz", .gpio = 4, .active_low = 1, .default_trigger = "default-on" }, +}; + +#define ARV4525PW_PHYRESET 13 +#define ARV4525PW_RELAY 31 + +static struct gpio +arv4525pw_gpios[] __initdata = { + { ARV4525PW_PHYRESET, GPIOF_OUT_INIT_HIGH, "phyreset" }, + { ARV4525PW_RELAY, GPIOF_OUT_INIT_HIGH, "relay" }, +}; + + +static struct gpio_led +arv752dpw22_gpio_leds[] __initdata = { + { .name = "soc:blue:power", .gpio = 3, .active_low = 1, .default_trigger = "default-on" }, + { .name = "soc:red:internet", .gpio = 5, .active_low = 1, .default_trigger = "default-on" }, + { .name = "soc:red:power", .gpio = 6, .active_low = 1, .default_trigger = "default-on" }, + { .name = "soc:red:wps", .gpio = 8, .active_low = 1, .default_trigger = "default-on" }, + { .name = "soc:red:fxo", .gpio = 103, .active_low = 1, .default_trigger = "default-on" }, + { .name = "soc:red:voice", .gpio = 104, .active_low = 1, .default_trigger = "default-on" }, + { .name = "soc:green:usb", .gpio = 105, .active_low = 1, .default_trigger = "default-on" }, + { .name = "soc:green:wifi", .gpio = 106, .active_low = 1, .default_trigger = "default-on" }, + { .name = "soc:green:wifi1", .gpio = 107, .active_low = 1, .default_trigger = "default-on" }, + { .name = "soc:blue:wifi", .gpio = 108, .active_low = 1, .default_trigger = "default-on" }, + { .name = "soc:blue:wifi1", .gpio = 109, .active_low = 1, .default_trigger = "default-on" }, + { .name = "soc:green:eth1", .gpio = 111, .active_low = 1, .default_trigger = "default-on" }, + { .name = "soc:green:eth2", .gpio = 112, .active_low = 1, .default_trigger = "default-on" }, + { .name = "soc:green:eth3", .gpio = 113, .active_low = 1, .default_trigger = "default-on" }, + { .name = "soc:green:eth4", .gpio = 114, .active_low = 1, .default_trigger = "default-on", }, +}; + +static struct gpio_keys_button +arv752dpw22_gpio_keys[] __initdata = { + { + .desc = "btn0", + .type = EV_KEY, + .code = BTN_0, + .debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL, + .gpio = 12, + .active_low = 1, + }, + { + .desc = "btn1", + .type = EV_KEY, + .code = BTN_1, + .debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL, + .gpio = 13, + .active_low = 1, + }, + { + .desc = "btn2", + .type = EV_KEY, + .code = BTN_2, + .debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL, + .gpio = 28, + .active_low = 1, + }, +}; + +static struct gpio_led +arv7518pw_gpio_leds[] __initdata = { + { .name = "soc:red:power", .gpio = 7, .active_low = 1, }, + { .name = "soc:green:power", .gpio = 2, .active_low = 1, .default_trigger = "default-on" }, + { .name = "soc:green:wifi", .gpio = 6, .active_low = 1, }, + { .name = "soc:green:adsl", .gpio = 4, .active_low = 1, }, + { .name = "soc:green:internet", .gpio = 5, .active_low = 1, }, + { .name = "soc:red:internet", .gpio = 8, .active_low = 1, }, + { .name = "soc:green:voip", .gpio = 100, .active_low = 1, }, + { .name = "soc:green:phone1", .gpio = 101, .active_low = 1, }, + { .name = "soc:green:phone2", .gpio = 102, .active_low = 1, }, + { .name = "soc:orange:fail", .gpio = 103, .active_low = 1, }, + { .name = "soc:green:usb", .gpio = 19, .active_low = 1, }, + { .name = "soc:orange:wps", .gpio = 104, .active_low = 1, }, + { .name = "soc:green:wps", .gpio = 105, .active_low = 1, }, + { .name = "soc:red:wps", .gpio = 106, .active_low = 1, }, + +}; + +static struct gpio_keys_button +arv7518pw_gpio_keys[] __initdata = { + /*{ + .desc = "reset", + .type = EV_KEY, + .code = BTN_1, + .debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL, + .gpio = 23, + .active_low = 1, + },*/ + { + .desc = "wifi", + .type = EV_KEY, + .code = BTN_2, + .debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL, + .gpio = 25, + .active_low = 1, + }, +}; + +static struct gpio_keys_button +arv7525pw_gpio_keys[] __initdata = { + { + .desc = "restart", + .type = EV_KEY, + .code = BTN_0, + .debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL, + .gpio = 29, + .active_low = 1, + }, +}; + +static void __init +arv_load_nor(unsigned int max) +{ +#define UBOOT_MAGIC 0x27051956 + + int i; + int sector = -1; + + if (ltq_brn_boot) { + if (max == 0x800000) + ltq_register_nor(&arv75xx_brnboot_flash_data); + else + ltq_register_nor(&arv45xx_brnboot_flash_data); + return; + } + + for (i = 1; i < 4 && sector < 0; i++) { + unsigned int uboot_magic; + memcpy_fromio(&uboot_magic, (void *)KSEG1ADDR(LTQ_FLASH_START) + (i * 0x10000), 4); + if (uboot_magic == UBOOT_MAGIC) + sector = i; + } + + if (sector < 0) + return; + + arv_partitions[0].size = arv_partitions[1].offset = (sector - 1) * 0x10000; + arv_partitions[2].offset = arv_partitions[0].size + 0x10000; + arv_partitions[2].size = max - arv_partitions[2].offset - 0x10000; + arv_partitions[3].offset = max - 0x10000; + ltq_register_nor(&arv_flash_data); +} + +static void __init +arv_register_ethernet(unsigned int mac_addr) +{ + memcpy_fromio(<q_eth_data.mac.sa_data, + (void *)KSEG1ADDR(LTQ_FLASH_START + mac_addr), 6); + ltq_register_etop(<q_eth_data); +} + +static u16 arv_ath5k_eeprom_data[ATH5K_PLAT_EEP_MAX_WORDS]; +static u16 arv_ath9k_eeprom_data[ATH9K_PLAT_EEP_MAX_WORDS]; +static u8 arv_athxk_eeprom_mac[6]; + +static void __init +arv_register_ath5k(unsigned int ath_addr, unsigned int mac_addr) +{ + int i; + + memcpy_fromio(arv_athxk_eeprom_mac, + (void *)KSEG1ADDR(LTQ_FLASH_START + mac_addr), 6); + arv_athxk_eeprom_mac[5]++; + memcpy_fromio(arv_ath5k_eeprom_data, + (void *)KSEG1ADDR(LTQ_FLASH_START + ath_addr), ATH5K_PLAT_EEP_MAX_WORDS); + // swap eeprom bytes + for (i = 0; i < ATH5K_PLAT_EEP_MAX_WORDS>>1; i++) { + arv_ath5k_eeprom_data[i] = swab16(arv_ath5k_eeprom_data[i]); + if (i == 0x17e>>1) { + /* + * regdomain is invalid. it's unknown how did original + * fw convered value to 0x82d4 so for now force to 0x67 + */ + arv_ath5k_eeprom_data[i] &= 0x0000; + arv_ath5k_eeprom_data[i] |= 0x67; + } + } +} + +static void __init +arv_register_ath9k(unsigned int ath_addr, unsigned int mac_addr) +{ + int i; + u16 *eepdata, sum, el; + + memcpy_fromio(arv_athxk_eeprom_mac, + (void *)KSEG1ADDR(LTQ_FLASH_START + mac_addr), 6); + arv_athxk_eeprom_mac[5]++; + memcpy_fromio(arv_ath9k_eeprom_data, + (void *)KSEG1ADDR(LTQ_FLASH_START + ath_addr), ATH9K_PLAT_EEP_MAX_WORDS); + + // force regdomain to 0x67 + arv_ath9k_eeprom_data[0x208>>1] = 0x67; + + // calculate new checksum + sum = arv_ath9k_eeprom_data[0x200>>1]; + el = sum / sizeof(u16) - 2; /* skip length and (old) checksum */ + eepdata = (u16 *) (&arv_ath9k_eeprom_data[0x204>>1]); /* after checksum */ + for (i = 0; i < el; i++) + sum ^= *eepdata++; + sum ^= 0xffff; + arv_ath9k_eeprom_data[0x202>>1] = sum; +} + +static void __init +arv3527p_init(void) +{ +#define ARV3527P_MAC_ADDR 0x3f0016 + + ltq_register_gpio_stp(); + // ltq_add_device_gpio_leds(arv3527p_gpio_leds, ARRAY_SIZE(arv3527p_gpio_leds)); + arv_load_nor(0x400000); + arv_register_ethernet(ARV3527P_MAC_ADDR); +} + +MIPS_MACHINE(LANTIQ_MACH_ARV3527P, + "ARV3527P", + "ARV3527P - Arcor Easybox 401", + arv3527p_init); + +static void __init +arv4510pw_init(void) +{ +#define ARV4510PW_MAC_ADDR 0x3f0014 + + ltq_register_gpio_stp(); + ltq_add_device_gpio_leds(-1, ARRAY_SIZE(arv4510pw_gpio_leds), arv4510pw_gpio_leds); + arv_load_nor(0x400000); + ltq_pci_data.irq[12] = (INT_NUM_IM2_IRL0 + 31); + ltq_pci_data.irq[15] = (INT_NUM_IM0_IRL0 + 26); + ltq_pci_data.gpio |= PCI_EXIN2 | PCI_REQ2; + ltq_register_pci(<q_pci_data); + arv_register_ethernet(ARV4510PW_MAC_ADDR); +} + +MIPS_MACHINE(LANTIQ_MACH_ARV4510PW, + "ARV4510PW", + "ARV4510PW - Wippies Homebox", + arv4510pw_init); + +static void __init +arv4518pw_init(void) +{ +#define ARV4518PW_EBU 0 +#define ARV4518PW_USB 14 +#define ARV4518PW_SWITCH_RESET 13 +#define ARV4518PW_ATH_ADDR 0x3f0400 +#define ARV4518PW_MAC_ADDR 0x3f0016 + + ltq_register_gpio_ebu(ARV4518PW_EBU); + ltq_add_device_gpio_leds(-1, ARRAY_SIZE(arv4518pw_gpio_leds), arv4518pw_gpio_leds); + ltq_register_gpio_keys_polled(-1, LTQ_KEYS_POLL_INTERVAL, + ARRAY_SIZE(arv4518pw_gpio_keys), arv4518pw_gpio_keys); + arv_load_nor(0x400000); + ltq_pci_data.gpio = PCI_GNT2 | PCI_REQ2; + ltq_register_pci(<q_pci_data); + xway_register_dwc(ARV4518PW_USB); + arv_register_ethernet(ARV4518PW_MAC_ADDR); + arv_register_ath5k(ARV4518PW_ATH_ADDR, ARV4518PW_MAC_ADDR); + ltq_register_ath5k(arv_ath5k_eeprom_data, arv_athxk_eeprom_mac); + ltq_register_tapi(); + + gpio_request(ARV4518PW_SWITCH_RESET, "switch"); + gpio_direction_output(ARV4518PW_SWITCH_RESET, 1); + gpio_export(ARV4518PW_SWITCH_RESET, 0); +} + +MIPS_MACHINE(LANTIQ_MACH_ARV4518PW, + "ARV4518PW", + "ARV4518PW - SMC7908A-ISP, Airties WAV-221", + arv4518pw_init); + +static void __init +arv4519pw_init(void) +{ +#define ARV4519PW_EBU 0 +#define ARV4519PW_USB 14 +#define ARV4519PW_RELAY 31 +#define ARV4519PW_SWITCH_RESET 13 +#define ARV4519PW_ATH_ADDR 0x3f0400 +#define ARV4519PW_MAC_ADDR 0x3f0016 + + arv_load_nor(0x400000); + ltq_register_gpio_ebu(ARV4519PW_EBU); + ltq_add_device_gpio_leds(-1, ARRAY_SIZE(arv4519pw_gpio_leds), arv4519pw_gpio_leds); + ltq_register_gpio_keys_polled(-1, LTQ_KEYS_POLL_INTERVAL, + ARRAY_SIZE(arv4519pw_gpio_keys), arv4519pw_gpio_keys); + ltq_pci_data.gpio = PCI_GNT2 | PCI_REQ1; + ltq_register_pci(<q_pci_data); + xway_register_dwc(ARV4519PW_USB); + arv_register_ethernet(ARV4519PW_MAC_ADDR); + arv_register_ath5k(ARV4519PW_ATH_ADDR, ARV4519PW_MAC_ADDR); + ltq_register_ath5k(arv_ath5k_eeprom_data, arv_athxk_eeprom_mac); + ltq_register_tapi(); + + gpio_request(ARV4519PW_RELAY, "relay"); + gpio_direction_output(ARV4519PW_RELAY, 1); + gpio_export(ARV4519PW_RELAY, 0); + + gpio_request(ARV4519PW_SWITCH_RESET, "switch"); + gpio_set_value(ARV4519PW_SWITCH_RESET, 1); + gpio_export(ARV4519PW_SWITCH_RESET, 0); +} + +MIPS_MACHINE(LANTIQ_MACH_ARV4519PW, + "ARV4519PW", + "ARV4519PW - Vodafone, Pirelli", + arv4519pw_init); + +static void __init +arv4520pw_init(void) +{ +#define ARV4520PW_EBU 0x400 +#define ARV4520PW_USB 28 +#define ARV4520PW_SWITCH_RESET 110 +#define ARV4520PW_MAC_ADDR 0x3f0016 + + ltq_register_gpio_ebu(ARV4520PW_EBU); + ltq_add_device_gpio_leds(-1, ARRAY_SIZE(arv4520pw_gpio_leds), arv4520pw_gpio_leds); + arv_load_nor(0x400000); + ltq_register_pci(<q_pci_data); + ltq_register_tapi(); + arv_register_ethernet(ARV4520PW_MAC_ADDR); + ltq_register_rt2x00(NULL, (const u8 *) ltq_eth_data.mac.sa_data); + xway_register_dwc(ARV4520PW_USB); + ltq_register_tapi(); + + gpio_request(ARV4520PW_SWITCH_RESET, "switch"); + gpio_set_value(ARV4520PW_SWITCH_RESET, 1); +} + +MIPS_MACHINE(LANTIQ_MACH_ARV4520PW, + "ARV4520PW", + "ARV4520PW - Airties WAV-281, Arcor A800", + arv4520pw_init); + +static void __init +arv452Cpw_init(void) +{ +#define ARV452CPW_EBU 0x77f +#define ARV452CPW_USB 28 +#define ARV452CPW_RELAY1 31 +#define ARV452CPW_RELAY2 107 +#define ARV452CPW_SWITCH_RESET 110 +#define ARV452CPW_ATH_ADDR 0x3f0400 +#define ARV452CPW_MAC_ADDR 0x3f0016 + + ltq_register_gpio_ebu(ARV452CPW_EBU); + ltq_add_device_gpio_leds(-1, ARRAY_SIZE(arv452cpw_gpio_leds), arv452cpw_gpio_leds); + arv_load_nor(0x400000); + ltq_register_pci(<q_pci_data); + xway_register_dwc(ARV452CPW_USB); + arv_register_ethernet(ARV452CPW_MAC_ADDR); + arv_register_ath5k(ARV452CPW_ATH_ADDR, ARV452CPW_MAC_ADDR); + ltq_register_ath5k(arv_ath5k_eeprom_data, arv_athxk_eeprom_mac); + ltq_register_tapi(); + + gpio_request(ARV452CPW_SWITCH_RESET, "switch"); + gpio_set_value(ARV452CPW_SWITCH_RESET, 1); + gpio_export(ARV452CPW_SWITCH_RESET, 0); + + gpio_request(ARV452CPW_RELAY1, "relay1"); + gpio_direction_output(ARV452CPW_RELAY1, 1); + gpio_export(ARV452CPW_RELAY1, 0); + + gpio_request(ARV452CPW_RELAY2, "relay2"); + gpio_set_value(ARV452CPW_RELAY2, 1); + gpio_export(ARV452CPW_RELAY2, 0); +} + +MIPS_MACHINE(LANTIQ_MACH_ARV452CPW, + "ARV452CPW", + "ARV452CPW - Arcor A801", + arv452Cpw_init); + +static void __init +arv4525pw_init(void) +{ +#define ARV4525PW_ATH_ADDR 0x3f0400 +#define ARV4525PW_MAC_ADDR 0x3f0016 + + arv_load_nor(0x400000); + ltq_add_device_gpio_leds(-1, ARRAY_SIZE(arv4525pw_gpio_leds), arv4525pw_gpio_leds); + gpio_request_array(arv4525pw_gpios, ARRAY_SIZE(arv4525pw_gpios)); + gpio_export(ARV4525PW_RELAY, false); + gpio_export(ARV4525PW_PHYRESET, false); + ltq_pci_data.clock = PCI_CLOCK_INT; + ltq_register_pci(<q_pci_data); + arv_register_ath5k(ARV4525PW_ATH_ADDR, ARV4525PW_MAC_ADDR); + ltq_register_ath5k(arv_ath5k_eeprom_data, arv_athxk_eeprom_mac); + ltq_eth_data.mii_mode = PHY_INTERFACE_MODE_MII; + arv_register_ethernet(ARV4525PW_MAC_ADDR); + ltq_register_tapi(); +} + +MIPS_MACHINE(LANTIQ_MACH_ARV4525PW, + "ARV4525PW", + "ARV4525PW - Speedport W502V", + arv4525pw_init); + +static void __init +arv7525pw_init(void) +{ +#define ARV7525P_MAC_ADDR 0x3f0016 + + arv_load_nor(0x400000); + ltq_add_device_gpio_leds(-1, ARRAY_SIZE(arv4525pw_gpio_leds), arv4525pw_gpio_leds); + ltq_register_gpio_keys_polled(-1, LTQ_KEYS_POLL_INTERVAL, + ARRAY_SIZE(arv7525pw_gpio_keys), arv7525pw_gpio_keys); + ltq_pci_data.clock = PCI_CLOCK_INT; + ltq_pci_data.gpio = PCI_GNT1 | PCI_EXIN1; + ltq_pci_data.irq[14] = (INT_NUM_IM3_IRL0 + 31); + ltq_register_pci(<q_pci_data); + ltq_eth_data.mii_mode = PHY_INTERFACE_MODE_MII; + ltq_register_rt2x00("RT2860.eeprom", NULL); + ltq_register_tapi(); + arv_register_ethernet(ARV7525P_MAC_ADDR); +} + +MIPS_MACHINE(LANTIQ_MACH_ARV7525PW, + "ARV7525PW", + "ARV7525PW - Speedport W303V", + arv7525pw_init); + +static void __init +arv7518pw_init(void) +{ +#define ARV7518PW_EBU 0x2 +#define ARV7518PW_USB 14 +#define ARV7518PW_SWITCH_RESET 13 +#define ARV7518PW_ATH_ADDR 0x7f0400 +#define ARV7518PW_MAC_ADDR 0x7f0016 + + arv_load_nor(0x800000); + ltq_register_gpio_ebu(ARV7518PW_EBU); + ltq_add_device_gpio_leds(-1, ARRAY_SIZE(arv7518pw_gpio_leds), arv7518pw_gpio_leds); + ltq_register_gpio_keys_polled(-1, LTQ_KEYS_POLL_INTERVAL, + ARRAY_SIZE(arv7518pw_gpio_keys), arv7518pw_gpio_keys); + ltq_register_pci(<q_pci_data); + ltq_register_tapi(); + xway_register_dwc(ARV7518PW_USB); + arv_register_ethernet(ARV7518PW_MAC_ADDR); + arv_register_ath9k(ARV7518PW_ATH_ADDR, ARV7518PW_MAC_ADDR); + ltq_register_ath9k(arv_ath9k_eeprom_data, arv_athxk_eeprom_mac); + ltq_pci_ath_fixup(14, arv_ath9k_eeprom_data); + ltq_register_tapi(); + + gpio_request(ARV7518PW_SWITCH_RESET, "switch"); + gpio_direction_output(ARV7518PW_SWITCH_RESET, 1); + gpio_export(ARV7518PW_SWITCH_RESET, 0); +} + +MIPS_MACHINE(LANTIQ_MACH_ARV7518PW, + "ARV7518PW", + "ARV7518PW - ASTORIA", + arv7518pw_init); + +static void __init +arv752dpw22_init(void) +{ +#define ARV752DPW22_EBU 0x2 +#define ARV752DPW22_USB 100 +#define ARV752DPW22_RELAY 101 +#define ARV752DPW22_MAC_ADDR 0x7f0016 + + arv_load_nor(0x800000); + ltq_register_gpio_ebu(ARV752DPW22_EBU); + ltq_add_device_gpio_leds(-1, ARRAY_SIZE(arv752dpw22_gpio_leds), arv752dpw22_gpio_leds); + ltq_register_gpio_keys_polled(-1, LTQ_KEYS_POLL_INTERVAL, + ARRAY_SIZE(arv752dpw22_gpio_keys), arv752dpw22_gpio_keys); + ltq_pci_data.irq[15] = (INT_NUM_IM3_IRL0 + 31); + ltq_pci_data.gpio |= PCI_EXIN1 | PCI_REQ2; + ltq_register_pci(<q_pci_data); + xway_register_dwc(ARV752DPW22_USB); + arv_register_ethernet(ARV752DPW22_MAC_ADDR); + ltq_register_tapi(); + + gpio_request(ARV752DPW22_RELAY, "relay"); + gpio_set_value(ARV752DPW22_RELAY, 1); + gpio_export(ARV752DPW22_RELAY, 0); +} + +MIPS_MACHINE(LANTIQ_MACH_ARV752DPW22, + "ARV752DPW22", + "ARV752DPW22 - Arcor A803", + arv752dpw22_init); + +static void __init +arv752dpw_init(void) +{ +#define ARV752DPW22_EBU 0x2 +#define ARV752DPW22_USB 100 +#define ARV752DPW22_RELAY 101 +#define ARV752DPW22_MAC_ADDR 0x7f0016 + + arv_load_nor(0x800000); + ltq_register_gpio_ebu(ARV752DPW22_EBU); + ltq_add_device_gpio_leds(-1, ARRAY_SIZE(arv752dpw22_gpio_leds), arv752dpw22_gpio_leds); + ltq_register_gpio_keys_polled(-1, LTQ_KEYS_POLL_INTERVAL, ARRAY_SIZE(arv752dpw22_gpio_keys), arv752dpw22_gpio_keys); + ltq_pci_data.irq[14] = (INT_NUM_IM3_IRL0 + 31); + ltq_pci_data.gpio |= PCI_EXIN1 | PCI_REQ2; + ltq_register_pci(<q_pci_data); + ltq_register_tapi(); + xway_register_dwc(ARV752DPW22_USB); + ltq_register_rt2x00("RT2860.eeprom", NULL); + arv_register_ethernet(ARV752DPW22_MAC_ADDR); + gpio_request(ARV752DPW22_RELAY, "relay"); + gpio_set_value(ARV752DPW22_RELAY, 1); + gpio_export(ARV752DPW22_RELAY, 0); + +} + +MIPS_MACHINE(LANTIQ_MACH_ARV752DPW, + "ARV752DPW", + "ARV752DPW - Arcor A802", + arv752dpw_init); diff --git a/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/mach-bthomehubv2b.c b/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/mach-bthomehubv2b.c new file mode 100644 index 000000000..44fe2f4ef --- /dev/null +++ b/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/mach-bthomehubv2b.c @@ -0,0 +1,542 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2011 Andrej VlaÅ¡ić + * Copyright (C) 2011 Luka Perkov + * + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/leds.h> +#include <linux/gpio.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> +#include <linux/mtd/physmap.h> +#include <linux/input.h> +#include <linux/ath5k_platform.h> +#include <linux/ath9k_platform.h> +#include <linux/pci.h> +#include <linux/phy.h> +#include <linux/io.h> +#include <linux/string.h> +#include <linux/delay.h> +#include <linux/module.h> + +#include <irq.h> +#include <lantiq_soc.h> +#include <lantiq_platform.h> +#include <dev-gpio-leds.h> +#include <dev-gpio-buttons.h> + +#include "../machtypes.h" +//#include "dev-wifi-ath9k.h" +#include "devices.h" +#include "dev-dwc_otg.h" + +#undef USE_BTHH_GPIO_INIT + +// this reads certain data from u-boot if it's there +#define USE_UBOOT_ENV_DATA + +#define UBOOT_ENV_OFFSET 0x040000 +#define UBOOT_ENV_SIZE 0x010000 + +#ifdef NAND_ORGLAYOUT +// this is only here for reference +// definition of NAND flash area +static struct mtd_partition bthomehubv2b_nand_partitions[] = +{ + { + .name = "ART", + .offset = 0x0000000, + .size = 0x0004000, + }, + { + .name = "image1", + .offset = 0x0004000, + .size = 0x0E00000, + }, + { + .name = "unknown1", + .offset = 0x0E04000, + .size = 0x00FC000, + }, + { + .name = "image2", + .offset = 0x0F00000, + .size = 0x0E00000, + }, + { + .name = "unknown2", + .offset = 0x1D00000, + .size = 0x0300000, + }, + +}; +#endif + +#ifdef NAND_KEEPOPENRG +// this allows both firmwares to co-exist + +static struct mtd_partition bthomehubv2b_nand_partitions[] = +{ + { + .name = "art", + .offset = 0x0000000, + .size = 0x0004000, + }, + { + .name = "Image1", + .offset = 0x0004000, + .size = 0x0E00000, + }, + { + .name = "linux", + .offset = 0x0E04000, + .size = 0x11fC000, + }, + { + .name = "wholeflash", + .offset = 0x0000000, + .size = 0x2000000, + }, + +}; +#endif + +// this gives more jffs2 by overwriting openrg + +static struct mtd_partition bthomehubv2b_nand_partitions[] = +{ + { + .name = "art", + .offset = 0x0000000, + .size = 0x0004000, + }, + { + .name = "linux", + .offset = 0x0004000, + .size = 0x1ffC000, + }, + { + .name = "wholeflash", + .offset = 0x0000000, + .size = 0x2000000, + }, + +}; + +extern void __init xway_register_nand(struct mtd_partition *parts, int count); + +// end BTHH_USE_NAND + +static struct gpio_led +bthomehubv2b_gpio_leds[] __initdata = { + + { .name = "soc:orange:upgrading", .gpio = 213, }, + { .name = "soc:orange:phone", .gpio = 214, }, + { .name = "soc:blue:phone", .gpio = 215, }, + { .name = "soc:orange:wireless", .gpio = 216, }, + { .name = "soc:blue:wireless", .gpio = 217, }, + { .name = "soc:red:broadband", .gpio = 218, }, + { .name = "soc:orange:broadband", .gpio = 219, }, + { .name = "soc:blue:broadband", .gpio = 220, }, + { .name = "soc:red:power", .gpio = 221, }, + { .name = "soc:orange:power", .gpio = 222, }, + { .name = "soc:blue:power", .gpio = 223, }, +}; + +static struct gpio_keys_button +bthomehubv2b_gpio_keys[] __initdata = { + { + .desc = "restart", + .type = EV_KEY, + .code = BTN_0, + .debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL, + .gpio = 2, + .active_low = 1, + }, + { + .desc = "findhandset", + .type = EV_KEY, + .code = BTN_1, + .debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL, + .gpio = 15, + .active_low = 1, + }, + { + .desc = "wps", + .type = EV_KEY, + .code = BTN_2, + .debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL, + .gpio = 22, + .active_low = 1, + }, +}; + +// definition of NOR flash area - as per original. +static struct mtd_partition bthomehubv2b_partitions[] = +{ + { + .name = "uboot", + .offset = 0x000000, + .size = 0x040000, + }, + { + .name = "uboot_env", + .offset = UBOOT_ENV_OFFSET, + .size = UBOOT_ENV_SIZE, + }, + { + .name = "rg_conf_1", + .offset = 0x050000, + .size = 0x010000, + }, + { + .name = "rg_conf_2", + .offset = 0x060000, + .size = 0x010000, + }, + { + .name = "rg_conf_factory", + .offset = 0x070000, + .size = 0x010000, + }, +}; + + +/* nor flash */ +/* bt homehubv2b has a very small nor flash */ +/* so make it look for a small one, else we get a lot of alias chips identified - */ +/* not a bug problem, but fills the logs. */ +static struct resource bthhv2b_nor_resource = + MEM_RES("nor", LTQ_FLASH_START, 0x80000); + +static struct platform_device ltq_nor = { + .name = "ltq_nor", + .resource = &bthhv2b_nor_resource, + .num_resources = 1, +}; + +static void __init bthhv2b_register_nor(struct physmap_flash_data *data) +{ + ltq_nor.dev.platform_data = data; + platform_device_register(<q_nor); +} + +static struct physmap_flash_data bthomehubv2b_flash_data = { + .nr_parts = ARRAY_SIZE(bthomehubv2b_partitions), + .parts = bthomehubv2b_partitions, +}; + + + + +static struct ltq_pci_data ltq_pci_data = { + .clock = PCI_CLOCK_INT, + .gpio = PCI_GNT1 | PCI_REQ1, + .irq = { [14] = INT_NUM_IM0_IRL0 + 22, }, +}; + + + + +static struct ltq_eth_data ltq_eth_data = { + .mii_mode = PHY_INTERFACE_MODE_MII, +}; + + + + +static char __init *get_uboot_env_var(char *haystack, int haystack_len, char *needle, int needle_len) { + int i; + for (i = 0; i <= haystack_len - needle_len; i++) { + if (memcmp(haystack + i, needle, needle_len) == 0) { + return haystack + i + needle_len; + } + } + return NULL; +} + +/* + * bthomehubv2b_parse_hex_* are not uniq. in arm/orion there are also duplicates: + * dns323_parse_hex_* + * TODO: one day write a patch for this :) + */ +static int __init bthomehubv2b_parse_hex_nibble(char n) { + if (n >= '0' && n <= '9') + return n - '0'; + + if (n >= 'A' && n <= 'F') + return n - 'A' + 10; + + if (n >= 'a' && n <= 'f') + return n - 'a' + 10; + + return -1; +} + +static int __init bthomehubv2b_parse_hex_byte(const char *b) { + int hi; + int lo; + + hi = bthomehubv2b_parse_hex_nibble(b[0]); + lo = bthomehubv2b_parse_hex_nibble(b[1]); + + if (hi < 0 || lo < 0) + return -1; + + return (hi << 4) | lo; +} + +static int __init bthomehubv2b_register_ethernet(void) { + u_int8_t addr[6]; + int i; + char *mac = "01:02:03:04:05:06"; + int gotmac = 0; + char *boardid = "BTHHV2B"; + int gotboardid = 0; + + char *uboot_env_page; + uboot_env_page = ioremap(LTQ_FLASH_START + UBOOT_ENV_OFFSET, UBOOT_ENV_SIZE); + if (uboot_env_page) + { + char *Data = NULL; + Data = get_uboot_env_var(uboot_env_page, UBOOT_ENV_SIZE, "\0ethaddr=", 9); + if (Data) + { + mac = Data; + } + + Data = get_uboot_env_var(uboot_env_page, UBOOT_ENV_SIZE, "\0boardid=", 9); + + if (Data) + boardid = Data; + } + else + { + printk("bthomehubv2b: Failed to get uboot_env_page"); + } + + if (!mac) { + goto error_fail; + } + + if (!boardid) { + goto error_fail; + } + + /* Sanity check the string we're looking at */ + for (i = 0; i < 5; i++) { + if (*(mac + (i * 3) + 2) != ':') { + goto error_fail; + } + } + + for (i = 0; i < 6; i++) { + int byte; + byte = bthomehubv2b_parse_hex_byte(mac + (i * 3)); + if (byte < 0) { + goto error_fail; + } + addr[i] = byte; + } + + if (gotmac) + printk("bthomehubv2b: Found ethernet MAC address: "); + else + printk("bthomehubv2b: using default MAC (pls set ethaddr in u-boot): "); + + for (i = 0; i < 6; i++) + printk("%.2x%s", addr[i], (i < 5) ? ":" : ".\n"); + + memcpy(<q_eth_data.mac.sa_data, addr, 6); + ltq_register_etop(<q_eth_data); + + //memcpy(&bthomehubv2b_ath5k_eeprom_mac, addr, 6); + //bthomehubv2b_ath5k_eeprom_mac[5]++; + + if (gotboardid) + printk("bthomehubv2b: Board id is %s.", boardid); + else + printk("bthomehubv2b: Default Board id is %s.", boardid); + + if (strncmp(boardid, "BTHHV2B", 7) == 0) { + // read in dev-wifi-ath9k + //memcpy(&bthomehubv2b_ath5k_eeprom_data, sx763_eeprom_data, ATH5K_PLAT_EEP_MAX_WORDS); + } + else { + printk("bthomehubv2b: Board id is unknown, fix uboot_env data."); + } + + + // should not unmap while we are using the ram? + if (uboot_env_page) + iounmap(uboot_env_page); + + return 0; + +error_fail: + if (uboot_env_page) + iounmap(uboot_env_page); + return -EINVAL; +} + + +#define PORTA2_HW_PASS1 0 +#define PORTA2_HW_PASS1_SC14480 1 +#define PORTA2_HW_PASS2 2 + +int porta2_hw_revision = -1; +EXPORT_SYMBOL(porta2_hw_revision); + +#define LTQ_GPIO_OUT 0x00 +#define LTQ_GPIO_IN 0x04 +#define LTQ_GPIO_DIR 0x08 +#define LTQ_GPIO_ALTSEL0 0x0C +#define LTQ_GPIO_ALTSEL1 0x10 +#define LTQ_GPIO_OD 0x14 +#define LTQ_GPIO_PUDSEL 0x1C +#define LTQ_GPIO_PUDEN 0x20 + +#ifdef USE_BTHH_GPIO_INIT +static void bthomehubv2b_board_prom_init(void) +{ + int revision = 0; + unsigned int gpio = 0; + void __iomem *mem = ioremap(LTQ_GPIO0_BASE_ADDR, LTQ_GPIO_SIZE*2); + +#define DANUBE_GPIO_P0_OUT (unsigned short *)(mem + LTQ_GPIO_OUT) +#define DANUBE_GPIO_P0_IN (unsigned short *)(mem + LTQ_GPIO_IN) +#define DANUBE_GPIO_P0_DIR (unsigned short *)(mem + LTQ_GPIO_DIR) +#define DANUBE_GPIO_P0_ALTSEL0 (unsigned short *)(mem + LTQ_GPIO_ALTSEL0) +#define DANUBE_GPIO_P0_ALTSEL1 (unsigned short *)(mem + LTQ_GPIO_ALTSEL1) + +#define DANUBE_GPIO_P1_OUT (unsigned short *)(mem + LTQ_GPIO_SIZE + LTQ_GPIO_OUT) +#define DANUBE_GPIO_P1_IN (unsigned short *)(mem + LTQ_GPIO_SIZE + LTQ_GPIO_IN) +#define DANUBE_GPIO_P1_DIR (unsigned short *)(mem + LTQ_GPIO_SIZE + LTQ_GPIO_DIR) +#define DANUBE_GPIO_P1_ALTSEL0 (unsigned short *)(mem + LTQ_GPIO_SIZE + LTQ_GPIO_ALTSEL0) +#define DANUBE_GPIO_P1_ALTSEL1 (unsigned short *)(mem + LTQ_GPIO_SIZE + LTQ_GPIO_ALTSEL1) +#define DANUBE_GPIO_P1_OD (unsigned short *)(mem + LTQ_GPIO_SIZE + LTQ_GPIO_OD) + + printk("About to sense board using GPIOs at %8.8X\n", (unsigned int)mem); + + + /* First detect HW revision of the board. For that we need to set the GPIO + * lines according to table 7.2.1/7.2.2 in HSI */ + *DANUBE_GPIO_P0_OUT = 0x0200; + *DANUBE_GPIO_P0_DIR = 0x2610; + *DANUBE_GPIO_P0_ALTSEL0 = 0x7812; + *DANUBE_GPIO_P0_ALTSEL1 = 0x0000; + + *DANUBE_GPIO_P1_OUT = 0x7008; + *DANUBE_GPIO_P1_DIR = 0xF3AE; + *DANUBE_GPIO_P1_ALTSEL0 = 0x83A7; + *DANUBE_GPIO_P1_ALTSEL1 = 0x0400; + + gpio = (*DANUBE_GPIO_P0_IN & 0xFFFF) | + ((*DANUBE_GPIO_P1_IN & 0xFFFF) << 16); + + revision |= (gpio & (1 << 27)) ? (1 << 0) : 0; + revision |= (gpio & (1 << 20)) ? (1 << 1) : 0; + revision |= (gpio & (1 << 8)) ? (1 << 2) : 0; + revision |= (gpio & (1 << 6)) ? (1 << 3) : 0; + revision |= (gpio & (1 << 5)) ? (1 << 4) : 0; + revision |= (gpio & (1 << 0)) ? (1 << 5) : 0; + + porta2_hw_revision = revision; + printk("PORTA2: detected HW revision %d\n", revision); + + /* Set GPIO lines according to HW revision. */ + /* !!! Note that we are setting SPI_CS5 (GPIO 9) to be GPIO out with value + * of HIGH since the FXO does not use the SPI CS mechanism, it does it + * manually by controlling the GPIO line. We need the CS line to be disabled + * (HIGH) until needed since it will intefere with other devices on the SPI + * bus. */ + *DANUBE_GPIO_P0_OUT = 0x0200; + /* + * During the manufacturing process a different machine takes over uart0 + * so set it as input (so it wouldn't drive the line) + */ +#define cCONFIG_SHC_BT_MFG_TEST 0 + *DANUBE_GPIO_P0_DIR = 0x2671 | (cCONFIG_SHC_BT_MFG_TEST ? 0 : (1 << 12)); + + if (revision == PORTA2_HW_PASS1_SC14480 || revision == PORTA2_HW_PASS2) + *DANUBE_GPIO_P0_ALTSEL0 = 0x7873; + else + *DANUBE_GPIO_P0_ALTSEL0 = 0x3873; + + *DANUBE_GPIO_P0_ALTSEL1 = 0x0001; + + + //################################################################################### + // Register values before patch + // P1_ALTSEL0 = 0x83A7 + // P1_ALTSEL1 = 0x0400 + // P1_OU T = 0x7008 + // P1_DIR = 0xF3AE + // P1_OD = 0xE3Fc + printk("\nApplying Patch for CPU1 IRQ Issue\n"); + *DANUBE_GPIO_P1_ALTSEL0 &= ~(1<<12); // switch P1.12 (GPIO28) to GPIO functionality + *DANUBE_GPIO_P1_ALTSEL1 &= ~(1<<12); // switch P1.12 (GPIO28) to GPIO functionality + *DANUBE_GPIO_P1_OUT &= ~(1<<12); // set P1.12 (GPIO28) to 0 + *DANUBE_GPIO_P1_DIR |= (1<<12); // configure P1.12 (GPIO28) as output + *DANUBE_GPIO_P1_OD |= (1<<12); // activate Push/Pull mode + udelay(100); // wait a little bit (100us) + *DANUBE_GPIO_P1_OD &= ~(1<<12); // switch back from Push/Pull to Open Drain + // important: before! setting output to 1 (3,3V) the mode must be switched + // back to Open Drain because the reset pin of the SC14488 is internally + // pulled to 1,8V + *DANUBE_GPIO_P1_OUT |= (1<<12); // set output P1.12 (GPIO28) to 1 + // Register values after patch, should be the same as before + // P1_ALTSEL0 = 0x83A7 + // P1_ALTSEL1 = 0x0400 + // P1_OUT = 0x7008 + // P1_DIR = 0xF3AE + // P1_OD = 0xE3Fc + //################################################################################### + + + *DANUBE_GPIO_P1_OUT = 0x7008; + *DANUBE_GPIO_P1_DIR = 0xEBAE | (revision == PORTA2_HW_PASS2 ? 0x1000 : 0); + *DANUBE_GPIO_P1_ALTSEL0 = 0x8BA7; + *DANUBE_GPIO_P1_ALTSEL1 = 0x0400; + + iounmap(mem); +} +#endif +static void __init bthomehubv2b_init(void) { +#define bthomehubv2b_USB 13 + + // read the board version +#ifdef USE_BTHH_GPIO_INIT + bthomehubv2b_board_prom_init(); +#endif + + // register extra GPPOs used by LEDs as GPO 0x200+ + ltq_register_gpio_stp(); + ltq_add_device_gpio_leds(-1, ARRAY_SIZE(bthomehubv2b_gpio_leds), bthomehubv2b_gpio_leds); + bthhv2b_register_nor(&bthomehubv2b_flash_data); + xway_register_nand(bthomehubv2b_nand_partitions, ARRAY_SIZE(bthomehubv2b_nand_partitions)); + ltq_register_pci(<q_pci_data); + ltq_register_tapi(); + ltq_register_gpio_keys_polled(-1, LTQ_KEYS_POLL_INTERVAL, ARRAY_SIZE(bthomehubv2b_gpio_keys), bthomehubv2b_gpio_keys); +// ltq_register_ath9k(); + xway_register_dwc(bthomehubv2b_USB); + bthomehubv2b_register_ethernet(); + +} + +MIPS_MACHINE(LANTIQ_MACH_BTHOMEHUBV2BOPENRG, + "BTHOMEHUBV2BOPENRG", + "BTHOMEHUBV2B - BT Homehub V2.0 Type B with OpenRG image retained", + bthomehubv2b_init); + +MIPS_MACHINE(LANTIQ_MACH_BTHOMEHUBV2B, + "BTHOMEHUBV2B", + "BTHOMEHUBV2B - BT Homehub V2.0 Type B", + bthomehubv2b_init); diff --git a/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/mach-fritz_ar9.c b/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/mach-fritz_ar9.c new file mode 100644 index 000000000..5bd634180 --- /dev/null +++ b/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/mach-fritz_ar9.c @@ -0,0 +1,115 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin <blogic@openwrt.org> + */ + +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> +#include <linux/mtd/physmap.h> +#include <linux/input.h> +#include <linux/phy.h> +#include <linux/spi/spi_gpio.h> +#include <linux/spi/flash.h> + +#include <lantiq_soc.h> +#include <irq.h> + +#include "../machtypes.h" +#include "devices.h" +#include "dev-ifxhcd.h" +#include "dev-gpio-leds.h" +#include "dev-gpio-buttons.h" + +static struct mtd_partition fritz7320_partitions[] = { + { + .name = "urlader", + .offset = 0x0, + .size = 0x20000, + }, + { + .name = "linux", + .offset = 0x20000, + .size = 0xf60000, + }, + { + .name = "tffs (1)", + .offset = 0xf80000, + .size = 0x40000, + }, + { + .name = "tffs (2)", + .offset = 0xfc0000, + .size = 0x40000, + }, +}; + +static struct physmap_flash_data fritz7320_flash_data = { + .nr_parts = ARRAY_SIZE(fritz7320_partitions), + .parts = fritz7320_partitions, +}; + +static struct gpio_led +fritz7320_gpio_leds[] __initdata = { + { .name = "soc:green:power", .gpio = 44, .active_low = 1, .default_trigger = "default-on" }, + { .name = "soc:green:internet", .gpio = 47, .active_low = 1, .default_trigger = "default-on" }, + { .name = "soc:green:dect", .gpio = 38, .active_low = 1, .default_trigger = "default-on" }, + { .name = "soc:green:wlan", .gpio = 37, .active_low = 1, .default_trigger = "default-on" }, + { .name = "soc:green:dual1", .gpio = 35, .active_low = 1, .default_trigger = "default-on" }, + { .name = "soc:red:dual2", .gpio = 45, .active_low = 1, .default_trigger = "default-on" }, +}; + +static struct gpio_keys_button +fritz7320_gpio_keys[] __initdata = { + { + .desc = "wifi", + .type = EV_KEY, + .code = BTN_0, + .debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL, + .gpio = 1, + .active_low = 1, + }, + { + .desc = "dect", + .type = EV_KEY, + .code = BTN_1, + .debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL, + .gpio = 2, + .active_low = 1, + }, +}; + +static struct ltq_pci_data ltq_pci_data = { + .clock = PCI_CLOCK_INT, + .gpio = PCI_GNT1 | PCI_REQ1, + .irq = { + [14] = INT_NUM_IM0_IRL0 + 22, + }, +}; + +static struct ltq_eth_data ltq_eth_data = { + .mii_mode = PHY_INTERFACE_MODE_RMII, +}; + +static int usb_pins[2] = { 50, 51 }; + +static void __init +fritz7320_init(void) +{ + ltq_register_gpio_keys_polled(-1, LTQ_KEYS_POLL_INTERVAL, + ARRAY_SIZE(fritz7320_gpio_keys), fritz7320_gpio_keys); + ltq_add_device_gpio_leds(-1, ARRAY_SIZE(fritz7320_gpio_leds), fritz7320_gpio_leds); + ltq_register_pci(<q_pci_data); + ltq_register_etop(<q_eth_data); + ltq_register_nor(&fritz7320_flash_data); + xway_register_hcd(usb_pins); +} + +MIPS_MACHINE(LANTIQ_MACH_FRITZ7320, + "FRITZ7320", + "FRITZ!BOX 7320", + fritz7320_init); diff --git a/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/mach-fritz_vr9.c b/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/mach-fritz_vr9.c new file mode 100644 index 000000000..293c7b750 --- /dev/null +++ b/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/mach-fritz_vr9.c @@ -0,0 +1,164 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin <blogic@openwrt.org> + */ + +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> +#include <linux/mtd/physmap.h> +#include <linux/input.h> +#include <linux/phy.h> +#include <linux/spi/spi_gpio.h> +#include <linux/spi/flash.h> + +#include <lantiq_soc.h> +#include <irq.h> + +#include "../machtypes.h" +#include "devices.h" +#include "dev-ifxhcd.h" +#include "dev-gpio-leds.h" +#include "dev-gpio-buttons.h" + +static struct mtd_partition fritz3370_partitions[] = { + { + .name = "linux", + .offset = 0x0, + .size = 0x400000, + }, + { + .name = "filesystem", + .offset = 0x400000, + .size = 0x3000000, + }, + { + .name = "reserved-kernel", + .offset = 0x3400000, + .size = 0x400000, + }, + { + .name = "reserved", + .offset = 0x3800000, + .size = 0x3000000, + }, + { + .name = "config", + .offset = 0x6800000, + .size = 0x200000, + }, + { + .name = "nand-filesystem", + .offset = 0x6a00000, + .size = 0x1600000, + }, +}; + +static struct mtd_partition spi_flash_partitions[] = { + { + .name = "urlader", + .offset = 0x0, + .size = 0x20000, + }, + { + .name = "tffs", + .offset = 0x20000, + .size = 0x10000, + }, + { + .name = "tffs", + .offset = 0x30000, + .size = 0x10000, + }, +}; + +static struct gpio_led +fritz3370_gpio_leds[] __initdata = { + { .name = "soc:green:1", .gpio = 32, .active_low = 1, .default_trigger = "default-on" }, + { .name = "soc:red:2", .gpio = 33, .active_low = 1, .default_trigger = "default-on" }, + { .name = "soc:red:3", .gpio = 34, .active_low = 1, .default_trigger = "default-on" }, + { .name = "soc:green:4", .gpio = 35, .active_low = 1, .default_trigger = "default-on" }, + { .name = "soc:green:5", .gpio = 36, .active_low = 1, .default_trigger = "default-on" }, + { .name = "soc:green:6", .gpio = 47, .active_low = 1, .default_trigger = "default-on" }, +}; + +static struct gpio_keys_button +fritz3370_gpio_keys[] __initdata = { + { + .desc = "wifi", + .type = EV_KEY, + .code = BTN_0, + .debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL, + .gpio = 29, + .active_low = 1, + }, +}; + +static struct ltq_eth_data ltq_eth_data = { + .mii_mode = PHY_INTERFACE_MODE_RMII, +}; + +static int usb_pins[2] = { 5, 14 }; + +#define SPI_GPIO_MRST 16 +#define SPI_GPIO_MTSR 17 +#define SPI_GPIO_CLK 18 +#define SPI_GPIO_CS0 10 + +static struct spi_gpio_platform_data spi_gpio_data = { + .sck = SPI_GPIO_CLK, + .mosi = SPI_GPIO_MTSR, + .miso = SPI_GPIO_MRST, + .num_chipselect = 2, +}; + +static struct platform_device spi_gpio_device = { + .name = "spi_gpio", + .dev.platform_data = &spi_gpio_data, +}; + +static struct flash_platform_data spi_flash_data = { + .name = "SPL", + .parts = spi_flash_partitions, + .nr_parts = ARRAY_SIZE(spi_flash_partitions), +}; + +static struct spi_board_info spi_flash __initdata = { + .modalias = "m25p80", + .bus_num = 0, + .chip_select = 0, + .max_speed_hz = 10 * 1000 * 1000, + .mode = SPI_MODE_3, + .chip_select = 0, + .controller_data = (void *) SPI_GPIO_CS0, + .platform_data = &spi_flash_data +}; + +static void __init +spi_gpio_init(void) +{ + spi_register_board_info(&spi_flash, 1); + platform_device_register(&spi_gpio_device); +} + +static void __init +fritz3370_init(void) +{ + spi_gpio_init(); + platform_device_register_simple("pcie-xway", 0, NULL, 0); + xway_register_nand(fritz3370_partitions, ARRAY_SIZE(fritz3370_partitions)); + xway_register_hcd(usb_pins); + ltq_add_device_gpio_leds(-1, ARRAY_SIZE(fritz3370_gpio_leds), fritz3370_gpio_leds); + ltq_register_gpio_keys_polled(-1, LTQ_KEYS_POLL_INTERVAL, + ARRAY_SIZE(fritz3370_gpio_keys), fritz3370_gpio_keys); + ltq_register_vrx200(<q_eth_data); +} + +MIPS_MACHINE(LANTIQ_MACH_FRITZ3370, + "FRITZ3370", + "FRITZ!BOX 3370", + fritz3370_init); diff --git a/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/mach-gigasx76x.c b/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/mach-gigasx76x.c new file mode 100644 index 000000000..af27825cb --- /dev/null +++ b/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/mach-gigasx76x.c @@ -0,0 +1,168 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2011 Andrej VlaÅ¡ić + * Copyright (C) 2011 Luka Perkov + * + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/leds.h> +#include <linux/gpio.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> +#include <linux/mtd/physmap.h> +#include <linux/input.h> +#include <linux/pci.h> +#include <linux/phy.h> +#include <linux/io.h> +#include <linux/if_ether.h> +#include <linux/etherdevice.h> +#include <linux/string.h> + +#include <irq.h> +#include <lantiq_soc.h> +#include <lantiq_platform.h> +#include <dev-gpio-leds.h> +#include <dev-gpio-buttons.h> + +#include "../machtypes.h" +#include "dev-wifi-athxk.h" +#include "devices.h" +#include "dev-dwc_otg.h" + +#include "mach-gigasx76x.h" + +static u8 ltq_ethaddr[6] = { 0 }; + +static int __init +setup_ethaddr(char *str) +{ + if (!mac_pton(str, ltq_ethaddr)) + memset(ltq_ethaddr, 0, 6); + return 0; +} +__setup("ethaddr=", setup_ethaddr); + + +enum { + UNKNOWN = 0, + SX761, + SX762, + SX763, +}; +static u8 board __initdata = SX763; + +static int __init +setup_board(char *str) +{ + if (!strcmp(str, "sx761")) + board = SX761; + else if (!strcmp(str, "sx762")) + board = SX762; + else if (!strcmp(str, "sx763")) + board = SX763; + else + board = UNKNOWN; + return 0; +} +__setup("board=", setup_board); + +static struct mtd_partition gigasx76x_partitions[] = +{ + { + .name = "uboot", + .offset = 0x0, + .size = 0x10000, + }, + { + .name = "uboot_env", + .offset = 0x10000, + .size = 0x10000, + }, + { + .name = "linux", + .offset = 0x20000, + .size = 0x7e0000, + }, +}; + +static struct gpio_led +gigasx76x_gpio_leds[] __initdata = { + { .name = "soc:green:voip", .gpio = 216, }, + { .name = "soc:green:adsl", .gpio = 217, }, + { .name = "soc:green:usb", .gpio = 218, }, + { .name = "soc:green:wifi", .gpio = 219, }, + { .name = "soc:green:phone2", .gpio = 220, }, + { .name = "soc:green:phone1", .gpio = 221, }, + { .name = "soc:green:line", .gpio = 222, }, + { .name = "soc:green:online", .gpio = 223, }, +}; + +static struct gpio_keys_button +gigasx76x_gpio_keys[] __initdata = { + { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL, + .gpio = 22, + .active_low = 1, + }, + { + .desc = "reset", + .type = EV_KEY, + .code = BTN_0, + .debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL, + .gpio = 14, + .active_low = 0, + }, +}; + +static struct physmap_flash_data gigasx76x_flash_data = { + .nr_parts = ARRAY_SIZE(gigasx76x_partitions), + .parts = gigasx76x_partitions, +}; + +static struct ltq_pci_data ltq_pci_data = { + .clock = PCI_CLOCK_INT, + .gpio = PCI_GNT1 | PCI_REQ1, + .irq = { [14] = INT_NUM_IM0_IRL0 + 22, }, +}; + +static struct ltq_eth_data ltq_eth_data = { + .mii_mode = PHY_INTERFACE_MODE_MII, +}; + +static void __init +gigasx76x_init(void) +{ +#define GIGASX76X_USB 29 + + ltq_register_gpio_stp(); + ltq_register_nor(&gigasx76x_flash_data); + ltq_register_pci(<q_pci_data); + ltq_register_tapi(); + ltq_add_device_gpio_leds(-1, ARRAY_SIZE(gigasx76x_gpio_leds), gigasx76x_gpio_leds); + ltq_register_gpio_keys_polled(-1, LTQ_KEYS_POLL_INTERVAL, ARRAY_SIZE(gigasx76x_gpio_keys), gigasx76x_gpio_keys); + xway_register_dwc(GIGASX76X_USB); + + if (!is_valid_ether_addr(ltq_ethaddr)) + random_ether_addr(ltq_ethaddr); + + memcpy(<q_eth_data.mac.sa_data, ltq_ethaddr, 6); + ltq_register_etop(<q_eth_data); + if (board == SX762) + ltq_register_ath5k(sx762_eeprom_data, ltq_ethaddr); + else + ltq_register_ath5k(sx763_eeprom_data, ltq_ethaddr); +} + +MIPS_MACHINE(LANTIQ_MACH_GIGASX76X, + "GIGASX76X", + "GIGASX76X - Gigaset SX761,SX762,SX763", + gigasx76x_init); diff --git a/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/mach-gigasx76x.h b/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/mach-gigasx76x.h new file mode 100644 index 000000000..74e5ba28f --- /dev/null +++ b/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/mach-gigasx76x.h @@ -0,0 +1,210 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2011 Andrej VlaÅ¡ić + * Copyright (C) 2011 Luka Perkov + * + */ + +#ifndef _MACH_GIGASX76X_H__ +#define _MACH_GIGASX76X_H__ + +#include <linux/ath5k_platform.h> + +static u16 sx763_eeprom_data[ATH5K_PLAT_EEP_MAX_WORDS] = +{ +0x0013,0x168c,0x0200,0x0001,0x0000,0x5001,0x0000,0x2051,0x2051,0x1c0a,0x0100, +0x0000,0x01c2,0x0002,0xc606,0x0001,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0xf165,0x7fbe,0x0003,0x0000, +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x5aa5,0x0000,0x0000,0x0313,0x4943, +0x2053,0x7104,0x1202,0x0400,0x0306,0x0001,0x0000,0x0500,0x410e,0x39b1,0x1eb5, +0x4e2d,0x3056,0xffff,0xe902,0x0700,0x0106,0x0000,0x0100,0x1500,0x0752,0x4101, +0x6874,0x7265,0x736f,0x4320,0x6d6f,0x756d,0x696e,0x6163,0x6974,0x6e6f,0x2c73, +0x4920,0x636e,0x002e,0x5241,0x3035,0x3130,0x302d,0x3030,0x2d30,0x3030,0x3030, +0x5700,0x7269,0x6c65,0x7365,0x2073,0x414c,0x204e,0x6552,0x6566,0x6572,0x636e, +0x2065,0x6143,0x6472,0x3000,0x0030,0x00ff,0x2100,0x0602,0x2201,0x0205,0x8d80, +0x005b,0x0522,0x4002,0x8954,0x2200,0x0205,0x1b00,0x00b7,0x0522,0x8002,0x12a8, +0x2201,0x0205,0x3600,0x016e,0x0522,0x0002,0x2551,0x2202,0x0205,0x6c00,0x02dc, +0x0522,0x8002,0x37f9,0x2203,0x0205,0xa200,0x044a,0x0222,0x0803,0x0822,0x0604, +0x0300,0xbe7f,0x65f1,0x0222,0x0105,0x00ff,0x0000,0x0000,0x0000,0x0000,0x0000, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0x0037,0x971f,0x5003,0x9a66,0x0001,0x81c4,0x016a, +0x02ff,0x84ff,0x15a3,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, +0x0000,0x0000,0x0000,0x2d2c,0x0000,0x0000,0x0000,0x0000,0xe028,0xa492,0x1c00, +0x000e,0xb8ca,0x0013,0x0000,0x0000,0x6b4b,0xc059,0x1571,0x0000,0x0000,0x0000, +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, +0x2370,0x00a5,0x9618,0x419a,0x68a2,0xda35,0x001c,0x0007,0xb0ff,0x01b5,0x0000, +0x0000,0xff70,0x19ff,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, +0x0000,0x0000,0x0000,0x0000,0x0000,0x3170,0x00a5,0x9618,0x419a,0x68a2,0xda35, +0x001c,0x000e,0xb0ff,0x21b5,0x0000,0x2fd8,0xff70,0x1226,0x19ff,0x07be,0x6201, +0x032e,0x0587,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x1112, +0x1441,0x4231,0x3234,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, +0x0000,0x0000,0x0000,0x0000,0x8000,0x0000,0x0000,0x0000,0x0000,0x8000,0x0000, +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x4d31,0x7f54,0x3c93,0x1205,0x1931, +0x492d,0x7f50,0x3c93,0x0e01,0x192d,0x0070,0x0000,0x8140,0x724b,0x2ba9,0x3a09, +0x99d9,0x1949,0x0070,0x0000,0x80e0,0x624a,0x2af8,0x35c7,0x9d47,0x1938,0x0000, +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, +0x0000,0x0000,0x0000,0x0000,0x7082,0x0820,0xb882,0x0820,0x7092,0x28a0,0x8992, +0x28a0,0xa292,0x28a0,0x70a2,0xa7ac,0x0000,0x0000,0x2464,0x6424,0x0000,0x0000, +0x70a2,0xa7ac,0x0000,0x0000,0x2464,0x6424,0x0000,0x0000,0x8989,0x0000,0x0000, +0x0000,0x2424,0x0000,0x0000,0x0000,0x7075,0xa2ac,0xb800,0x0000,0x2464,0x2424, +0x2400,0x0000,0x7075,0xa2ac,0x0000,0x0000,0x2464,0x2424,0x0000,0x0000,0x7075, +0xa7ac,0x0000,0x0000,0x2464,0x6424,0x0000,0x0000,0x7075,0xa7ac,0x0000,0x0000, +0x2464,0x6424,0x0000,0x0000,0x8989,0x0000,0x0000,0x0000,0x2424,0x0000,0x0000, +0x0000,0x0000,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff}; + +static u16 sx762_eeprom_data[ATH5K_PLAT_EEP_MAX_WORDS] = +{ +0x001a,0x168c,0x0200,0x0001,0x0000,0x5001,0x0000,0x2051,0x2051,0x1c0a,0x0100, +0x0000,0x01c2,0x0002,0xc606,0x0001,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0xf165,0x7fbe,0x0003,0x0000, +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x5aa5,0x0000,0x0000,0x0313,0x4943, +0x2053,0x7104,0x1202,0x0400,0x0306,0x0001,0x0000,0x0500,0x410e,0x39b1,0x1eb5, +0x4e2d,0x3056,0xffff,0xe902,0x0700,0x0106,0x0000,0x0100,0x1500,0x0752,0x4101, +0x6874,0x7265,0x736f,0x4320,0x6d6f,0x756d,0x696e,0x6163,0x6974,0x6e6f,0x2c73, +0x4920,0x636e,0x002e,0x5241,0x3035,0x3130,0x302d,0x3030,0x2d30,0x3030,0x3030, +0x5700,0x7269,0x6c65,0x7365,0x2073,0x414c,0x204e,0x6552,0x6566,0x6572,0x636e, +0x2065,0x6143,0x6472,0x3000,0x0030,0x00ff,0x2100,0x0602,0x2201,0x0205,0x8d80, +0x005b,0x0522,0x4002,0x8954,0x2200,0x0205,0x1b00,0x00b7,0x0522,0x8002,0x12a8, +0x2201,0x0205,0x3600,0x016e,0x0522,0x0002,0x2551,0x2202,0x0205,0x6c00,0x02dc, +0x0522,0x8002,0x37f9,0x2203,0x0205,0xa200,0x044a,0x0222,0x0803,0x0822,0x0604, +0x0300,0xbe7f,0x65f1,0x0222,0x0105,0x00ff,0x0000,0x0000,0x0000,0x0000,0x0000, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0x0037,0x6aaa,0x5003,0x9a66,0x0001,0x81c4,0x016a, +0x02ff,0x84ff,0x15a3,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, +0x0000,0x0000,0x0000,0x2d2c,0x0000,0x0000,0x0000,0x0000,0xe028,0xa492,0x1c00, +0x000e,0xb8ca,0x0013,0x0000,0x0000,0x6b4b,0xc059,0x1571,0x0000,0x0000,0x0000, +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, +0x2370,0x00a5,0x9618,0x419a,0x68a2,0xda35,0x001c,0x0007,0xb0ff,0x01b5,0x0000, +0x0000,0xff70,0x19ff,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, +0x0000,0x0000,0x0000,0x0000,0x0000,0x3170,0x00a5,0x9618,0x419a,0x68a2,0xda35, +0x001c,0x000e,0xb0ff,0x21b5,0x0000,0x2fd8,0xff70,0x1226,0x19ff,0x07fa,0x6201, +0x032e,0x0587,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x1112, +0x1441,0x4231,0x3234,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, +0x0000,0x0000,0x0000,0x0000,0x8000,0x0000,0x0000,0x0000,0x0000,0x8000,0x0000, +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x4d31,0x7f54,0x3c93,0x1205,0x1931, +0x492d,0x7f50,0x3c93,0x0e01,0x192d,0x0070,0x0000,0x8180,0x724d,0xab59,0x3a08, +0xdd79,0x2559,0x0070,0x0000,0x81a0,0x6e4d,0x2b99,0x3a09,0x9989,0x2157,0x0000, +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, +0x0000,0x0000,0x0000,0x0000,0x7092,0x4924,0xb892,0x4924,0x7092,0x289e,0x8992, +0x289e,0xa292,0x289e,0x70a2,0xa7ac,0x0000,0x0000,0x2462,0x5e13,0x0000,0x0000, +0x70a2,0xa7ac,0x0000,0x0000,0x1e5c,0x5713,0x0000,0x0000,0x8989,0x0000,0x0000, +0x0000,0x2424,0x0000,0x0000,0x0000,0x7075,0xa2ac,0xb800,0x0000,0x2868,0x2828, +0x2800,0x0000,0x7075,0xa2ac,0x0000,0x0000,0x2868,0x2828,0x0000,0x0000,0x7075, +0xac00,0x0000,0x0000,0x2161,0x2100,0x0000,0x0000,0x7075,0xac00,0x0000,0x0000, +0x1b5b,0x1b00,0x0000,0x0000,0x8989,0x0000,0x0000,0x0000,0x2121,0x0000,0x0000, +0x0000,0x0000,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, +0xffff,0xffff}; + +#endif diff --git a/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/mach-h201l.c b/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/mach-h201l.c new file mode 100644 index 000000000..86101f588 --- /dev/null +++ b/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/mach-h201l.c @@ -0,0 +1,100 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2012 Luka Perkov <openwrt@lukaperkov.net> + */ + +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/leds.h> +#include <linux/gpio.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> +#include <linux/mtd/physmap.h> +#include <linux/input.h> +#include <linux/kernel.h> +#include <linux/delay.h> +#include <linux/io.h> +#include <linux/if_ether.h> +#include <linux/etherdevice.h> +#include <linux/string.h> + +#include <lantiq_soc.h> +#include <lantiq_platform.h> +#include <dev-gpio-leds.h> +#include <dev-gpio-buttons.h> + +#include "../machtypes.h" +#include "devices.h" +#include "dev-dwc_otg.h" + +static u8 ltq_ethaddr[6] = { 0 }; + +static int __init +setup_ethaddr(char *str) +{ + if (!mac_pton(str, ltq_ethaddr)) + memset(ltq_ethaddr, 0, 6); + return 0; +} +__setup("ethaddr=", setup_ethaddr); + +static struct mtd_partition h201l_partitions[] __initdata = +{ + { + .name = "uboot", + .offset = 0x0, + .size = 0x20000, + }, + { + .name = "uboot_env", + .offset = 0x20000, + .size = 0x10000, + }, + { + .name = "linux", + .offset = 0x30000, + .size = 0x7d0000, + }, +}; + +static struct physmap_flash_data h201l_flash_data __initdata = { + .nr_parts = ARRAY_SIZE(h201l_partitions), + .parts = h201l_partitions, +}; + +static struct gpio_led +h201l_leds_gpio[] __initdata = { +}; + +static struct gpio_keys_button +h201l_gpio_keys[] __initdata = { +}; + +static struct ltq_eth_data ltq_eth_data = { + .mii_mode = PHY_INTERFACE_MODE_RMII, +}; + +static void __init +h201l_init(void) +{ + ltq_register_gpio_stp(); + ltq_register_nor(&h201l_flash_data); + ltq_add_device_gpio_leds(-1, ARRAY_SIZE(h201l_leds_gpio), h201l_leds_gpio); + ltq_register_gpio_keys_polled(-1, LTQ_KEYS_POLL_INTERVAL, ARRAY_SIZE(h201l_gpio_keys), h201l_gpio_keys); + + if (!is_valid_ether_addr(ltq_ethaddr)) + random_ether_addr(ltq_ethaddr); + + memcpy(<q_eth_data.mac.sa_data, ltq_ethaddr, 6); + ltq_register_etop(<q_eth_data); + + xway_register_dwc(-1); +} + +MIPS_MACHINE(LANTIQ_MACH_H201L, + "H201L", + "ZTE ZXV10 H201L", + h201l_init); diff --git a/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/mach-netgear.c b/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/mach-netgear.c new file mode 100644 index 000000000..29b072810 --- /dev/null +++ b/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/mach-netgear.c @@ -0,0 +1,239 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin <blogic@openwrt.org> + * Copyright (C) 2012 Pieter Voorthuijsen <p.voorthuijsen@gmail.com> + */ + +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> +#include <linux/mtd/physmap.h> +#include <linux/input.h> +#include <linux/phy.h> +#include <linux/spi/spi.h> +#include <linux/spi/flash.h> +#include <linux/spi/spi_gpio.h> +#include <linux/ath9k_platform.h> +#include <linux/if_ether.h> +#include <linux/etherdevice.h> +#include <linux/kobject.h> +#include <linux/sysfs.h> + +#include <lantiq_soc.h> +#include <irq.h> +#include <dev-gpio-leds.h> +#include <dev-gpio-buttons.h> +#include "dev-wifi-athxk.h" + +#include "../machtypes.h" +#include "devices.h" +#include "dev-dwc_otg.h" +#include "pci-ath-fixup.h" +#include <mtd/mtd-abi.h> +#include <asm-generic/sizes.h> + +static struct mtd_partition dgn3500_partitions[] = { + { + .name = "u-boot", + .offset = 0, + .size = 0x10000, + .mask_flags = MTD_WRITEABLE, + }, + { + .name = "environment", + .offset = 0x10000, + .size = 0x10000, + .mask_flags = MTD_WRITEABLE, + }, + { + .name = "calibration", + .offset = 0x20000, + .size = 0x10000, + .mask_flags = MTD_WRITEABLE, + }, + { + .name = "linux", + .offset = 0x50000, + .size = 0xfa0000, + }, +}; + +static struct ltq_pci_data ltq_pci_data = { + .clock = PCI_CLOCK_INT, + .gpio = PCI_GNT1 | PCI_REQ1, + .irq = { + [14] = INT_NUM_IM0_IRL0 + 22, + }, +}; + +static struct ltq_eth_data ltq_eth_data = { + .mii_mode = PHY_INTERFACE_MODE_MII, +}; + +static struct gpio_led +dgn3500_gpio_leds[] __initdata = { + { .name = "soc:green:power", .gpio = 34, .active_low = 1, }, + { .name = "soc:red:power", .gpio = 39, .active_low = 1, }, + { .name = "soc:orange:wlan", .gpio = 51, .active_low = 1, }, + { .name = "soc:green:wps", .gpio = 52, .active_low = 1, }, + { .name = "soc:green:usb", .gpio = 22, .active_low = 1, }, + { .name = "soc:green:dsl", .gpio = 4, .active_low = 1, }, + { .name = "soc:green:internet", .gpio = 2, .active_low = 1, }, +}; + +static struct gpio_keys_button +dgn3500_gpio_keys[] __initdata = { + { + .desc = "wps", + .type = EV_KEY, + .code = BTN_0, + .debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL, + .gpio = 54, + .active_low = 1, + }, + { + .desc = "reset", + .type = EV_KEY, + .code = BTN_1, + .debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL, + .gpio = 36, + .active_low = 1, + }, +}; + +#define SPI_GPIO_MRST 16 +#define SPI_GPIO_MTSR 17 +#define SPI_GPIO_CLK 18 +#define SPI_GPIO_CS0 10 + +static struct spi_gpio_platform_data spi_gpio_data = { + .sck = SPI_GPIO_CLK, + .mosi = SPI_GPIO_MTSR, + .miso = SPI_GPIO_MRST, + .num_chipselect = 2, +}; + +static struct platform_device spi_gpio_device = { + .name = "spi_gpio", + .dev.platform_data = &spi_gpio_data, +}; + +static struct flash_platform_data spi_flash_data = { + .name = "sflash", + .parts = dgn3500_partitions, + .nr_parts = ARRAY_SIZE(dgn3500_partitions), +}; + +static struct spi_board_info spi_flash __initdata = { + .modalias = "m25p80", + .bus_num = 0, + .chip_select = 0, + .max_speed_hz = 10 * 1000 * 1000, + .mode = SPI_MODE_3, + .chip_select = 0, + .controller_data = (void *) SPI_GPIO_CS0, + .platform_data = &spi_flash_data +}; + +static u8 ltq_ethaddr[6] = { 0 }; + +static int __init setup_ethaddr(char *str) +{ + if (!mac_pton(str, ltq_ethaddr)) + memset(ltq_ethaddr, 0, 6); + return 0; +} +__setup("ethaddr=", setup_ethaddr); + +static u16 dgn3500_eeprom_data[ATH9K_PLAT_EEP_MAX_WORDS] = {0}; + +static ssize_t ath_eeprom_read(struct file *filp, struct kobject *kobj, + struct bin_attribute *attr, char *buf, + loff_t offset, size_t count) +{ + if (unlikely(offset >= sizeof(dgn3500_eeprom_data))) + return 0; + if ((offset + count) > sizeof(dgn3500_eeprom_data)) + count = sizeof(dgn3500_eeprom_data) - offset; + if (unlikely(!count)) + return count; + + memcpy(buf, (char *)(dgn3500_eeprom_data) + offset, count); + + return count; +} + +extern struct ath9k_platform_data ath9k_pdata; + +static ssize_t ath_eeprom_write(struct file *filp, struct kobject *kobj, + struct bin_attribute *attr, char *buf, + loff_t offset, size_t count) +{ + int i; + char *eeprom_bytes = (char *)dgn3500_eeprom_data; + + if (unlikely(offset >= sizeof(dgn3500_eeprom_data))) + return -EFBIG; + if ((offset + count) > sizeof(dgn3500_eeprom_data)) + count = sizeof(dgn3500_eeprom_data) - offset; + if (unlikely(!count)) + return count; + if (count % 2) + return 0; + + /* The PCI fixup routine requires an endian swap of the calibartion data + * stored in flash */ + for (i = 0; i < count; i += 2) { + eeprom_bytes[offset + i + 1] = buf[i]; + eeprom_bytes[offset + i] = buf[i+1]; + } + + /* The original data does not contain a checksum. Set the country and + * calculate new checksum when all data is received */ + if ((count + offset) == sizeof(dgn3500_eeprom_data)) + memcpy(ath9k_pdata.eeprom_data, dgn3500_eeprom_data, + sizeof(ath9k_pdata.eeprom_data)); + + return count; +} + +static struct bin_attribute dev_attr_ath_eeprom = { + .attr = { + .name = "ath_eeprom", + .mode = S_IRUGO|S_IWUSR, + }, + .read = ath_eeprom_read, + .write = ath_eeprom_write, +}; + +static void __init dgn3500_init(void) +{ + if (sysfs_create_bin_file(firmware_kobj, &dev_attr_ath_eeprom)) + printk(KERN_INFO "Failed to create ath eeprom sysfs entry\n"); + ltq_add_device_gpio_leds(-1, ARRAY_SIZE(dgn3500_gpio_leds), + dgn3500_gpio_leds); + ltq_register_gpio_keys_polled(-1, LTQ_KEYS_POLL_INTERVAL, + ARRAY_SIZE(dgn3500_gpio_keys), dgn3500_gpio_keys); + platform_device_register(&spi_gpio_device); + ltq_register_pci(<q_pci_data); + spi_register_board_info(&spi_flash, 1); + if (!is_valid_ether_addr(ltq_ethaddr)) { + printk(KERN_INFO "MAC invalid using random\n"); + random_ether_addr(ltq_ethaddr); + } + memcpy(<q_eth_data.mac.sa_data, ltq_ethaddr, 6); + ltq_register_etop(<q_eth_data); + ltq_register_ath9k(dgn3500_eeprom_data, ltq_ethaddr); + ltq_pci_ath_fixup(14, dgn3500_eeprom_data); + /* The usb power is always enabled, protected by a fuse */ + xway_register_dwc(-1); +} + +MIPS_MACHINE(LANTIQ_MACH_DGN3500B, + "DGN3500B", + "Netgear DGN3500B", + dgn3500_init); diff --git a/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/mach-p2601hnfx.c b/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/mach-p2601hnfx.c new file mode 100644 index 000000000..247dfb572 --- /dev/null +++ b/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/mach-p2601hnfx.c @@ -0,0 +1,113 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin <blogic@openwrt.org> + */ + +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/leds.h> +#include <linux/gpio.h> +#include <linux/gpio_buttons.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> +#include <linux/mtd/physmap.h> +#include <linux/input.h> +#include <linux/etherdevice.h> +#include <linux/mdio-gpio.h> +#include <linux/kernel.h> +#include <linux/delay.h> + +#include <lantiq_soc.h> +#include <lantiq_platform.h> +#include <dev-gpio-leds.h> +#include <dev-gpio-buttons.h> + +#include "../machtypes.h" +#include "devices.h" +#include "dev-dwc_otg.h" + +static struct mtd_partition p2601hnfx_partitions[] __initdata = +{ + { + .name = "uboot", + .offset = 0x0, + .size = 0x20000, + }, + { + .name = "uboot_env", + .offset = 0x20000, + .size = 0x20000, + }, + { + .name = "linux", + .offset = 0x40000, + .size = 0xfc0000, + }, +}; + +static struct physmap_flash_data p2601hnfx_flash_data __initdata = { + .nr_parts = ARRAY_SIZE(p2601hnfx_partitions), + .parts = p2601hnfx_partitions, +}; + +static struct gpio_led +p2601hnfx_leds_gpio[] __initdata = { + { .name = "soc:yellow:phone", .gpio = 216, .active_low = 1 }, + { .name = "soc:green:phone", .gpio = 217, .active_low = 1 }, + { .name = "soc:yellow:wifi", .gpio = 218, .active_low = 1 }, + { .name = "soc:green:power", .gpio = 219, .active_low = 1 }, + { .name = "soc:red:internet", .gpio = 220, .active_low = 1 }, + { .name = "soc:green:internet", .gpio = 221, .active_low = 1 }, + { .name = "soc:green:dsl", .gpio = 222, .active_low = 1 }, + { .name = "soc:green:wifi", .gpio = 223, .active_low = 1 }, +}; + +static struct gpio_keys_button +p2601hnfx_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = BTN_0, + .debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL, + .gpio = 53, + .active_low = 1, + }, + { + .desc = "wifi", + .type = EV_KEY, + .code = BTN_1, + .debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL, + .gpio = 54, + .active_low = 1, + }, +}; + +static struct ltq_eth_data ltq_eth_data = { + .mii_mode = PHY_INTERFACE_MODE_RMII, +}; + +static void __init +p2601hnfx_init(void) +{ +#define P2601HNFX_USB 9 + + ltq_register_gpio_stp(); + ltq_register_nor(&p2601hnfx_flash_data); + ltq_add_device_gpio_leds(-1, ARRAY_SIZE(p2601hnfx_leds_gpio), p2601hnfx_leds_gpio); + ltq_register_gpio_keys_polled(-1, LTQ_KEYS_POLL_INTERVAL, ARRAY_SIZE(p2601hnfx_gpio_keys), p2601hnfx_gpio_keys); + ltq_register_etop(<q_eth_data); + xway_register_dwc(P2601HNFX_USB); + + // enable the ethernet ports on the SoC +// ltq_w32((ltq_r32(LTQ_GPORT_P0_CTL) & ~(1 << 17)) | (1 << 18), LTQ_GPORT_P0_CTL); +// ltq_w32((ltq_r32(LTQ_GPORT_P1_CTL) & ~(1 << 17)) | (1 << 18), LTQ_GPORT_P1_CTL); +// ltq_w32((ltq_r32(LTQ_GPORT_P2_CTL) & ~(1 << 17)) | (1 << 18), LTQ_GPORT_P2_CTL); +} + +MIPS_MACHINE(LANTIQ_MACH_P2601HNFX, + "P2601HNFX", + "ZyXEL P-2601HN-Fx", + p2601hnfx_init); diff --git a/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/mach-wbmr.c b/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/mach-wbmr.c new file mode 100644 index 000000000..a57e09212 --- /dev/null +++ b/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/mach-wbmr.c @@ -0,0 +1,120 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin <blogic@openwrt.org> + */ + +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/leds.h> +#include <linux/gpio.h> +#include <linux/gpio_buttons.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> +#include <linux/mtd/physmap.h> +#include <linux/input.h> + +#include <lantiq_soc.h> +#include <irq.h> +#include <dev-gpio-leds.h> +#include <dev-gpio-buttons.h> + +#include "../machtypes.h" +#include "devices.h" +#include "dev-dwc_otg.h" + +static struct mtd_partition wbmr_partitions[] = +{ + { + .name = "uboot", + .offset = 0x0, + .size = 0x40000, + }, + { + .name = "uboot-env", + .offset = 0x40000, + .size = 0x20000, + }, + { + .name = "linux", + .offset = 0x60000, + .size = 0x1f20000, + }, + { + .name = "calibration", + .offset = 0x1fe0000, + .size = 0x20000, + }, +}; + +static struct physmap_flash_data wbmr_flash_data = { + .nr_parts = ARRAY_SIZE(wbmr_partitions), + .parts = wbmr_partitions, +}; + +static struct gpio_led +wbmr_gpio_leds[] __initdata = { + { .name = "soc:blue:movie", .gpio = 20, .active_low = 1, }, + { .name = "soc:red:internet", .gpio = 18, .active_low = 1, }, + { .name = "soc:green:internet", .gpio = 17, .active_low = 1, }, + { .name = "soc:green:adsl", .gpio = 16, .active_low = 1, }, + { .name = "soc:green:wlan", .gpio = 15, .active_low = 1, }, + { .name = "soc:red:security", .gpio = 14, .active_low = 1, }, + { .name = "soc:green:power", .gpio = 1, .active_low = 1, }, + { .name = "soc:red:power", .gpio = 5, .active_low = 1, }, + { .name = "soc:green:usb", .gpio = 28, .active_low = 1, }, +}; + +static struct gpio_keys_button +wbmr_gpio_keys[] __initdata = { + { + .desc = "aoss", + .type = EV_KEY, + .code = BTN_0, + .debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL, + .gpio = 0, + .active_low = 1, + }, + { + .desc = "reset", + .type = EV_KEY, + .code = BTN_1, + .debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL, + .gpio = 37, + .active_low = 1, + }, +}; + +static struct ltq_pci_data ltq_pci_data = { + .clock = PCI_CLOCK_INT, + .gpio = PCI_GNT1 | PCI_REQ1, + .irq = { + [14] = INT_NUM_IM0_IRL0 + 22, + }, +}; + +static struct ltq_eth_data ltq_eth_data = { + .mii_mode = PHY_INTERFACE_MODE_RGMII, +}; + +static void __init +wbmr_init(void) +{ +#define WMBR_BRN_MAC 0x1fd0024 + + ltq_add_device_gpio_leds(-1, ARRAY_SIZE(wbmr_gpio_leds), wbmr_gpio_leds); + ltq_register_gpio_keys_polled(-1, LTQ_KEYS_POLL_INTERVAL, ARRAY_SIZE(wbmr_gpio_keys), wbmr_gpio_keys); + ltq_register_nor(&wbmr_flash_data); + ltq_register_pci(<q_pci_data); + memcpy_fromio(<q_eth_data.mac.sa_data, + (void *)KSEG1ADDR(LTQ_FLASH_START + WMBR_BRN_MAC), 6); + ltq_register_etop(<q_eth_data); + xway_register_dwc(36); +} + +MIPS_MACHINE(LANTIQ_MACH_WBMR, + "WBMR", + "WBMR", + wbmr_init); diff --git a/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/nand.c b/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/nand.c new file mode 100644 index 000000000..9ab91d881 --- /dev/null +++ b/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/nand.c @@ -0,0 +1,216 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin <blogic@openwrt.org> + */ + +#include <linux/mtd/physmap.h> +#include <linux/mtd/nand.h> +#include <linux/platform_device.h> +#include <linux/io.h> + +#include <lantiq_soc.h> +#include <lantiq_irq.h> +#include <lantiq_platform.h> + +#include "devices.h" + +/* nand registers */ +#define LTQ_EBU_NAND_WAIT 0xB4 +#define LTQ_EBU_NAND_ECC0 0xB8 +#define LTQ_EBU_NAND_ECC_AC 0xBC +#define LTQ_EBU_NAND_CON 0xB0 +#define LTQ_EBU_ADDSEL1 0x24 + +/* gpio definitions */ +#define PIN_ALE 13 +#define PIN_CLE 24 +#define PIN_CS1 23 +#define PIN_RDY 48 /* NFLASH_READY */ +#define PIN_RD 49 /* NFLASH_READ_N */ + +#define NAND_CMD_ALE (1 << 2) +#define NAND_CMD_CLE (1 << 3) +#define NAND_CMD_CS (1 << 4) +#define NAND_WRITE_CMD_RESET 0xff +#define NAND_WRITE_CMD (NAND_CMD_CS | NAND_CMD_CLE) +#define NAND_WRITE_ADDR (NAND_CMD_CS | NAND_CMD_ALE) +#define NAND_WRITE_DATA (NAND_CMD_CS) +#define NAND_READ_DATA (NAND_CMD_CS) +#define NAND_WAIT_WR_C (1 << 3) +#define NAND_WAIT_RD (0x1) + +#define ADDSEL1_MASK(x) (x << 4) +#define ADDSEL1_REGEN 1 +#define BUSCON1_SETUP (1 << 22) +#define BUSCON1_BCGEN_RES (0x3 << 12) +#define BUSCON1_WAITWRC2 (2 << 8) +#define BUSCON1_WAITRDC2 (2 << 6) +#define BUSCON1_HOLDC1 (1 << 4) +#define BUSCON1_RECOVC1 (1 << 2) +#define BUSCON1_CMULT4 1 +#define NAND_CON_NANDM 1 +#define NAND_CON_CSMUX (1 << 1) +#define NAND_CON_CS_P (1 << 4) +#define NAND_CON_SE_P (1 << 5) +#define NAND_CON_WP_P (1 << 6) +#define NAND_CON_PRE_P (1 << 7) +#define NAND_CON_IN_CS0 0 +#define NAND_CON_OUT_CS0 0 +#define NAND_CON_IN_CS1 (1 << 8) +#define NAND_CON_OUT_CS1 (1 << 10) +#define NAND_CON_CE (1 << 20) + +#define NAND_BASE_ADDRESS (KSEG1 | 0x14000000) + +static const char *part_probes[] = { "cmdlinepart", NULL }; + +static void xway_select_chip(struct mtd_info *mtd, int chip) +{ + switch (chip) { + case -1: + ltq_ebu_w32_mask(NAND_CON_CE, 0, LTQ_EBU_NAND_CON); + ltq_ebu_w32_mask(NAND_CON_NANDM, 0, LTQ_EBU_NAND_CON); + break; + case 0: + ltq_ebu_w32_mask(0, NAND_CON_NANDM, LTQ_EBU_NAND_CON); + ltq_ebu_w32_mask(0, NAND_CON_CE, LTQ_EBU_NAND_CON); + /* reset the nand chip */ + while ((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0) + ; + ltq_w32(NAND_WRITE_CMD_RESET, + ((u32 *) (NAND_BASE_ADDRESS | NAND_WRITE_CMD))); + break; + default: + BUG(); + } +} + +static void xway_cmd_ctrl(struct mtd_info *mtd, int data, unsigned int ctrl) +{ + struct nand_chip *this = mtd->priv; + + if (ctrl & NAND_CTRL_CHANGE) { + if (ctrl & NAND_CLE) + this->IO_ADDR_W = (void __iomem *) + (NAND_BASE_ADDRESS | NAND_WRITE_CMD); + else if (ctrl & NAND_ALE) + this->IO_ADDR_W = (void __iomem *) + (NAND_BASE_ADDRESS | NAND_WRITE_ADDR); + } + + if (data != NAND_CMD_NONE) { + *(volatile u8*) ((u32) this->IO_ADDR_W) = data; + while ((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0) + ; + } +} + +static int xway_dev_ready(struct mtd_info *mtd) +{ + return ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_RD; +} + +void nand_write(unsigned int addr, unsigned int val) +{ + ltq_w32(val, ((u32 *) (NAND_BASE_ADDRESS | addr))); + while ((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0) + ; +} + +unsigned char xway_read_byte(struct mtd_info *mtd) +{ + return ltq_r8((void __iomem *)(NAND_BASE_ADDRESS | (NAND_READ_DATA))); +} + +static void xway_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) +{ + int i; + + for (i = 0; i < len; i++) + { + unsigned char res8 = ltq_r8((void __iomem *)(NAND_BASE_ADDRESS | (NAND_READ_DATA))); + buf[i] = res8; + } +} + +static void xway_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) +{ + int i; + + for (i = 0; i < len; i++) + { + ltq_w8(buf[i], ((u32*)(NAND_BASE_ADDRESS | (NAND_WRITE_DATA)))); + while((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0); + } +} + +int xway_probe(struct platform_device *pdev) +{ + /* might need this later ? + ltq_gpio_request(PIN_CS1, 2, 1, "NAND_CS1"); + */ + ltq_gpio_request(&pdev->dev, PIN_CLE, 2, 1, "NAND_CLE"); + ltq_gpio_request(&pdev->dev, PIN_ALE, 2, 1, "NAND_ALE"); + if (ltq_is_ar9() || ltq_is_vr9()) { + ltq_gpio_request(&pdev->dev, PIN_RDY, 2, 0, "NAND_BSY"); + ltq_gpio_request(&pdev->dev, PIN_RD, 2, 1, "NAND_RD"); + } + + ltq_ebu_w32((NAND_BASE_ADDRESS & 0x1fffff00) + | ADDSEL1_MASK(3) | ADDSEL1_REGEN, LTQ_EBU_ADDSEL1); + + ltq_ebu_w32(BUSCON1_SETUP | BUSCON1_BCGEN_RES | BUSCON1_WAITWRC2 + | BUSCON1_WAITRDC2 | BUSCON1_HOLDC1 | BUSCON1_RECOVC1 + | BUSCON1_CMULT4, LTQ_EBU_BUSCON1); + + ltq_ebu_w32(NAND_CON_NANDM | NAND_CON_CSMUX | NAND_CON_CS_P + | NAND_CON_SE_P | NAND_CON_WP_P | NAND_CON_PRE_P + | NAND_CON_IN_CS0 | NAND_CON_OUT_CS0, LTQ_EBU_NAND_CON); + + ltq_w32(NAND_WRITE_CMD_RESET, + ((u32 *) (NAND_BASE_ADDRESS | NAND_WRITE_CMD))); + while ((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0) + ; + + return 0; +} + +static struct platform_nand_data falcon_flash_nand_data = { + .chip = { + .nr_chips = 1, + .chip_delay = 30, + .part_probe_types = part_probes, + }, + .ctrl = { + .probe = xway_probe, + .cmd_ctrl = xway_cmd_ctrl, + .dev_ready = xway_dev_ready, + .select_chip = xway_select_chip, + .read_byte = xway_read_byte, + .read_buf = xway_read_buf, + .write_buf = xway_write_buf, + } +}; + +static struct resource ltq_nand_res = + MEM_RES("nand", 0x14000000, 0x7ffffff); + +static struct platform_device ltq_flash_nand = { + .name = "gen_nand", + .id = -1, + .num_resources = 1, + .resource = <q_nand_res, + .dev = { + .platform_data = &falcon_flash_nand_data, + }, +}; + +void __init xway_register_nand(struct mtd_partition *parts, int count) +{ + falcon_flash_nand_data.chip.partitions = parts; + falcon_flash_nand_data.chip.nr_partitions = count; + platform_device_register(<q_flash_nand); +} diff --git a/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/pci-ath-fixup.c b/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/pci-ath-fixup.c new file mode 100644 index 000000000..c87ffb209 --- /dev/null +++ b/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/pci-ath-fixup.c @@ -0,0 +1,109 @@ +/* + * Atheros AP94 reference board PCI initialization + * + * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/pci.h> +#include <linux/init.h> +#include <linux/delay.h> +#include <lantiq_soc.h> + +#define LTQ_PCI_MEM_BASE 0x18000000 + +struct ath_fixup { + u16 *cal_data; + unsigned slot; +}; + +static int ath_num_fixups; +static struct ath_fixup ath_fixups[2]; + +static void ath_pci_fixup(struct pci_dev *dev) +{ + void __iomem *mem; + u16 *cal_data = NULL; + u16 cmd; + u32 bar0; + u32 val; + unsigned i; + + for (i = 0; i < ath_num_fixups; i++) { + if (ath_fixups[i].cal_data == NULL) + continue; + + if (ath_fixups[i].slot != PCI_SLOT(dev->devfn)) + continue; + + cal_data = ath_fixups[i].cal_data; + break; + } + + if (cal_data == NULL) + return; + + if (*cal_data != 0xa55a) { + pr_err("pci %s: invalid calibration data\n", pci_name(dev)); + return; + } + + pr_info("pci %s: fixup device configuration\n", pci_name(dev)); + + mem = ioremap(LTQ_PCI_MEM_BASE, 0x10000); + if (!mem) { + pr_err("pci %s: ioremap error\n", pci_name(dev)); + return; + } + + pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar0); + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, LTQ_PCI_MEM_BASE); + pci_read_config_word(dev, PCI_COMMAND, &cmd); + cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config_word(dev, PCI_COMMAND, cmd); + + /* set pointer to first reg address */ + cal_data += 3; + while (*cal_data != 0xffff) { + u32 reg; + reg = *cal_data++; + val = *cal_data++; + val |= (*cal_data++) << 16; + + ltq_w32(swab32(val), mem + reg); + udelay(100); + } + + pci_read_config_dword(dev, PCI_VENDOR_ID, &val); + dev->vendor = val & 0xffff; + dev->device = (val >> 16) & 0xffff; + + pci_read_config_dword(dev, PCI_CLASS_REVISION, &val); + dev->revision = val & 0xff; + dev->class = val >> 8; /* upper 3 bytes */ + + pr_info("pci %s: fixup info: [%04x:%04x] revision %02x class %#08x\n", + pci_name(dev), dev->vendor, dev->device, dev->revision, dev->class); + + pci_read_config_word(dev, PCI_COMMAND, &cmd); + cmd &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + pci_write_config_word(dev, PCI_COMMAND, cmd); + + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, bar0); + + iounmap(mem); +} +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATHEROS, PCI_ANY_ID, ath_pci_fixup); + +void __init ltq_pci_ath_fixup(unsigned slot, u16 *cal_data) +{ + if (ath_num_fixups >= ARRAY_SIZE(ath_fixups)) + return; + + ath_fixups[ath_num_fixups].slot = slot; + ath_fixups[ath_num_fixups].cal_data = cal_data; + ath_num_fixups++; +} diff --git a/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/pci-ath-fixup.h b/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/pci-ath-fixup.h new file mode 100644 index 000000000..095d2619c --- /dev/null +++ b/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/pci-ath-fixup.h @@ -0,0 +1,6 @@ +#ifndef _PCI_ATH_FIXUP +#define _PCI_ATH_FIXUP + +void ltq_pci_ath_fixup(unsigned slot, u16 *cal_data) __init; + +#endif /* _PCI_ATH_FIXUP */ diff --git a/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/prom.c b/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/prom.c new file mode 100644 index 000000000..f776d5a91 --- /dev/null +++ b/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/prom.c @@ -0,0 +1,110 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin <blogic@openwrt.org> + */ + +#include <linux/export.h> +#include <linux/clk.h> +#include <asm/bootinfo.h> +#include <asm/time.h> + +#include <lantiq_soc.h> + +#include "../prom.h" +#include "devices.h" + +#define SOC_DANUBE "Danube" +#define SOC_TWINPASS "Twinpass" +#define SOC_AMAZON_SE "Amazon_SE" +#define SOC_AR9 "AR9" +#define SOC_GR9 "GR9" +#define SOC_VR9 "VR9" + +#define PART_SHIFT 12 +#define PART_MASK 0x0FFFFFFF +#define REV_SHIFT 28 +#define REV_MASK 0xF0000000 + + +void __init ltq_soc_detect(struct ltq_soc_info *i) +{ + i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT; + i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT; + sprintf(i->rev_type, "1.%d", i->rev); + switch (i->partnum) { + case SOC_ID_DANUBE1: + case SOC_ID_DANUBE2: + i->name = SOC_DANUBE; + i->type = SOC_TYPE_DANUBE; + break; + + case SOC_ID_TWINPASS: + i->name = SOC_TWINPASS; + i->type = SOC_TYPE_DANUBE; + break; + + case SOC_ID_ARX188: + case SOC_ID_ARX168_1: + case SOC_ID_ARX168_2: + case SOC_ID_ARX182: + i->name = SOC_AR9; + i->type = SOC_TYPE_AR9; + break; + + case SOC_ID_GRX188: + case SOC_ID_GRX168: + i->name = SOC_GR9; + i->type = SOC_TYPE_AR9; + break; + + case SOC_ID_AMAZON_SE_1: + case SOC_ID_AMAZON_SE_2: + i->name = SOC_AMAZON_SE; + i->type = SOC_TYPE_AMAZON_SE; +#ifdef CONFIG_PCI + panic("ase is only supported for non pci kernels"); +#endif + break; + + case SOC_ID_VRX282: + case SOC_ID_VRX268: + case SOC_ID_VRX288: + i->name = SOC_VR9; + i->type = SOC_TYPE_VR9_1; + break; + + case SOC_ID_GRX268: + case SOC_ID_GRX288: + i->name = SOC_GR9; + i->type = SOC_TYPE_VR9_1; + break; + + case SOC_ID_VRX268_2: + case SOC_ID_VRX288_2: + i->name = SOC_VR9; + i->type = SOC_TYPE_VR9_2; + break; + + case SOC_ID_GRX282_2: + case SOC_ID_GRX288_2: + i->name = SOC_GR9; + i->type = SOC_TYPE_VR9_2; + + default: + unreachable(); + break; + } +} + +void __init ltq_soc_setup(void) +{ + if (ltq_is_ase()) + ltq_register_ase_asc(); + else + ltq_register_asc(1); + ltq_register_gpio(); + ltq_register_wdt(); +} diff --git a/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/sysctrl.c b/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/sysctrl.c new file mode 100644 index 000000000..de4ce8f1c --- /dev/null +++ b/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/sysctrl.c @@ -0,0 +1,283 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2011 John Crispin <blogic@openwrt.org> + */ + +#include <linux/ioport.h> +#include <linux/export.h> +#include <linux/clkdev.h> + +#include <lantiq_soc.h> + +#include "../clk.h" +#include "../devices.h" + +/* clock control register */ +#define CGU_IFCCR 0x0018 +/* system clock register */ +#define CGU_SYS 0x0010 +/* pci control register */ +#define CGU_PCICR 0x0034 +/* ephy configuration register */ +#define CGU_EPHY 0x10 +/* power control register */ +#define PMU_PWDCR 0x1C +/* power status register */ +#define PMU_PWDSR 0x20 +/* power control register */ +#define PMU_PWDCR1 0x24 +/* power status register */ +#define PMU_PWDSR1 0x28 +/* power control register */ +#define PWDCR(x) ((x) ? (PMU_PWDCR1) : (PMU_PWDCR)) +/* power status register */ +#define PWDSR(x) ((x) ? (PMU_PWDSR1) : (PMU_PWDSR)) + +/* PMU - power management unit */ +#define PMU_USB0_P BIT(0) +#define PMU_PCI BIT(4) +#define PMU_DMA BIT(5) +#define PMU_USB0 BIT(6) +#define PMU_EPHY BIT(7) /* ase */ +#define PMU_SPI BIT(8) +#define PMU_DFE BIT(9) +#define PMU_EBU BIT(10) +#define PMU_STP BIT(11) +#define PMU_GPT BIT(12) +#define PMU_PPE BIT(13) +#define PMU_AHBS BIT(13) /* vr9 */ +#define PMU_FPI BIT(14) +#define PMU_AHBM BIT(15) +#define PMU_PPE_QSB BIT(18) +#define PMU_PPE_SLL01 BIT(19) +#define PMU_PPE_TC BIT(21) +#define PMU_PPE_EMA BIT(22) +#define PMU_PPE_DPLUM BIT(23) +#define PMU_PPE_DPLUS BIT(24) +#define PMU_USB1_P BIT(26) +#define PMU_USB1 BIT(27) +#define PMU_SWITCH BIT(28) +#define PMU_PPE_TOP BIT(29) +#define PMU_GPHY BIT(30) +#define PMU_PCIE_CLK BIT(31) + +#define PMU1_PCIE_PHY BIT(0) +#define PMU1_PCIE_CTL BIT(1) +#define PMU1_PCIE_PDI BIT(4) +#define PMU1_PCIE_MSI BIT(5) + +#define ltq_pmu_w32(x, y) ltq_w32((x), ltq_pmu_membase + (y)) +#define ltq_pmu_r32(x) ltq_r32(ltq_pmu_membase + (x)) + +static struct resource ltq_cgu_resource = + MEM_RES("cgu", LTQ_CGU_BASE_ADDR, LTQ_CGU_SIZE); + +static struct resource ltq_pmu_resource = + MEM_RES("pmu", LTQ_PMU_BASE_ADDR, LTQ_PMU_SIZE); + +static struct resource ltq_ebu_resource = + MEM_RES("ebu", LTQ_EBU_BASE_ADDR, LTQ_EBU_SIZE); + +void __iomem *ltq_cgu_membase; +void __iomem *ltq_ebu_membase; +static void __iomem *ltq_pmu_membase; + +static int ltq_cgu_enable(struct clk *clk) +{ + ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) | clk->bits, CGU_IFCCR); + return 0; +} + +static void ltq_cgu_disable(struct clk *clk) +{ + ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) & ~clk->bits, CGU_IFCCR); +} + +static int ltq_pmu_enable(struct clk *clk) +{ + int err = 1000000; + + ltq_pmu_w32(ltq_pmu_r32(PWDCR(clk->module)) & ~clk->bits, + PWDCR(clk->module)); + do {} while (--err && (ltq_pmu_r32(PWDSR(clk->module)) & clk->bits)); + + if (!err) + panic("activating PMU module failed!\n"); + + return 0; +} + +static void ltq_pmu_disable(struct clk *clk) +{ + ltq_pmu_w32(ltq_pmu_r32(PWDCR(clk->module)) | clk->bits, + PWDCR(clk->module)); +} + +static int ltq_pci_enable(struct clk *clk) +{ + unsigned int ifccr = ltq_cgu_r32(CGU_IFCCR); + /* set clock bus speed */ + if (ltq_is_ar9()) { + ifccr &= ~0x1f00000; + if (clk->rate == CLOCK_33M) + ifccr |= 0xe00000; + else + ifccr |= 0x700000; /* 62.5M */ + } else { + ifccr &= ~0xf00000; + if (clk->rate == CLOCK_33M) + ifccr |= 0x800000; + else + ifccr |= 0x400000; /* 62.5M */ + } + ltq_cgu_w32(ifccr, CGU_IFCCR); + return 0; +} + +static int ltq_pci_ext_enable(struct clk *clk) +{ + /* enable external pci clock */ + ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) & ~(1 << 16), + CGU_IFCCR); + ltq_cgu_w32((1 << 30), CGU_PCICR); + return 0; +} + +static void ltq_pci_ext_disable(struct clk *clk) +{ + /* disable external pci clock (internal) */ + ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) | (1 << 16), + CGU_IFCCR); + ltq_cgu_w32((1 << 31) | (1 << 30), CGU_PCICR); +} + +/* manage the clock gates via PMU */ +static inline void clkdev_add_pmu(const char *dev, const char *con, + unsigned int module, unsigned int bits) +{ + struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); + + clk->cl.dev_id = dev; + clk->cl.con_id = con; + clk->cl.clk = clk; + clk->enable = ltq_pmu_enable; + clk->disable = ltq_pmu_disable; + clk->module = module; + clk->bits = bits; + clkdev_add(&clk->cl); +} + +/* manage the clock generator */ +static inline void clkdev_add_cgu(const char *dev, const char *con, + unsigned int bits) +{ + struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); + + clk->cl.dev_id = dev; + clk->cl.con_id = con; + clk->cl.clk = clk; + clk->enable = ltq_cgu_enable; + clk->disable = ltq_cgu_disable; + clk->bits = bits; + clkdev_add(&clk->cl); +} + +/* pci needs its own enable function */ +static inline void clkdev_add_pci(void) +{ + struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); + struct clk *clk_ext = kzalloc(sizeof(struct clk), GFP_KERNEL); + + /* main pci clock */ + clk->cl.dev_id = "ltq_pci"; + clk->cl.con_id = NULL; + clk->cl.clk = clk; + clk->rate = CLOCK_33M; + clk->enable = ltq_pci_enable; + clk->disable = ltq_pmu_disable; + clk->module = 0; + clk->bits = PMU_PCI; + clkdev_add(&clk->cl); + + /* use internal/external bus clock */ + clk_ext->cl.dev_id = "ltq_pci"; + clk_ext->cl.con_id = "external"; + clk_ext->cl.clk = clk_ext; + clk_ext->enable = ltq_pci_ext_enable; + clk_ext->disable = ltq_pci_ext_disable; + clkdev_add(&clk_ext->cl); + +} + +void __init ltq_soc_init(void) +{ + ltq_pmu_membase = ltq_remap_resource(<q_pmu_resource); + if (!ltq_pmu_membase) + panic("Failed to remap pmu memory\n"); + + ltq_cgu_membase = ltq_remap_resource(<q_cgu_resource); + if (!ltq_cgu_membase) + panic("Failed to remap cgu memory\n"); + + ltq_ebu_membase = ltq_remap_resource(<q_ebu_resource); + if (!ltq_ebu_membase) + panic("Failed to remap ebu memory\n"); + + /* make sure to unprotect the memory region where flash is located */ + ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0); + + /* add our clocks */ + clkdev_add_pmu("ltq_fpi", NULL, 0, PMU_FPI); + clkdev_add_pmu("ltq_dma", NULL, 0, PMU_DMA); + clkdev_add_pmu("ltq_stp", NULL, 0, PMU_STP); + clkdev_add_pmu("ltq_spi.0", NULL, 0, PMU_SPI); + clkdev_add_pmu("ltq_gptu", NULL, 0, PMU_GPT); + clkdev_add_pmu("ltq_ebu", NULL, 0, PMU_EBU); + if (!ltq_is_vr9()) + clkdev_add_pmu("ltq_etop", NULL, 0, PMU_PPE); + if (!ltq_is_ase()) + clkdev_add_pci(); + if (ltq_is_ase()) { + if (ltq_cgu_r32(CGU_SYS) & (1 << 5)) + clkdev_add_static(CLOCK_266M, CLOCK_133M, CLOCK_133M); + else + clkdev_add_static(CLOCK_133M, CLOCK_133M, CLOCK_133M); + clkdev_add_cgu("ltq_etop", "ephycgu", CGU_EPHY), + clkdev_add_pmu("ltq_etop", "ephy", 0, PMU_EPHY); + clkdev_add_pmu("ltq_dsl", NULL, 0, + PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 | + PMU_AHBS | PMU_DFE); + } else if (ltq_is_vr9()) { + clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(), + ltq_vr9_fpi_hz()); + clkdev_add_pmu("ltq_pcie", "phy", 1, PMU1_PCIE_PHY); + clkdev_add_pmu("ltq_pcie", "bus", 0, PMU_PCIE_CLK); + clkdev_add_pmu("ltq_pcie", "msi", 1, PMU1_PCIE_MSI); + clkdev_add_pmu("ltq_pcie", "pdi", 1, PMU1_PCIE_PDI); + clkdev_add_pmu("ltq_pcie", "ctl", 1, PMU1_PCIE_CTL); + clkdev_add_pmu("ltq_pcie", "ahb", 0, PMU_AHBM | PMU_AHBS); + clkdev_add_pmu("usb0", NULL, 0, PMU_USB0 | PMU_USB0_P); + clkdev_add_pmu("usb1", NULL, 0, PMU_USB1 | PMU_USB1_P); + clkdev_add_pmu("ltq_vrx200", NULL, 0, + PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM | + PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 | + PMU_PPE_QSB); + clkdev_add_pmu("ltq_dsl", NULL, 0, PMU_DFE | PMU_AHBS); + } else if (ltq_is_ar9()) { + clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(), + ltq_ar9_fpi_hz()); + clkdev_add_pmu("ltq_etop", "switch", 0, PMU_SWITCH); + clkdev_add_pmu("ltq_dsl", NULL, 0, + PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 | + PMU_PPE_QSB | PMU_AHBS | PMU_DFE); + } else { + clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(), + ltq_danube_io_region_clock()); + clkdev_add_pmu("ltq_dsl", NULL, 0, + PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 | + PMU_PPE_QSB | PMU_AHBS | PMU_DFE); + } +} diff --git a/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/timer.c b/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/timer.c new file mode 100644 index 000000000..9794c87c7 --- /dev/null +++ b/target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/timer.c @@ -0,0 +1,846 @@ +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/version.h> +#include <linux/types.h> +#include <linux/fs.h> +#include <linux/miscdevice.h> +#include <linux/init.h> +#include <linux/uaccess.h> +#include <linux/unistd.h> +#include <linux/errno.h> +#include <linux/interrupt.h> +#include <linux/sched.h> + +#include <asm/irq.h> +#include <asm/div64.h> +#include "../clk.h" + +#include <lantiq_soc.h> +#include <lantiq_irq.h> +#include <lantiq_timer.h> + +#define MAX_NUM_OF_32BIT_TIMER_BLOCKS 6 + +#ifdef TIMER1A +#define FIRST_TIMER TIMER1A +#else +#define FIRST_TIMER 2 +#endif + +/* + * GPTC divider is set or not. + */ +#define GPTU_CLC_RMC_IS_SET 0 + +/* + * Timer Interrupt (IRQ) + */ +/* Must be adjusted when ICU driver is available */ +#define TIMER_INTERRUPT (INT_NUM_IM3_IRL0 + 22) + +/* + * Bits Operation + */ +#define GET_BITS(x, msb, lsb) \ + (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb)) +#define SET_BITS(x, msb, lsb, value) \ + (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | \ + (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb))) + +/* + * GPTU Register Mapping + */ +#define LQ_GPTU (KSEG1 + 0x1E100A00) +#define LQ_GPTU_CLC ((volatile u32 *)(LQ_GPTU + 0x0000)) +#define LQ_GPTU_ID ((volatile u32 *)(LQ_GPTU + 0x0008)) +#define LQ_GPTU_CON(n, X) ((volatile u32 *)(LQ_GPTU + 0x0010 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ +#define LQ_GPTU_RUN(n, X) ((volatile u32 *)(LQ_GPTU + 0x0018 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ +#define LQ_GPTU_RELOAD(n, X) ((volatile u32 *)(LQ_GPTU + 0x0020 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ +#define LQ_GPTU_COUNT(n, X) ((volatile u32 *)(LQ_GPTU + 0x0028 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ +#define LQ_GPTU_IRNEN ((volatile u32 *)(LQ_GPTU + 0x00F4)) +#define LQ_GPTU_IRNICR ((volatile u32 *)(LQ_GPTU + 0x00F8)) +#define LQ_GPTU_IRNCR ((volatile u32 *)(LQ_GPTU + 0x00FC)) + +/* + * Clock Control Register + */ +#define GPTU_CLC_SMC GET_BITS(*LQ_GPTU_CLC, 23, 16) +#define GPTU_CLC_RMC GET_BITS(*LQ_GPTU_CLC, 15, 8) +#define GPTU_CLC_FSOE (*LQ_GPTU_CLC & (1 << 5)) +#define GPTU_CLC_EDIS (*LQ_GPTU_CLC & (1 << 3)) +#define GPTU_CLC_SPEN (*LQ_GPTU_CLC & (1 << 2)) +#define GPTU_CLC_DISS (*LQ_GPTU_CLC & (1 << 1)) +#define GPTU_CLC_DISR (*LQ_GPTU_CLC & (1 << 0)) + +#define GPTU_CLC_SMC_SET(value) SET_BITS(0, 23, 16, (value)) +#define GPTU_CLC_RMC_SET(value) SET_BITS(0, 15, 8, (value)) +#define GPTU_CLC_FSOE_SET(value) ((value) ? (1 << 5) : 0) +#define GPTU_CLC_SBWE_SET(value) ((value) ? (1 << 4) : 0) +#define GPTU_CLC_EDIS_SET(value) ((value) ? (1 << 3) : 0) +#define GPTU_CLC_SPEN_SET(value) ((value) ? (1 << 2) : 0) +#define GPTU_CLC_DISR_SET(value) ((value) ? (1 << 0) : 0) + +/* + * ID Register + */ +#define GPTU_ID_ID GET_BITS(*LQ_GPTU_ID, 15, 8) +#define GPTU_ID_CFG GET_BITS(*LQ_GPTU_ID, 7, 5) +#define GPTU_ID_REV GET_BITS(*LQ_GPTU_ID, 4, 0) + +/* + * Control Register of Timer/Counter nX + * n is the index of block (1 based index) + * X is either A or B + */ +#define GPTU_CON_SRC_EG(n, X) (*LQ_GPTU_CON(n, X) & (1 << 10)) +#define GPTU_CON_SRC_EXT(n, X) (*LQ_GPTU_CON(n, X) & (1 << 9)) +#define GPTU_CON_SYNC(n, X) (*LQ_GPTU_CON(n, X) & (1 << 8)) +#define GPTU_CON_EDGE(n, X) GET_BITS(*LQ_GPTU_CON(n, X), 7, 6) +#define GPTU_CON_INV(n, X) (*LQ_GPTU_CON(n, X) & (1 << 5)) +#define GPTU_CON_EXT(n, X) (*LQ_GPTU_CON(n, A) & (1 << 4)) /* Timer/Counter B does not have this bit */ +#define GPTU_CON_STP(n, X) (*LQ_GPTU_CON(n, X) & (1 << 3)) +#define GPTU_CON_CNT(n, X) (*LQ_GPTU_CON(n, X) & (1 << 2)) +#define GPTU_CON_DIR(n, X) (*LQ_GPTU_CON(n, X) & (1 << 1)) +#define GPTU_CON_EN(n, X) (*LQ_GPTU_CON(n, X) & (1 << 0)) + +#define GPTU_CON_SRC_EG_SET(value) ((value) ? 0 : (1 << 10)) +#define GPTU_CON_SRC_EXT_SET(value) ((value) ? (1 << 9) : 0) +#define GPTU_CON_SYNC_SET(value) ((value) ? (1 << 8) : 0) +#define GPTU_CON_EDGE_SET(value) SET_BITS(0, 7, 6, (value)) +#define GPTU_CON_INV_SET(value) ((value) ? (1 << 5) : 0) +#define GPTU_CON_EXT_SET(value) ((value) ? (1 << 4) : 0) +#define GPTU_CON_STP_SET(value) ((value) ? (1 << 3) : 0) +#define GPTU_CON_CNT_SET(value) ((value) ? (1 << 2) : 0) +#define GPTU_CON_DIR_SET(value) ((value) ? (1 << 1) : 0) + +#define GPTU_RUN_RL_SET(value) ((value) ? (1 << 2) : 0) +#define GPTU_RUN_CEN_SET(value) ((value) ? (1 << 1) : 0) +#define GPTU_RUN_SEN_SET(value) ((value) ? (1 << 0) : 0) + +#define GPTU_IRNEN_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0) +#define GPTU_IRNCR_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0) + +#define TIMER_FLAG_MASK_SIZE(x) (x & 0x0001) +#define TIMER_FLAG_MASK_TYPE(x) (x & 0x0002) +#define TIMER_FLAG_MASK_STOP(x) (x & 0x0004) +#define TIMER_FLAG_MASK_DIR(x) (x & 0x0008) +#define TIMER_FLAG_NONE_EDGE 0x0000 +#define TIMER_FLAG_MASK_EDGE(x) (x & 0x0030) +#define TIMER_FLAG_REAL 0x0000 +#define TIMER_FLAG_INVERT 0x0040 +#define TIMER_FLAG_MASK_INVERT(x) (x & 0x0040) +#define TIMER_FLAG_MASK_TRIGGER(x) (x & 0x0070) +#define TIMER_FLAG_MASK_SYNC(x) (x & 0x0080) +#define TIMER_FLAG_CALLBACK_IN_HB 0x0200 +#define TIMER_FLAG_MASK_HANDLE(x) (x & 0x0300) +#define TIMER_FLAG_MASK_SRC(x) (x & 0x1000) + +struct timer_dev_timer { + unsigned int f_irq_on; + unsigned int irq; + unsigned int flag; + unsigned long arg1; + unsigned long arg2; +}; + +struct timer_dev { + struct mutex gptu_mutex; + unsigned int number_of_timers; + unsigned int occupation; + unsigned int f_gptu_on; + struct timer_dev_timer timer[MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2]; +}; + +unsigned long ltq_danube_fpi_bus_clock(int fpi); +unsigned long ltq_vr9_fpi_bus_clock(int fpi); + +unsigned int ltq_get_fpi_bus_clock(int fpi) { + if (ltq_is_ase()) + return CLOCK_133M; + else if (ltq_is_vr9()) + return ltq_vr9_fpi_bus_clock(fpi); + + return ltq_danube_fpi_bus_clock(fpi); +} + + +static long gptu_ioctl(struct file *, unsigned int, unsigned long); +static int gptu_open(struct inode *, struct file *); +static int gptu_release(struct inode *, struct file *); + +static struct file_operations gptu_fops = { + .owner = THIS_MODULE, + .unlocked_ioctl = gptu_ioctl, + .open = gptu_open, + .release = gptu_release +}; + +static struct miscdevice gptu_miscdev = { + .minor = MISC_DYNAMIC_MINOR, + .name = "gptu", + .fops = &gptu_fops, +}; + +static struct timer_dev timer_dev; + +static irqreturn_t timer_irq_handler(int irq, void *p) +{ + unsigned int timer; + unsigned int flag; + struct timer_dev_timer *dev_timer = (struct timer_dev_timer *)p; + + timer = irq - TIMER_INTERRUPT; + if (timer < timer_dev.number_of_timers + && dev_timer == &timer_dev.timer[timer]) { + /* Clear interrupt. */ + ltq_w32(1 << timer, LQ_GPTU_IRNCR); + + /* Call user hanler or signal. */ + flag = dev_timer->flag; + if (!(timer & 0x01) + || TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) { + /* 16-bit timer or timer A of 32-bit timer */ + switch (TIMER_FLAG_MASK_HANDLE(flag)) { + case TIMER_FLAG_CALLBACK_IN_IRQ: + case TIMER_FLAG_CALLBACK_IN_HB: + if (dev_timer->arg1) + (*(timer_callback)dev_timer->arg1)(dev_timer->arg2); + break; + case TIMER_FLAG_SIGNAL: + send_sig((int)dev_timer->arg2, (struct task_struct *)dev_timer->arg1, 0); + break; + } + } + } + return IRQ_HANDLED; +} + +static inline void lq_enable_gptu(void) +{ + struct clk *clk = clk_get_sys("ltq_gptu", NULL); + clk_enable(clk); + + //ltq_pmu_enable(PMU_GPT); + + /* Set divider as 1, disable write protection for SPEN, enable module. */ + *LQ_GPTU_CLC = + GPTU_CLC_SMC_SET(0x00) | + GPTU_CLC_RMC_SET(0x01) | + GPTU_CLC_FSOE_SET(0) | + GPTU_CLC_SBWE_SET(1) | + GPTU_CLC_EDIS_SET(0) | + GPTU_CLC_SPEN_SET(0) | + GPTU_CLC_DISR_SET(0); +} + +static inline void lq_disable_gptu(void) +{ + struct clk *clk = clk_get_sys("ltq_gptu", NULL); + ltq_w32(0x00, LQ_GPTU_IRNEN); + ltq_w32(0xfff, LQ_GPTU_IRNCR); + + /* Set divider as 0, enable write protection for SPEN, disable module. */ + *LQ_GPTU_CLC = + GPTU_CLC_SMC_SET(0x00) | + GPTU_CLC_RMC_SET(0x00) | + GPTU_CLC_FSOE_SET(0) | + GPTU_CLC_SBWE_SET(0) | + GPTU_CLC_EDIS_SET(0) | + GPTU_CLC_SPEN_SET(0) | + GPTU_CLC_DISR_SET(1); + + clk_enable(clk); +} + +int lq_request_timer(unsigned int timer, unsigned int flag, + unsigned long value, unsigned long arg1, unsigned long arg2) +{ + int ret = 0; + unsigned int con_reg, irnen_reg; + int n, X; + + if (timer >= FIRST_TIMER + timer_dev.number_of_timers) + return -EINVAL; + + printk(KERN_INFO "request_timer(%d, 0x%08X, %lu)...", + timer, flag, value); + + if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) + value &= 0xFFFF; + else + timer &= ~0x01; + + mutex_lock(&timer_dev.gptu_mutex); + + /* + * Allocate timer. + */ + if (timer < FIRST_TIMER) { + unsigned int mask; + unsigned int shift; + /* This takes care of TIMER1B which is the only choice for Voice TAPI system */ + unsigned int offset = TIMER2A; + + /* + * Pick up a free timer. + */ + if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) { + mask = 1 << offset; + shift = 1; + } else { + mask = 3 << offset; + shift = 2; + } + for (timer = offset; + timer < offset + timer_dev.number_of_timers; + timer += shift, mask <<= shift) + if (!(timer_dev.occupation & mask)) { + timer_dev.occupation |= mask; + break; + } + if (timer >= offset + timer_dev.number_of_timers) { + printk("failed![%d]\n", __LINE__); + mutex_unlock(&timer_dev.gptu_mutex); + return -EINVAL; + } else + ret = timer; + } else { + register unsigned int mask; + + /* + * Check if the requested timer is free. + */ + mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; + if ((timer_dev.occupation & mask)) { + printk("failed![%d] mask %#x, timer_dev.occupation %#x\n", + __LINE__, mask, timer_dev.occupation); + mutex_unlock(&timer_dev.gptu_mutex); + return -EBUSY; + } else { + timer_dev.occupation |= mask; + ret = 0; + } + } + + /* + * Prepare control register value. + */ + switch (TIMER_FLAG_MASK_EDGE(flag)) { + default: + case TIMER_FLAG_NONE_EDGE: + con_reg = GPTU_CON_EDGE_SET(0x00); + break; + case TIMER_FLAG_RISE_EDGE: + con_reg = GPTU_CON_EDGE_SET(0x01); + break; + case TIMER_FLAG_FALL_EDGE: + con_reg = GPTU_CON_EDGE_SET(0x02); + break; + case TIMER_FLAG_ANY_EDGE: + con_reg = GPTU_CON_EDGE_SET(0x03); + break; + } + if (TIMER_FLAG_MASK_TYPE(flag) == TIMER_FLAG_TIMER) + con_reg |= + TIMER_FLAG_MASK_SRC(flag) == + TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : + GPTU_CON_SRC_EXT_SET(0); + else + con_reg |= + TIMER_FLAG_MASK_SRC(flag) == + TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : + GPTU_CON_SRC_EG_SET(0); + con_reg |= + TIMER_FLAG_MASK_SYNC(flag) == + TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : + GPTU_CON_SYNC_SET(1); + con_reg |= + TIMER_FLAG_MASK_INVERT(flag) == + TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1); + con_reg |= + TIMER_FLAG_MASK_SIZE(flag) == + TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : + GPTU_CON_EXT_SET(1); + con_reg |= + TIMER_FLAG_MASK_STOP(flag) == + TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0); + con_reg |= + TIMER_FLAG_MASK_TYPE(flag) == + TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : + GPTU_CON_CNT_SET(1); + con_reg |= + TIMER_FLAG_MASK_DIR(flag) == + TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0); + + /* + * Fill up running data. + */ + timer_dev.timer[timer - FIRST_TIMER].flag = flag; + timer_dev.timer[timer - FIRST_TIMER].arg1 = arg1; + timer_dev.timer[timer - FIRST_TIMER].arg2 = arg2; + if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) + timer_dev.timer[timer - FIRST_TIMER + 1].flag = flag; + + /* + * Enable GPTU module. + */ + if (!timer_dev.f_gptu_on) { + lq_enable_gptu(); + timer_dev.f_gptu_on = 1; + } + + /* + * Enable IRQ. + */ + if (TIMER_FLAG_MASK_HANDLE(flag) != TIMER_FLAG_NO_HANDLE) { + if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL) + timer_dev.timer[timer - FIRST_TIMER].arg1 = + (unsigned long) find_task_by_vpid((int) arg1); + + irnen_reg = 1 << (timer - FIRST_TIMER); + + if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL + || (TIMER_FLAG_MASK_HANDLE(flag) == + TIMER_FLAG_CALLBACK_IN_IRQ + && timer_dev.timer[timer - FIRST_TIMER].arg1)) { + enable_irq(timer_dev.timer[timer - FIRST_TIMER].irq); + timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 1; + } + } else + irnen_reg = 0; + + /* + * Write config register, reload value and enable interrupt. + */ + n = timer >> 1; + X = timer & 0x01; + *LQ_GPTU_CON(n, X) = con_reg; + *LQ_GPTU_RELOAD(n, X) = value; + /* printk("reload value = %d\n", (u32)value); */ + *LQ_GPTU_IRNEN |= irnen_reg; + + mutex_unlock(&timer_dev.gptu_mutex); + printk("successful!\n"); + return ret; +} +EXPORT_SYMBOL(lq_request_timer); + +int lq_free_timer(unsigned int timer) +{ + unsigned int flag; + unsigned int mask; + int n, X; + + if (!timer_dev.f_gptu_on) + return -EINVAL; + + if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers) + return -EINVAL; + + mutex_lock(&timer_dev.gptu_mutex); + + flag = timer_dev.timer[timer - FIRST_TIMER].flag; + if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) + timer &= ~0x01; + + mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; + if (((timer_dev.occupation & mask) ^ mask)) { + mutex_unlock(&timer_dev.gptu_mutex); + return -EINVAL; + } + + n = timer >> 1; + X = timer & 0x01; + + if (GPTU_CON_EN(n, X)) + *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1); + + *LQ_GPTU_IRNEN &= ~GPTU_IRNEN_TC_SET(n, X, 1); + *LQ_GPTU_IRNCR |= GPTU_IRNCR_TC_SET(n, X, 1); + + if (timer_dev.timer[timer - FIRST_TIMER].f_irq_on) { + disable_irq(timer_dev.timer[timer - FIRST_TIMER].irq); + timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 0; + } + + timer_dev.occupation &= ~mask; + if (!timer_dev.occupation && timer_dev.f_gptu_on) { + lq_disable_gptu(); + timer_dev.f_gptu_on = 0; + } + + mutex_unlock(&timer_dev.gptu_mutex); + + return 0; +} +EXPORT_SYMBOL(lq_free_timer); + +int lq_start_timer(unsigned int timer, int is_resume) +{ + unsigned int flag; + unsigned int mask; + int n, X; + + if (!timer_dev.f_gptu_on) + return -EINVAL; + + if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers) + return -EINVAL; + + mutex_lock(&timer_dev.gptu_mutex); + + flag = timer_dev.timer[timer - FIRST_TIMER].flag; + if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) + timer &= ~0x01; + + mask = (TIMER_FLAG_MASK_SIZE(flag) == + TIMER_FLAG_16BIT ? 1 : 3) << timer; + if (((timer_dev.occupation & mask) ^ mask)) { + mutex_unlock(&timer_dev.gptu_mutex); + return -EINVAL; + } + + n = timer >> 1; + X = timer & 0x01; + + *LQ_GPTU_RUN(n, X) = GPTU_RUN_RL_SET(!is_resume) | GPTU_RUN_SEN_SET(1); + + mutex_unlock(&timer_dev.gptu_mutex); + + return 0; +} +EXPORT_SYMBOL(lq_start_timer); + +int lq_stop_timer(unsigned int timer) +{ + unsigned int flag; + unsigned int mask; + int n, X; + + if (!timer_dev.f_gptu_on) + return -EINVAL; + + if (timer < FIRST_TIMER + || timer >= FIRST_TIMER + timer_dev.number_of_timers) + return -EINVAL; + + mutex_lock(&timer_dev.gptu_mutex); + + flag = timer_dev.timer[timer - FIRST_TIMER].flag; + if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) + timer &= ~0x01; + + mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; + if (((timer_dev.occupation & mask) ^ mask)) { + mutex_unlock(&timer_dev.gptu_mutex); + return -EINVAL; + } + + n = timer >> 1; + X = timer & 0x01; + + *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1); + + mutex_unlock(&timer_dev.gptu_mutex); + + return 0; +} +EXPORT_SYMBOL(lq_stop_timer); + +int lq_reset_counter_flags(u32 timer, u32 flags) +{ + unsigned int oflag; + unsigned int mask, con_reg; + int n, X; + + if (!timer_dev.f_gptu_on) + return -EINVAL; + + if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers) + return -EINVAL; + + mutex_lock(&timer_dev.gptu_mutex); + + oflag = timer_dev.timer[timer - FIRST_TIMER].flag; + if (TIMER_FLAG_MASK_SIZE(oflag) != TIMER_FLAG_16BIT) + timer &= ~0x01; + + mask = (TIMER_FLAG_MASK_SIZE(oflag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; + if (((timer_dev.occupation & mask) ^ mask)) { + mutex_unlock(&timer_dev.gptu_mutex); + return -EINVAL; + } + + switch (TIMER_FLAG_MASK_EDGE(flags)) { + default: + case TIMER_FLAG_NONE_EDGE: + con_reg = GPTU_CON_EDGE_SET(0x00); + break; + case TIMER_FLAG_RISE_EDGE: + con_reg = GPTU_CON_EDGE_SET(0x01); + break; + case TIMER_FLAG_FALL_EDGE: + con_reg = GPTU_CON_EDGE_SET(0x02); + break; + case TIMER_FLAG_ANY_EDGE: + con_reg = GPTU_CON_EDGE_SET(0x03); + break; + } + if (TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER) + con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : GPTU_CON_SRC_EXT_SET(0); + else + con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : GPTU_CON_SRC_EG_SET(0); + con_reg |= TIMER_FLAG_MASK_SYNC(flags) == TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : GPTU_CON_SYNC_SET(1); + con_reg |= TIMER_FLAG_MASK_INVERT(flags) == TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1); + con_reg |= TIMER_FLAG_MASK_SIZE(flags) == TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : GPTU_CON_EXT_SET(1); + con_reg |= TIMER_FLAG_MASK_STOP(flags) == TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0); + con_reg |= TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : GPTU_CON_CNT_SET(1); + con_reg |= TIMER_FLAG_MASK_DIR(flags) == TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0); + + timer_dev.timer[timer - FIRST_TIMER].flag = flags; + if (TIMER_FLAG_MASK_SIZE(flags) != TIMER_FLAG_16BIT) + timer_dev.timer[timer - FIRST_TIMER + 1].flag = flags; + + n = timer >> 1; + X = timer & 0x01; + + *LQ_GPTU_CON(n, X) = con_reg; + smp_wmb(); + printk(KERN_INFO "[%s]: counter%d oflags %#x, nflags %#x, GPTU_CON %#x\n", __func__, timer, oflag, flags, *LQ_GPTU_CON(n, X)); + mutex_unlock(&timer_dev.gptu_mutex); + return 0; +} +EXPORT_SYMBOL(lq_reset_counter_flags); + +int lq_get_count_value(unsigned int timer, unsigned long *value) +{ + unsigned int flag; + unsigned int mask; + int n, X; + + if (!timer_dev.f_gptu_on) + return -EINVAL; + + if (timer < FIRST_TIMER + || timer >= FIRST_TIMER + timer_dev.number_of_timers) + return -EINVAL; + + mutex_lock(&timer_dev.gptu_mutex); + + flag = timer_dev.timer[timer - FIRST_TIMER].flag; + if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) + timer &= ~0x01; + + mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; + if (((timer_dev.occupation & mask) ^ mask)) { + mutex_unlock(&timer_dev.gptu_mutex); + return -EINVAL; + } + + n = timer >> 1; + X = timer & 0x01; + + *value = *LQ_GPTU_COUNT(n, X); + + mutex_unlock(&timer_dev.gptu_mutex); + + return 0; +} +EXPORT_SYMBOL(lq_get_count_value); + +u32 lq_cal_divider(unsigned long freq) +{ + u64 module_freq, fpi = ltq_get_fpi_bus_clock(2); + u32 clock_divider = 1; + module_freq = fpi * 1000; + do_div(module_freq, clock_divider * freq); + return module_freq; +} +EXPORT_SYMBOL(lq_cal_divider); + +int lq_set_timer(unsigned int timer, unsigned int freq, int is_cyclic, + int is_ext_src, unsigned int handle_flag, unsigned long arg1, + unsigned long arg2) +{ + unsigned long divider; + unsigned int flag; + + divider = lq_cal_divider(freq); + if (divider == 0) + return -EINVAL; + flag = ((divider & ~0xFFFF) ? TIMER_FLAG_32BIT : TIMER_FLAG_16BIT) + | (is_cyclic ? TIMER_FLAG_CYCLIC : TIMER_FLAG_ONCE) + | (is_ext_src ? TIMER_FLAG_EXT_SRC : TIMER_FLAG_INT_SRC) + | TIMER_FLAG_TIMER | TIMER_FLAG_DOWN + | TIMER_FLAG_MASK_HANDLE(handle_flag); + + printk(KERN_INFO "lq_set_timer(%d, %d), divider = %lu\n", + timer, freq, divider); + return lq_request_timer(timer, flag, divider, arg1, arg2); +} +EXPORT_SYMBOL(lq_set_timer); + +int lq_set_counter(unsigned int timer, unsigned int flag, u32 reload, + unsigned long arg1, unsigned long arg2) +{ + printk(KERN_INFO "lq_set_counter(%d, %#x, %d)\n", timer, flag, reload); + return lq_request_timer(timer, flag, reload, arg1, arg2); +} +EXPORT_SYMBOL(lq_set_counter); + +static long gptu_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) +{ + int ret; + struct gptu_ioctl_param param; + + if (!access_ok(VERIFY_READ, arg, sizeof(struct gptu_ioctl_param))) + return -EFAULT; + copy_from_user(¶m, (void *) arg, sizeof(param)); + + if ((((cmd == GPTU_REQUEST_TIMER || cmd == GPTU_SET_TIMER + || GPTU_SET_COUNTER) && param.timer < 2) + || cmd == GPTU_GET_COUNT_VALUE || cmd == GPTU_CALCULATE_DIVIDER) + && !access_ok(VERIFY_WRITE, arg, + sizeof(struct gptu_ioctl_param))) + return -EFAULT; + + switch (cmd) { + case GPTU_REQUEST_TIMER: + ret = lq_request_timer(param.timer, param.flag, param.value, + (unsigned long) param.pid, + (unsigned long) param.sig); + if (ret > 0) { + copy_to_user(&((struct gptu_ioctl_param *) arg)-> + timer, &ret, sizeof(&ret)); + ret = 0; + } + break; + case GPTU_FREE_TIMER: + ret = lq_free_timer(param.timer); + break; + case GPTU_START_TIMER: + ret = lq_start_timer(param.timer, param.flag); + break; + case GPTU_STOP_TIMER: + ret = lq_stop_timer(param.timer); + break; + case GPTU_GET_COUNT_VALUE: + ret = lq_get_count_value(param.timer, ¶m.value); + if (!ret) + copy_to_user(&((struct gptu_ioctl_param *) arg)-> + value, ¶m.value, + sizeof(param.value)); + break; + case GPTU_CALCULATE_DIVIDER: + param.value = lq_cal_divider(param.value); + if (param.value == 0) + ret = -EINVAL; + else { + copy_to_user(&((struct gptu_ioctl_param *) arg)-> + value, ¶m.value, + sizeof(param.value)); + ret = 0; + } + break; + case GPTU_SET_TIMER: + ret = lq_set_timer(param.timer, param.value, + TIMER_FLAG_MASK_STOP(param.flag) != + TIMER_FLAG_ONCE ? 1 : 0, + TIMER_FLAG_MASK_SRC(param.flag) == + TIMER_FLAG_EXT_SRC ? 1 : 0, + TIMER_FLAG_MASK_HANDLE(param.flag) == + TIMER_FLAG_SIGNAL ? TIMER_FLAG_SIGNAL : + TIMER_FLAG_NO_HANDLE, + (unsigned long) param.pid, + (unsigned long) param.sig); + if (ret > 0) { + copy_to_user(&((struct gptu_ioctl_param *) arg)-> + timer, &ret, sizeof(&ret)); + ret = 0; + } + break; + case GPTU_SET_COUNTER: + lq_set_counter(param.timer, param.flag, param.value, 0, 0); + if (ret > 0) { + copy_to_user(&((struct gptu_ioctl_param *) arg)-> + timer, &ret, sizeof(&ret)); + ret = 0; + } + break; + default: + ret = -ENOTTY; + } + + return ret; +} + +static int gptu_open(struct inode *inode, struct file *file) +{ + return 0; +} + +static int gptu_release(struct inode *inode, struct file *file) +{ + return 0; +} + +int __init lq_gptu_init(void) +{ + int ret; + unsigned int i; + + ltq_w32(0, LQ_GPTU_IRNEN); + ltq_w32(0xfff, LQ_GPTU_IRNCR); + + memset(&timer_dev, 0, sizeof(timer_dev)); + mutex_init(&timer_dev.gptu_mutex); + + lq_enable_gptu(); + timer_dev.number_of_timers = GPTU_ID_CFG * 2; + lq_disable_gptu(); + if (timer_dev.number_of_timers > MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2) + timer_dev.number_of_timers = MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2; + printk(KERN_INFO "gptu: totally %d 16-bit timers/counters\n", timer_dev.number_of_timers); + + ret = misc_register(&gptu_miscdev); + if (ret) { + printk(KERN_ERR "gptu: can't misc_register, get error %d\n", -ret); + return ret; + } else { + printk(KERN_INFO "gptu: misc_register on minor %d\n", gptu_miscdev.minor); + } + + for (i = 0; i < timer_dev.number_of_timers; i++) { + ret = request_irq(TIMER_INTERRUPT + i, timer_irq_handler, IRQF_TIMER, gptu_miscdev.name, &timer_dev.timer[i]); + if (ret) { + for (; i >= 0; i--) + free_irq(TIMER_INTERRUPT + i, &timer_dev.timer[i]); + misc_deregister(&gptu_miscdev); + printk(KERN_ERR "gptu: failed in requesting irq (%d), get error %d\n", i, -ret); + return ret; + } else { + timer_dev.timer[i].irq = TIMER_INTERRUPT + i; + disable_irq(timer_dev.timer[i].irq); + printk(KERN_INFO "gptu: succeeded to request irq %d\n", timer_dev.timer[i].irq); + } + } + + return 0; +} + +void __exit lq_gptu_exit(void) +{ + unsigned int i; + + for (i = 0; i < timer_dev.number_of_timers; i++) { + if (timer_dev.timer[i].f_irq_on) + disable_irq(timer_dev.timer[i].irq); + free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]); + } + lq_disable_gptu(); + misc_deregister(&gptu_miscdev); +} + +module_init(lq_gptu_init); +module_exit(lq_gptu_exit); |