diff options
Diffstat (limited to 'target/linux/ifxmips/files/include/asm-mips')
10 files changed, 337 insertions, 340 deletions
diff --git a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips.h b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips.h index 6dc184a54..c8cf0aef5 100644 --- a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips.h +++ b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips.h @@ -19,9 +19,9 @@ #ifndef _IFXMIPS_H__ #define _IFXMIPS_H__ -#define ifxmips_r32(reg) __raw_readl(reg) -#define ifxmips_w32(val,reg) __raw_writel(val,reg) -#define ifxmips_w32_mask(clear,set,reg) ifxmips_w32((ifxmips_r32(reg) & ~clear) | set, reg) +#define ifxmips_r32(reg) __raw_readl(reg) +#define ifxmips_w32(val, reg) __raw_writel(val, reg) +#define ifxmips_w32_mask(clear, set, reg) ifxmips_w32((ifxmips_r32(reg) & ~clear) | set, reg) /*------------ GENERAL */ @@ -111,7 +111,7 @@ #define IFXMIPS_RCU_BASE_ADDR 0xBF203000 /* reset request */ -#define IFXMIPS_RCU_RST ((u32*)(IFXMIPS_RCU_BASE_ADDR + 0x0010)) +#define IFXMIPS_RCU_RST ((u32 *)(IFXMIPS_RCU_BASE_ADDR + 0x0010)) #define IFXMIPS_RCU_RST_CPU1 (1 << 3) #define IFXMIPS_RCU_RST_ALL 0x40000000 @@ -125,13 +125,13 @@ #define IFXMIPS_GPTU_BASE_ADDR 0xB8000300 /* clock control register */ -#define IFXMIPS_GPTU_GPT_CLC ((u32*)(IFXMIPS_GPTU_BASE_ADDR + 0x0000)) +#define IFXMIPS_GPTU_GPT_CLC ((u32 *)(IFXMIPS_GPTU_BASE_ADDR + 0x0000)) /* captur reload register */ -#define IFXMIPS_GPTU_GPT_CAPREL ((u32*)(IFXMIPS_GPTU_BASE_ADDR + 0x0030)) +#define IFXMIPS_GPTU_GPT_CAPREL ((u32 *)(IFXMIPS_GPTU_BASE_ADDR + 0x0030)) /* timer 6 control register */ -#define IFXMIPS_GPTU_GPT_T6CON ((u32*)(IFXMIPS_GPTU_BASE_ADDR + 0x0020)) +#define IFXMIPS_GPTU_GPT_T6CON ((u32 *)(IFXMIPS_GPTU_BASE_ADDR + 0x0020)) /*------------ EBU */ @@ -139,33 +139,33 @@ #define IFXMIPS_EBU_BASE_ADDR 0xBE105300 /* bus configuration register */ -#define IFXMIPS_EBU_BUSCON0 ((u32*)(IFXMIPS_EBU_BASE_ADDR + 0x0060)) -#define IFXMIPS_EBU_PCC_CON ((u32*)(IFXMIPS_EBU_BASE_ADDR + 0x0090)) -#define IFXMIPS_EBU_PCC_IEN ((u32*)(IFXMIPS_EBU_BASE_ADDR + 0x00A4)) -#define IFXMIPS_EBU_PCC_ISTAT ((u32*)(IFXMIPS_EBU_BASE_ADDR + 0x00A0)) +#define IFXMIPS_EBU_BUSCON0 ((u32 *)(IFXMIPS_EBU_BASE_ADDR + 0x0060)) +#define IFXMIPS_EBU_PCC_CON ((u32 *)(IFXMIPS_EBU_BASE_ADDR + 0x0090)) +#define IFXMIPS_EBU_PCC_IEN ((u32 *)(IFXMIPS_EBU_BASE_ADDR + 0x00A4)) +#define IFXMIPS_EBU_PCC_ISTAT ((u32 *)(IFXMIPS_EBU_BASE_ADDR + 0x00A0)) /*------------ CGU */ #define IFXMIPS_CGU_BASE_ADDR (KSEG1 + 0x1F103000) -#define IFXMIPS_CGU_PLL0_CFG ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0004)) -#define IFXMIPS_CGU_PLL1_CFG ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0008)) -#define IFXMIPS_CGU_PLL2_CFG ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x000C)) -#define IFXMIPS_CGU_SYS ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0010)) -#define IFXMIPS_CGU_UPDATE ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0014)) -#define IFXMIPS_CGU_IF_CLK ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0018)) -#define IFXMIPS_CGU_OSC_CON ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x001C)) -#define IFXMIPS_CGU_SMD ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0020)) -#define IFXMIPS_CGU_CT1SR ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0028)) -#define IFXMIPS_CGU_CT2SR ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x002C)) -#define IFXMIPS_CGU_PCMCR ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0030)) -#define IFXMIPS_CGU_PCI_CR ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0034)) -#define IFXMIPS_CGU_PD_PC ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0038)) -#define IFXMIPS_CGU_FMR ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x003C)) +#define IFXMIPS_CGU_PLL0_CFG ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0004)) +#define IFXMIPS_CGU_PLL1_CFG ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0008)) +#define IFXMIPS_CGU_PLL2_CFG ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x000C)) +#define IFXMIPS_CGU_SYS ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0010)) +#define IFXMIPS_CGU_UPDATE ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0014)) +#define IFXMIPS_CGU_IF_CLK ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0018)) +#define IFXMIPS_CGU_OSC_CON ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x001C)) +#define IFXMIPS_CGU_SMD ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0020)) +#define IFXMIPS_CGU_CT1SR ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0028)) +#define IFXMIPS_CGU_CT2SR ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x002C)) +#define IFXMIPS_CGU_PCMCR ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0030)) +#define IFXMIPS_CGU_PCI_CR ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0034)) +#define IFXMIPS_CGU_PD_PC ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0038)) +#define IFXMIPS_CGU_FMR ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x003C)) /* clock mux */ -#define IFXMIPS_CGU_SYS ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0010)) -#define IFXMIPS_CGU_IFCCR ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0018)) -#define IFXMIPS_CGU_PCICR ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0034)) +#define IFXMIPS_CGU_SYS ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0010)) +#define IFXMIPS_CGU_IFCCR ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0018)) +#define IFXMIPS_CGU_PCICR ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0034)) #define CLOCK_60M 60000000 #define CLOCK_83M 83333333 @@ -179,8 +179,8 @@ #define IFXMIPS_PMU_BASE_ADDR (KSEG1 + 0x1F102000) -#define IFXMIPS_PMU_PWDCR ((u32*)(IFXMIPS_PMU_BASE_ADDR + 0x001C)) -#define IFXMIPS_PMU_PWDSR ((u32*)(IFXMIPS_PMU_BASE_ADDR + 0x0020)) +#define IFXMIPS_PMU_PWDCR ((u32 *)(IFXMIPS_PMU_BASE_ADDR + 0x001C)) +#define IFXMIPS_PMU_PWDSR ((u32 *)(IFXMIPS_PMU_BASE_ADDR + 0x0020)) /*------------ ICU */ @@ -188,17 +188,17 @@ #define IFXMIPS_ICU_BASE_ADDR 0xBF880200 -#define IFXMIPS_ICU_IM0_ISR ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0000)) -#define IFXMIPS_ICU_IM0_IER ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0008)) -#define IFXMIPS_ICU_IM0_IOSR ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0010)) -#define IFXMIPS_ICU_IM0_IRSR ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0018)) -#define IFXMIPS_ICU_IM0_IMR ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0020)) +#define IFXMIPS_ICU_IM0_ISR ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x0000)) +#define IFXMIPS_ICU_IM0_IER ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x0008)) +#define IFXMIPS_ICU_IM0_IOSR ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x0010)) +#define IFXMIPS_ICU_IM0_IRSR ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x0018)) +#define IFXMIPS_ICU_IM0_IMR ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x0020)) -#define IFXMIPS_ICU_IM1_ISR ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0028)) -#define IFXMIPS_ICU_IM2_IER ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0058)) -#define IFXMIPS_ICU_IM3_IER ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0080)) -#define IFXMIPS_ICU_IM4_IER ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x00A8)) -#define IFXMIPS_ICU_IM5_IER ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x00D0)) +#define IFXMIPS_ICU_IM1_ISR ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x0028)) +#define IFXMIPS_ICU_IM2_IER ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x0058)) +#define IFXMIPS_ICU_IM3_IER ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x0080)) +#define IFXMIPS_ICU_IM4_IER ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x00A8)) +#define IFXMIPS_ICU_IM5_IER ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x00D0)) #define IFXMIPS_ICU_OFFSET (IFXMIPS_ICU_IM1_ISR - IFXMIPS_ICU_IM0_ISR) @@ -209,15 +209,15 @@ #define ETHERNET_PACKET_DMA_BUFFER_SIZE 0x600 -#define IFXMIPS_PPE32_MEM_MAP ((u32*)(IFXMIPS_PPE32_BASE_ADDR + 0x10000)) -#define IFXMIPS_PPE32_SRST ((u32*)(IFXMIPS_PPE32_BASE_ADDR + 0x10080)) +#define IFXMIPS_PPE32_MEM_MAP ((u32 *)(IFXMIPS_PPE32_BASE_ADDR + 0x10000)) +#define IFXMIPS_PPE32_SRST ((u32 *)(IFXMIPS_PPE32_BASE_ADDR + 0x10080)) #define MII_MODE 1 #define REV_MII_MODE 2 /* mdio access */ -#define IFXMIPS_PPE32_MDIO_CFG ((u32*)(IFXMIPS_PPE32_BASE_ADDR + 0x11800)) -#define IFXMIPS_PPE32_MDIO_ACC ((u32*)(IFXMIPS_PPE32_BASE_ADDR + 0x11804)) +#define IFXMIPS_PPE32_MDIO_CFG ((u32 *)(IFXMIPS_PPE32_BASE_ADDR + 0x11800)) +#define IFXMIPS_PPE32_MDIO_ACC ((u32 *)(IFXMIPS_PPE32_BASE_ADDR + 0x11804)) #define MDIO_ACC_REQUEST 0x80000000 #define MDIO_ACC_READ 0x40000000 @@ -228,20 +228,20 @@ #define MDIO_ACC_VAL_MASK 0xffff /* configuration */ -#define IFXMIPS_PPE32_CFG ((u32*)(IFXMIPS_PPE32_MEM_MAP + 0x1808)) +#define IFXMIPS_PPE32_CFG ((u32 *)(IFXMIPS_PPE32_MEM_MAP + 0x1808)) #define PPE32_MII_MASK 0xfffffffc #define PPE32_MII_NORMAL 0x8 #define PPE32_MII_REVERSE 0xe /* packet length */ -#define IFXMIPS_PPE32_IG_PLEN_CTRL ((u32*)(IFXMIPS_PPE32_MEM_MAP + 0x1820)) +#define IFXMIPS_PPE32_IG_PLEN_CTRL ((u32 *)(IFXMIPS_PPE32_MEM_MAP + 0x1820)) #define PPE32_PLEN_OVER 0x5ee #define PPE32_PLEN_UNDER 0x400000 /* enet */ -#define IFXMIPS_PPE32_ENET_MAC_CFG ((u32*)(IFXMIPS_PPE32_MEM_MAP + 0x1840)) +#define IFXMIPS_PPE32_ENET_MAC_CFG ((u32 *)(IFXMIPS_PPE32_MEM_MAP + 0x1840)) #define PPE32_CGEN 0x800 @@ -249,45 +249,45 @@ /*------------ DMA */ #define IFXMIPS_DMA_BASE_ADDR 0xBE104100 -#define IFXMIPS_DMA_CS ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x18)) -#define IFXMIPS_DMA_CIE ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x2C)) -#define IFXMIPS_DMA_IRNEN ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0xf4)) -#define IFXMIPS_DMA_CCTRL ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x1C)) -#define IFXMIPS_DMA_CIS ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x28)) -#define IFXMIPS_DMA_CDLEN ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x24)) -#define IFXMIPS_DMA_PS ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x40)) -#define IFXMIPS_DMA_PCTRL ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x44)) -#define IFXMIPS_DMA_CTRL ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x10)) -#define IFXMIPS_DMA_CPOLL ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x14)) -#define IFXMIPS_DMA_CDBA ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x20)) +#define IFXMIPS_DMA_CS ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x18)) +#define IFXMIPS_DMA_CIE ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x2C)) +#define IFXMIPS_DMA_IRNEN ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0xf4)) +#define IFXMIPS_DMA_CCTRL ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x1C)) +#define IFXMIPS_DMA_CIS ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x28)) +#define IFXMIPS_DMA_CDLEN ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x24)) +#define IFXMIPS_DMA_PS ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x40)) +#define IFXMIPS_DMA_PCTRL ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x44)) +#define IFXMIPS_DMA_CTRL ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x10)) +#define IFXMIPS_DMA_CPOLL ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x14)) +#define IFXMIPS_DMA_CDBA ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x20)) /*------------ PCI */ #define PCI_CR_PR_BASE_ADDR (KSEG1 + 0x1E105400) -#define PCI_CR_FCI_ADDR_MAP0 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00C0)) -#define PCI_CR_FCI_ADDR_MAP1 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00C4)) -#define PCI_CR_FCI_ADDR_MAP2 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00C8)) -#define PCI_CR_FCI_ADDR_MAP3 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00CC)) -#define PCI_CR_FCI_ADDR_MAP4 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00D0)) -#define PCI_CR_FCI_ADDR_MAP5 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00D4)) -#define PCI_CR_FCI_ADDR_MAP6 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00D8)) -#define PCI_CR_FCI_ADDR_MAP7 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00DC)) -#define PCI_CR_CLK_CTRL ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0000)) -#define PCI_CR_PCI_MOD ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0030)) -#define PCI_CR_PC_ARB ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0080)) -#define PCI_CR_FCI_ADDR_MAP11hg ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00E4)) -#define PCI_CR_BAR11MASK ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0044)) -#define PCI_CR_BAR12MASK ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0048)) -#define PCI_CR_BAR13MASK ((u32*)(PCI_CR_PR_BASE_ADDR + 0x004C)) -#define PCI_CS_BASE_ADDR1 ((u32*)(PCI_CS_PR_BASE_ADDR + 0x0010)) -#define PCI_CR_PCI_ADDR_MAP11 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0064)) -#define PCI_CR_FCI_BURST_LENGTH ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00E8)) -#define PCI_CR_PCI_EOI ((u32*)(PCI_CR_PR_BASE_ADDR + 0x002C)) +#define PCI_CR_FCI_ADDR_MAP0 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00C0)) +#define PCI_CR_FCI_ADDR_MAP1 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00C4)) +#define PCI_CR_FCI_ADDR_MAP2 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00C8)) +#define PCI_CR_FCI_ADDR_MAP3 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00CC)) +#define PCI_CR_FCI_ADDR_MAP4 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00D0)) +#define PCI_CR_FCI_ADDR_MAP5 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00D4)) +#define PCI_CR_FCI_ADDR_MAP6 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00D8)) +#define PCI_CR_FCI_ADDR_MAP7 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00DC)) +#define PCI_CR_CLK_CTRL ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0000)) +#define PCI_CR_PCI_MOD ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0030)) +#define PCI_CR_PC_ARB ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0080)) +#define PCI_CR_FCI_ADDR_MAP11hg ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00E4)) +#define PCI_CR_BAR11MASK ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0044)) +#define PCI_CR_BAR12MASK ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0048)) +#define PCI_CR_BAR13MASK ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x004C)) +#define PCI_CS_BASE_ADDR1 ((u32 *)(PCI_CS_PR_BASE_ADDR + 0x0010)) +#define PCI_CR_PCI_ADDR_MAP11 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0064)) +#define PCI_CR_FCI_BURST_LENGTH ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00E8)) +#define PCI_CR_PCI_EOI ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x002C)) #define PCI_CS_PR_BASE_ADDR (KSEG1 + 0x17000000) -#define PCI_CS_STS_CMD ((u32*)(PCI_CS_PR_BASE_ADDR + 0x0004)) +#define PCI_CS_STS_CMD ((u32 *)(PCI_CS_PR_BASE_ADDR + 0x0004)) #define PCI_MASTER0_REQ_MASK_2BITS 8 #define PCI_MASTER1_REQ_MASK_2BITS 10 @@ -299,18 +299,18 @@ #define IFXMIPS_WDT_BASE_ADDR (KSEG1 + 0x1F880000) -#define IFXMIPS_BIU_WDT_CR ((u32*)(IFXMIPS_WDT_BASE_ADDR + 0x03F0)) -#define IFXMIPS_BIU_WDT_SR ((u32*)(IFXMIPS_WDT_BASE_ADDR + 0x03F8)) +#define IFXMIPS_BIU_WDT_CR ((u32 *)(IFXMIPS_WDT_BASE_ADDR + 0x03F0)) +#define IFXMIPS_BIU_WDT_SR ((u32 *)(IFXMIPS_WDT_BASE_ADDR + 0x03F8)) /*------------ LED */ #define IFXMIPS_LED_BASE_ADDR (KSEG1 + 0x1E100BB0) -#define IFXMIPS_LED_CON0 ((u32*)(IFXMIPS_LED_BASE_ADDR + 0x0000)) -#define IFXMIPS_LED_CON1 ((u32*)(IFXMIPS_LED_BASE_ADDR + 0x0004)) -#define IFXMIPS_LED_CPU0 ((u32*)(IFXMIPS_LED_BASE_ADDR + 0x0008)) -#define IFXMIPS_LED_CPU1 ((u32*)(IFXMIPS_LED_BASE_ADDR + 0x000C)) -#define IFXMIPS_LED_AR ((u32*)(IFXMIPS_LED_BASE_ADDR + 0x0010)) +#define IFXMIPS_LED_CON0 ((u32 *)(IFXMIPS_LED_BASE_ADDR + 0x0000)) +#define IFXMIPS_LED_CON1 ((u32 *)(IFXMIPS_LED_BASE_ADDR + 0x0004)) +#define IFXMIPS_LED_CPU0 ((u32 *)(IFXMIPS_LED_BASE_ADDR + 0x0008)) +#define IFXMIPS_LED_CPU1 ((u32 *)(IFXMIPS_LED_BASE_ADDR + 0x000C)) +#define IFXMIPS_LED_AR ((u32 *)(IFXMIPS_LED_BASE_ADDR + 0x0010)) #define LED_CON0_SWU (1 << 31) #define LED_CON0_AD1 (1 << 25) @@ -339,24 +339,24 @@ #define IFXMIPS_GPIO_BASE_ADDR (0xBE100B00) -#define IFXMIPS_GPIO_P0_OUT ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0010)) -#define IFXMIPS_GPIO_P1_OUT ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0040)) -#define IFXMIPS_GPIO_P0_IN ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0014)) -#define IFXMIPS_GPIO_P1_IN ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0044)) -#define IFXMIPS_GPIO_P0_DIR ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0018)) -#define IFXMIPS_GPIO_P1_DIR ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0048)) -#define IFXMIPS_GPIO_P0_ALTSEL0 ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x001C)) -#define IFXMIPS_GPIO_P1_ALTSEL0 ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x004C)) -#define IFXMIPS_GPIO_P0_ALTSEL1 ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0020)) -#define IFXMIPS_GPIO_P1_ALTSEL1 ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0050)) -#define IFXMIPS_GPIO_P0_OD ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0024)) -#define IFXMIPS_GPIO_P1_OD ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0054)) -#define IFXMIPS_GPIO_P0_STOFF ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0028)) -#define IFXMIPS_GPIO_P1_STOFF ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0058)) -#define IFXMIPS_GPIO_P0_PUDSEL ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x002C)) -#define IFXMIPS_GPIO_P1_PUDSEL ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x005C)) -#define IFXMIPS_GPIO_P0_PUDEN ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0030)) -#define IFXMIPS_GPIO_P1_PUDEN ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0060)) +#define IFXMIPS_GPIO_P0_OUT ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0010)) +#define IFXMIPS_GPIO_P1_OUT ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0040)) +#define IFXMIPS_GPIO_P0_IN ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0014)) +#define IFXMIPS_GPIO_P1_IN ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0044)) +#define IFXMIPS_GPIO_P0_DIR ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0018)) +#define IFXMIPS_GPIO_P1_DIR ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0048)) +#define IFXMIPS_GPIO_P0_ALTSEL0 ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x001C)) +#define IFXMIPS_GPIO_P1_ALTSEL0 ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x004C)) +#define IFXMIPS_GPIO_P0_ALTSEL1 ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0020)) +#define IFXMIPS_GPIO_P1_ALTSEL1 ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0050)) +#define IFXMIPS_GPIO_P0_OD ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0024)) +#define IFXMIPS_GPIO_P1_OD ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0054)) +#define IFXMIPS_GPIO_P0_STOFF ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0028)) +#define IFXMIPS_GPIO_P1_STOFF ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0058)) +#define IFXMIPS_GPIO_P0_PUDSEL ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x002C)) +#define IFXMIPS_GPIO_P1_PUDSEL ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x005C)) +#define IFXMIPS_GPIO_P0_PUDEN ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0030)) +#define IFXMIPS_GPIO_P1_PUDEN ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0060)) /*------------ SSC */ @@ -364,71 +364,71 @@ #define IFXMIPS_SSC_BASE_ADDR (KSEG1 + 0x1e100800) -#define IFXMIPS_SSC_CLC ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0000)) -#define IFXMIPS_SSC_IRN ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x00F4)) -#define IFXMIPS_SSC_SFCON ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0060)) -#define IFXMIPS_SSC_WHBGPOSTAT ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0078)) -#define IFXMIPS_SSC_STATE ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0014)) -#define IFXMIPS_SSC_WHBSTATE ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0018)) -#define IFXMIPS_SSC_FSTAT ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0038)) -#define IFXMIPS_SSC_ID ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0008)) -#define IFXMIPS_SSC_TB ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0020)) -#define IFXMIPS_SSC_RXFCON ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0030)) -#define IFXMIPS_SSC_TXFCON ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0034)) -#define IFXMIPS_SSC_CON ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0010)) -#define IFXMIPS_SSC_GPOSTAT ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0074)) -#define IFXMIPS_SSC_RB ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0024)) -#define IFXMIPS_SSC_RXCNT ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0084)) -#define IFXMIPS_SSC_GPOCON ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0070)) -#define IFXMIPS_SSC_BR ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0040)) -#define IFXMIPS_SSC_RXREQ ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0080)) -#define IFXMIPS_SSC_SFSTAT ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0064)) -#define IFXMIPS_SSC_RXCNT ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0084)) +#define IFXMIPS_SSC_CLC ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0000)) +#define IFXMIPS_SSC_IRN ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x00F4)) +#define IFXMIPS_SSC_SFCON ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0060)) +#define IFXMIPS_SSC_WHBGPOSTAT ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0078)) +#define IFXMIPS_SSC_STATE ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0014)) +#define IFXMIPS_SSC_WHBSTATE ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0018)) +#define IFXMIPS_SSC_FSTAT ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0038)) +#define IFXMIPS_SSC_ID ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0008)) +#define IFXMIPS_SSC_TB ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0020)) +#define IFXMIPS_SSC_RXFCON ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0030)) +#define IFXMIPS_SSC_TXFCON ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0034)) +#define IFXMIPS_SSC_CON ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0010)) +#define IFXMIPS_SSC_GPOSTAT ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0074)) +#define IFXMIPS_SSC_RB ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0024)) +#define IFXMIPS_SSC_RXCNT ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0084)) +#define IFXMIPS_SSC_GPOCON ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0070)) +#define IFXMIPS_SSC_BR ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0040)) +#define IFXMIPS_SSC_RXREQ ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0080)) +#define IFXMIPS_SSC_SFSTAT ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0064)) +#define IFXMIPS_SSC_RXCNT ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0084)) /*------------ MEI */ #define IFXMIPS_MEI_BASE_ADDR (KSEG1 + 0x1E116000) -#define MEI_DATA_XFR ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0000)) -#define MEI_VERSION ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0004)) -#define MEI_ARC_GP_STAT ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0008)) -#define MEI_DATA_XFR_STAT ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x000C)) -#define MEI_XFR_ADDR ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0010)) -#define MEI_MAX_WAIT ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0014)) -#define MEI_TO_ARC_INT ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0018)) -#define ARC_TO_MEI_INT ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x001C)) -#define ARC_TO_MEI_INT_MASK ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0020)) -#define MEI_DEBUG_WAD ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0024)) -#define MEI_DEBUG_RAD ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0028)) -#define MEI_DEBUG_DATA ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x002C)) -#define MEI_DEBUG_DEC ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0030)) -#define MEI_CONFIG ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0034)) -#define MEI_RST_CONTROL ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0038)) -#define MEI_DBG_MASTER ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x003C)) -#define MEI_CLK_CONTROL ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0040)) -#define MEI_BIST_CONTROL ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0044)) -#define MEI_BIST_STAT ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0048)) -#define MEI_XDATA_BASE_SH ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x004c)) -#define MEI_XDATA_BASE ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0050)) -#define MEI_XMEM_BAR_BASE ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0054)) -#define MEI_XMEM_BAR0 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0054)) -#define MEI_XMEM_BAR1 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0058)) -#define MEI_XMEM_BAR2 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x005C)) -#define MEI_XMEM_BAR3 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0060)) -#define MEI_XMEM_BAR4 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0064)) -#define MEI_XMEM_BAR5 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0068)) -#define MEI_XMEM_BAR6 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x006C)) -#define MEI_XMEM_BAR7 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0070)) -#define MEI_XMEM_BAR8 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0074)) -#define MEI_XMEM_BAR9 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0078)) -#define MEI_XMEM_BAR10 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x007C)) -#define MEI_XMEM_BAR11 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0080)) -#define MEI_XMEM_BAR12 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0084)) -#define MEI_XMEM_BAR13 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0088)) -#define MEI_XMEM_BAR14 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x008C)) -#define MEI_XMEM_BAR15 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0090)) -#define MEI_XMEM_BAR16 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0094)) +#define MEI_DATA_XFR ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0000)) +#define MEI_VERSION ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0004)) +#define MEI_ARC_GP_STAT ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0008)) +#define MEI_DATA_XFR_STAT ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x000C)) +#define MEI_XFR_ADDR ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0010)) +#define MEI_MAX_WAIT ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0014)) +#define MEI_TO_ARC_INT ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0018)) +#define ARC_TO_MEI_INT ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x001C)) +#define ARC_TO_MEI_INT_MASK ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0020)) +#define MEI_DEBUG_WAD ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0024)) +#define MEI_DEBUG_RAD ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0028)) +#define MEI_DEBUG_DATA ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x002C)) +#define MEI_DEBUG_DEC ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0030)) +#define MEI_CONFIG ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0034)) +#define MEI_RST_CONTROL ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0038)) +#define MEI_DBG_MASTER ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x003C)) +#define MEI_CLK_CONTROL ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0040)) +#define MEI_BIST_CONTROL ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0044)) +#define MEI_BIST_STAT ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0048)) +#define MEI_XDATA_BASE_SH ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x004c)) +#define MEI_XDATA_BASE ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0050)) +#define MEI_XMEM_BAR_BASE ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0054)) +#define MEI_XMEM_BAR0 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0054)) +#define MEI_XMEM_BAR1 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0058)) +#define MEI_XMEM_BAR2 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x005C)) +#define MEI_XMEM_BAR3 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0060)) +#define MEI_XMEM_BAR4 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0064)) +#define MEI_XMEM_BAR5 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0068)) +#define MEI_XMEM_BAR6 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x006C)) +#define MEI_XMEM_BAR7 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0070)) +#define MEI_XMEM_BAR8 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0074)) +#define MEI_XMEM_BAR9 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0078)) +#define MEI_XMEM_BAR10 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x007C)) +#define MEI_XMEM_BAR11 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0080)) +#define MEI_XMEM_BAR12 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0084)) +#define MEI_XMEM_BAR13 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0088)) +#define MEI_XMEM_BAR14 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x008C)) +#define MEI_XMEM_BAR15 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0090)) +#define MEI_XMEM_BAR16 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0094)) /*------------ DEU */ @@ -478,39 +478,39 @@ /*------------ MPS */ #define IFXMIPS_MPS_BASE_ADDR (KSEG1 + 0x1F107000) -#define IFXMIPS_MPS_SRAM ((u32*)(KSEG1 + 0x1F200000)) - -#define IFXMIPS_MPS_CHIPID ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0344)) -#define IFXMIPS_MPS_VC0ENR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0000)) -#define IFXMIPS_MPS_VC1ENR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0004)) -#define IFXMIPS_MPS_VC2ENR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0008)) -#define IFXMIPS_MPS_VC3ENR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x000C)) -#define IFXMIPS_MPS_RVC0SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0010)) -#define IFXMIPS_MPS_RVC1SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0014)) -#define IFXMIPS_MPS_RVC2SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0018)) -#define IFXMIPS_MPS_RVC3SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x001C)) -#define IFXMIPS_MPS_SVC0SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0020)) -#define IFXMIPS_MPS_SVC1SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0024)) -#define IFXMIPS_MPS_SVC2SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0028)) -#define IFXMIPS_MPS_SVC3SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x002C)) -#define IFXMIPS_MPS_CVC0SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0030)) -#define IFXMIPS_MPS_CVC1SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0034)) -#define IFXMIPS_MPS_CVC2SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0038)) -#define IFXMIPS_MPS_CVC3SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x003C)) -#define IFXMIPS_MPS_RAD0SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0040)) -#define IFXMIPS_MPS_RAD1SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0044)) -#define IFXMIPS_MPS_SAD0SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0048)) -#define IFXMIPS_MPS_SAD1SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x004C)) -#define IFXMIPS_MPS_CAD0SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0050)) -#define IFXMIPS_MPS_CAD1SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0054)) -#define IFXMIPS_MPS_AD0ENR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0058)) -#define IFXMIPS_MPS_AD1ENR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x005C)) +#define IFXMIPS_MPS_SRAM ((u32 *)(KSEG1 + 0x1F200000)) + +#define IFXMIPS_MPS_CHIPID ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0344)) +#define IFXMIPS_MPS_VC0ENR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0000)) +#define IFXMIPS_MPS_VC1ENR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0004)) +#define IFXMIPS_MPS_VC2ENR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0008)) +#define IFXMIPS_MPS_VC3ENR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x000C)) +#define IFXMIPS_MPS_RVC0SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0010)) +#define IFXMIPS_MPS_RVC1SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0014)) +#define IFXMIPS_MPS_RVC2SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0018)) +#define IFXMIPS_MPS_RVC3SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x001C)) +#define IFXMIPS_MPS_SVC0SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0020)) +#define IFXMIPS_MPS_SVC1SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0024)) +#define IFXMIPS_MPS_SVC2SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0028)) +#define IFXMIPS_MPS_SVC3SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x002C)) +#define IFXMIPS_MPS_CVC0SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0030)) +#define IFXMIPS_MPS_CVC1SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0034)) +#define IFXMIPS_MPS_CVC2SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0038)) +#define IFXMIPS_MPS_CVC3SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x003C)) +#define IFXMIPS_MPS_RAD0SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0040)) +#define IFXMIPS_MPS_RAD1SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0044)) +#define IFXMIPS_MPS_SAD0SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0048)) +#define IFXMIPS_MPS_SAD1SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x004C)) +#define IFXMIPS_MPS_CAD0SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0050)) +#define IFXMIPS_MPS_CAD1SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0054)) +#define IFXMIPS_MPS_AD0ENR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0058)) +#define IFXMIPS_MPS_AD1ENR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x005C)) #define IFXMIPS_MPS_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1)) -#define IFXMIPS_MPS_CHIPID_VERSION_SET(value) (((( 1 << 4) - 1) & (value)) << 28) +#define IFXMIPS_MPS_CHIPID_VERSION_SET(value) ((((1 << 4) - 1) & (value)) << 28) #define IFXMIPS_MPS_CHIPID_PARTNUM_GET(value) (((value) >> 12) & ((1 << 16) - 1)) -#define IFXMIPS_MPS_CHIPID_PARTNUM_SET(value) (((( 1 << 16) - 1) & (value)) << 12) +#define IFXMIPS_MPS_CHIPID_PARTNUM_SET(value) ((((1 << 16) - 1) & (value)) << 12) #define IFXMIPS_MPS_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 10) - 1)) -#define IFXMIPS_MPS_CHIPID_MANID_SET(value) (((( 1 << 10) - 1) & (value)) << 1) +#define IFXMIPS_MPS_CHIPID_MANID_SET(value) ((((1 << 10) - 1) & (value)) << 1) #endif diff --git a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_dma.h b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_dma.h index d4933ac77..bcf0f12c5 100644 --- a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_dma.h +++ b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_dma.h @@ -14,7 +14,7 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. * * Copyright (C) 2005 infineon - * Copyright (C) 2007 John Crispin <blogic@openwrt.org> + * Copyright (C) 2007 John Crispin <blogic@openwrt.org> * */ #ifndef _IFXMIPS_DMA_H__ @@ -56,16 +56,16 @@ enum attr_t{ #define IFXMIPS_DMA_RX -1 #define IFXMIPS_DMA_TX 1 -typedef struct dma_chan_map { +struct dma_chan_map { const char *dev_name; enum attr_t dir; int pri; int irq; int rel_chan_no; -} _dma_chan_map; +}; #ifdef CONFIG_CPU_LITTLE_ENDIAN -typedef struct rx_desc{ +struct rx_desc { u32 data_length:16; volatile u32 reserved:7; volatile u32 byte_offset:2; @@ -74,11 +74,10 @@ typedef struct rx_desc{ volatile u32 Res:1; volatile u32 C:1; volatile u32 OWN:1; - volatile u32 Data_Pointer; - /* fix me:should be 28 bits here, 32 bits just for host simulation purpose */ -}_rx_desc; + volatile u32 Data_Pointer; /* fixme: should be 28 bits here */ +}; -typedef struct tx_desc{ +struct tx_desc { volatile u32 data_length:16; volatile u32 reserved1:7; volatile u32 byte_offset:5; @@ -86,14 +85,12 @@ typedef struct tx_desc{ volatile u32 SoP:1; volatile u32 C:1; volatile u32 OWN:1; - volatile u32 Data_Pointer;/* fix me:should be 28 bits here */ -}_tx_desc; + volatile u32 Data_Pointer; /* fixme: should be 28 bits here */ +}; #else /* BIG */ -typedef struct rx_desc{ - union - { - struct - { +struct rx_desc { + union { + struct { volatile u32 OWN:1; volatile u32 C:1; volatile u32 SoP:1; @@ -102,17 +99,15 @@ typedef struct rx_desc{ volatile u32 byte_offset:2; volatile u32 reserve:7; volatile u32 data_length:16; - }field; + } field; volatile u32 word; - }status; + } status; volatile u32 Data_Pointer; -}_rx_desc; +}; -typedef struct tx_desc{ - union - { - struct - { +struct tx_desc { + union { + struct { volatile u32 OWN:1; volatile u32 C:1; volatile u32 SoP:1; @@ -120,84 +115,81 @@ typedef struct tx_desc{ volatile u32 byte_offset:5; volatile u32 reserved:7; volatile u32 data_length:16; - }field; + } field; volatile u32 word; - }status; + } status; volatile u32 Data_Pointer; -}_tx_desc; -#endif //ENDIAN +}; +#endif /* ENDIAN */ -typedef struct dma_channel_info{ - /*relative channel number*/ +struct dma_channel_info { + /* relative channel number */ int rel_chan_no; - /*class for this channel for QoS*/ + /* class for this channel for QoS */ int pri; - /*specify byte_offset*/ + /* specify byte_offset */ int byte_offset; - /*direction*/ + /* direction */ int dir; - /*irq number*/ + /* irq number */ int irq; - /*descriptor parameter*/ + /* descriptor parameter */ int desc_base; int desc_len; int curr_desc; - int prev_desc;/*only used if it is a tx channel*/ - /*weight setting for WFQ algorithm*/ + int prev_desc; /* only used if it is a tx channel*/ + /* weight setting for WFQ algorithm*/ int weight; int default_weight; int packet_size; int burst_len; - /*on or off of this channel*/ + /* on or off of this channel */ int control; - /**optional information for the upper layer devices*/ + /* optional information for the upper layer devices */ #if defined(CONFIG_IFXMIPS_ETHERNET_D2) || defined(CONFIG_IFXMIPS_PPA) - void* opt[64]; + void *opt[64]; #else - void* opt[25]; + void *opt[25]; #endif - /*Pointer to the peripheral device who is using this channel*/ - void* dma_dev; - /*channel operations*/ - void (*open)(struct dma_channel_info* pCh); - void (*close)(struct dma_channel_info* pCh); - void (*reset)(struct dma_channel_info* pCh); - void (*enable_irq)(struct dma_channel_info* pCh); - void (*disable_irq)(struct dma_channel_info* pCh); -}_dma_channel_info; - -typedef struct dma_device_info{ - /*device name of this peripheral*/ - char device_name[15]; + /* Pointer to the peripheral device who is using this channel */ + void *dma_dev; + /* channel operations */ + void (*open)(struct dma_channel_info *pCh); + void (*close)(struct dma_channel_info *pCh); + void (*reset)(struct dma_channel_info *pCh); + void (*enable_irq)(struct dma_channel_info *pCh); + void (*disable_irq)(struct dma_channel_info *pCh); +}; + +struct dma_device_info { + /* device name of this peripheral */ + const char *device_name; int reserved; int tx_burst_len; int rx_burst_len; int default_weight; - int current_tx_chan; - int current_rx_chan; - int num_tx_chan; - int num_rx_chan; - int max_rx_chan_num; - int max_tx_chan_num; - _dma_channel_info* tx_chan[20]; - _dma_channel_info* rx_chan[20]; + int current_tx_chan; + int current_rx_chan; + int num_tx_chan; + int num_rx_chan; + int max_rx_chan_num; + int max_tx_chan_num; + struct dma_channel_info *tx_chan[20]; + struct dma_channel_info *rx_chan[20]; /*functions, optional*/ - u8* (*buffer_alloc)(int len,int* offset, void** opt); - void (*buffer_free)(u8* dataptr, void* opt); - int (*intr_handler)(struct dma_device_info* info, int status); - void * priv; /* used by peripheral driver only */ -}_dma_device_info; - -_dma_device_info* dma_device_reserve(char* dev_name); - -void dma_device_release(_dma_device_info* dev); - -void dma_device_register(_dma_device_info* info); - -void dma_device_unregister(_dma_device_info* info); + u8 *(*buffer_alloc)(int len, int *offset, void **opt); + void (*buffer_free)(u8 *dataptr, void *opt); + int (*intr_handler)(struct dma_device_info *info, int status); + void *priv; /* used by peripheral driver only */ +}; -int dma_device_read(struct dma_device_info* info, u8** dataptr, void** opt); +struct dma_device_info *dma_device_reserve(char *dev_name); +void dma_device_release(struct dma_device_info *dev); +void dma_device_register(struct dma_device_info *info); +void dma_device_unregister(struct dma_device_info *info); +int dma_device_read(struct dma_device_info *info, u8 **dataptr, void **opt); +int dma_device_write(struct dma_device_info *info, u8 *dataptr, int len, + void *opt); -int dma_device_write(struct dma_device_info* info, u8* dataptr, int len, void* opt); #endif diff --git a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_ebu.h b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_ebu.h index f9278ed15..4c9396ae8 100644 --- a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_ebu.h +++ b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_ebu.h @@ -13,7 +13,7 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. * - * Copyright (C) 2007 John Crispin <blogic@openwrt.org> + * Copyright (C) 2007 John Crispin <blogic@openwrt.org> */ #ifndef _IFXMIPS_EBU_H__ #define _IFXMIPS_EBU_H__ diff --git a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_gpio.h b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_gpio.h index 237db01ec..a4c8c3ffb 100644 --- a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_gpio.h +++ b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_gpio.h @@ -12,29 +12,29 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. - * Copyright (C) 2007 John Crispin <blogic@openwrt.org> + * Copyright (C) 2007 John Crispin <blogic@openwrt.org> */ #ifndef _IFXMIPS_GPIO_H__ #define _IFXMIPS_GPIO_H__ -extern int ifxmips_port_reserve_pin (unsigned int port, unsigned int pin); -extern int ifxmips_port_free_pin (unsigned int port, unsigned int pin); -extern int ifxmips_port_set_open_drain (unsigned int port, unsigned int pin); -extern int ifxmips_port_clear_open_drain (unsigned int port, unsigned int pin); -extern int ifxmips_port_set_pudsel (unsigned int port, unsigned int pin); -extern int ifxmips_port_clear_pudsel (unsigned int port, unsigned int pin); -extern int ifxmips_port_set_puden (unsigned int port, unsigned int pin); -extern int ifxmips_port_clear_puden (unsigned int port, unsigned int pin); -extern int ifxmips_port_set_stoff (unsigned int port, unsigned int pin); -extern int ifxmips_port_clear_stoff (unsigned int port, unsigned int pin); -extern int ifxmips_port_set_dir_out (unsigned int port, unsigned int pin); -extern int ifxmips_port_set_dir_in (unsigned int port, unsigned int pin); -extern int ifxmips_port_set_output (unsigned int port, unsigned int pin); -extern int ifxmips_port_clear_output (unsigned int port, unsigned int pin); -extern int ifxmips_port_get_input (unsigned int port, unsigned int pin); -extern int ifxmips_port_set_altsel0 (unsigned int port, unsigned int pin); -extern int ifxmips_port_clear_altsel0 (unsigned int port, unsigned int pin); -extern int ifxmips_port_set_altsel1 (unsigned int port, unsigned int pin); -extern int ifxmips_port_clear_altsel1 (unsigned int port, unsigned int pin); +extern int ifxmips_port_reserve_pin(unsigned int port, unsigned int pin); +extern int ifxmips_port_free_pin(unsigned int port, unsigned int pin); +extern int ifxmips_port_set_open_drain(unsigned int port, unsigned int pin); +extern int ifxmips_port_clear_open_drain(unsigned int port, unsigned int pin); +extern int ifxmips_port_set_pudsel(unsigned int port, unsigned int pin); +extern int ifxmips_port_clear_pudsel(unsigned int port, unsigned int pin); +extern int ifxmips_port_set_puden(unsigned int port, unsigned int pin); +extern int ifxmips_port_clear_puden(unsigned int port, unsigned int pin); +extern int ifxmips_port_set_stoff(unsigned int port, unsigned int pin); +extern int ifxmips_port_clear_stoff(unsigned int port, unsigned int pin); +extern int ifxmips_port_set_dir_out(unsigned int port, unsigned int pin); +extern int ifxmips_port_set_dir_in(unsigned int port, unsigned int pin); +extern int ifxmips_port_set_output(unsigned int port, unsigned int pin); +extern int ifxmips_port_clear_output(unsigned int port, unsigned int pin); +extern int ifxmips_port_get_input(unsigned int port, unsigned int pin); +extern int ifxmips_port_set_altsel0(unsigned int port, unsigned int pin); +extern int ifxmips_port_clear_altsel0(unsigned int port, unsigned int pin); +extern int ifxmips_port_set_altsel1(unsigned int port, unsigned int pin); +extern int ifxmips_port_clear_altsel1(unsigned int port, unsigned int pin); #endif diff --git a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_gptu.h b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_gptu.h index 6ad4cc58c..4ff1ee0af 100644 --- a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_gptu.h +++ b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_gptu.h @@ -141,21 +141,15 @@ struct gptu_ioctl_param { */ typedef void (*timer_callback)(unsigned long arg); - -#if defined(__KERNEL__) - extern int ifxmips_request_timer(unsigned int, unsigned int, unsigned long, unsigned long, unsigned long); - extern int ifxmips_free_timer(unsigned int); - extern int ifxmips_start_timer(unsigned int, int); - extern int ifxmips_stop_timer(unsigned int); - extern int ifxmips_reset_counter_flags(u32 timer, u32 flags); - extern int ifxmips_get_count_value(unsigned int, unsigned long *); - - extern u32 cal_divider(unsigned long); - - extern int set_timer(unsigned int, unsigned int, int, int, unsigned int, unsigned long, unsigned long); -extern int set_counter (unsigned int timer, unsigned int flag, u32 reload, unsigned long arg1, unsigned long arg2); -// extern int set_counter(unsigned int, int, int, int, unsigned int, unsigned int, unsigned long, unsigned long); -#endif // defined(__KERNEL__) - - -#endif // __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ +xtern int ifxmips_request_timer(unsigned int, unsigned int, unsigned long, unsigned long, unsigned long); +extern int ifxmips_free_timer(unsigned int); +extern int ifxmips_start_timer(unsigned int, int); +extern int ifxmips_stop_timer(unsigned int); +extern int ifxmips_reset_counter_flags(u32 timer, u32 flags); +extern int ifxmips_get_count_value(unsigned int, unsigned long *); +extern u32 ifxmips_cal_divider(unsigned long); +extern int ifxmips_set_timer(unsigned int, unsigned int, int, int, unsigned int, unsigned long, unsigned long); +extern int ifxmips_set_counter(unsigned int timer, unsigned int flag, + u32 reload, unsigned long arg1, unsigned long arg2); + +#endif /* __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ */ diff --git a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_led.h b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_led.h index 5e0d7f3e1..c97657a89 100644 --- a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_led.h +++ b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_led.h @@ -13,9 +13,9 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. * - * Copyright (C) 2007 John Crispin <blogic@openwrt.org> + * Copyright (C) 2007 John Crispin <blogic@openwrt.org> */ -#ifndef _IFXMIPS_LED_H__ +#ifndef _IFXMIPS_LED_H__ #define _IFXMIPS_LED_H__ extern void ifxmips_led_set(unsigned int led); diff --git a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_pmu.h b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_pmu.h index b84273445..c1ba6cbfb 100644 --- a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_pmu.h +++ b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_pmu.h @@ -13,18 +13,18 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. * - * Copyright (C) 2007 John Crispin <blogic@openwrt.org> + * Copyright (C) 2007 John Crispin <blogic@openwrt.org> */ #ifndef _IFXMIPS_PMU_H__ #define _IFXMIPS_PMU_H__ -#define IFXMIPS_PMU_PWDCR_DMA 0x20 -#define IFXMIPS_PMU_PWDCR_LED 0x800 -#define IFXMIPS_PMU_PWDCR_GPT 0x1000 -#define IFXMIPS_PMU_PWDCR_PPE 0x2000 -#define IFXMIPS_PMU_PWDCR_FPI 0x4000 +#define IFXMIPS_PMU_PWDCR_DMA 0x20 +#define IFXMIPS_PMU_PWDCR_LED 0x800 +#define IFXMIPS_PMU_PWDCR_GPT 0x1000 +#define IFXMIPS_PMU_PWDCR_PPE 0x2000 +#define IFXMIPS_PMU_PWDCR_FPI 0x4000 -void ifxmips_pmu_enable (unsigned int module); -void ifxmips_pmu_disable (unsigned int module); +void ifxmips_pmu_enable(unsigned int module); +void ifxmips_pmu_disable(unsigned int module); #endif diff --git a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_prom.h b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_prom.h index 822ff0bca..e640ad7ac 100644 --- a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_prom.h +++ b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_prom.h @@ -13,12 +13,12 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. * - * Copyright (C) 2008 John Crispin <blogic@openwrt.org> + * Copyright (C) 2008 John Crispin <blogic@openwrt.org> */ #ifndef _IFXPROM_H__ #define _IFXPROM_H__ -extern void prom_printf(const char * fmt, ...); +extern void prom_printf(const char *fmt, ...); extern u32 *prom_get_cp1_base(void); extern u32 prom_get_cp1_size(void); extern int ifxmips_has_brn_block(void); diff --git a/target/linux/ifxmips/files/include/asm-mips/mach-ifxmips/gpio.h b/target/linux/ifxmips/files/include/asm-mips/mach-ifxmips/gpio.h index 8a9651017..92adc4848 100644 --- a/target/linux/ifxmips/files/include/asm-mips/mach-ifxmips/gpio.h +++ b/target/linux/ifxmips/files/include/asm-mips/mach-ifxmips/gpio.h @@ -1,5 +1,5 @@ /* - * include/asm-mips/mach-ifxmips/gpio.h + * include/asm-mips/mach-ifxmips/gpio.h * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -25,10 +25,11 @@ #include <asm/ifxmips/ifxmips.h> #include <asm/ifxmips/ifxmips_gpio.h> -#define GPIO_TO_PORT(x) ((x > 15)?(1):(0)) -#define GPIO_TO_GPIO(x) ((x > 15)?(x-16):(x)) +#define GPIO_TO_PORT(x) ((x > 15) ? (1) : (0)) +#define GPIO_TO_GPIO(x) ((x > 15) ? (x-16) : (x)) -static inline int gpio_direction_input(unsigned gpio) { +static inline int gpio_direction_input(unsigned gpio) +{ ifxmips_port_set_open_drain(GPIO_TO_PORT(gpio), GPIO_TO_GPIO(gpio)); ifxmips_port_clear_altsel0(GPIO_TO_PORT(gpio), GPIO_TO_GPIO(gpio)); ifxmips_port_clear_altsel1(GPIO_TO_PORT(gpio), GPIO_TO_GPIO(gpio)); @@ -36,7 +37,8 @@ static inline int gpio_direction_input(unsigned gpio) { return 0; } -static inline int gpio_direction_output(unsigned gpio, int value) { +static inline int gpio_direction_output(unsigned gpio, int value) +{ ifxmips_port_clear_open_drain(GPIO_TO_PORT(gpio), GPIO_TO_GPIO(gpio)); ifxmips_port_clear_altsel0(GPIO_TO_PORT(gpio), GPIO_TO_GPIO(gpio)); ifxmips_port_clear_altsel1(GPIO_TO_PORT(gpio), GPIO_TO_GPIO(gpio)); @@ -44,43 +46,53 @@ static inline int gpio_direction_output(unsigned gpio, int value) { return 0; } -static inline int gpio_get_value(unsigned gpio) { +static inline int gpio_get_value(unsigned gpio) +{ ifxmips_port_get_input(GPIO_TO_PORT(gpio), GPIO_TO_GPIO(gpio)); return 0; } -static inline void gpio_set_value(unsigned gpio, int value) { - if(value) +static inline void gpio_set_value(unsigned gpio, int value) +{ + if (value) ifxmips_port_set_output(GPIO_TO_PORT(gpio), GPIO_TO_GPIO(gpio)); else - ifxmips_port_clear_output(GPIO_TO_PORT(gpio), GPIO_TO_GPIO(gpio)); + ifxmips_port_clear_output(GPIO_TO_PORT(gpio), + GPIO_TO_GPIO(gpio)); } -static inline int gpio_request(unsigned gpio, const char *label) { +static inline int gpio_request(unsigned gpio, const char *label) +{ return 0; } -static inline void gpio_free(unsigned gpio) { +static inline void gpio_free(unsigned gpio) +{ } -static inline int gpio_to_irq(unsigned gpio) { +static inline int gpio_to_irq(unsigned gpio) +{ return 0; } -static inline int irq_to_gpio(unsigned irq) { +static inline int irq_to_gpio(unsigned irq) +{ return 0; } -static inline int gpio_cansleep(unsigned gpio) { +static inline int gpio_cansleep(unsigned gpio) +{ return 0; } -static inline int gpio_get_value_cansleep(unsigned gpio) { +static inline int gpio_get_value_cansleep(unsigned gpio) +{ might_sleep(); - return gpio_get_value(gpio); + return gpio_get_value(gpio); } -static inline void gpio_set_value_cansleep(unsigned gpio, int value) { +static inline void gpio_set_value_cansleep(unsigned gpio, int value) +{ might_sleep(); gpio_set_value(gpio, value); } diff --git a/target/linux/ifxmips/files/include/asm-mips/mach-ifxmips/irq.h b/target/linux/ifxmips/files/include/asm-mips/mach-ifxmips/irq.h index f178abf48..80342ae3a 100644 --- a/target/linux/ifxmips/files/include/asm-mips/mach-ifxmips/irq.h +++ b/target/linux/ifxmips/files/include/asm-mips/mach-ifxmips/irq.h @@ -1,5 +1,5 @@ /* - * include/asm-mips/mach-ifxmips/irq.h + * include/asm-mips/mach-ifxmips/irq.h * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -15,15 +15,14 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. * - * Copyright (C) 2007 John Crispin <blogic@openwrt.org> + * Copyright (C) 2007 John Crispin <blogic@openwrt.org> * */ #ifndef __IFXMIPS_IRQ_H #define __IFXMIPS_IRQ_H -#define NR_IRQS 256 +#define NR_IRQS 256 #include_next <irq.h> #endif - |