1 files changed, 44 insertions, 4 deletions

diff --git a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips.h b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips.h
index 706e7390a..a2efc7883 100644
--- a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips.h
+++ b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips.h
@@ -88,7 +88,7 @@
 #define IFXMIPS_ASC1_RXFCON		((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0040))
 
 /* control */
-#define IFXMIPS_ASC1_CON			((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0010))
+#define IFXMIPS_ASC1_CON		((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0010))
 
 /* timer reload */
 #define IFXMIPS_ASC1_BG			((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0050))
@@ -103,12 +103,12 @@
 
 
 /*------------ RCU */
-
 #define IFXMIPS_RCU_BASE_ADDR	0xBF203000
 
 /* reset request */
-#define IFXMIPS_RCU_REQ			((u32*)(IFXMIPS_RCU_BASE_ADDR + 0x0010))
-#define IFXMIPS_RST_ALL			0x40000000
+#define IFXMIPS_RCU_RST			((u32*)(IFXMIPS_RCU_BASE_ADDR + 0x0010))
+#define IFXMIPS_RCU_RST_CPU1	(1 << 3)
+#define IFXMIPS_RCU_RST_ALL		0x40000000
 
 #define IFXMIPS_RCU_RST_REQ_DFE	(1 << 7)
 #define IFXMIPS_RCU_RST_REQ_AFE	(1 << 11)
@@ -440,6 +440,45 @@
 #define MEI_XMEM_BAR16			((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0094))
 
 
+/*------------ DEU */
+
+#define IFXMIPS_DEU_BASE     (KSEG1 + 0x1E103100)
+#define IFXMIPS_DEU_CLK			((u32 *)(IFXMIPS_DEU_BASE + 0x0000))
+#define IFXMIPS_DEU_ID			((u32 *)(IFXMIPS_DEU_BASE + 0x0008))
+
+#define IFXMIPS_DES_CON			((u32 *)(IFXMIPS_DEU_BASE + 0x0010))
+#define IFXMIPS_DES_IHR			((u32 *)(IFXMIPS_DEU_BASE + 0x0014))
+#define IFXMIPS_DES_ILR			((u32 *)(IFXMIPS_DEU_BASE + 0x0018))
+#define IFXMIPS_DES_K1HR		((u32 *)(IFXMIPS_DEU_BASE + 0x001C))
+#define IFXMIPS_DES_K1LR		((u32 *)(IFXMIPS_DEU_BASE + 0x0020))
+#define IFXMIPS_DES_K3HR		((u32 *)(IFXMIPS_DEU_BASE + 0x0024))
+#define IFXMIPS_DES_K3LR		((u32 *)(IFXMIPS_DEU_BASE + 0x0028))
+#define IFXMIPS_DES_IVHR		((u32 *)(IFXMIPS_DEU_BASE + 0x002C))
+#define IFXMIPS_DES_IVLR		((u32 *)(IFXMIPS_DEU_BASE + 0x0030))
+#define IFXMIPS_DES_OHR			((u32 *)(IFXMIPS_DEU_BASE + 0x0040))
+#define IFXMIPS_DES_OLR			((u32 *)(IFXMIPS_DEU_BASE + 0x0050))
+#define IFXMIPS_AES_CON			((u32 *)(IFXMIPS_DEU_BASE + 0x0050))
+#define IFXMIPS_AES_ID3R		((u32 *)(IFXMIPS_DEU_BASE + 0x0054))
+#define IFXMIPS_AES_ID2R		((u32 *)(IFXMIPS_DEU_BASE + 0x0058))
+#define IFXMIPS_AES_ID1R		((u32 *)(IFXMIPS_DEU_BASE + 0x005C))
+#define IFXMIPS_AES_ID0R		((u32 *)(IFXMIPS_DEU_BASE + 0x0060))
+#define IFXMIPS_AES_K7R			((u32 *)(IFXMIPS_DEU_BASE + 0x0064))
+#define IFXMIPS_AES_K6R			((u32 *)(IFXMIPS_DEU_BASE + 0x0068))
+#define IFXMIPS_AES_K5R			((u32 *)(IFXMIPS_DEU_BASE + 0x006C))
+#define IFXMIPS_AES_K4R			((u32 *)(IFXMIPS_DEU_BASE + 0x0070))
+#define IFXMIPS_AES_K3R			((u32 *)(IFXMIPS_DEU_BASE + 0x0074))
+#define IFXMIPS_AES_K2R			((u32 *)(IFXMIPS_DEU_BASE + 0x0078))
+#define IFXMIPS_AES_K1R			((u32 *)(IFXMIPS_DEU_BASE + 0x007C))
+#define IFXMIPS_AES_K0R			((u32 *)(IFXMIPS_DEU_BASE + 0x0080))
+#define IFXMIPS_AES_IV3R		((u32 *)(IFXMIPS_DEU_BASE + 0x0084))
+#define IFXMIPS_AES_IV2R		((u32 *)(IFXMIPS_DEU_BASE + 0x0088))
+#define IFXMIPS_AES_IV1R		((u32 *)(IFXMIPS_DEU_BASE + 0x008C))
+#define IFXMIPS_AES_IV0R		((u32 *)(IFXMIPS_DEU_BASE + 0x0090))
+#define IFXMIPS_AES_0D3R		((u32 *)(IFXMIPS_DEU_BASE + 0x0094))
+#define IFXMIPS_AES_0D2R		((u32 *)(IFXMIPS_DEU_BASE + 0x0098))
+#define IFXMIPS_AES_OD1R		((u32 *)(IFXMIPS_DEU_BASE + 0x009C))
+#define IFXMIPS_AES_OD0R		((u32 *)(IFXMIPS_DEU_BASE + 0x00A0))
+
 /*------------ FUSE */
 
 #define IFXMIPS_FUSE_BASE_ADDR	(KSEG1 + 0x1F107354)
@@ -448,6 +487,7 @@
 /*------------ MPS */
 
 #define IFXMIPS_MPS_BASE_ADDR	(KSEG1 + 0x1F107000)
+#define IFXMIPS_MPS_SRAM		((u32*)(KSEG1 + 0x1F200000))
 
 #define IFXMIPS_MPS_CHIPID		((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0344))
 #define IFXMIPS_MPS_VC0ENR		((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0000))