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-rw-r--r--target/linux/ifxmips/files/arch/mips/ifxmips/clock.c99
-rw-r--r--target/linux/ifxmips/files/arch/mips/ifxmips/dma-core.c56
-rw-r--r--target/linux/ifxmips/files/arch/mips/ifxmips/gpio.c136
-rw-r--r--target/linux/ifxmips/files/arch/mips/ifxmips/pmu.c14
-rw-r--r--target/linux/ifxmips/files/arch/mips/ifxmips/prom.c25
-rw-r--r--target/linux/ifxmips/files/arch/mips/ifxmips/reset.c20
-rw-r--r--target/linux/ifxmips/files/arch/mips/ifxmips/setup.c6
-rw-r--r--target/linux/ifxmips/files/arch/mips/ifxmips/timer.c575
8 files changed, 441 insertions, 490 deletions
diff --git a/target/linux/ifxmips/files/arch/mips/ifxmips/clock.c b/target/linux/ifxmips/files/arch/mips/ifxmips/clock.c
index 40a6b9919..d44bf44e4 100644
--- a/target/linux/ifxmips/files/arch/mips/ifxmips/clock.c
+++ b/target/linux/ifxmips/files/arch/mips/ifxmips/clock.c
@@ -70,33 +70,31 @@ unsigned int ifxmips_clocks[] = {CLOCK_167M, CLOCK_133M, CLOCK_111M, CLOCK_83M }
#define DDR_HZ ifxmips_clocks[ifxmips_r32(IFXMIPS_CGU_SYS) & 0x3]
-
-static inline unsigned int
-get_input_clock(int pll)
+static inline unsigned int get_input_clock(int pll)
{
- switch(pll)
- {
+ switch (pll) {
case 0:
- if(ifxmips_r32(IFXMIPS_CGU_PLL0_CFG) & CGU_PLL0_SRC)
+ if (ifxmips_r32(IFXMIPS_CGU_PLL0_CFG) & CGU_PLL0_SRC)
return BASIS_INPUT_CRYSTAL_USB;
- else if(CGU_PLL0_PHASE_DIVIDER_ENABLE)
+ else if (CGU_PLL0_PHASE_DIVIDER_ENABLE)
return BASIC_INPUT_CLOCK_FREQUENCY_1;
else
return BASIC_INPUT_CLOCK_FREQUENCY_2;
case 1:
- if(CGU_PLL1_SRC)
+ if (CGU_PLL1_SRC)
return BASIS_INPUT_CRYSTAL_USB;
- else if(CGU_PLL0_PHASE_DIVIDER_ENABLE)
+ else if (CGU_PLL0_PHASE_DIVIDER_ENABLE)
return BASIC_INPUT_CLOCK_FREQUENCY_1;
else
return BASIC_INPUT_CLOCK_FREQUENCY_2;
case 2:
- switch(CGU_PLL2_SRC)
- {
+ switch (CGU_PLL2_SRC) {
case 0:
return cgu_get_pll0_fdiv();
case 1:
- return CGU_PLL2_PHASE_DIVIDER_ENABLE ? BASIC_INPUT_CLOCK_FREQUENCY_1 : BASIC_INPUT_CLOCK_FREQUENCY_2;
+ return CGU_PLL2_PHASE_DIVIDER_ENABLE ?
+ BASIC_INPUT_CLOCK_FREQUENCY_1 :
+ BASIC_INPUT_CLOCK_FREQUENCY_2;
case 2:
return BASIS_INPUT_CRYSTAL_USB;
}
@@ -105,8 +103,7 @@ get_input_clock(int pll)
}
}
-static inline unsigned int
-cal_dsm(int pll, unsigned int num, unsigned int den)
+static inline unsigned int cal_dsm(int pll, unsigned int num, unsigned int den)
{
u64 res, clock = get_input_clock(pll);
@@ -115,8 +112,8 @@ cal_dsm(int pll, unsigned int num, unsigned int den)
return res;
}
-static inline unsigned int
-mash_dsm(int pll, unsigned int M, unsigned int N, unsigned int K)
+static inline unsigned int mash_dsm(int pll, unsigned int M, unsigned int N,
+ unsigned int K)
{
unsigned int num = ((N + 1) << 10) + K;
unsigned int den = (M + 1) << 10;
@@ -124,8 +121,8 @@ mash_dsm(int pll, unsigned int M, unsigned int N, unsigned int K)
return cal_dsm(pll, num, den);
}
-static inline unsigned int
-ssff_dsm_1(int pll, unsigned int M, unsigned int N, unsigned int K)
+static inline unsigned int ssff_dsm_1(int pll, unsigned int M, unsigned int N,
+ unsigned int K)
{
unsigned int num = ((N + 1) << 11) + K + 512;
unsigned int den = (M + 1) << 11;
@@ -133,8 +130,8 @@ ssff_dsm_1(int pll, unsigned int M, unsigned int N, unsigned int K)
return cal_dsm(pll, num, den);
}
-static inline unsigned int
-ssff_dsm_2(int pll, unsigned int M, unsigned int N, unsigned int K)
+static inline unsigned int ssff_dsm_2(int pll, unsigned int M, unsigned int N,
+ unsigned int K)
{
unsigned int num = K >= 512 ?
((N + 1) << 12) + K - 512 : ((N + 1) << 12) + K + 3584;
@@ -143,22 +140,20 @@ ssff_dsm_2(int pll, unsigned int M, unsigned int N, unsigned int K)
return cal_dsm(pll, num, den);
}
-static inline unsigned int
-dsm(int pll, unsigned int M, unsigned int N, unsigned int K,
- unsigned int dsmsel, unsigned int phase_div_en)
+static inline unsigned int dsm(int pll, unsigned int M, unsigned int N,
+ unsigned int K, unsigned int dsmsel, unsigned int phase_div_en)
{
- if(!dsmsel)
+ if (!dsmsel)
return mash_dsm(pll, M, N, K);
- else if(!phase_div_en)
+ else if (!phase_div_en)
return mash_dsm(pll, M, N, K);
else
return ssff_dsm_2(pll, M, N, K);
}
-static inline unsigned int
-cgu_get_pll0_fosc(void)
+static inline unsigned int cgu_get_pll0_fosc(void)
{
- if(CGU_PLL0_BYPASS)
+ if (CGU_PLL0_BYPASS)
return get_input_clock(0);
else
return !CGU_PLL0_CFG_FRAC_EN
@@ -168,19 +163,16 @@ cgu_get_pll0_fosc(void)
CGU_PLL0_CFG_DSMSEL, CGU_PLL0_PHASE_DIVIDER_ENABLE);
}
-static unsigned int
-cgu_get_pll0_fdiv(void)
+static unsigned int cgu_get_pll0_fdiv(void)
{
- register unsigned int div = CGU_PLL2_CFG_INPUT_DIV + 1;
+ unsigned int div = CGU_PLL2_CFG_INPUT_DIV + 1;
return (cgu_get_pll0_fosc() + (div >> 1)) / div;
}
-unsigned int
-cgu_get_io_region_clock(void)
+unsigned int cgu_get_io_region_clock(void)
{
- register unsigned int ret = cgu_get_pll0_fosc();
- switch(ifxmips_r32(IFXMIPS_CGU_PLL2_CFG) & CGU_SYS_DDR_SEL)
- {
+ unsigned int ret = cgu_get_pll0_fosc();
+ switch (ifxmips_r32(IFXMIPS_CGU_PLL2_CFG) & CGU_SYS_DDR_SEL) {
default:
case 0:
return (ret + 1) / 2;
@@ -193,36 +185,36 @@ cgu_get_io_region_clock(void)
}
}
-unsigned int
-cgu_get_fpi_bus_clock(int fpi)
+unsigned int cgu_get_fpi_bus_clock(int fpi)
{
- register unsigned int ret = cgu_get_io_region_clock();
- if((fpi == 2) && (ifxmips_r32(IFXMIPS_CGU_SYS) & CGU_SYS_FPI_SEL))
+ unsigned int ret = cgu_get_io_region_clock();
+ if ((fpi == 2) && (ifxmips_r32(IFXMIPS_CGU_SYS) & CGU_SYS_FPI_SEL))
ret >>= 1;
return ret;
}
void cgu_setup_pci_clk(int external_clock)
{
- //set clock to 33Mhz
- ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) & ~0xf00000, IFXMIPS_CGU_IFCCR);
- ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) | 0x800000, IFXMIPS_CGU_IFCCR);
- if(external_clock)
- {
- ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) & ~ (1 << 16), IFXMIPS_CGU_IFCCR);
+ /* set clock to 33Mhz */
+ ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) & ~0xf00000,
+ IFXMIPS_CGU_IFCCR);
+ ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) | 0x800000,
+ IFXMIPS_CGU_IFCCR);
+ if (external_clock) {
+ ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) & ~(1 << 16),
+ IFXMIPS_CGU_IFCCR);
ifxmips_w32((1 << 30), IFXMIPS_CGU_PCICR);
} else {
- ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) | (1 << 16), IFXMIPS_CGU_IFCCR);
+ ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) | (1 << 16),
+ IFXMIPS_CGU_IFCCR);
ifxmips_w32((1 << 31) | (1 << 30), IFXMIPS_CGU_PCICR);
}
}
-unsigned int
-ifxmips_get_cpu_hz(void)
+unsigned int ifxmips_get_cpu_hz(void)
{
unsigned int ddr_clock = DDR_HZ;
- switch(ifxmips_r32(IFXMIPS_CGU_SYS) & 0xc)
- {
+ switch (ifxmips_r32(IFXMIPS_CGU_SYS) & 0xc) {
case 0:
return CLOCK_333M;
case 4:
@@ -232,11 +224,10 @@ ifxmips_get_cpu_hz(void)
}
EXPORT_SYMBOL(ifxmips_get_cpu_hz);
-unsigned int
-ifxmips_get_fpi_hz(void)
+unsigned int ifxmips_get_fpi_hz(void)
{
unsigned int ddr_clock = DDR_HZ;
- if(ifxmips_r32(IFXMIPS_CGU_SYS) & 0x40)
+ if (ifxmips_r32(IFXMIPS_CGU_SYS) & 0x40)
return ddr_clock >> 1;
return ddr_clock;
}
diff --git a/target/linux/ifxmips/files/arch/mips/ifxmips/dma-core.c b/target/linux/ifxmips/files/arch/mips/ifxmips/dma-core.c
index b31c62280..b334200ca 100644
--- a/target/linux/ifxmips/files/arch/mips/ifxmips/dma-core.c
+++ b/target/linux/ifxmips/files/arch/mips/ifxmips/dma-core.c
@@ -37,13 +37,13 @@ extern void ifxmips_enable_irq(unsigned int irq_nr);
extern void ifxmips_disable_irq(unsigned int irq_nr);
u64 *g_desc_list;
-_dma_device_info dma_devs[MAX_DMA_DEVICE_NUM];
-_dma_channel_info dma_chan[MAX_DMA_CHANNEL_NUM];
+struct dma_device_info dma_devs[MAX_DMA_DEVICE_NUM];
+struct dma_channel_info dma_chan[MAX_DMA_CHANNEL_NUM];
static const char *global_device_name[MAX_DMA_DEVICE_NUM] =
{ "PPE", "DEU", "SPI", "SDIO", "MCTRL0", "MCTRL1" };
-_dma_chan_map default_dma_map[MAX_DMA_CHANNEL_NUM] = {
+struct dma_chan_map default_dma_map[MAX_DMA_CHANNEL_NUM] = {
{"PPE", IFXMIPS_DMA_RX, 0, IFXMIPS_DMA_CH0_INT, 0},
{"PPE", IFXMIPS_DMA_TX, 0, IFXMIPS_DMA_CH1_INT, 0},
{"PPE", IFXMIPS_DMA_RX, 1, IFXMIPS_DMA_CH2_INT, 1},
@@ -66,7 +66,7 @@ _dma_chan_map default_dma_map[MAX_DMA_CHANNEL_NUM] = {
{"MCTRL1", IFXMIPS_DMA_TX, 1, IFXMIPS_DMA_CH19_INT, 1}
};
-_dma_chan_map *chan_map = default_dma_map;
+struct dma_chan_map *chan_map = default_dma_map;
volatile u32 g_ifxmips_dma_int_status;
volatile int g_ifxmips_dma_in_process; /* 0=not in process, 1=in process */
@@ -87,7 +87,7 @@ void common_buffer_free(u8 *dataptr, void *opt)
kfree(dataptr);
}
-void enable_ch_irq(_dma_channel_info *pCh)
+void enable_ch_irq(struct dma_channel_info *pCh)
{
int chan_no = (int)(pCh - dma_chan);
unsigned long flag;
@@ -100,7 +100,7 @@ void enable_ch_irq(_dma_channel_info *pCh)
ifxmips_enable_irq(pCh->irq);
}
-void disable_ch_irq(_dma_channel_info *pCh)
+void disable_ch_irq(struct dma_channel_info *pCh)
{
unsigned long flag;
int chan_no = (int) (pCh - dma_chan);
@@ -114,7 +114,7 @@ void disable_ch_irq(_dma_channel_info *pCh)
ifxmips_mask_and_ack_irq(pCh->irq);
}
-void open_chan(_dma_channel_info *pCh)
+void open_chan(struct dma_channel_info *pCh)
{
unsigned long flag;
int chan_no = (int)(pCh - dma_chan);
@@ -127,7 +127,7 @@ void open_chan(_dma_channel_info *pCh)
local_irq_restore(flag);
}
-void close_chan(_dma_channel_info *pCh)
+void close_chan(struct dma_channel_info *pCh)
{
unsigned long flag;
int chan_no = (int) (pCh - dma_chan);
@@ -139,7 +139,7 @@ void close_chan(_dma_channel_info *pCh)
local_irq_restore(flag);
}
-void reset_chan(_dma_channel_info *pCh)
+void reset_chan(struct dma_channel_info *pCh)
{
int chan_no = (int) (pCh - dma_chan);
@@ -149,8 +149,8 @@ void reset_chan(_dma_channel_info *pCh)
void rx_chan_intr_handler(int chan_no)
{
- _dma_device_info *pDev = (_dma_device_info *)dma_chan[chan_no].dma_dev;
- _dma_channel_info *pCh = &dma_chan[chan_no];
+ struct dma_device_info *pDev = (struct dma_device_info *)dma_chan[chan_no].dma_dev;
+ struct dma_channel_info *pCh = &dma_chan[chan_no];
struct rx_desc *rx_desc_p;
int tmp;
unsigned long flag;
@@ -179,8 +179,8 @@ void rx_chan_intr_handler(int chan_no)
inline void tx_chan_intr_handler(int chan_no)
{
- _dma_device_info *pDev = (_dma_device_info *)dma_chan[chan_no].dma_dev;
- _dma_channel_info *pCh = &dma_chan[chan_no];
+ struct dma_device_info *pDev = (struct dma_device_info *)dma_chan[chan_no].dma_dev;
+ struct dma_channel_info *pCh = &dma_chan[chan_no];
int tmp;
unsigned long flag;
@@ -242,11 +242,11 @@ void do_dma_tasklet(unsigned long unused)
irqreturn_t dma_interrupt(int irq, void *dev_id)
{
- _dma_channel_info *pCh;
+ struct dma_channel_info *pCh;
int chan_no = 0;
int tmp;
- pCh = (_dma_channel_info *)dev_id;
+ pCh = (struct dma_channel_info *)dev_id;
chan_no = (int)(pCh - dma_chan);
if (chan_no < 0 || chan_no > 19)
BUG();
@@ -265,7 +265,7 @@ irqreturn_t dma_interrupt(int irq, void *dev_id)
return IRQ_HANDLED;
}
-_dma_device_info *dma_device_reserve(char *dev_name)
+struct dma_device_info *dma_device_reserve(char *dev_name)
{
int i;
@@ -282,21 +282,21 @@ _dma_device_info *dma_device_reserve(char *dev_name)
}
EXPORT_SYMBOL(dma_device_reserve);
-void dma_device_release(_dma_device_info *dev)
+void dma_device_release(struct dma_device_info *dev)
{
dev->reserved = 0;
}
EXPORT_SYMBOL(dma_device_release);
-void dma_device_register(_dma_device_info *dev)
+void dma_device_register(struct dma_device_info *dev)
{
int i, j;
int chan_no = 0;
u8 *buffer;
int byte_offset;
unsigned long flag;
- _dma_device_info *pDev;
- _dma_channel_info *pCh;
+ struct dma_device_info *pDev;
+ struct dma_channel_info *pCh;
struct rx_desc *rx_desc_p;
struct tx_desc *tx_desc_p;
@@ -331,7 +331,7 @@ void dma_device_register(_dma_device_info *dev)
for (j = 0; j < pCh->desc_len; j++) {
rx_desc_p = (struct rx_desc *)pCh->desc_base + j;
- pDev = (_dma_device_info *)(pCh->dma_dev);
+ pDev = (struct dma_device_info *)(pCh->dma_dev);
buffer = pDev->buffer_alloc(pCh->packet_size, &byte_offset, (void *)&(pCh->opt[j]));
if (!buffer)
break;
@@ -364,11 +364,11 @@ void dma_device_register(_dma_device_info *dev)
}
EXPORT_SYMBOL(dma_device_register);
-void dma_device_unregister(_dma_device_info *dev)
+void dma_device_unregister(struct dma_device_info *dev)
{
int i, j;
int chan_no;
- _dma_channel_info *pCh;
+ struct dma_channel_info *pCh;
struct rx_desc *rx_desc_p;
struct tx_desc *tx_desc_p;
unsigned long flag;
@@ -442,7 +442,7 @@ int dma_device_read(struct dma_device_info *dma_dev, u8 **dataptr, void **opt)
int len;
int byte_offset = 0;
void *p = NULL;
- _dma_channel_info *pCh = dma_dev->rx_chan[dma_dev->current_rx_chan];
+ struct dma_channel_info *pCh = dma_dev->rx_chan[dma_dev->current_rx_chan];
struct rx_desc *rx_desc_p;
/* get the rx data first */
@@ -488,13 +488,13 @@ int dma_device_write(struct dma_device_info *dma_dev, u8 *dataptr, int len, void
{
unsigned long flag;
u32 tmp, byte_offset;
- _dma_channel_info *pCh;
+ struct dma_channel_info *pCh;
int chan_no;
struct tx_desc *tx_desc_p;
local_irq_save(flag);
pCh = dma_dev->tx_chan[dma_dev->current_tx_chan];
- chan_no = (int)(pCh - (_dma_channel_info *) dma_chan);
+ chan_no = (int)(pCh - (struct dma_channel_info *) dma_chan);
tx_desc_p = (struct tx_desc *)pCh->desc_base + pCh->prev_desc;
while (tx_desc_p->status.field.OWN == CPU_OWN && tx_desc_p->status.field.C) {
@@ -546,13 +546,13 @@ int dma_device_write(struct dma_device_info *dma_dev, u8 *dataptr, int len, void
}
EXPORT_SYMBOL(dma_device_write);
-int map_dma_chan(_dma_chan_map *map)
+int map_dma_chan(struct dma_chan_map *map)
{
int i, j;
int result;
for (i = 0; i < MAX_DMA_DEVICE_NUM; i++)
- strcpy(dma_devs[i].device_name, global_device_name[i]);
+ dma_devs[i].device_name = &global_device_name[i];
for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) {
dma_chan[i].irq = map[i].irq;
diff --git a/target/linux/ifxmips/files/arch/mips/ifxmips/gpio.c b/target/linux/ifxmips/files/arch/mips/ifxmips/gpio.c
index bd34b9117..2100ebb4c 100644
--- a/target/linux/ifxmips/files/arch/mips/ifxmips/gpio.c
+++ b/target/linux/ifxmips/files/arch/mips/ifxmips/gpio.c
@@ -51,7 +51,7 @@ static struct timer_list rst_button_timer;
extern struct sock *uevent_sock;
extern u64 uevent_next_seqnum(void);
static unsigned long seen;
-static int pressed = 0;
+static int pressed;
struct event_t {
struct work_struct wq;
@@ -61,26 +61,24 @@ struct event_t {
#endif
#define IFXMIPS_GPIO_SANITY {if (port > MAX_PORTS || pin > PINS_PER_PORT) return -EINVAL; }
-int
-ifxmips_port_reserve_pin(unsigned int port, unsigned int pin)
+
+int ifxmips_port_reserve_pin(unsigned int port, unsigned int pin)
{
IFXMIPS_GPIO_SANITY;
- printk("%s : call to obseleted function\n", __func__);
+ printk(KERN_INFO "%s : call to obseleted function\n", __func__);
return 0;
}
EXPORT_SYMBOL(ifxmips_port_reserve_pin);
-int
-ifxmips_port_free_pin(unsigned int port, unsigned int pin)
+int ifxmips_port_free_pin(unsigned int port, unsigned int pin)
{
IFXMIPS_GPIO_SANITY;
- printk("%s : call to obseleted function\n", __func__);
+ printk(KERN_INFO "%s : call to obseleted function\n", __func__);
return 0;
}
EXPORT_SYMBOL(ifxmips_port_free_pin);
-int
-ifxmips_port_set_open_drain(unsigned int port, unsigned int pin)
+int ifxmips_port_set_open_drain(unsigned int port, unsigned int pin)
{
IFXMIPS_GPIO_SANITY;
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_OD + (port * 0xC)) | (1 << pin),
@@ -89,8 +87,7 @@ ifxmips_port_set_open_drain(unsigned int port, unsigned int pin)
}
EXPORT_SYMBOL(ifxmips_port_set_open_drain);
-int
-ifxmips_port_clear_open_drain(unsigned int port, unsigned int pin)
+int ifxmips_port_clear_open_drain(unsigned int port, unsigned int pin)
{
IFXMIPS_GPIO_SANITY;
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_OD + (port * 0xC)) & ~(1 << pin),
@@ -99,110 +96,99 @@ ifxmips_port_clear_open_drain(unsigned int port, unsigned int pin)
}
EXPORT_SYMBOL(ifxmips_port_clear_open_drain);
-int
-ifxmips_port_set_pudsel(unsigned int port, unsigned int pin)
+int ifxmips_port_set_pudsel(unsigned int port, unsigned int pin)
{
- IFXMIPS_GPIO_SANITY;
+ IFXMIPS_GPIO_SANITY;
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_PUDSEL + (port * 0xC)) | (1 << pin),
IFXMIPS_GPIO_P0_PUDSEL + (port * 0xC));
return 0;
}
EXPORT_SYMBOL(ifxmips_port_set_pudsel);
-int
-ifxmips_port_clear_pudsel (unsigned int port, unsigned int pin)
+int ifxmips_port_clear_pudsel(unsigned int port, unsigned int pin)
{
- IFXMIPS_GPIO_SANITY;
+ IFXMIPS_GPIO_SANITY;
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_PUDSEL + (port * 0xC)) & ~(1 << pin),
IFXMIPS_GPIO_P0_PUDSEL + (port * 0xC));
return 0;
}
EXPORT_SYMBOL(ifxmips_port_clear_pudsel);
-int
-ifxmips_port_set_puden(unsigned int port, unsigned int pin)
+int ifxmips_port_set_puden(unsigned int port, unsigned int pin)
{
- IFXMIPS_GPIO_SANITY;
+ IFXMIPS_GPIO_SANITY;
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_PUDEN + (port * 0xC)) | (1 << pin),
IFXMIPS_GPIO_P0_PUDEN + (port * 0xC));
return 0;
}
EXPORT_SYMBOL(ifxmips_port_set_puden);
-int
-ifxmips_port_clear_puden(unsigned int port, unsigned int pin)
+int ifxmips_port_clear_puden(unsigned int port, unsigned int pin)
{
- IFXMIPS_GPIO_SANITY;
+ IFXMIPS_GPIO_SANITY;
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_PUDEN + (port * 0xC)) & ~(1 << pin),
IFXMIPS_GPIO_P0_PUDEN + (port * 0xC));
return 0;
}
EXPORT_SYMBOL(ifxmips_port_clear_puden);
-int
-ifxmips_port_set_stoff(unsigned int port, unsigned int pin)
+int ifxmips_port_set_stoff(unsigned int port, unsigned int pin)
{
- IFXMIPS_GPIO_SANITY;
+ IFXMIPS_GPIO_SANITY;
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_STOFF + (port * 0xC)) | (1 << pin),
IFXMIPS_GPIO_P0_STOFF + (port * 0xC));
return 0;
}
EXPORT_SYMBOL(ifxmips_port_set_stoff);
-int
-ifxmips_port_clear_stoff(unsigned int port, unsigned int pin)
+int ifxmips_port_clear_stoff(unsigned int port, unsigned int pin)
{
- IFXMIPS_GPIO_SANITY;
+ IFXMIPS_GPIO_SANITY;
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_STOFF + (port * 0xC)) & ~(1 << pin),
IFXMIPS_GPIO_P0_STOFF + (port * 0xC));
return 0;
}
EXPORT_SYMBOL(ifxmips_port_clear_stoff);
-int
-ifxmips_port_set_dir_out(unsigned int port, unsigned int pin)
+int ifxmips_port_set_dir_out(unsigned int port, unsigned int pin)
{
- IFXMIPS_GPIO_SANITY;
+ IFXMIPS_GPIO_SANITY;
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_DIR + (port * 0xC)) | (1 << pin),
IFXMIPS_GPIO_P0_DIR + (port * 0xC));
return 0;
}
EXPORT_SYMBOL(ifxmips_port_set_dir_out);
-int
-ifxmips_port_set_dir_in(unsigned int port, unsigned int pin)
+int ifxmips_port_set_dir_in(unsigned int port, unsigned int pin)
{
- IFXMIPS_GPIO_SANITY;
+ IFXMIPS_GPIO_SANITY;
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_DIR + (port * 0xC)) & ~(1 << pin),
IFXMIPS_GPIO_P0_DIR + (port * 0xC));
return 0;
}
EXPORT_SYMBOL(ifxmips_port_set_dir_in);
-int
-ifxmips_port_set_output(unsigned int port, unsigned int pin)
+int ifxmips_port_set_output(unsigned int port, unsigned int pin)
{
- IFXMIPS_GPIO_SANITY;
+ IFXMIPS_GPIO_SANITY;
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_OUT + (port * 0xC)) | (1 << pin),
IFXMIPS_GPIO_P0_OUT + (port * 0xC));
return 0;
}
EXPORT_SYMBOL(ifxmips_port_set_output);
-int
-ifxmips_port_clear_output(unsigned int port, unsigned int pin)
+int ifxmips_port_clear_output(unsigned int port, unsigned int pin)
{
- IFXMIPS_GPIO_SANITY;
+ IFXMIPS_GPIO_SANITY;
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_OUT + (port * 0xC)) & ~(1 << pin),
IFXMIPS_GPIO_P0_OUT + (port * 0xC));
return 0;
}
EXPORT_SYMBOL(ifxmips_port_clear_output);
-int
-ifxmips_port_get_input(unsigned int port, unsigned int pin)
+int ifxmips_port_get_input(unsigned int port, unsigned int pin)
{
- IFXMIPS_GPIO_SANITY;
+ IFXMIPS_GPIO_SANITY;
if (ifxmips_r32(IFXMIPS_GPIO_P0_IN + (port * 0xC)) & (1 << pin))
return 0;
else
@@ -210,40 +196,36 @@ ifxmips_port_get_input(unsigned int port, unsigned int pin)
}
EXPORT_SYMBOL(ifxmips_port_get_input);
-int
-ifxmips_port_set_altsel0(unsigned int port, unsigned int pin)
+int ifxmips_port_set_altsel0(unsigned int port, unsigned int pin)
{
- IFXMIPS_GPIO_SANITY;
+ IFXMIPS_GPIO_SANITY;
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0xC)) | (1 << pin),
IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0xC));
return 0;
}
EXPORT_SYMBOL(ifxmips_port_set_altsel0);
-int
-ifxmips_port_clear_altsel0(unsigned int port, unsigned int pin)
+int ifxmips_port_clear_altsel0(unsigned int port, unsigned int pin)
{
- IFXMIPS_GPIO_SANITY;
+ IFXMIPS_GPIO_SANITY;
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0xC)) & ~(1 << pin),
IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0xC));
return 0;
}
EXPORT_SYMBOL(ifxmips_port_clear_altsel0);
-int
-ifxmips_port_set_altsel1(unsigned int port, unsigned int pin)
+int ifxmips_port_set_altsel1(unsigned int port, unsigned int pin)
{
- IFXMIPS_GPIO_SANITY;
+ IFXMIPS_GPIO_SANITY;
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0xC)) | (1 << pin),
IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0xC));
return 0;
}
EXPORT_SYMBOL(ifxmips_port_set_altsel1);
-int
-ifxmips_port_clear_altsel1(unsigned int port, unsigned int pin)
+int ifxmips_port_clear_altsel1(unsigned int port, unsigned int pin)
{
- IFXMIPS_GPIO_SANITY;
+ IFXMIPS_GPIO_SANITY;
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0xC)) & ~(1 << pin),
IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0xC));
return 0;
@@ -251,16 +233,14 @@ ifxmips_port_clear_altsel1(unsigned int port, unsigned int pin)
EXPORT_SYMBOL(ifxmips_port_clear_altsel1);
#ifdef CONFIG_IFXMIPS_GPIO_RST_BTN
-static inline void
-add_msg(struct sk_buff *skb, char *msg)
+static inline void add_msg(struct sk_buff *skb, char *msg)
{
char *scratch;
scratch = skb_put(skb, strlen(msg) + 1);
sprintf(scratch, msg);
}
-static void
-hotplug_button(struct work_struct *wq)
+static void hotplug_button(struct work_struct *wq)
{
struct sk_buff *skb;
struct event_t *event;
@@ -269,17 +249,17 @@ hotplug_button(struct work_struct *wq)
char buf[128];
event = container_of(wq, struct event_t, wq);
- if(!uevent_sock)
+ if (!uevent_sock)
goto done;
s = event->set ? "pressed" : "released";
len = strlen(s) + 2;
skb = alloc_skb(len + 2048, GFP_KERNEL);
- if(!skb)
+ if (!skb)
goto done;
scratch = skb_put(skb, len);
- sprintf(scratch, "%s@",s);
+ sprintf(scratch, "%s@", s);
add_msg(skb, "HOME=/");
add_msg(skb, "PATH=/sbin:/bin:/usr/sbin:/usr/bin");
add_msg(skb, "SUBSYSTEM=button");
@@ -296,24 +276,21 @@ done:
kfree(event);
}
-static void
-reset_button_poll(unsigned long unused)
+static void reset_button_poll(unsigned long unused)
{
struct event_t *event;
rst_button_timer.expires = jiffies + (HZ / 4);
add_timer(&rst_button_timer);
- if (pressed != ifxmips_port_get_input(rst_port, rst_pin))
- {
- if(pressed)
+ if (pressed != ifxmips_port_get_input(rst_port, rst_pin)) {
+ if (pressed)
pressed = 0;
else
pressed = 1;
- event = (struct event_t *) kzalloc(sizeof(struct event_t), GFP_ATOMIC);
- if (!event)
- {
- printk("Could not alloc hotplug event\n");
+ event = kzalloc(sizeof(struct event_t), GFP_ATOMIC);
+ if (!event) {
+ printk(KERN_INFO "Could not alloc hotplug event\n");
return;
}
event->set = pressed;
@@ -325,8 +302,7 @@ reset_button_poll(unsigned long unused)
}
#endif
-static int
-ifxmips_gpio_probe(struct platform_device *dev)
+static int ifxmips_gpio_probe(struct platform_device *dev)
{
int retval = 0;
@@ -346,8 +322,7 @@ ifxmips_gpio_probe(struct platform_device *dev)
return retval;
}
-static int
-ifxmips_gpio_remove(struct platform_device *pdev)
+static int ifxmips_gpio_remove(struct platform_device *pdev)
{
#ifdef CONFIG_IFXMIPS_GPIO_RST_BTN
del_timer_sync(&rst_button_timer);
@@ -355,8 +330,7 @@ ifxmips_gpio_remove(struct platform_device *pdev)
return 0;
}
-static struct
-platform_driver ifxmips_gpio_driver = {
+static struct platform_driver ifxmips_gpio_driver = {
.probe = ifxmips_gpio_probe,
.remove = ifxmips_gpio_remove,
.driver = {
@@ -365,8 +339,7 @@ platform_driver ifxmips_gpio_driver = {
},
};
-int __init
-ifxmips_gpio_init(void)
+int __init ifxmips_gpio_init(void)
{
int ret = platform_driver_register(&ifxmips_gpio_driver);
if (ret)
@@ -374,8 +347,7 @@ ifxmips_gpio_init(void)
return ret;
}
-void __exit
-ifxmips_gpio_exit(void)
+void __exit ifxmips_gpio_exit(void)
{
platform_driver_unregister(&ifxmips_gpio_driver);
}
diff --git a/target/linux/ifxmips/files/arch/mips/ifxmips/pmu.c b/target/linux/ifxmips/files/arch/mips/ifxmips/pmu.c
index 2831182ab..eac50b62d 100644
--- a/target/linux/ifxmips/files/arch/mips/ifxmips/pmu.c
+++ b/target/linux/ifxmips/files/arch/mips/ifxmips/pmu.c
@@ -13,7 +13,7 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
*
- * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
+ * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*/
#include <linux/kernel.h>
@@ -21,21 +21,21 @@
#include <linux/version.h>
#include <asm/ifxmips/ifxmips.h>
-void
-ifxmips_pmu_enable(unsigned int module)
+void ifxmips_pmu_enable(unsigned int module)
{
int err = 1000000;
- ifxmips_w32(ifxmips_r32(IFXMIPS_PMU_PWDCR) & ~module, IFXMIPS_PMU_PWDCR);
- while (--err && (ifxmips_r32(IFXMIPS_PMU_PWDSR) & module)) {}
+ ifxmips_w32(ifxmips_r32(IFXMIPS_PMU_PWDCR) & ~module,
+ IFXMIPS_PMU_PWDCR);
+ while (--err && (ifxmips_r32(IFXMIPS_PMU_PWDSR) & module))
+ ;
if (!err)
panic("activating PMU module failed!");
}
EXPORT_SYMBOL(ifxmips_pmu_enable);
-void
-ifxmips_pmu_disable(unsigned int module)
+void ifxmips_pmu_disable(unsigned int module)
{
ifxmips_w32(ifxmips_r32(IFXMIPS_PMU_PWDCR) | module, IFXMIPS_PMU_PWDCR);
}
diff --git a/target/linux/ifxmips/files/arch/mips/ifxmips/prom.c b/target/linux/ifxmips/files/arch/mips/ifxmips/prom.c
index ef8750b6f..a0fc68ebd 100644
--- a/target/linux/ifxmips/files/arch/mips/ifxmips/prom.c
+++ b/target/linux/ifxmips/files/arch/mips/ifxmips/prom.c
@@ -26,11 +26,11 @@
static char buf[1024]; /* for prom_printf() */
/* for voice cpu (MIPS24K) */
-unsigned int *prom_cp1_base = NULL;
-unsigned int prom_cp1_size = 0;
+unsigned int *prom_cp1_base;
+unsigned int prom_cp1_size;
/* for Multithreading (APRP) on MIPS34K */
-unsigned long physical_memsize = 0L;
+unsigned long physical_memsize;
#ifdef IFXMIPS_PROM_ASC0
#define IFXMIPS_ASC_DIFF 0
@@ -57,7 +57,8 @@ void prom_putchar(char c)
unsigned long flags;
local_irq_save(flags);
- while((asc_r32(IFXMIPS_ASC_FSTAT) & ASCFSTAT_TXFFLMASK) >> ASCFSTAT_TXFFLOFF);
+ while ((asc_r32(IFXMIPS_ASC_FSTAT) & ASCFSTAT_TXFFLMASK) >> ASCFSTAT_TXFFLOFF)
+ ;
if (c == '\n')
asc_w32('\r', IFXMIPS_ASC_TBUF);
@@ -105,10 +106,9 @@ void __init prom_init(void)
mips_machtype = MACH_INFINEON_IFXMIPS;
if (argc) {
- argv = (char**)KSEG1ADDR((unsigned long)argv);
+ argv = (char **)KSEG1ADDR((unsigned long)argv);
arcs_cmdline[0] = '\0';
- for (i = 1; i < argc; i++)
- {
+ for (i = 1; i < argc; i++) {
char *a = (char *)KSEG1ADDR(argv[i]);
if (!argv[i])
continue;
@@ -129,25 +129,22 @@ void __init prom_init(void)
strcpy(&(arcs_cmdline[0]),
"console=ttyS0,115200 rootfstype=squashfs,jffs2 init=/etc/preinit");
}
- envp = (char**)KSEG1ADDR((unsigned long)envp);
- while(*envp)
- {
+ envp = (char **)KSEG1ADDR((unsigned long)envp);
+ while (*envp) {
char *e = (char *)KSEG1ADDR(*envp);
- if (!strncmp(e, "memsize=", 8))
- {
+ if (!strncmp(e, "memsize=", 8)) {
e += 8;
memsize = simple_strtoul(e, NULL, 10);
}
envp++;
}
-
memsize *= 1024 * 1024;
/* only on Twinpass/Danube a second CPU is used for Voice */
if ((cpu_data[0].cputype == CPU_24K) && (prom_cp1_size)) {
memsize -= prom_cp1_size;
- prom_cp1_base = (unsigned int*)KSEG1ADDR(memsize);
+ prom_cp1_base = (unsigned int *)KSEG1ADDR(memsize);
prom_printf("Using %dMB Ram and reserving %dMB for cp1\n",
memsize>>20, prom_cp1_size>>20);
diff --git a/target/linux/ifxmips/files/arch/mips/ifxmips/reset.c b/target/linux/ifxmips/files/arch/mips/ifxmips/reset.c
index c85d75381..531294885 100644
--- a/target/linux/ifxmips/files/arch/mips/ifxmips/reset.c
+++ b/target/linux/ifxmips/files/arch/mips/ifxmips/reset.c
@@ -13,14 +13,14 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
*
- * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
+ * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*/
#include <linux/kernel.h>
#include <linux/pm.h>
-#include <asm/reboot.h>
+#include <linux/reboot.h>
+#include <linux/io.h>
#include <asm/system.h>
-#include <asm/io.h>
#include <asm/ifxmips/ifxmips.h>
static void ifxmips_machine_restart(char *command)
@@ -28,22 +28,26 @@ static void ifxmips_machine_restart(char *command)
printk(KERN_NOTICE "System restart\n");
local_irq_disable();
- ifxmips_w32(ifxmips_r32(IFXMIPS_RCU_RST) | IFXMIPS_RCU_RST_ALL, IFXMIPS_RCU_RST);
- for(;;);
+ ifxmips_w32(ifxmips_r32(IFXMIPS_RCU_RST) | IFXMIPS_RCU_RST_ALL,
+ IFXMIPS_RCU_RST);
+ for (;;)
+ ;
}
static void ifxmips_machine_halt(void)
{
printk(KERN_NOTICE "System halted.\n");
local_irq_disable();
- for(;;);
+ for (;;)
+ ;
}
static void ifxmips_machine_power_off(void)
{
- printk (KERN_NOTICE "Please turn off the power now.\n");
+ printk(KERN_NOTICE "Please turn off the power now.\n");
local_irq_disable();
- for(;;);
+ for (;;)
+ ;
}
void ifxmips_reboot_setup(void)
diff --git a/target/linux/ifxmips/files/arch/mips/ifxmips/setup.c b/target/linux/ifxmips/files/arch/mips/ifxmips/setup.c
index 1cfac14a8..f36bb0572 100644
--- a/target/linux/ifxmips/files/arch/mips/ifxmips/setup.c
+++ b/target/linux/ifxmips/files/arch/mips/ifxmips/setup.c
@@ -19,11 +19,13 @@
#include <linux/init.h>
-#include <asm/time.h>
-#include <asm/traps.h>
+#include <linux/time.h>
#include <linux/cpu.h>
+
+#include <asm/traps.h>
#include <asm/irq.h>
#include <asm/bootinfo.h>
+
#include <asm/ifxmips/ifxmips.h>
#include <asm/ifxmips/ifxmips_irq.h>
#include <asm/ifxmips/ifxmips_pmu.h>
diff --git a/target/linux/ifxmips/files/arch/mips/ifxmips/timer.c b/target/linux/ifxmips/files/arch/mips/ifxmips/timer.c
index 248ced21e..8d8d431a8 100644
--- a/target/linux/ifxmips/files/arch/mips/ifxmips/timer.c
+++ b/target/linux/ifxmips/files/arch/mips/ifxmips/timer.c
@@ -5,130 +5,135 @@
#include <linux/fs.h>
#include <linux/miscdevice.h>
#include <linux/init.h>
-#include <asm/uaccess.h>
-#include <asm/unistd.h>
-#include <asm/irq.h>
-#include <asm/div64.h>
+#include <linux/uaccess.h>
+#include <linux/unistd.h>
#include <linux/errno.h>
#include <linux/interrupt.h>
+#include <asm/irq.h>
+#include <asm/div64.h>
+
#include <asm/ifxmips/ifxmips.h>
#include <asm/ifxmips/ifxmips_irq.h>
#include <asm/ifxmips/ifxmips_cgu.h>
#include <asm/ifxmips/ifxmips_gptu.h>
#include <asm/ifxmips/ifxmips_pmu.h>
-#define MAX_NUM_OF_32BIT_TIMER_BLOCKS 6
+#define MAX_NUM_OF_32BIT_TIMER_BLOCKS 6
#ifdef TIMER1A
-#define FIRST_TIMER TIMER1A
+#define FIRST_TIMER TIMER1A
#else
-#define FIRST_TIMER 2
+#define FIRST_TIMER 2
#endif
/*
* GPTC divider is set or not.
*/
-#define GPTU_CLC_RMC_IS_SET 0
+#define GPTU_CLC_RMC_IS_SET 0
/*
* Timer Interrupt (IRQ)
*/
-#define TIMER_INTERRUPT INT_NUM_IM3_IRL0 + 22 // Must be adjusted when ICU driver is available
+/* Must be adjusted when ICU driver is available */
+#define TIMER_INTERRUPT (INT_NUM_IM3_IRL0 + 22)
/*
* Bits Operation
*/
-#define GET_BITS(x, msb, lsb) (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
-#define SET_BITS(x, msb, lsb, value) (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb)))
+#define GET_BITS(x, msb, lsb) \
+ (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
+#define SET_BITS(x, msb, lsb, value) \
+ (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | \
+ (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb)))
/*
* GPTU Register Mapping
*/
-#define IFXMIPS_GPTU (KSEG1 + 0x1E100A00)
-#define IFXMIPS_GPTU_CLC ((volatile u32*)(IFXMIPS_GPTU + 0x0000))
-#define IFXMIPS_GPTU_ID ((volatile u32*)(IFXMIPS_GPTU + 0x0008))
-#define IFXMIPS_GPTU_CON(n, X) ((volatile u32*)(IFXMIPS_GPTU + 0x0010 + ((X) * 4) + ((n) - 1) * 0x0020)) // X must be either A or B
-#define IFXMIPS_GPTU_RUN(n, X) ((volatile u32*)(IFXMIPS_GPTU + 0x0018 + ((X) * 4) + ((n) - 1) * 0x0020)) // X must be either A or B
-#define IFXMIPS_GPTU_RELOAD(n, X) ((volatile u32*)(IFXMIPS_GPTU + 0x0020 + ((X) * 4) + ((n) - 1) * 0x0020)) // X must be either A or B
-#define IFXMIPS_GPTU_COUNT(n, X) ((volatile u32*)(IFXMIPS_GPTU + 0x0028 + ((X) * 4) + ((n) - 1) * 0x0020)) // X must be either A or B
-#define IFXMIPS_GPTU_IRNEN ((volatile u32*)(IFXMIPS_GPTU + 0x00F4))
-#define IFXMIPS_GPTU_IRNICR ((volatile u32*)(IFXMIPS_GPTU + 0x00F8))
-#define IFXMIPS_GPTU_IRNCR ((volatile u32*)(IFXMIPS_GPTU + 0x00FC))
+#define IFXMIPS_GPTU (KSEG1 + 0x1E100A00)
+#define IFXMIPS_GPTU_CLC ((volatile u32 *)(IFXMIPS_GPTU + 0x0000))
+#define IFXMIPS_GPTU_ID ((volatile u32 *)(IFXMIPS_GPTU + 0x0008))
+#define IFXMIPS_GPTU_CON(n, X) ((volatile u32 *)(IFXMIPS_GPTU + 0x0010 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */
+#define IFXMIPS_GPTU_RUN(n, X) ((volatile u32 *)(IFXMIPS_GPTU + 0x0018 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */
+#define IFXMIPS_GPTU_RELOAD(n, X) ((volatile u32 *)(IFXMIPS_GPTU + 0x0020 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */
+#define IFXMIPS_GPTU_COUNT(n, X) ((volatile u32 *)(IFXMIPS_GPTU + 0x0028 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */
+#define IFXMIPS_GPTU_IRNEN ((volatile u32 *)(IFXMIPS_GPTU + 0x00F4))
+#define IFXMIPS_GPTU_IRNICR ((volatile u32 *)(IFXMIPS_GPTU + 0x00F8))
+#define IFXMIPS_GPTU_IRNCR ((volatile u32 *)(IFXMIPS_GPTU + 0x00FC))
/*
* Clock Control Register
*/
-#define GPTU_CLC_SMC GET_BITS(*IFXMIPS_GPTU_CLC, 23, 16)
-#define GPTU_CLC_RMC GET_BITS(*IFXMIPS_GPTU_CLC, 15, 8)
-#define GPTU_CLC_FSOE (*IFXMIPS_GPTU_CLC & (1 << 5))
-#define GPTU_CLC_EDIS (*IFXMIPS_GPTU_CLC & (1 << 3))
-#define GPTU_CLC_SPEN (*IFXMIPS_GPTU_CLC & (1 << 2))
-#define GPTU_CLC_DISS (*IFXMIPS_GPTU_CLC & (1 << 1))
-#define GPTU_CLC_DISR (*IFXMIPS_GPTU_CLC & (1 << 0))
-
-#define GPTU_CLC_SMC_SET(value) SET_BITS(0, 23, 16, (value))
-#define GPTU_CLC_RMC_SET(value) SET_BITS(0, 15, 8, (value))
-#define GPTU_CLC_FSOE_SET(value) ((value) ? (1 << 5) : 0)
-#define GPTU_CLC_SBWE_SET(value) ((value) ? (1 << 4) : 0)
-#define GPTU_CLC_EDIS_SET(value) ((value) ? (1 << 3) : 0)
-#define GPTU_CLC_SPEN_SET(value) ((value) ? (1 << 2) : 0)
-#define GPTU_CLC_DISR_SET(value) ((value) ? (1 << 0) : 0)
+#define GPTU_CLC_SMC GET_BITS(*IFXMIPS_GPTU_CLC, 23, 16)
+#define GPTU_CLC_RMC GET_BITS(*IFXMIPS_GPTU_CLC, 15, 8)
+#define GPTU_CLC_FSOE (*IFXMIPS_GPTU_CLC & (1 << 5))
+#define GPTU_CLC_EDIS (*IFXMIPS_GPTU_CLC & (1 << 3))
+#define GPTU_CLC_SPEN (*IFXMIPS_GPTU_CLC & (1 << 2))
+#define GPTU_CLC_DISS (*IFXMIPS_GPTU_CLC & (1 << 1))
+#define GPTU_CLC_DISR (*IFXMIPS_GPTU_CLC & (1 << 0))
+
+#define GPTU_CLC_SMC_SET(value) SET_BITS(0, 23, 16, (value))
+#define GPTU_CLC_RMC_SET(value) SET_BITS(0, 15, 8, (value))
+#define GPTU_CLC_FSOE_SET(value) ((value) ? (1 << 5) : 0)
+#define GPTU_CLC_SBWE_SET(value) ((value) ? (1 << 4) : 0)
+#define GPTU_CLC_EDIS_SET(value) ((value) ? (1 << 3) : 0)
+#define GPTU_CLC_SPEN_SET(value) ((value) ? (1 << 2) : 0)
+#define GPTU_CLC_DISR_SET(value) ((value) ? (1 << 0) : 0)
/*
* ID Register
*/
-#define GPTU_ID_ID GET_BITS(*IFXMIPS_GPTU_ID, 15, 8)
-#define GPTU_ID_CFG GET_BITS(*IFXMIPS_GPTU_ID, 7, 5)
-#define GPTU_ID_REV GET_BITS(*IFXMIPS_GPTU_ID, 4, 0)
+#define GPTU_ID_ID GET_BITS(*IFXMIPS_GPTU_ID, 15, 8)
+#define GPTU_ID_CFG GET_BITS(*IFXMIPS_GPTU_ID, 7, 5)
+#define GPTU_ID_REV GET_BITS(*IFXMIPS_GPTU_ID, 4, 0)
/*
* Control Register of Timer/Counter nX
* n is the index of block (1 based index)
* X is either A or B
*/
-#define GPTU_CON_SRC_EG(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 10))
-#define GPTU_CON_SRC_EXT(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 9))
-#define GPTU_CON_SYNC(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 8))
-#define GPTU_CON_EDGE(n, X) GET_BITS(*IFXMIPS_GPTU_CON(n, X), 7, 6)
-#define GPTU_CON_INV(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 5))
-#define GPTU_CON_EXT(n, X) (*IFXMIPS_GPTU_CON(n, A) & (1 << 4)) // Timer/Counter B does not have this bit
-#define GPTU_CON_STP(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 3))
-#define GPTU_CON_CNT(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 2))
-#define GPTU_CON_DIR(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 1))
-#define GPTU_CON_EN(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 0))
-
-#define GPTU_CON_SRC_EG_SET(value) ((value) ? 0 : (1 << 10))
-#define GPTU_CON_SRC_EXT_SET(value) ((value) ? (1 << 9) : 0)
-#define GPTU_CON_SYNC_SET(value) ((value) ? (1 << 8) : 0)
-#define GPTU_CON_EDGE_SET(value) SET_BITS(0, 7, 6, (value))
-#define GPTU_CON_INV_SET(value) ((value) ? (1 << 5) : 0)
-#define GPTU_CON_EXT_SET(value) ((value) ? (1 << 4) : 0)
-#define GPTU_CON_STP_SET(value) ((value) ? (1 << 3) : 0)
-#define GPTU_CON_CNT_SET(value) ((value) ? (1 << 2) : 0)
-#define GPTU_CON_DIR_SET(value) ((value) ? (1 << 1) : 0)
-
-#define GPTU_RUN_RL_SET(value) ((value) ? (1 << 2) : 0)
-#define GPTU_RUN_CEN_SET(value) ((value) ? (1 << 1) : 0)
-#define GPTU_RUN_SEN_SET(value) ((value) ? (1 << 0) : 0)
-
-#define GPTU_IRNEN_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
-#define GPTU_IRNCR_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
-
-#define TIMER_FLAG_MASK_SIZE(x) (x & 0x0001)
-#define TIMER_FLAG_MASK_TYPE(x) (x & 0x0002)
-#define TIMER_FLAG_MASK_STOP(x) (x & 0x0004)
-#define TIMER_FLAG_MASK_DIR(x) (x & 0x0008)
-#define TIMER_FLAG_NONE_EDGE 0x0000
-#define TIMER_FLAG_MASK_EDGE(x) (x & 0x0030)
-#define TIMER_FLAG_REAL 0x0000
-#define TIMER_FLAG_INVERT 0x0040
-#define TIMER_FLAG_MASK_INVERT(x) (x & 0x0040)
-#define TIMER_FLAG_MASK_TRIGGER(x) (x & 0x0070)
-#define TIMER_FLAG_MASK_SYNC(x) (x & 0x0080)
-#define TIMER_FLAG_CALLBACK_IN_HB 0x0200
-#define TIMER_FLAG_MASK_HANDLE(x) (x & 0x0300)
-#define TIMER_FLAG_MASK_SRC(x) (x & 0x1000)
+#define GPTU_CON_SRC_EG(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 10))
+#define GPTU_CON_SRC_EXT(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 9))
+#define GPTU_CON_SYNC(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 8))
+#define GPTU_CON_EDGE(n, X) GET_BITS(*IFXMIPS_GPTU_CON(n, X), 7, 6)
+#define GPTU_CON_INV(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 5))
+#define GPTU_CON_EXT(n, X) (*IFXMIPS_GPTU_CON(n, A) & (1 << 4)) /* Timer/Counter B does not have this bit */
+#define GPTU_CON_STP(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 3))
+#define GPTU_CON_CNT(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 2))
+#define GPTU_CON_DIR(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 1))
+#define GPTU_CON_EN(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 0))
+
+#define GPTU_CON_SRC_EG_SET(value) ((value) ? 0 : (1 << 10))
+#define GPTU_CON_SRC_EXT_SET(value) ((value) ? (1 << 9) : 0)
+#define GPTU_CON_SYNC_SET(value) ((value) ? (1 << 8) : 0)
+#define GPTU_CON_EDGE_SET(value) SET_BITS(0, 7, 6, (value))
+#define GPTU_CON_INV_SET(value) ((value) ? (1 << 5) : 0)
+#define GPTU_CON_EXT_SET(value) ((value) ? (1 << 4) : 0)
+#define GPTU_CON_STP_SET(value) ((value) ? (1 << 3) : 0)
+#define GPTU_CON_CNT_SET(value) ((value) ? (1 << 2) : 0)
+#define GPTU_CON_DIR_SET(value) ((value) ? (1 << 1) : 0)
+
+#define GPTU_RUN_RL_SET(value) ((value) ? (1 << 2) : 0)
+#define GPTU_RUN_CEN_SET(value) ((value) ? (1 << 1) : 0)
+#define GPTU_RUN_SEN_SET(value) ((value) ? (1 << 0) : 0)
+
+#define GPTU_IRNEN_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
+#define GPTU_IRNCR_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
+
+#define TIMER_FLAG_MASK_SIZE(x) (x & 0x0001)
+#define TIMER_FLAG_MASK_TYPE(x) (x & 0x0002)
+#define TIMER_FLAG_MASK_STOP(x) (x & 0x0004)
+#define TIMER_FLAG_MASK_DIR(x) (x & 0x0008)
+#define TIMER_FLAG_NONE_EDGE 0x0000
+#define TIMER_FLAG_MASK_EDGE(x) (x & 0x0030)
+#define TIMER_FLAG_REAL 0x0000
+#define TIMER_FLAG_INVERT 0x0040
+#define TIMER_FLAG_MASK_INVERT(x) (x & 0x0040)
+#define TIMER_FLAG_MASK_TRIGGER(x) (x & 0x0070)
+#define TIMER_FLAG_MASK_SYNC(x) (x & 0x0080)
+#define TIMER_FLAG_CALLBACK_IN_HB 0x0200
+#define TIMER_FLAG_MASK_HANDLE(x) (x & 0x0300)
+#define TIMER_FLAG_MASK_SRC(x) (x & 0x1000)
struct timer_dev_timer {
unsigned int f_irq_on;
@@ -165,33 +170,31 @@ static struct miscdevice gptu_miscdev = {
static struct timer_dev timer_dev;
-
-static irqreturn_t
-timer_irq_handler(int irq, void *p)
+static irqreturn_t timer_irq_handler(int irq, void *p)
{
unsigned int timer;
unsigned int flag;
- struct timer_dev_timer *dev_timer = (struct timer_dev_timer*) p;
+ struct timer_dev_timer *dev_timer = (struct timer_dev_timer *)p;
timer = irq - TIMER_INTERRUPT;
- if(timer < timer_dev.number_of_timers && dev_timer == &timer_dev.timer[timer])
- {
+ if (timer < timer_dev.number_of_timers
+ && dev_timer == &timer_dev.timer[timer]) {
/* Clear interrupt. */
ifxmips_w32(1 << timer, IFXMIPS_GPTU_IRNCR);
/* Call user hanler or signal. */
flag = dev_timer->flag;
- if (!(timer & 0x01) || TIMER_FLAG_MASK_SIZE (flag) == TIMER_FLAG_16BIT)
- { /* 16-bit timer or timer A of 32-bit timer */
- switch(TIMER_FLAG_MASK_HANDLE (flag))
- {
+ if (!(timer & 0x01)
+ || TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) {
+ /* 16-bit timer or timer A of 32-bit timer */
+ switch (TIMER_FLAG_MASK_HANDLE(flag)) {
case TIMER_FLAG_CALLBACK_IN_IRQ:
case TIMER_FLAG_CALLBACK_IN_HB:
if (dev_timer->arg1)
- (*(timer_callback) dev_timer->arg1) (dev_timer->arg2);
+ (*(timer_callback)dev_timer->arg1)(dev_timer->arg2);
break;
case TIMER_FLAG_SIGNAL:
- send_sig ((int) dev_timer->arg2, (struct task_struct *) dev_timer->arg1, 0);
+ send_sig((int)dev_timer->arg2, (struct task_struct *)dev_timer->arg1, 0);
break;
}
}
@@ -199,45 +202,53 @@ timer_irq_handler(int irq, void *p)
return IRQ_HANDLED;
}
-static inline void
-ifxmips_enable_gptu(void)
+static inline void ifxmips_enable_gptu(void)
{
ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_GPT);
/* Set divider as 1, disable write protection for SPEN, enable module. */
*IFXMIPS_GPTU_CLC =
- GPTU_CLC_SMC_SET(0x00) | GPTU_CLC_RMC_SET(0x01) | GPTU_CLC_FSOE_SET(0) |
- GPTU_CLC_SBWE_SET(1) | GPTU_CLC_EDIS_SET(0) | GPTU_CLC_SPEN_SET(0) | GPTU_CLC_DISR_SET(0);
+ GPTU_CLC_SMC_SET(0x00) |
+ GPTU_CLC_RMC_SET(0x01) |
+ GPTU_CLC_FSOE_SET(0) |
+ GPTU_CLC_SBWE_SET(1) |
+ GPTU_CLC_EDIS_SET(0) |
+ GPTU_CLC_SPEN_SET(0) |
+ GPTU_CLC_DISR_SET(0);
}
-static inline void
-ifxmips_disable_gptu(void)
+static inline void ifxmips_disable_gptu(void)
{
ifxmips_w32(0x00, IFXMIPS_GPTU_IRNEN);
ifxmips_w32(0xfff, IFXMIPS_GPTU_IRNCR);
/* Set divider as 0, enable write protection for SPEN, disable module. */
*IFXMIPS_GPTU_CLC =
- GPTU_CLC_SMC_SET (0x00) | GPTU_CLC_RMC_SET (0x00) | GPTU_CLC_FSOE_SET (0) |
- GPTU_CLC_SBWE_SET (0) | GPTU_CLC_EDIS_SET (0) | GPTU_CLC_SPEN_SET (0) | GPTU_CLC_DISR_SET (1);
+ GPTU_CLC_SMC_SET(0x00) |
+ GPTU_CLC_RMC_SET(0x00) |
+ GPTU_CLC_FSOE_SET(0) |
+ GPTU_CLC_SBWE_SET(0) |
+ GPTU_CLC_EDIS_SET(0) |
+ GPTU_CLC_SPEN_SET(0) |
+ GPTU_CLC_DISR_SET(1);
ifxmips_pmu_disable(IFXMIPS_PMU_PWDCR_GPT);
}
-int
-ifxmips_request_timer(unsigned int timer, unsigned int flag, unsigned long value,
- unsigned long arg1, unsigned long arg2)
+int ifxmips_request_timer(unsigned int timer, unsigned int flag,
+ unsigned long value, unsigned long arg1, unsigned long arg2)
{
int ret = 0;
unsigned int con_reg, irnen_reg;
int n, X;
- if(timer >= FIRST_TIMER + timer_dev.number_of_timers)
+ if (timer >= FIRST_TIMER + timer_dev.number_of_timers)
return -EINVAL;
- printk(KERN_INFO "request_timer(%d, 0x%08X, %lu)...", (u32)timer, (u32)flag, value);
+ printk(KERN_INFO "request_timer(%d, 0x%08X, %lu)...",
+ timer, flag, value);
- if(TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT)
+ if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT)
value &= 0xFFFF;
else
timer &= ~0x01;
@@ -250,16 +261,16 @@ ifxmips_request_timer(unsigned int timer, unsigned int flag, unsigned long value
if (timer < FIRST_TIMER) {
unsigned int mask;
unsigned int shift;
- unsigned int offset = TIMER2A;/* This takes care of TIMER1B which is the only choice for Voice TAPI system */
+ /* This takes care of TIMER1B which is the only choice for Voice TAPI system */
+ unsigned int offset = TIMER2A;
/*
* Pick up a free timer.
*/
- if (TIMER_FLAG_MASK_SIZE (flag) == TIMER_FLAG_16BIT) {
+ if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) {
mask = 1 << offset;
shift = 1;
- }
- else {
+ } else {
mask = 3 << offset;
shift = 2;
}
@@ -274,23 +285,21 @@ ifxmips_request_timer(unsigned int timer, unsigned int flag, unsigned long value
printk("failed![%d]\n", __LINE__);
mutex_unlock(&timer_dev.gptu_mutex);
return -EINVAL;
- }
- else
+ } else
ret = timer;
- }
- else {
+ } else {
register unsigned int mask;
/*
* Check if the requested timer is free.
*/
- mask = (TIMER_FLAG_MASK_SIZE (flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
+ mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
if ((timer_dev.occupation & mask)) {
- printk("failed![%d] mask %#x, timer_dev.occupation %#x\n", __LINE__, mask, timer_dev.occupation);
+ printk("failed![%d] mask %#x, timer_dev.occupation %#x\n",
+ __LINE__, mask, timer_dev.occupation);
mutex_unlock(&timer_dev.gptu_mutex);
return -EBUSY;
- }
- else {
+ } else {
timer_dev.occupation |= mask;
ret = 0;
}
@@ -299,52 +308,52 @@ ifxmips_request_timer(unsigned int timer, unsigned int flag, unsigned long value
/*
* Prepare control register value.
*/
- switch (TIMER_FLAG_MASK_EDGE (flag)) {
+ switch (TIMER_FLAG_MASK_EDGE(flag)) {
default:
case TIMER_FLAG_NONE_EDGE:
- con_reg = GPTU_CON_EDGE_SET (0x00);
+ con_reg = GPTU_CON_EDGE_SET(0x00);
break;
case TIMER_FLAG_RISE_EDGE:
- con_reg = GPTU_CON_EDGE_SET (0x01);
+ con_reg = GPTU_CON_EDGE_SET(0x01);
break;
case TIMER_FLAG_FALL_EDGE:
- con_reg = GPTU_CON_EDGE_SET (0x02);
+ con_reg = GPTU_CON_EDGE_SET(0x02);
break;
case TIMER_FLAG_ANY_EDGE:
- con_reg = GPTU_CON_EDGE_SET (0x03);
+ con_reg = GPTU_CON_EDGE_SET(0x03);
break;
}
- if (TIMER_FLAG_MASK_TYPE (flag) == TIMER_FLAG_TIMER)
+ if (TIMER_FLAG_MASK_TYPE(flag) == TIMER_FLAG_TIMER)
con_reg |=
- TIMER_FLAG_MASK_SRC (flag) ==
- TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET (1) :
- GPTU_CON_SRC_EXT_SET (0);
+ TIMER_FLAG_MASK_SRC(flag) ==
+ TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) :
+ GPTU_CON_SRC_EXT_SET(0);
else
con_reg |=
- TIMER_FLAG_MASK_SRC (flag) ==
- TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET (1) :
- GPTU_CON_SRC_EG_SET (0);
+ TIMER_FLAG_MASK_SRC(flag) ==
+ TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) :
+ GPTU_CON_SRC_EG_SET(0);
con_reg |=
- TIMER_FLAG_MASK_SYNC (flag) ==
- TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET (0) :
- GPTU_CON_SYNC_SET (1);
+ TIMER_FLAG_MASK_SYNC(flag) ==
+ TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) :
+ GPTU_CON_SYNC_SET(1);
con_reg |=
- TIMER_FLAG_MASK_INVERT (flag) ==
- TIMER_FLAG_REAL ? GPTU_CON_INV_SET (0) : GPTU_CON_INV_SET (1);
+ TIMER_FLAG_MASK_INVERT(flag) ==
+ TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1);
con_reg |=
- TIMER_FLAG_MASK_SIZE (flag) ==
- TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET (0) :
- GPTU_CON_EXT_SET (1);
+ TIMER_FLAG_MASK_SIZE(flag) ==
+ TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) :
+ GPTU_CON_EXT_SET(1);
con_reg |=
- TIMER_FLAG_MASK_STOP (flag) ==
- TIMER_FLAG_ONCE ? GPTU_CON_STP_SET (1) : GPTU_CON_STP_SET (0);
+ TIMER_FLAG_MASK_STOP(flag) ==
+ TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0);
con_reg |=
- TIMER_FLAG_MASK_TYPE (flag) ==
- TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET (0) :
- GPTU_CON_CNT_SET (1);
+ TIMER_FLAG_MASK_TYPE(flag) ==
+ TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) :
+ GPTU_CON_CNT_SET(1);
con_reg |=
- TIMER_FLAG_MASK_DIR (flag) ==
- TIMER_FLAG_UP ? GPTU_CON_DIR_SET (1) : GPTU_CON_DIR_SET (0);
+ TIMER_FLAG_MASK_DIR(flag) ==
+ TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0);
/*
* Fill up running data.
@@ -352,36 +361,35 @@ ifxmips_request_timer(unsigned int timer, unsigned int flag, unsigned long value
timer_dev.timer[timer - FIRST_TIMER].flag = flag;
timer_dev.timer[timer - FIRST_TIMER].arg1 = arg1;
timer_dev.timer[timer - FIRST_TIMER].arg2 = arg2;
- if (TIMER_FLAG_MASK_SIZE (flag) != TIMER_FLAG_16BIT)
+ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
timer_dev.timer[timer - FIRST_TIMER + 1].flag = flag;
/*
* Enable GPTU module.
*/
if (!timer_dev.f_gptu_on) {
- ifxmips_enable_gptu ();
+ ifxmips_enable_gptu();
timer_dev.f_gptu_on = 1;
}
/*
* Enable IRQ.
*/
- if (TIMER_FLAG_MASK_HANDLE (flag) != TIMER_FLAG_NO_HANDLE) {
- if (TIMER_FLAG_MASK_HANDLE (flag) == TIMER_FLAG_SIGNAL)
+ if (TIMER_FLAG_MASK_HANDLE(flag) != TIMER_FLAG_NO_HANDLE) {
+ if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL)
timer_dev.timer[timer - FIRST_TIMER].arg1 =
- (unsigned long) find_task_by_vpid ((int) arg1);
+ (unsigned long) find_task_by_vpid((int) arg1);
irnen_reg = 1 << (timer - FIRST_TIMER);
- if (TIMER_FLAG_MASK_HANDLE (flag) == TIMER_FLAG_SIGNAL
- || (TIMER_FLAG_MASK_HANDLE (flag) ==
+ if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL
+ || (TIMER_FLAG_MASK_HANDLE(flag) ==
TIMER_FLAG_CALLBACK_IN_IRQ
&& timer_dev.timer[timer - FIRST_TIMER].arg1)) {
- enable_irq (timer_dev.timer[timer - FIRST_TIMER].irq);
+ enable_irq(timer_dev.timer[timer - FIRST_TIMER].irq);
timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 1;
}
- }
- else
+ } else
irnen_reg = 0;
/*
@@ -389,38 +397,37 @@ ifxmips_request_timer(unsigned int timer, unsigned int flag, unsigned long value
*/
n = timer >> 1;
X = timer & 0x01;
- *IFXMIPS_GPTU_CON (n, X) = con_reg;
- *IFXMIPS_GPTU_RELOAD (n, X) = value;
-// printk("reload value = %d\n", (u32)value);
+ *IFXMIPS_GPTU_CON(n, X) = con_reg;
+ *IFXMIPS_GPTU_RELOAD(n, X) = value;
+ /* printk("reload value = %d\n", (u32)value); */
*IFXMIPS_GPTU_IRNEN |= irnen_reg;
mutex_unlock(&timer_dev.gptu_mutex);
printk("successful!\n");
return ret;
}
+EXPORT_SYMBOL(ifxmips_request_timer);
-int
-ifxmips_free_timer(unsigned int timer)
+int ifxmips_free_timer(unsigned int timer)
{
unsigned int flag;
unsigned int mask;
int n, X;
- if(!timer_dev.f_gptu_on)
+ if (!timer_dev.f_gptu_on)
return -EINVAL;
- if(timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
+ if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
return -EINVAL;
mutex_lock(&timer_dev.gptu_mutex);
flag = timer_dev.timer[timer - FIRST_TIMER].flag;
- if(TIMER_FLAG_MASK_SIZE (flag) != TIMER_FLAG_16BIT)
+ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
timer &= ~0x01;
- mask = (TIMER_FLAG_MASK_SIZE (flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
- if(((timer_dev.occupation & mask) ^ mask))
- {
+ mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
+ if (((timer_dev.occupation & mask) ^ mask)) {
mutex_unlock(&timer_dev.gptu_mutex);
return -EINVAL;
}
@@ -428,20 +435,19 @@ ifxmips_free_timer(unsigned int timer)
n = timer >> 1;
X = timer & 0x01;
- if(GPTU_CON_EN (n, X))
- *IFXMIPS_GPTU_RUN (n, X) = GPTU_RUN_CEN_SET (1);
+ if (GPTU_CON_EN(n, X))
+ *IFXMIPS_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1);
- *IFXMIPS_GPTU_IRNEN &= ~GPTU_IRNEN_TC_SET (n, X, 1);
- *IFXMIPS_GPTU_IRNCR |= GPTU_IRNCR_TC_SET (n, X, 1);
+ *IFXMIPS_GPTU_IRNEN &= ~GPTU_IRNEN_TC_SET(n, X, 1);
+ *IFXMIPS_GPTU_IRNCR |= GPTU_IRNCR_TC_SET(n, X, 1);
- if(timer_dev.timer[timer - FIRST_TIMER].f_irq_on) {
- disable_irq (timer_dev.timer[timer - FIRST_TIMER].irq);
+ if (timer_dev.timer[timer - FIRST_TIMER].f_irq_on) {
+ disable_irq(timer_dev.timer[timer - FIRST_TIMER].irq);
timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 0;
}
timer_dev.occupation &= ~mask;
- if(!timer_dev.occupation && timer_dev.f_gptu_on)
- {
+ if (!timer_dev.occupation && timer_dev.f_gptu_on) {
ifxmips_disable_gptu();
timer_dev.f_gptu_on = 0;
}
@@ -450,30 +456,29 @@ ifxmips_free_timer(unsigned int timer)
return 0;
}
+EXPORT_SYMBOL(ifxmips_free_timer);
-int
-ifxmips_start_timer(unsigned int timer, int is_resume)
+int ifxmips_start_timer(unsigned int timer, int is_resume)
{
unsigned int flag;
unsigned int mask;
int n, X;
- if(!timer_dev.f_gptu_on)
+ if (!timer_dev.f_gptu_on)
return -EINVAL;
- if(timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
+ if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
return -EINVAL;
mutex_lock(&timer_dev.gptu_mutex);
flag = timer_dev.timer[timer - FIRST_TIMER].flag;
- if(TIMER_FLAG_MASK_SIZE (flag) != TIMER_FLAG_16BIT)
+ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
timer &= ~0x01;
- mask = (TIMER_FLAG_MASK_SIZE (flag) ==
+ mask = (TIMER_FLAG_MASK_SIZE(flag) ==
TIMER_FLAG_16BIT ? 1 : 3) << timer;
- if(((timer_dev.occupation & mask) ^ mask))
- {
+ if (((timer_dev.occupation & mask) ^ mask)) {
mutex_unlock(&timer_dev.gptu_mutex);
return -EINVAL;
}
@@ -481,15 +486,15 @@ ifxmips_start_timer(unsigned int timer, int is_resume)
n = timer >> 1;
X = timer & 0x01;
- *IFXMIPS_GPTU_RUN (n, X) = GPTU_RUN_RL_SET (!is_resume) | GPTU_RUN_SEN_SET (1);
+ *IFXMIPS_GPTU_RUN(n, X) = GPTU_RUN_RL_SET(!is_resume) | GPTU_RUN_SEN_SET(1);
mutex_unlock(&timer_dev.gptu_mutex);
return 0;
}
+EXPORT_SYMBOL(ifxmips_start_timer);
-int
-ifxmips_stop_timer(unsigned int timer)
+int ifxmips_stop_timer(unsigned int timer)
{
unsigned int flag;
unsigned int mask;
@@ -505,12 +510,11 @@ ifxmips_stop_timer(unsigned int timer)
mutex_lock(&timer_dev.gptu_mutex);
flag = timer_dev.timer[timer - FIRST_TIMER].flag;
- if(TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
+ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
timer &= ~0x01;
- mask = (TIMER_FLAG_MASK_SIZE (flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
- if(((timer_dev.occupation & mask) ^ mask))
- {
+ mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
+ if (((timer_dev.occupation & mask) ^ mask)) {
mutex_unlock(&timer_dev.gptu_mutex);
return -EINVAL;
}
@@ -518,41 +522,39 @@ ifxmips_stop_timer(unsigned int timer)
n = timer >> 1;
X = timer & 0x01;
- *IFXMIPS_GPTU_RUN (n, X) = GPTU_RUN_CEN_SET (1);
+ *IFXMIPS_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1);
mutex_unlock(&timer_dev.gptu_mutex);
return 0;
}
+EXPORT_SYMBOL(ifxmips_stop_timer);
-int
-ifxmips_reset_counter_flags(u32 timer, u32 flags)
+int ifxmips_reset_counter_flags(u32 timer, u32 flags)
{
unsigned int oflag;
unsigned int mask, con_reg;
int n, X;
- if(!timer_dev.f_gptu_on)
+ if (!timer_dev.f_gptu_on)
return -EINVAL;
- if(timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
+ if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
return -EINVAL;
mutex_lock(&timer_dev.gptu_mutex);
oflag = timer_dev.timer[timer - FIRST_TIMER].flag;
- if(TIMER_FLAG_MASK_SIZE (oflag) != TIMER_FLAG_16BIT)
+ if (TIMER_FLAG_MASK_SIZE(oflag) != TIMER_FLAG_16BIT)
timer &= ~0x01;
- mask = (TIMER_FLAG_MASK_SIZE (oflag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
- if(((timer_dev.occupation & mask) ^ mask))
- {
+ mask = (TIMER_FLAG_MASK_SIZE(oflag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
+ if (((timer_dev.occupation & mask) ^ mask)) {
mutex_unlock(&timer_dev.gptu_mutex);
return -EINVAL;
}
- switch(TIMER_FLAG_MASK_EDGE (flags))
- {
+ switch (TIMER_FLAG_MASK_EDGE(flags)) {
default:
case TIMER_FLAG_NONE_EDGE:
con_reg = GPTU_CON_EDGE_SET(0x00);
@@ -567,19 +569,19 @@ ifxmips_reset_counter_flags(u32 timer, u32 flags)
con_reg = GPTU_CON_EDGE_SET(0x03);
break;
}
- if(TIMER_FLAG_MASK_TYPE (flags) == TIMER_FLAG_TIMER)
- con_reg |= TIMER_FLAG_MASK_SRC (flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET (1) : GPTU_CON_SRC_EXT_SET (0);
+ if (TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER)
+ con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : GPTU_CON_SRC_EXT_SET(0);
else
- con_reg |= TIMER_FLAG_MASK_SRC (flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET (1) : GPTU_CON_SRC_EG_SET (0);
- con_reg |= TIMER_FLAG_MASK_SYNC (flags) == TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET (0) : GPTU_CON_SYNC_SET (1);
- con_reg |= TIMER_FLAG_MASK_INVERT (flags) == TIMER_FLAG_REAL ? GPTU_CON_INV_SET (0) : GPTU_CON_INV_SET (1);
- con_reg |= TIMER_FLAG_MASK_SIZE (flags) == TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET (0) : GPTU_CON_EXT_SET (1);
- con_reg |= TIMER_FLAG_MASK_STOP (flags) == TIMER_FLAG_ONCE ? GPTU_CON_STP_SET (1) : GPTU_CON_STP_SET (0);
- con_reg |= TIMER_FLAG_MASK_TYPE (flags) == TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET (0) : GPTU_CON_CNT_SET (1);
- con_reg |= TIMER_FLAG_MASK_DIR (flags) == TIMER_FLAG_UP ? GPTU_CON_DIR_SET (1) : GPTU_CON_DIR_SET (0);
+ con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : GPTU_CON_SRC_EG_SET(0);
+ con_reg |= TIMER_FLAG_MASK_SYNC(flags) == TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : GPTU_CON_SYNC_SET(1);
+ con_reg |= TIMER_FLAG_MASK_INVERT(flags) == TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1);
+ con_reg |= TIMER_FLAG_MASK_SIZE(flags) == TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : GPTU_CON_EXT_SET(1);
+ con_reg |= TIMER_FLAG_MASK_STOP(flags) == TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0);
+ con_reg |= TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : GPTU_CON_CNT_SET(1);
+ con_reg |= TIMER_FLAG_MASK_DIR(flags) == TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0);
timer_dev.timer[timer - FIRST_TIMER].flag = flags;
- if(TIMER_FLAG_MASK_SIZE(flags) != TIMER_FLAG_16BIT)
+ if (TIMER_FLAG_MASK_SIZE(flags) != TIMER_FLAG_16BIT)
timer_dev.timer[timer - FIRST_TIMER + 1].flag = flags;
n = timer >> 1;
@@ -587,36 +589,33 @@ ifxmips_reset_counter_flags(u32 timer, u32 flags)
*IFXMIPS_GPTU_CON(n, X) = con_reg;
smp_wmb();
- printk(KERN_INFO "[%s]: counter%d oflags %#x, nflags %#x, GPTU_CON %#x\n", __func__, timer, oflag, flags, *IFXMIPS_GPTU_CON (n, X));
+ printk(KERN_INFO "[%s]: counter%d oflags %#x, nflags %#x, GPTU_CON %#x\n", __func__, timer, oflag, flags, *IFXMIPS_GPTU_CON(n, X));
mutex_unlock(&timer_dev.gptu_mutex);
return 0;
}
EXPORT_SYMBOL(ifxmips_reset_counter_flags);
-inline int
-ifxmips_get_count_value(unsigned int timer, unsigned long *value)
+int ifxmips_get_count_value(unsigned int timer, unsigned long *value)
{
-
unsigned int flag;
unsigned int mask;
int n, X;
- if(!timer_dev.f_gptu_on)
+ if (!timer_dev.f_gptu_on)
return -EINVAL;
- if(timer < FIRST_TIMER
+ if (timer < FIRST_TIMER
|| timer >= FIRST_TIMER + timer_dev.number_of_timers)
return -EINVAL;
mutex_lock(&timer_dev.gptu_mutex);
flag = timer_dev.timer[timer - FIRST_TIMER].flag;
- if(TIMER_FLAG_MASK_SIZE (flag) != TIMER_FLAG_16BIT)
+ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
timer &= ~0x01;
- mask = (TIMER_FLAG_MASK_SIZE (flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
- if (((timer_dev.occupation & mask) ^ mask))
- {
+ mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
+ if (((timer_dev.occupation & mask) ^ mask)) {
mutex_unlock(&timer_dev.gptu_mutex);
return -EINVAL;
}
@@ -624,15 +623,15 @@ ifxmips_get_count_value(unsigned int timer, unsigned long *value)
n = timer >> 1;
X = timer & 0x01;
- *value = *IFXMIPS_GPTU_COUNT (n, X);
+ *value = *IFXMIPS_GPTU_COUNT(n, X);
mutex_unlock(&timer_dev.gptu_mutex);
return 0;
}
+EXPORT_SYMBOL(ifxmips_get_count_value);
-u32
-ifxmips_cal_divider(unsigned long freq)
+u32 ifxmips_cal_divider(unsigned long freq)
{
u64 module_freq, fpi = cgu_get_fpi_bus_clock(2);
u32 clock_divider = 1;
@@ -640,11 +639,11 @@ ifxmips_cal_divider(unsigned long freq)
do_div(module_freq, clock_divider * freq);
return module_freq;
}
+EXPORT_SYMBOL(ifxmips_cal_divider);
-int
-ifxmips_set_timer (unsigned int timer, unsigned int freq, int is_cyclic,
- int is_ext_src, unsigned int handle_flag, unsigned long arg1,
- unsigned long arg2)
+int ifxmips_set_timer(unsigned int timer, unsigned int freq, int is_cyclic,
+ int is_ext_src, unsigned int handle_flag, unsigned long arg1,
+ unsigned long arg2)
{
unsigned long divider;
unsigned int flag;
@@ -656,97 +655,99 @@ ifxmips_set_timer (unsigned int timer, unsigned int freq, int is_cyclic,
| (is_cyclic ? TIMER_FLAG_CYCLIC : TIMER_FLAG_ONCE)
| (is_ext_src ? TIMER_FLAG_EXT_SRC : TIMER_FLAG_INT_SRC)
| TIMER_FLAG_TIMER | TIMER_FLAG_DOWN
- | TIMER_FLAG_MASK_HANDLE (handle_flag);
+ | TIMER_FLAG_MASK_HANDLE(handle_flag);
- printk(KERN_INFO "set_timer(%d, %d), divider = %lu\n", timer, freq, divider);
- return ifxmips_request_timer (timer, flag, divider, arg1, arg2);
+ printk(KERN_INFO "ifxmips_set_timer(%d, %d), divider = %lu\n",
+ timer, freq, divider);
+ return ifxmips_request_timer(timer, flag, divider, arg1, arg2);
}
+EXPORT_SYMBOL(ifxmips_set_timer);
-int
-ifxmips_set_counter(unsigned int timer, unsigned int flag, u32 reload, unsigned long arg1, unsigned long arg2)
+int ifxmips_set_counter(unsigned int timer, unsigned int flag, u32 reload,
+ unsigned long arg1, unsigned long arg2)
{
- printk(KERN_INFO "set_counter(%d, %#x, %d)\n", timer, flag, reload);
+ printk(KERN_INFO "ifxmips_set_counter(%d, %#x, %d)\n", timer, flag, reload);
return ifxmips_request_timer(timer, flag, reload, arg1, arg2);
}
+EXPORT_SYMBOL(ifxmips_set_counter);
-static int
-gptu_ioctl (struct inode *inode, struct file *file, unsigned int cmd,
- unsigned long arg)
+static int gptu_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
+ unsigned long arg)
{
int ret;
struct gptu_ioctl_param param;
- if (!access_ok (VERIFY_READ, arg, sizeof (struct gptu_ioctl_param)))
+ if (!access_ok(VERIFY_READ, arg, sizeof(struct gptu_ioctl_param)))
return -EFAULT;
- copy_from_user (&param, (void *) arg, sizeof (param));
+ copy_from_user(&param, (void *) arg, sizeof(param));
if ((((cmd == GPTU_REQUEST_TIMER || cmd == GPTU_SET_TIMER
|| GPTU_SET_COUNTER) && param.timer < 2)
|| cmd == GPTU_GET_COUNT_VALUE || cmd == GPTU_CALCULATE_DIVIDER)
- && !access_ok (VERIFY_WRITE, arg,
- sizeof (struct gptu_ioctl_param)))
+ && !access_ok(VERIFY_WRITE, arg,
+ sizeof(struct gptu_ioctl_param)))
return -EFAULT;
switch (cmd) {
case GPTU_REQUEST_TIMER:
- ret = ifxmips_request_timer (param.timer, param.flag, param.value,
+ ret = ifxmips_request_timer(param.timer, param.flag, param.value,
(unsigned long) param.pid,
(unsigned long) param.sig);
if (ret > 0) {
- copy_to_user (&((struct gptu_ioctl_param *) arg)->
- timer, &ret, sizeof (&ret));
+ copy_to_user(&((struct gptu_ioctl_param *) arg)->
+ timer, &ret, sizeof(&ret));
ret = 0;
}
break;
case GPTU_FREE_TIMER:
- ret = ifxmips_free_timer (param.timer);
+ ret = ifxmips_free_timer(param.timer);
break;
case GPTU_START_TIMER:
- ret = ifxmips_start_timer (param.timer, param.flag);
+ ret = ifxmips_start_timer(param.timer, param.flag);
break;
case GPTU_STOP_TIMER:
- ret = ifxmips_stop_timer (param.timer);
+ ret = ifxmips_stop_timer(param.timer);
break;
case GPTU_GET_COUNT_VALUE:
- ret = ifxmips_get_count_value (param.timer, &param.value);
+ ret = ifxmips_get_count_value(param.timer, &param.value);
if (!ret)
- copy_to_user (&((struct gptu_ioctl_param *) arg)->
+ copy_to_user(&((struct gptu_ioctl_param *) arg)->
value, &param.value,
- sizeof (param.value));
+ sizeof(param.value));
break;
case GPTU_CALCULATE_DIVIDER:
- param.value = ifxmips_cal_divider (param.value);
+ param.value = ifxmips_cal_divider(param.value);
if (param.value == 0)
ret = -EINVAL;
else {
- copy_to_user (&((struct gptu_ioctl_param *) arg)->
+ copy_to_user(&((struct gptu_ioctl_param *) arg)->
value, &param.value,
- sizeof (param.value));
+ sizeof(param.value));
ret = 0;
}
break;
case GPTU_SET_TIMER:
- ret = ifxmips_set_timer (param.timer, param.value,
- TIMER_FLAG_MASK_STOP (param.flag) !=
+ ret = ifxmips_set_timer(param.timer, param.value,
+ TIMER_FLAG_MASK_STOP(param.flag) !=
TIMER_FLAG_ONCE ? 1 : 0,
- TIMER_FLAG_MASK_SRC (param.flag) ==
+ TIMER_FLAG_MASK_SRC(param.flag) ==
TIMER_FLAG_EXT_SRC ? 1 : 0,
- TIMER_FLAG_MASK_HANDLE (param.flag) ==
+ TIMER_FLAG_MASK_HANDLE(param.flag) ==
TIMER_FLAG_SIGNAL ? TIMER_FLAG_SIGNAL :
TIMER_FLAG_NO_HANDLE,
(unsigned long) param.pid,
(unsigned long) param.sig);
if (ret > 0) {
- copy_to_user (&((struct gptu_ioctl_param *) arg)->
- timer, &ret, sizeof (&ret));
+ copy_to_user(&((struct gptu_ioctl_param *) arg)->
+ timer, &ret, sizeof(&ret));
ret = 0;
}
break;
case GPTU_SET_COUNTER:
- ifxmips_set_counter (param.timer, param.flag, param.value, 0, 0);
+ ifxmips_set_counter(param.timer, param.flag, param.value, 0, 0);
if (ret > 0) {
- copy_to_user (&((struct gptu_ioctl_param *) arg)->
- timer, &ret, sizeof (&ret));
+ copy_to_user(&((struct gptu_ioctl_param *) arg)->
+ timer, &ret, sizeof(&ret));
ret = 0;
}
break;
@@ -757,19 +758,17 @@ gptu_ioctl (struct inode *inode, struct file *file, unsigned int cmd,
return ret;
}
-static int
-gptu_open(struct inode *inode, struct file *file)
+static int gptu_open(struct inode *inode, struct file *file)
{
return 0;
}
-static int
-gptu_release(struct inode *inode, struct file *file)
+static int gptu_release(struct inode *inode, struct file *file)
{
return 0;
}
-int __init
-ifxmips_gptu_init(void)
+
+int __init ifxmips_gptu_init(void)
{
int ret;
unsigned int i;
@@ -777,32 +776,29 @@ ifxmips_gptu_init(void)
ifxmips_w32(0, IFXMIPS_GPTU_IRNEN);
ifxmips_w32(0xfff, IFXMIPS_GPTU_IRNCR);
- memset(&timer_dev, 0, sizeof (timer_dev));
+ memset(&timer_dev, 0, sizeof(timer_dev));
mutex_init(&timer_dev.gptu_mutex);
ifxmips_enable_gptu();
timer_dev.number_of_timers = GPTU_ID_CFG * 2;
- ifxmips_disable_gptu ();
- if(timer_dev.number_of_timers > MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2)
+ ifxmips_disable_gptu();
+ if (timer_dev.number_of_timers > MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2)
timer_dev.number_of_timers = MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2;
- printk (KERN_INFO "gptu: totally %d 16-bit timers/counters\n", timer_dev.number_of_timers);
+ printk(KERN_INFO "gptu: totally %d 16-bit timers/counters\n", timer_dev.number_of_timers);
ret = misc_register(&gptu_miscdev);
- if(ret)
- {
+ if (ret) {
printk(KERN_ERR "gptu: can't misc_register, get error %d\n", -ret);
return ret;
} else {
printk(KERN_INFO "gptu: misc_register on minor %d\n", gptu_miscdev.minor);
}
- for(i = 0; i < timer_dev.number_of_timers; i++)
- {
- ret = request_irq (TIMER_INTERRUPT + i, timer_irq_handler, IRQF_TIMER, gptu_miscdev.name, &timer_dev.timer[i]);
- if(ret)
- {
+ for (i = 0; i < timer_dev.number_of_timers; i++) {
+ ret = request_irq(TIMER_INTERRUPT + i, timer_irq_handler, IRQF_TIMER, gptu_miscdev.name, &timer_dev.timer[i]);
+ if (ret) {
for (; i >= 0; i--)
- free_irq (TIMER_INTERRUPT + i, &timer_dev.timer[i]);
+ free_irq(TIMER_INTERRUPT + i, &timer_dev.timer[i]);
misc_deregister(&gptu_miscdev);
printk(KERN_ERR "gptu: failed in requesting irq (%d), get error %d\n", i, -ret);
return ret;
@@ -816,29 +812,18 @@ ifxmips_gptu_init(void)
return 0;
}
-void __exit
-ifxmips_gptu_exit(void)
+void __exit ifxmips_gptu_exit(void)
{
unsigned int i;
- for(i = 0; i < timer_dev.number_of_timers; i++)
- {
- if(timer_dev.timer[i].f_irq_on)
- disable_irq (timer_dev.timer[i].irq);
+ for (i = 0; i < timer_dev.number_of_timers; i++) {
+ if (timer_dev.timer[i].f_irq_on)
+ disable_irq(timer_dev.timer[i].irq);
free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]);
}
ifxmips_disable_gptu();
misc_deregister(&gptu_miscdev);
}
-EXPORT_SYMBOL(ifxmips_request_timer);
-EXPORT_SYMBOL(ifxmips_free_timer);
-EXPORT_SYMBOL(ifxmips_start_timer);
-EXPORT_SYMBOL(ifxmips_stop_timer);
-EXPORT_SYMBOL(ifxmips_get_count_value);
-EXPORT_SYMBOL(ifxmips_cal_divider);
-EXPORT_SYMBOL(ifxmips_set_timer);
-EXPORT_SYMBOL(ifxmips_set_counter);
-
module_init(ifxmips_gptu_init);
module_exit(ifxmips_gptu_exit);
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-26 10:36:58 +0000