diff options
Diffstat (limited to 'target/linux/generic/patches-3.9/021-bcma_backport.patch')
| -rw-r--r-- | target/linux/generic/patches-3.9/021-bcma_backport.patch | 140 |
1 files changed, 140 insertions, 0 deletions
diff --git a/target/linux/generic/patches-3.9/021-bcma_backport.patch b/target/linux/generic/patches-3.9/021-bcma_backport.patch new file mode 100644 index 000000000..2885aea38 --- /dev/null +++ b/target/linux/generic/patches-3.9/021-bcma_backport.patch @@ -0,0 +1,140 @@ +--- a/drivers/bcma/driver_chipcommon.c ++++ b/drivers/bcma/driver_chipcommon.c +@@ -25,13 +25,14 @@ static inline u32 bcma_cc_write32_masked + return value; + } + +-static u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc) ++u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc) + { + if (cc->capabilities & BCMA_CC_CAP_PMU) + return bcma_pmu_get_alp_clock(cc); + + return 20000000; + } ++EXPORT_SYMBOL_GPL(bcma_chipco_get_alp_clock); + + static u32 bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc *cc) + { +@@ -213,6 +214,7 @@ u32 bcma_chipco_gpio_out(struct bcma_drv + + return res; + } ++EXPORT_SYMBOL_GPL(bcma_chipco_gpio_out); + + u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value) + { +@@ -225,6 +227,7 @@ u32 bcma_chipco_gpio_outen(struct bcma_d + + return res; + } ++EXPORT_SYMBOL_GPL(bcma_chipco_gpio_outen); + + /* + * If the bit is set to 0, chipcommon controlls this GPIO, +--- a/drivers/bcma/driver_chipcommon_pmu.c ++++ b/drivers/bcma/driver_chipcommon_pmu.c +@@ -174,19 +174,35 @@ u32 bcma_pmu_get_alp_clock(struct bcma_d + struct bcma_bus *bus = cc->core->bus; + + switch (bus->chipinfo.id) { ++ case BCMA_CHIP_ID_BCM4313: ++ case BCMA_CHIP_ID_BCM43224: ++ case BCMA_CHIP_ID_BCM43225: ++ case BCMA_CHIP_ID_BCM43227: ++ case BCMA_CHIP_ID_BCM43228: ++ case BCMA_CHIP_ID_BCM4331: ++ case BCMA_CHIP_ID_BCM43421: ++ case BCMA_CHIP_ID_BCM43428: ++ case BCMA_CHIP_ID_BCM43431: + case BCMA_CHIP_ID_BCM4716: +- case BCMA_CHIP_ID_BCM4748: + case BCMA_CHIP_ID_BCM47162: +- case BCMA_CHIP_ID_BCM4313: +- case BCMA_CHIP_ID_BCM5357: ++ case BCMA_CHIP_ID_BCM4748: + case BCMA_CHIP_ID_BCM4749: ++ case BCMA_CHIP_ID_BCM5357: + case BCMA_CHIP_ID_BCM53572: ++ case BCMA_CHIP_ID_BCM6362: + /* always 20Mhz */ + return 20000 * 1000; +- case BCMA_CHIP_ID_BCM5356: + case BCMA_CHIP_ID_BCM4706: ++ case BCMA_CHIP_ID_BCM5356: + /* always 25Mhz */ + return 25000 * 1000; ++ case BCMA_CHIP_ID_BCM43460: ++ case BCMA_CHIP_ID_BCM4352: ++ case BCMA_CHIP_ID_BCM4360: ++ if (cc->status & BCMA_CC_CHIPST_4360_XTAL_40MZ) ++ return 40000 * 1000; ++ else ++ return 20000 * 1000; + default: + bcma_warn(bus, "No ALP clock specified for %04X device, pmu rev. %d, using default %d Hz\n", + bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK); +@@ -373,7 +389,7 @@ void bcma_pmu_spuravoid_pllupdate(struct + tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT; + bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp); + +- tmp = 1 << 10; ++ tmp = BCMA_CC_PMU_CTL_PLL_UPD; + break; + + case BCMA_CHIP_ID_BCM4331: +@@ -394,7 +410,7 @@ void bcma_pmu_spuravoid_pllupdate(struct + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2, + 0x03000a08); + } +- tmp = 1 << 10; ++ tmp = BCMA_CC_PMU_CTL_PLL_UPD; + break; + + case BCMA_CHIP_ID_BCM43224: +@@ -427,7 +443,7 @@ void bcma_pmu_spuravoid_pllupdate(struct + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5, + 0x88888815); + } +- tmp = 1 << 10; ++ tmp = BCMA_CC_PMU_CTL_PLL_UPD; + break; + + case BCMA_CHIP_ID_BCM4716: +@@ -461,7 +477,7 @@ void bcma_pmu_spuravoid_pllupdate(struct + 0x88888815); + } + +- tmp = 3 << 9; ++ tmp = BCMA_CC_PMU_CTL_PLL_UPD | BCMA_CC_PMU_CTL_NOILPONW; + break; + + case BCMA_CHIP_ID_BCM43227: +@@ -497,7 +513,7 @@ void bcma_pmu_spuravoid_pllupdate(struct + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5, + 0x88888815); + } +- tmp = 1 << 10; ++ tmp = BCMA_CC_PMU_CTL_PLL_UPD; + break; + default: + bcma_err(bus, "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n", +--- a/include/linux/bcma/bcma_driver_chipcommon.h ++++ b/include/linux/bcma/bcma_driver_chipcommon.h +@@ -104,6 +104,7 @@ + #define BCMA_CC_CHIPST_4706_MIPS_BENDIAN BIT(3) /* 0: little, 1: big endian */ + #define BCMA_CC_CHIPST_4706_PCIE1_DISABLE BIT(5) /* PCIE1 enable strap pin */ + #define BCMA_CC_CHIPST_5357_NAND_BOOT BIT(4) /* NAND boot, valid for CC rev 38 and/or BCM5357 */ ++#define BCMA_CC_CHIPST_4360_XTAL_40MZ 0x00000001 + #define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */ + #define BCMA_CC_JCMD_START 0x80000000 + #define BCMA_CC_JCMD_BUSY 0x80000000 +@@ -607,6 +608,8 @@ void bcma_chipco_bcm4331_ext_pa_lines_ct + + extern u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks); + ++extern u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc); ++ + void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value); + + u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask); |