diff options
Diffstat (limited to 'target/linux/coldfire/patches/003-MCF547x-and-MCF548x-support-in-Linux-2.6.38.patch')
| -rw-r--r-- | target/linux/coldfire/patches/003-MCF547x-and-MCF548x-support-in-Linux-2.6.38.patch | 7673 |
1 files changed, 7673 insertions, 0 deletions
diff --git a/target/linux/coldfire/patches/003-MCF547x-and-MCF548x-support-in-Linux-2.6.38.patch b/target/linux/coldfire/patches/003-MCF547x-and-MCF548x-support-in-Linux-2.6.38.patch new file mode 100644 index 000000000..08bc86fc4 --- /dev/null +++ b/target/linux/coldfire/patches/003-MCF547x-and-MCF548x-support-in-Linux-2.6.38.patch @@ -0,0 +1,7673 @@ +From b19b66d24fe96f4f79753762048328fe985351a6 Mon Sep 17 00:00:00 2001 +From: Alison Wang <b18965@freescale.com> +Date: Thu, 4 Aug 2011 09:59:38 +0800 +Subject: [PATCH 03/52] MCF547x and MCF548x support in Linux 2.6.38 + +MCF547x and MCF548x support in Linux 2.6.38. + +Signed-off-by: Alison Wang <b18965@freescale.com> +--- + arch/m68k/coldfire/m547x/Makefile | 7 + + arch/m68k/coldfire/m547x/config.c | 412 ++++++++ + arch/m68k/coldfire/m547x/devices.c | 176 +++ + arch/m68k/coldfire/m547x/mcf548x-devices.c | 126 +++ + arch/m68k/configs/m5474lite_defconfig | 1269 ++++++++++++++++++++++ + arch/m68k/configs/m5475evb_defconfig | 1324 +++++++++++++++++++++++ + arch/m68k/configs/m5485evb_defconfig | 1582 ++++++++++++++++++++++++++++ + arch/m68k/include/asm/cf_548x_cacheflush.h | 262 +++++ + arch/m68k/include/asm/m5485dma.h | 98 ++ + arch/m68k/include/asm/m5485dspi.h | 146 +++ + arch/m68k/include/asm/m5485gpio.h | 695 ++++++++++++ + arch/m68k/include/asm/m5485gpt.h | 90 ++ + arch/m68k/include/asm/m5485pci.h | 380 +++++++ + arch/m68k/include/asm/m5485psc.h | 475 +++++++++ + arch/m68k/include/asm/m5485sec.h | 177 ++++ + arch/m68k/include/asm/m5485sim.h | 346 ++++++ + arch/m68k/include/asm/m5485sram.h | 12 + + 17 files changed, 7577 insertions(+), 0 deletions(-) + create mode 100644 arch/m68k/coldfire/m547x/Makefile + create mode 100644 arch/m68k/coldfire/m547x/config.c + create mode 100644 arch/m68k/coldfire/m547x/devices.c + create mode 100644 arch/m68k/coldfire/m547x/mcf548x-devices.c + create mode 100644 arch/m68k/configs/m5474lite_defconfig + create mode 100644 arch/m68k/configs/m5475evb_defconfig + create mode 100644 arch/m68k/configs/m5485evb_defconfig + create mode 100644 arch/m68k/include/asm/cf_548x_cacheflush.h + create mode 100644 arch/m68k/include/asm/m5485dma.h + create mode 100644 arch/m68k/include/asm/m5485dspi.h + create mode 100644 arch/m68k/include/asm/m5485gpio.h + create mode 100644 arch/m68k/include/asm/m5485gpt.h + create mode 100644 arch/m68k/include/asm/m5485pci.h + create mode 100644 arch/m68k/include/asm/m5485psc.h + create mode 100644 arch/m68k/include/asm/m5485sec.h + create mode 100644 arch/m68k/include/asm/m5485sim.h + create mode 100644 arch/m68k/include/asm/m5485sram.h + +--- /dev/null ++++ b/arch/m68k/coldfire/m547x/Makefile +@@ -0,0 +1,7 @@ ++# ++# Makefile for Linux arch/m68k/coldfire/m547x source directory ++# ++ ++obj-$(CONFIG_M547X_8X) += config.o mcf548x-devices.o devices.o ++obj-$(CONFIG_PCI) += pci.o pci_dummy.o ++obj-$(CONFIG_MCD_DMA) += dma.o +--- /dev/null ++++ b/arch/m68k/coldfire/m547x/config.c +@@ -0,0 +1,412 @@ ++/* ++ * linux/arch/m68k/coldfire/config.c ++ * ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Kurt Mahan kmahan@freescale.com ++ * Matt Waddel Matt.Waddel@freescale.com ++ * Shrek Wu b16972@freescale.com ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++ ++#include <linux/module.h> ++#include <linux/init.h> ++#include <linux/string.h> ++#include <linux/kernel.h> ++#include <linux/console.h> ++#include <linux/bootmem.h> ++#include <linux/mm.h> ++#include <linux/clockchips.h> ++#include <asm/bootinfo.h> ++#include <asm/machdep.h> ++#include <asm/coldfire.h> ++#include <asm/cfcache.h> ++#include <asm/cacheflush.h> ++#include <linux/io.h> ++#include <asm/cfmmu.h> ++#include <asm/setup.h> ++#include <asm/irq.h> ++#include <asm/traps.h> ++#include <asm/movs.h> ++#include <asm/movs.h> ++#include <asm/page.h> ++#include <asm/pgalloc.h> ++ ++#include <asm/mcfsim.h> ++ ++#define UBOOT_PCI ++#include <asm/bootinfo.h> ++#include <asm/m5485gpt.h> ++ ++extern int get_irq_list(struct seq_file *p, void *v); ++extern char _text, _end; ++extern char _etext, _edata, __init_begin, __init_end; ++extern struct console mcfrs_console; ++extern char m68k_command_line[CL_SIZE]; ++extern unsigned long availmem; ++extern struct mem_info m68k_ramdisk; ++ ++static int irq_enable[NR_IRQS]; ++unsigned long num_pages; ++ ++/* cf dma physical addresses */ ++unsigned long cf_dma_base; ++EXPORT_SYMBOL(cf_dma_base); ++unsigned long cf_dma_end; ++EXPORT_SYMBOL(cf_dma_end); ++unsigned long cf_dma_size; ++EXPORT_SYMBOL(cf_dma_size); ++ ++/* ethernet mac addresses from uboot */ ++unsigned char uboot_enet0[6]; ++unsigned char uboot_enet1[6]; ++ ++void coldfire_sort_memrec(void) ++{ ++ int i, j; ++ ++ /* Sort the m68k_memory records by address */ ++ for (i = 0; i < m68k_num_memory; ++i) { ++ for (j = i + 1; j < m68k_num_memory; ++j) { ++ if (m68k_memory[i].addr > m68k_memory[j].addr) { ++ struct mem_info tmp; ++ tmp = m68k_memory[i]; ++ m68k_memory[i] = m68k_memory[j]; ++ m68k_memory[j] = tmp; ++ } ++ } ++ } ++ /* Trim off discontiguous bits */ ++ for (i = 1; i < m68k_num_memory; ++i) { ++ if ((m68k_memory[i-1].addr + m68k_memory[i-1].size) != ++ m68k_memory[i].addr) { ++ printk(KERN_DEBUG "m68k_parse_bootinfo: " ++ "addr gap between 0x%lx & 0x%lx\n", ++ m68k_memory[i-1].addr+m68k_memory[i-1].size, ++ m68k_memory[i].addr); ++ m68k_num_memory = i; ++ break; ++ } ++ } ++} ++ ++/* ++ * UBoot Handler ++ */ ++int __init uboot_commandline(char *bootargs) ++{ ++ int len = 0, cmd_line_len; ++ static struct uboot_record uboot_info; ++ u32 offset = PAGE_OFFSET_RAW - PHYS_OFFSET; ++ ++ extern unsigned long uboot_info_stk; ++ ++ /* validate address */ ++ if ((uboot_info_stk < PAGE_OFFSET_RAW) || ++ (uboot_info_stk >= (PAGE_OFFSET_RAW + CONFIG_SDRAM_SIZE))) ++ return 0; ++ ++ /* Add offset to get post-remapped kernel memory location */ ++ uboot_info.bdi = (struct bd_info *)((*(u32 *)(uboot_info_stk)) ++ + offset); ++ uboot_info.initrd_start = (*(u32 *)(uboot_info_stk+4)) + offset; ++ uboot_info.initrd_end = (*(u32 *)(uboot_info_stk+8)) + offset; ++ uboot_info.cmd_line_start = (*(u32 *)(uboot_info_stk+12)) + offset; ++ uboot_info.cmd_line_stop = (*(u32 *)(uboot_info_stk+16)) + offset; ++ ++#if defined(CONFIG_BLK_DEV_INITRD) ++ m68k_ramdisk.addr = uboot_info.initrd_start; ++ m68k_ramdisk.size = (uboot_info.initrd_end - uboot_info.initrd_start) ? ++ (uboot_info.initrd_end - uboot_info.initrd_start + 1) : 0; ++#endif ++ ++ /* copy over mac addresses */ ++ memcpy(uboot_enet0, uboot_info.bdi->bi_enet0addr, 6); ++ memcpy(uboot_enet1, uboot_info.bdi->bi_enet1addr, 6); ++ ++ /* copy command line */ ++ cmd_line_len = uboot_info.cmd_line_stop - uboot_info.cmd_line_start; ++ if ((cmd_line_len > 0) && (cmd_line_len < CL_SIZE-1)) ++ len = (int)strncpy(bootargs, (char *)uboot_info.cmd_line_start,\ ++ cmd_line_len); ++ ++ return len; ++} ++ ++/* ++ * This routine does things not done in the bootloader. ++ */ ++#define DEFAULT_COMMAND_LINE \ ++ "debug root=/dev/nfs rw \ ++ nfsroot=172.27.155.1:/tftpboot/rigo/rootfs/ \ ++ ip=172.27.155.75:172.27.155.1" ++ ++asmlinkage void __init cf_early_init(void) ++{ ++ SET_VBR((void *)MCF_RAMBAR0); ++ ++ /* Mask all interrupts */ ++ MCF_IMRL = 0xFFFFFFFF; ++ MCF_IMRH = 0xFFFFFFFF; ++ ++ m68k_machtype = MACH_CFMMU; ++ m68k_fputype = FPU_CFV4E; ++ m68k_mmutype = MMU_CFV4E; ++ m68k_cputype = CPU_CFV4E; ++ ++ m68k_num_memory = 0; ++ m68k_memory[m68k_num_memory].addr = CONFIG_SDRAM_BASE; ++ m68k_memory[m68k_num_memory++].size = CONFIG_SDRAM_SIZE; ++ ++ if (!uboot_commandline(m68k_command_line)) { ++#if defined(CONFIG_BOOTPARAM) ++ strncpy(m68k_command_line, CONFIG_BOOTPARAM_STRING, CL_SIZE-1); ++#else ++ strcpy(m68k_command_line, DEFAULT_COMMAND_LINE); ++#endif ++ } ++ ++ /* Invalidate caches via CACR */ ++ flush_bcache(); ++ cacr_set(CACHE_DISABLE_MODE); ++ ++ /* Turn on caches via CACR, enable EUSP */ ++ cacr_set(CACHE_INITIAL_MODE); ++} ++ ++/* Assembler routines */ ++asmlinkage void buserr(void); ++asmlinkage void trap(void); ++asmlinkage void system_call(void); ++asmlinkage void inthandler(void); ++ ++void __init coldfire_trap_init(void) ++{ ++ int i = 0; ++ e_vector *vectors; ++ ++ vectors = (e_vector *)MCF_RAMBAR0; ++ /* ++ * There is a common trap handler and common interrupt ++ * handler that handle almost every vector. We treat ++ * the system call and bus error special, they get their ++ * own first level handlers. ++ */ ++ for (i = 3; (i <= 23); i++) ++ vectors[i] = trap; ++ for (i = 33; (i <= 63); i++) ++ vectors[i] = trap; ++ for (i = 24; (i <= 31); i++) ++ vectors[i] = inthandler; ++ for (i = 64; (i < 255); i++) ++ vectors[i] = inthandler; ++ ++ vectors[255] = 0; ++ vectors[2] = buserr; ++ vectors[32] = system_call; ++} ++ ++void coldfire_tick(void) ++{ ++ /* Reset the ColdFire timer */ ++ MCF_SSR(0) = MCF_SSR_ST; ++} ++ ++void __init coldfire_sched_init(irq_handler_t handler) ++{ ++ int irq = ISC_SLTn(0); ++ ++ MCF_SCR(0) = 0; ++ MCF_ICR(irq) = ILP_SLT0; ++ request_irq(64 + irq, handler, IRQF_DISABLED, "ColdFire Timer 0", NULL); ++ MCF_SLTCNT(0) = MCF_BUSCLK / HZ; ++ MCF_SCR(0) |= MCF_SCR_TEN | MCF_SCR_IEN | MCF_SCR_RUN; ++} ++ ++unsigned long coldfire_gettimeoffset(void) ++{ ++ volatile unsigned long trr, tcn, offset; ++ trr = MCF_SLTCNT(0); ++ tcn = MCF_SCNT(0); ++ ++ offset = (trr - tcn) * ((1000000 >> 3) / HZ) / (trr >> 3); ++ if (MCF_SSR(0) & MCF_SSR_ST) ++ offset += 1000000 / HZ; ++ ++ return offset; ++} ++ ++static unsigned long long sched_dtim_clk_val; ++ ++unsigned long long sched_clock(void) ++{ ++ unsigned long flags; ++ unsigned long long cycles; ++ volatile unsigned long trr, tcn, offset; ++ ++ local_irq_save(flags); ++ trr = MCF_SLTCNT(0); ++ tcn = MCF_SCNT(0); ++ offset = (trr - tcn); ++ cycles = sched_dtim_clk_val; ++ local_irq_restore(flags); ++ ++ return cycles + offset; ++} ++ ++unsigned long long sys_dtim2_read(void) ++{ ++ unsigned long flags; ++ unsigned long long cycles; ++ volatile unsigned long trr, tcn, offset; ++ ++ local_irq_save(flags); ++ trr = MCF_SLTCNT(0); ++ tcn = MCF_SCNT(0); ++ offset = (trr - tcn); ++ cycles = sched_dtim_clk_val; ++ local_irq_restore(flags); ++ ++ return cycles + offset; ++} ++ ++static irqreturn_t coldfire_dtim_clk_irq(int irq, void *dev) ++{ ++ struct clock_event_device *evt = ++ (struct clock_event_device *)dev; ++ ++ MCF_SSR(0) = MCF_SSR_ST; ++ sched_dtim_clk_val += (MCF_BUSCLK) / HZ; ++ evt->event_handler(evt); ++ return IRQ_HANDLED; ++} ++ ++void sys_dtim2_init(struct clock_event_device *evt) ++{ ++ int irq = ISC_SLTn(0); ++ ++ sched_dtim_clk_val = 0; ++ MCF_SCR(0) = 0; ++ MCF_ICR(irq) = ILP_SLT0; ++ request_irq(64 + irq, coldfire_dtim_clk_irq, IRQF_DISABLED, ++ "ColdFire Timer 0", (void *)evt); ++ MCF_SLTCNT(0) = MCF_BUSCLK / HZ; ++ MCF_SCR(0) |= MCF_SCR_TEN | MCF_SCR_IEN | MCF_SCR_RUN; ++} ++ ++void coldfire_reboot(void) ++{ ++ /* disable interrupts and enable the watchdog */ ++ printk(KERN_INFO "Rebooting\n"); ++ ++ /*Disable the XLB priority settings, then set the core to same priority ++ * level as other XLB masters, also disable the PCI here, otherwise the ++ * watchdog may fail to reset. ++ */ ++ MCF_XARB_PRIEN = 0; ++ MCF_SPCR &= ~0x02; ++ asm("tpf"); ++ asm("movew #0x2700, %sr\n"); ++ MCF_GPT_GMS0 = MCF_GPT_GMS_WDEN | MCF_GPT_GMS_CE | MCF_GPT_GMS_TMS(4); ++ MCF_GPT_GCIR0 = (0x0A << 16) | 0x03; ++} ++ ++static void coldfire_get_model(char *model) ++{ ++ sprintf(model, "Version 4 ColdFire"); ++} ++ ++static void __init ++coldfire_bootmem_alloc(unsigned long memory_start, unsigned long memory_end) ++{ ++ unsigned long base_pfn; ++ ++ /* compute total pages in system */ ++ num_pages = PAGE_ALIGN(memory_end - PAGE_OFFSET) >> PAGE_SHIFT; ++ ++ /* align start/end to page boundries */ ++ memory_start = PAGE_ALIGN(memory_start); ++ memory_end = memory_end & PAGE_MASK; ++ ++ /* page numbers */ ++ base_pfn = __pa(PAGE_OFFSET) >> PAGE_SHIFT; ++ min_low_pfn = __pa(memory_start) >> PAGE_SHIFT; ++ max_low_pfn = __pa(memory_end) >> PAGE_SHIFT; ++ ++ high_memory = (void *)memory_end; ++ availmem = memory_start; ++ ++ /* setup bootmem data */ ++ m68k_setup_node(0); ++ availmem += init_bootmem_node(NODE_DATA(0), min_low_pfn, ++ base_pfn, max_low_pfn); ++ availmem = PAGE_ALIGN(availmem); ++ ++ printk(KERN_INFO "** availmem=0x%lx pa(am)=0x%lx\n", ++ availmem, __pa(availmem)); ++ printk(KERN_INFO "** mstart=0x%lx mend=0x%lx\n", ++ memory_start, memory_end); ++ printk(KERN_INFO "bpfn=0x%lx minpfn=0x%lx maxpfn=0x%lx\n", ++ base_pfn, min_low_pfn, max_low_pfn); ++ ++ /* turn over physram */ ++ free_bootmem(__pa(availmem), memory_end - (availmem)); ++ ++ /* configure physical dma area */ ++ cf_dma_base = __pa(PAGE_ALIGN(memory_start)); ++ cf_dma_size = CONFIG_DMA_SIZE; ++ cf_dma_end = CONFIG_SDRAM_BASE + cf_dma_size - 1; ++ ++ printk(KERN_INFO "dma: phys base=0x%lx phys end=0x%lx virt base=0x%x\n", ++ cf_dma_base, cf_dma_end, CONFIG_DMA_BASE); ++ ++ printk(KERN_INFO "mdma=0x%x pa(mdma)=0x%lx\n", ++ MAX_DMA_ADDRESS, __pa(MAX_DMA_ADDRESS)); ++} ++ ++void __init config_coldfire(void) ++{ ++ unsigned long endmem, startmem; ++ int i; ++ ++ /* ++ * Calculate endmem from m68k_memory, assume all are contiguous ++ */ ++ startmem = ((((int) &_end) + (PAGE_SIZE - 1)) & PAGE_MASK); ++ endmem = PAGE_OFFSET; ++ for (i = 0; i < m68k_num_memory; ++i) ++ endmem += m68k_memory[i].size; ++ ++ printk(KERN_INFO "starting up linux startmem 0x%lx, endmem 0x%lx, \ ++ size %luMB\n", startmem, endmem, (endmem - startmem) >> 20); ++ ++ memset(irq_enable, 0, sizeof(irq_enable)); ++ ++ /* ++ * Setup coldfire mach-specific handlers ++ */ ++ mach_max_dma_address = 0xffffffff; ++ mach_sched_init = coldfire_sched_init; ++ mach_tick = coldfire_tick; ++ mach_gettimeoffset = coldfire_gettimeoffset; ++ mach_reset = coldfire_reboot; ++ mach_get_model = coldfire_get_model; ++ ++ coldfire_bootmem_alloc(startmem, endmem-1); ++ ++#if defined(CONFIG_DUMMY_CONSOLE) || defined(CONFIG_FRAMEBUFFER_CONSOLE) ++ conswitchp = &dummy_con; ++#endif ++ ++#if defined(CONFIG_SERIAL_COLDFIRE) ++ /* ++ * This causes trouble when it is re-registered later. ++ * Currently this is fixed by conditionally commenting ++ * out the register_console in mcf_serial.c ++ */ ++ register_console(&mcfrs_console); ++#endif ++} +--- /dev/null ++++ b/arch/m68k/coldfire/m547x/devices.c +@@ -0,0 +1,176 @@ ++/* ++ * arch/m68k/coldfire/m547x/devices.c ++ * ++ * Coldfire M547x/M548x Platform Device Configuration ++ * ++ * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * Kurt Mahan <kmahan@freescale.com> ++ */ ++#include <linux/module.h> ++#include <linux/kernel.h> ++#include <linux/init.h> ++#include <linux/platform_device.h> ++#include <linux/fsl_devices.h> ++#include <linux/spi/spi.h> ++#include <linux/i2c.h> ++ ++#include <asm/coldfire.h> ++#include <asm/mcfsim.h> ++#include <asm/mcfqspi.h> ++ ++ ++#ifdef CONFIG_SPI ++/* ++ * ++ * DSPI ++ * ++ */ ++ ++/* number of supported SPI selects */ ++#define SPI_NUM_CHIPSELECTS 8 ++ ++void coldfire_spi_cs_control(u8 cs, u8 command) ++{ ++ /* nothing special required */ ++} ++ ++#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) ++static struct coldfire_spi_chip spidev_chip_info = { ++ .bits_per_word = 8, ++}; ++#endif ++ ++static struct spi_board_info spi_board_info[] = { ++#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) ++ { ++ .modalias = "spidev", ++ .max_speed_hz = 16000000, /* max clk (SCK) speed in HZ */ ++ .bus_num = 1, ++ .chip_select = 0, /* CS0 */ ++ .controller_data = &spidev_chip_info, ++ } ++#endif ++}; ++ ++static int spi_irq_list[] = { ++ /* IRQ, ICR Offset, ICR Val,Mask */ ++ 64 + ISC_DSPI_OVRFW, ISC_DSPI_OVRFW, 0x18, 0, ++ 64 + ISC_DSPI_RFOF, ISC_DSPI_RFOF, 0x18, 0, ++ 64 + ISC_DSPI_RFDF, ISC_DSPI_RFDF, 0x18, 0, ++ 64 + ISC_DSPI_TFUF, ISC_DSPI_TFUF, 0x18, 0, ++ 64 + ISC_DSPI_TCF, ISC_DSPI_TCF, 0x18, 0, ++ 64 + ISC_DSPI_TFFF, ISC_DSPI_TFFF, 0x18, 0, ++ 64 + ISC_DSPI_EOQF, ISC_DSPI_EOQF, 0x18, 0, ++ 0, 0, 0, 0, ++}; ++ ++static struct coldfire_spi_master coldfire_master_info = { ++ .bus_num = 1, ++ .num_chipselect = SPI_NUM_CHIPSELECTS, ++ .irq_list = spi_irq_list, ++ .irq_source = 0, /* not used */ ++ .irq_vector = 0, /* not used */ ++ .irq_mask = 0, /* not used */ ++ .irq_lp = 0, /* not used */ ++ .par_val = 0, /* not used */ ++ .cs_control = coldfire_spi_cs_control, ++}; ++ ++static struct resource coldfire_spi_resources[] = { ++ [0] = { ++ .name = "spi-par", ++ .start = MCF_MBAR + 0x00000a50, /* PAR_DSPI */ ++ .end = MCF_MBAR + 0x00000a50, /* PAR_DSPI */ ++ .flags = IORESOURCE_MEM ++ }, ++ ++ [1] = { ++ .name = "spi-module", ++ .start = MCF_MBAR + 0x00008a00, /* DSPI MCR Base */ ++ .end = MCF_MBAR + 0x00008ab8, /* DSPI mem map end */ ++ .flags = IORESOURCE_MEM ++ }, ++ ++ [2] = { ++ .name = "spi-int-level", ++ .start = MCF_MBAR + 0x740, /* ICR start */ ++ .end = MCF_MBAR + 0x740 + ISC_DSPI_EOQF, /* ICR end */ ++ .flags = IORESOURCE_MEM ++ }, ++ ++ [3] = { ++ .name = "spi-int-mask", ++ .start = MCF_MBAR + 0x70c, /* IMRL */ ++ .end = MCF_MBAR + 0x70c, /* IMRL */ ++ .flags = IORESOURCE_MEM ++ } ++}; ++ ++static struct platform_device coldfire_spi = { ++ .name = "spi_coldfire", ++ .id = -1, ++ .resource = coldfire_spi_resources, ++ .num_resources = ARRAY_SIZE(coldfire_spi_resources), ++ .dev = { ++ .platform_data = &coldfire_master_info, ++ } ++}; ++ ++/** ++ * m547x_8x_spi_init - Initialize SPI ++ */ ++static int __init m547x_8x_spi_init(void) ++{ ++ int retval; ++ ++ /* initialize the DSPI PAR */ ++ MCF_GPIO_PAR_DSPI = (MCF_GPIO_PAR_DSPI_PAR_CS5 | ++ MCF_GPIO_PAR_DSPI_PAR_CS3_DSPICS | ++ MCF_GPIO_PAR_DSPI_PAR_CS2_DSPICS | ++ MCF_GPIO_PAR_DSPI_PAR_CS0_DSPICS | ++ MCF_GPIO_PAR_DSPI_PAR_SCK_SCK | ++ MCF_GPIO_PAR_DSPI_PAR_SIN_SIN | ++ MCF_GPIO_PAR_DSPI_PAR_SOUT_SOUT); ++ ++ /* register device */ ++ retval = platform_device_register(&coldfire_spi); ++ if (retval < 0) ++ goto out; ++ ++ /* register board info */ ++ if (ARRAY_SIZE(spi_board_info)) ++ retval = spi_register_board_info(spi_board_info, ++ ARRAY_SIZE(spi_board_info)); ++ ++out: ++ return retval; ++} ++#endif ++ ++#ifdef CONFIG_I2C_BOARDINFO ++static struct i2c_board_info mcf_i2c_devices[] = { ++ { ++ I2C_BOARD_INFO("rv5c387a", 0x32), ++ }, ++}; ++#endif ++ ++/** ++ * m547x_8x_init_devices - Initialize M547X_8X devices ++ * ++ * Returns 0 on success. ++ */ ++static int __init m547x_8x_init_devices(void) ++{ ++#ifdef CONFIG_SPI ++ m547x_8x_spi_init(); ++#endif ++#ifdef CONFIG_I2C_BOARDINFO ++ i2c_register_board_info(0, mcf_i2c_devices, ++ ARRAY_SIZE(mcf_i2c_devices)); ++#endif ++ ++ return 0; ++} ++arch_initcall(m547x_8x_init_devices); +--- /dev/null ++++ b/arch/m68k/coldfire/m547x/mcf548x-devices.c +@@ -0,0 +1,126 @@ ++/* ++ * arch/m68k/coldfire/m547x/mcf548x-devices.c ++ * ++ * Coldfire M548x Platform Device Configuration ++ * ++ * Based on the Freescale MXC devices.c ++ * ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * Kurt Mahan <kmahan@freescale.com> ++ */ ++#include <linux/module.h> ++#include <linux/kernel.h> ++#include <linux/init.h> ++#include <linux/mtd/physmap.h> ++#include <linux/platform_device.h> ++#include <linux/fsl_devices.h> ++ ++#include <asm/coldfire.h> ++#include <asm/mcfsim.h> ++#include <asm/mcfuart.h> ++ ++static struct resource coldfire_i2c_resources[] = { ++ { /* I/O */ ++ .start = MCF_MBAR + 0x008F00, ++ .end = MCF_MBAR + 0x008F20, ++ .flags = IORESOURCE_MEM, ++ }, ++ { /* IRQ */ ++ .start = 40, ++ .end = 40, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static struct platform_device coldfire_i2c_device = { ++ .name = "mcf-i2c", ++ .id = 0, /*bus number*/ ++ .num_resources = ARRAY_SIZE(coldfire_i2c_resources), ++ .resource = coldfire_i2c_resources, ++}; ++ ++static struct resource coldfire_sec_resources[] = { ++ [0] = { /* I/O */ ++ .start = MCF_MBAR + 0x00020000, ++ .end = MCF_MBAR + 0x00033000, ++ .flags = IORESOURCE_MEM, ++ }, ++ [2] = { /* IRQ */ ++ .start = ISC_SEC, ++ .end = ISC_SEC, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static struct platform_device coldfire_sec_device = { ++ .name = "fsl-sec1", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(coldfire_sec_resources), ++ .resource = coldfire_sec_resources, ++}; ++ ++static int __init mcf5485_init_devices(void) ++{ ++ printk(KERN_INFO "MCF5485x INIT_DEVICES\n"); ++ ++ platform_device_register(&coldfire_i2c_device); ++ platform_device_register(&coldfire_sec_device); ++ return 0; ++} ++arch_initcall(mcf5485_init_devices); ++ ++static struct mcf_platform_uart m548x_uart_platform[] = { ++ { ++ .mapbase = MCF_MBAR + MCFUART_BASE1, ++ .irq = MCFINT_VECBASE + MCFINT_UART0, ++ }, ++ { ++ .mapbase = MCF_MBAR + MCFUART_BASE2, ++ .irq = MCFINT_VECBASE + MCFINT_UART1, ++ }, ++ { ++ .mapbase = MCF_MBAR + MCFUART_BASE3, ++ .irq = MCFINT_VECBASE + MCFINT_UART2, ++ }, ++ { ++ .mapbase = MCF_MBAR + MCFUART_BASE4, ++ .irq = MCFINT_VECBASE + MCFINT_UART3, ++ }, ++ { }, ++}; ++ ++static struct platform_device m548x_uart = { ++ .name = "mcfuart", ++ .id = 0, ++ .dev.platform_data = m548x_uart_platform, ++}; ++ ++static struct platform_device *m548x_devices[] __initdata = { ++ &m548x_uart, ++}; ++ ++void m548x_uarts_init(void) ++{ ++ const int nrlines = ARRAY_SIZE(m548x_uart_platform); ++ int line; ++ ++ /* Set GPIO port register to enable PSC(port) signals */ ++ for (line = 0; (line < nrlines); line++) { ++ MCF_PAR_PSCn(line) = (0 ++ | MCF_PAR_PSC_TXD ++ | MCF_PAR_PSC_RXD); ++ ++ MCF_ICR(m548x_uart_platform[line].irq - 64) = ILP_PSCn(line); ++ } ++} ++/***************************************************************************/ ++ ++static int __init init_BSP(void) ++{ ++ m548x_uarts_init(); ++ platform_add_devices(m548x_devices, ARRAY_SIZE(m548x_devices)); ++ return 0; ++} ++ ++arch_initcall(init_BSP); +--- /dev/null ++++ b/arch/m68k/configs/m5474lite_defconfig +@@ -0,0 +1,1269 @@ ++# ++# Automatically generated make config: don't edit ++# Linux kernel version: 2.6.29 ++# Tue Aug 24 16:17:48 2010 ++# ++CONFIG_M68K=y ++CONFIG_MMU=y ++CONFIG_GENERIC_TIME=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_RWSEM_GENERIC_SPINLOCK=y ++# CONFIG_ARCH_HAS_ILOG2_U32 is not set ++# CONFIG_ARCH_HAS_ILOG2_U64 is not set ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++# CONFIG_TIME_LOW_RES is not set ++CONFIG_GENERIC_IOMAP=y ++# CONFIG_NO_IOPORT is not set ++# CONFIG_NO_DMA is not set ++CONFIG_HZ=100 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++ ++# ++# General setup ++# ++CONFIG_EXPERIMENTAL=y ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_SWAP=y ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++# CONFIG_POSIX_MQUEUE is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++# CONFIG_AUDIT is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_CLASSIC_RCU=y ++# CONFIG_TREE_RCU is not set ++# CONFIG_PREEMPT_RCU is not set ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_PREEMPT_RCU_TRACE is not set ++CONFIG_IKCONFIG=y ++CONFIG_IKCONFIG_PROC=y ++CONFIG_LOG_BUF_SHIFT=17 ++CONFIG_GROUP_SCHED=y ++CONFIG_FAIR_GROUP_SCHED=y ++# CONFIG_RT_GROUP_SCHED is not set ++CONFIG_USER_SCHED=y ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUPS is not set ++CONFIG_SYSFS_DEPRECATED=y ++CONFIG_SYSFS_DEPRECATED_V2=y ++# CONFIG_RELAY is not set ++CONFIG_NAMESPACES=y ++# CONFIG_UTS_NS is not set ++# CONFIG_IPC_NS is not set ++# CONFIG_USER_NS is not set ++# CONFIG_PID_NS is not set ++# CONFIG_NET_NS is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++# CONFIG_EMBEDDED is not set ++CONFIG_UID16=y ++CONFIG_SYSCTL_SYSCALL=y ++CONFIG_KALLSYMS=y ++# CONFIG_KALLSYMS_EXTRA_PASS is not set ++CONFIG_HOTPLUG=y ++CONFIG_PRINTK=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++CONFIG_VM_EVENT_COUNTERS=y ++CONFIG_PCI_QUIRKS=y ++CONFIG_COMPAT_BRK=y ++CONFIG_SLAB=y ++# CONFIG_SLUB is not set ++# CONFIG_SLOB is not set ++# CONFIG_PROFILING is not set ++# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set ++CONFIG_SLABINFO=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=0 ++CONFIG_MODULES=y ++# CONFIG_MODULE_FORCE_LOAD is not set ++CONFIG_MODULE_UNLOAD=y ++CONFIG_MODULE_FORCE_UNLOAD=y ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++CONFIG_BLOCK=y ++CONFIG_LBD=y ++# CONFIG_BLK_DEV_IO_TRACE is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_AS=y ++CONFIG_IOSCHED_DEADLINE=y ++CONFIG_IOSCHED_CFQ=y ++# CONFIG_DEFAULT_AS is not set ++# CONFIG_DEFAULT_DEADLINE is not set ++CONFIG_DEFAULT_CFQ=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="cfq" ++# CONFIG_FREEZER is not set ++ ++# ++# Platform dependent setup ++# ++CONFIG_COLDFIRE=y ++CONFIG_CFV4E=y ++# CONFIG_FPU is not set ++CONFIG_MCD_DMA=y ++# CONFIG_AMIGA is not set ++# CONFIG_ATARI is not set ++CONFIG_PCI=y ++# CONFIG_MAC is not set ++# CONFIG_APOLLO is not set ++# CONFIG_VME is not set ++# CONFIG_HP300 is not set ++# CONFIG_SUN3X is not set ++# CONFIG_Q40 is not set ++# CONFIG_SUN3 is not set ++ ++# ++# Processor type ++# ++# CONFIG_M68020 is not set ++# CONFIG_M68030 is not set ++# CONFIG_M68040 is not set ++# CONFIG_M68060 is not set ++# CONFIG_M5445X is not set ++# CONFIG_HAVE_FSL_USB_DR is not set ++CONFIG_M547X_8X=y ++CONFIG_M547X=y ++# CONFIG_M548X is not set ++CONFIG_M5474LITE=y ++# CONFIG_M5475AFE is not set ++# CONFIG_M5475BFE is not set ++# CONFIG_M5475CFE is not set ++# CONFIG_M5475DFE is not set ++# CONFIG_M5475EFE is not set ++# CONFIG_M5475FFE is not set ++# CONFIG_M5484LITE is not set ++# CONFIG_M5485AFE is not set ++# CONFIG_M5485BFE is not set ++# CONFIG_M5485CFE is not set ++# CONFIG_M5485DFE is not set ++# CONFIG_M5485EFE is not set ++# CONFIG_M5485FFE is not set ++# CONFIG_M5441X is not set ++CONFIG_MCFCLK=266000000 ++# CONFIG_MCF_USER_HALT is not set ++CONFIG_MMU_CFV4E=y ++CONFIG_SDRAM_BASE=0x00000000 ++CONFIG_SDRAM_SIZE=0x04000000 ++CONFIG_NOR_FLASH_BASE=0xFF800000 ++CONFIG_DMA_BASE=0xef000000 ++CONFIG_DMA_SIZE=0x800000 ++CONFIG_VDSO=y ++# CONFIG_M68KFPU_EMU is not set ++CONFIG_ADVANCED=y ++# CONFIG_RMW_INSNS is not set ++CONFIG_SINGLE_MEMORY_CHUNK=y ++# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set ++CONFIG_SELECT_MEMORY_MODEL=y ++CONFIG_FLATMEM_MANUAL=y ++# CONFIG_DISCONTIGMEM_MANUAL is not set ++# CONFIG_SPARSEMEM_MANUAL is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_NEED_MULTIPLE_NODES=y ++CONFIG_PAGEFLAGS_EXTENDED=y ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++CONFIG_ZONE_DMA_FLAG=1 ++CONFIG_BOUNCE=y ++CONFIG_VIRT_TO_BUS=y ++CONFIG_UNEVICTABLE_LRU=y ++ ++# ++# General setup ++# ++CONFIG_BINFMT_ELF=y ++# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set ++CONFIG_HAVE_AOUT=y ++# CONFIG_BINFMT_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_PROC_HARDWARE=y ++CONFIG_ZONE_DMA=y ++# CONFIG_ARCH_SUPPORTS_MSI is not set ++CONFIG_PCI_LEGACY=y ++# CONFIG_PCI_STUB is not set ++ ++# ++# Power management options ++# ++# CONFIG_PM is not set ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_COMPAT_NET_DEV_OPS=y ++CONFIG_PACKET=y ++# CONFIG_PACKET_MMAP is not set ++CONFIG_UNIX=y ++CONFIG_XFRM=y ++# CONFIG_XFRM_USER is not set ++# CONFIG_XFRM_SUB_POLICY is not set ++# CONFIG_XFRM_MIGRATE is not set ++# CONFIG_XFRM_STATISTICS is not set ++CONFIG_NET_KEY=y ++# CONFIG_NET_KEY_MIGRATE is not set ++CONFIG_INET=y ++# CONFIG_IP_MULTICAST is not set ++CONFIG_IP_ADVANCED_ROUTER=y ++CONFIG_ASK_IP_FIB_HASH=y ++# CONFIG_IP_FIB_TRIE is not set ++CONFIG_IP_FIB_HASH=y ++# CONFIG_IP_MULTIPLE_TABLES is not set ++# CONFIG_IP_ROUTE_MULTIPATH is not set ++# CONFIG_IP_ROUTE_VERBOSE is not set ++CONFIG_IP_PNP=y ++# CONFIG_IP_PNP_DHCP is not set ++# CONFIG_IP_PNP_BOOTP is not set ++# CONFIG_IP_PNP_RARP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE is not set ++# CONFIG_ARPD is not set ++# CONFIG_SYN_COOKIES is not set ++CONFIG_INET_AH=y ++CONFIG_INET_ESP=y ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_LRO is not set ++CONFIG_INET_DIAG=y ++CONFIG_INET_TCP_DIAG=y ++# CONFIG_TCP_CONG_ADVANCED is not set ++CONFIG_TCP_CONG_CUBIC=y ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_BRIDGE is not set ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_ECONET is not set ++# CONFIG_WAN_ROUTER is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++CONFIG_CAN=y ++CONFIG_CAN_RAW=y ++# CONFIG_CAN_BCM is not set ++ ++# ++# CAN Device Drivers ++# ++# CONFIG_CAN_VCAN is not set ++# CONFIG_CAN_DEV is not set ++CONFIG_CAN_FLEXCAN=y ++# CONFIG_CAN_DEBUG_DEVICES is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_PHONET is not set ++CONFIG_WIRELESS=y ++# CONFIG_CFG80211 is not set ++CONFIG_WIRELESS_OLD_REGULATORY=y ++# CONFIG_WIRELESS_EXT is not set ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_KLIPS is not set ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ++# CONFIG_STANDALONE is not set ++CONFIG_PREVENT_FIRMWARE_BUILD=y ++CONFIG_FW_LOADER=y ++CONFIG_FIRMWARE_IN_KERNEL=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++# CONFIG_MTD_DEBUG is not set ++CONFIG_MTD_CONCAT=y ++CONFIG_MTD_PARTITIONS=y ++# CONFIG_MTD_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_CHAR=y ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_MTD_OOPS is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++CONFIG_MTD_CFI=y ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_GEN_PROBE=y ++# CONFIG_MTD_CFI_ADV_OPTIONS is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_CFI_INTELEXT=y ++CONFIG_MTD_CFI_AMDSTD=y ++CONFIG_MTD_CFI_STAA=y ++CONFIG_MTD_CFI_UTIL=y ++CONFIG_MTD_RAM=y ++CONFIG_MTD_ROM=y ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP=y ++CONFIG_MTD_PHYSMAP_COMPAT=y ++CONFIG_MTD_PHYSMAP_START=0xff800000 ++CONFIG_MTD_PHYSMAP_LEN=0x400000 ++CONFIG_MTD_PHYSMAP_BANKWIDTH=2 ++# CONFIG_MTD_INTEL_VR_NOR is not set ++# CONFIG_MTD_PLATRAM is not set ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_PMC551 is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOC2000 is not set ++# CONFIG_MTD_DOC2001 is not set ++# CONFIG_MTD_DOC2001PLUS is not set ++# CONFIG_MTD_NAND is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR flash memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++ ++# ++# UBI - Unsorted block images ++# ++# CONFIG_MTD_UBI is not set ++# CONFIG_PARPORT is not set ++CONFIG_BLK_DEV=y ++# CONFIG_BLK_CPQ_DA is not set ++# CONFIG_BLK_CPQ_CISS_DA is not set ++# CONFIG_BLK_DEV_DAC960 is not set ++# CONFIG_BLK_DEV_UMEM is not set ++# CONFIG_BLK_DEV_COW_COMMON is not set ++CONFIG_BLK_DEV_LOOP=y ++# CONFIG_BLK_DEV_CRYPTOLOOP is not set ++# CONFIG_BLK_DEV_NBD is not set ++# CONFIG_BLK_DEV_SX8 is not set ++CONFIG_BLK_DEV_RAM=y ++CONFIG_BLK_DEV_RAM_COUNT=16 ++CONFIG_BLK_DEV_RAM_SIZE=64000 ++# CONFIG_BLK_DEV_XIP is not set ++# CONFIG_CDROM_PKTCDVD is not set ++# CONFIG_ATA_OVER_ETH is not set ++# CONFIG_BLK_DEV_HD is not set ++CONFIG_MISC_DEVICES=y ++# CONFIG_PHANTOM is not set ++# CONFIG_SGI_IOC4 is not set ++# CONFIG_TIFM_CORE is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_HP_ILO is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++# CONFIG_EEPROM_AT24 is not set ++# CONFIG_EEPROM_LEGACY is not set ++# CONFIG_EEPROM_93CX6 is not set ++CONFIG_HAVE_IDE=y ++CONFIG_IDE=y ++ ++# ++# Please see Documentation/ide/ide.txt for help/info on IDE drives ++# ++# CONFIG_BLK_DEV_IDE_SATA is not set ++CONFIG_IDE_GD=y ++CONFIG_IDE_GD_ATA=y ++# CONFIG_IDE_GD_ATAPI is not set ++# CONFIG_BLK_DEV_IDECD is not set ++# CONFIG_BLK_DEV_IDETAPE is not set ++# CONFIG_IDE_TASK_IOCTL is not set ++CONFIG_IDE_PROC_FS=y ++ ++# ++# IDE chipset support/bugfixes ++# ++# CONFIG_BLK_DEV_PLATFORM is not set ++ ++# ++# PCI IDE chipsets support ++# ++# CONFIG_BLK_DEV_GENERIC is not set ++# CONFIG_BLK_DEV_OPTI621 is not set ++# CONFIG_BLK_DEV_AEC62XX is not set ++# CONFIG_BLK_DEV_ALI15X3 is not set ++# CONFIG_BLK_DEV_AMD74XX is not set ++# CONFIG_BLK_DEV_CMD64X is not set ++# CONFIG_BLK_DEV_TRIFLEX is not set ++# CONFIG_BLK_DEV_CS5520 is not set ++# CONFIG_BLK_DEV_CS5530 is not set ++# CONFIG_BLK_DEV_HPT366 is not set ++# CONFIG_BLK_DEV_JMICRON is not set ++# CONFIG_BLK_DEV_SC1200 is not set ++# CONFIG_BLK_DEV_PIIX is not set ++# CONFIG_BLK_DEV_IT8172 is not set ++# CONFIG_BLK_DEV_IT8213 is not set ++# CONFIG_BLK_DEV_IT821X is not set ++# CONFIG_BLK_DEV_NS87415 is not set ++# CONFIG_BLK_DEV_PDC202XX_OLD is not set ++# CONFIG_BLK_DEV_PDC202XX_NEW is not set ++# CONFIG_BLK_DEV_SVWKS is not set ++# CONFIG_BLK_DEV_SIIMAGE is not set ++# CONFIG_BLK_DEV_SLC90E66 is not set ++# CONFIG_BLK_DEV_TRM290 is not set ++# CONFIG_BLK_DEV_VIA82CXXX is not set ++# CONFIG_BLK_DEV_TC86C001 is not set ++# CONFIG_BLK_DEV_IDEDMA is not set ++ ++# ++# SCSI device support ++# ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_TGT is not set ++# CONFIG_SCSI_NETLINK is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++ ++# ++# Some SCSI devices (e.g. CD jukebox) support multiple LUNs ++# ++CONFIG_SCSI_MULTI_LUN=y ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++CONFIG_SCSI_WAIT_SCAN=m ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++# CONFIG_SCSI_LOWLEVEL is not set ++# CONFIG_SCSI_DH is not set ++CONFIG_ATA=y ++# CONFIG_ATA_NONSTANDARD is not set ++CONFIG_SATA_PMP=y ++# CONFIG_SATA_AHCI is not set ++CONFIG_SATA_SIL24=y ++CONFIG_ATA_SFF=y ++# CONFIG_SATA_SVW is not set ++# CONFIG_ATA_PIIX is not set ++# CONFIG_SATA_MV is not set ++# CONFIG_SATA_NV is not set ++# CONFIG_PDC_ADMA is not set ++# CONFIG_SATA_QSTOR is not set ++# CONFIG_SATA_PROMISE is not set ++# CONFIG_SATA_SX4 is not set ++CONFIG_SATA_SIL=y ++# CONFIG_SATA_SIS is not set ++# CONFIG_SATA_ULI is not set ++# CONFIG_SATA_VIA is not set ++# CONFIG_SATA_VITESSE is not set ++# CONFIG_SATA_INIC162X is not set ++# CONFIG_PATA_ALI is not set ++# CONFIG_PATA_AMD is not set ++# CONFIG_PATA_ARTOP is not set ++# CONFIG_PATA_ATIIXP is not set ++# CONFIG_PATA_CMD640_PCI is not set ++# CONFIG_PATA_CMD64X is not set ++# CONFIG_PATA_CS5520 is not set ++# CONFIG_PATA_CS5530 is not set ++# CONFIG_PATA_CYPRESS is not set ++# CONFIG_PATA_EFAR is not set ++# CONFIG_ATA_GENERIC is not set ++# CONFIG_PATA_HPT366 is not set ++# CONFIG_PATA_HPT37X is not set ++# CONFIG_PATA_HPT3X2N is not set ++# CONFIG_PATA_HPT3X3 is not set ++# CONFIG_PATA_IT821X is not set ++# CONFIG_PATA_IT8213 is not set ++# CONFIG_PATA_JMICRON is not set ++# CONFIG_PATA_TRIFLEX is not set ++# CONFIG_PATA_MARVELL is not set ++# CONFIG_PATA_MPIIX is not set ++# CONFIG_PATA_OLDPIIX is not set ++# CONFIG_PATA_NETCELL is not set ++# CONFIG_PATA_NINJA32 is not set ++# CONFIG_PATA_NS87410 is not set ++# CONFIG_PATA_NS87415 is not set ++# CONFIG_PATA_OPTI is not set ++# CONFIG_PATA_OPTIDMA is not set ++# CONFIG_PATA_PDC_OLD is not set ++# CONFIG_PATA_RADISYS is not set ++# CONFIG_PATA_RZ1000 is not set ++# CONFIG_PATA_SC1200 is not set ++# CONFIG_PATA_SERVERWORKS is not set ++# CONFIG_PATA_PDC2027X is not set ++# CONFIG_PATA_SIL680 is not set ++# CONFIG_PATA_SIS is not set ++# CONFIG_PATA_VIA is not set ++# CONFIG_PATA_WINBOND is not set ++# CONFIG_PATA_SCH is not set ++# CONFIG_MD is not set ++# CONFIG_FUSION is not set ++ ++# ++# IEEE 1394 (FireWire) support ++# ++ ++# ++# Enable only one of the two stacks, unless you know what you are doing ++# ++# CONFIG_FIREWIRE is not set ++# CONFIG_IEEE1394 is not set ++# CONFIG_I2O is not set ++CONFIG_NETDEVICES=y ++# CONFIG_DUMMY is not set ++# CONFIG_BONDING is not set ++# CONFIG_MACVLAN is not set ++# CONFIG_EQUALIZER is not set ++# CONFIG_TUN is not set ++# CONFIG_VETH is not set ++# CONFIG_ARCNET is not set ++CONFIG_PHYLIB=y ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++CONFIG_BROADCOM5222_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_NATIONAL8364x_PHY is not set ++# CONFIG_NATIONAL8384x_PHY is not set ++# CONFIG_MicrelKSZ8041_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_FIXED_PHY is not set ++# CONFIG_MDIO_BITBANG is not set ++CONFIG_NET_ETHERNET=y ++CONFIG_MII=y ++# CONFIG_HAPPYMEAL is not set ++# CONFIG_SUNGEM is not set ++# CONFIG_CASSINI is not set ++# CONFIG_NET_VENDOR_3COM is not set ++# CONFIG_DNET is not set ++# CONFIG_NET_TULIP is not set ++# CONFIG_HP100 is not set ++# CONFIG_IBM_NEW_EMAC_ZMII is not set ++# CONFIG_IBM_NEW_EMAC_RGMII is not set ++# CONFIG_IBM_NEW_EMAC_TAH is not set ++# CONFIG_IBM_NEW_EMAC_EMAC4 is not set ++# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set ++# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set ++# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set ++CONFIG_NET_PCI=y ++# CONFIG_PCNET32 is not set ++# CONFIG_AMD8111_ETH is not set ++# CONFIG_ADAPTEC_STARFIRE is not set ++# CONFIG_B44 is not set ++# CONFIG_FORCEDETH is not set ++CONFIG_E100=y ++# CONFIG_FEALNX is not set ++# CONFIG_NATSEMI is not set ++CONFIG_NE2K_PCI=y ++# CONFIG_8139CP is not set ++CONFIG_8139TOO=y ++CONFIG_8139TOO_PIO=y ++# CONFIG_8139TOO_TUNE_TWISTER is not set ++# CONFIG_8139TOO_8129 is not set ++# CONFIG_8139_OLD_RX_RESET is not set ++# CONFIG_R6040 is not set ++# CONFIG_SIS900 is not set ++# CONFIG_EPIC100 is not set ++# CONFIG_SMSC9420 is not set ++# CONFIG_SUNDANCE is not set ++# CONFIG_TLAN is not set ++# CONFIG_VIA_RHINE is not set ++# CONFIG_SC92031 is not set ++CONFIG_FEC_548x=y ++CONFIG_FEC_548x_ENABLE_FEC2=y ++CONFIG_FEC_548x_SHARED_PHY=y ++# CONFIG_ATL2 is not set ++CONFIG_NETDEV_1000=y ++# CONFIG_ACENIC is not set ++# CONFIG_DL2K is not set ++CONFIG_E1000=y ++# CONFIG_E1000E is not set ++# CONFIG_IP1000 is not set ++# CONFIG_IGB is not set ++# CONFIG_NS83820 is not set ++# CONFIG_HAMACHI is not set ++# CONFIG_YELLOWFIN is not set ++# CONFIG_R8169 is not set ++# CONFIG_SIS190 is not set ++# CONFIG_SKGE is not set ++# CONFIG_SKY2 is not set ++# CONFIG_VIA_VELOCITY is not set ++# CONFIG_TIGON3 is not set ++# CONFIG_BNX2 is not set ++# CONFIG_QLA3XXX is not set ++# CONFIG_ATL1 is not set ++# CONFIG_ATL1E is not set ++# CONFIG_ATL1C is not set ++# CONFIG_JME is not set ++# CONFIG_NETDEV_10000 is not set ++# CONFIG_TR is not set ++ ++# ++# Wireless LAN ++# ++# CONFIG_WLAN_PRE80211 is not set ++# CONFIG_WLAN_80211 is not set ++# CONFIG_IWLWIFI_LEDS is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_FDDI is not set ++# CONFIG_HIPPI is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++# CONFIG_NET_FC is not set ++# CONFIG_NETCONSOLE is not set ++# CONFIG_NETPOLL is not set ++# CONFIG_NET_POLL_CONTROLLER is not set ++# CONFIG_ISDN is not set ++# CONFIG_PHONE is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++# CONFIG_INPUT_MOUSEDEV_PSAUX is not set ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 ++# CONFIG_INPUT_JOYDEV is not set ++CONFIG_INPUT_EVDEV=y ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++CONFIG_INPUT_KEYBOARD=y ++# CONFIG_KEYBOARD_ATKBD is not set ++# CONFIG_KEYBOARD_SUNKBD is not set ++# CONFIG_KEYBOARD_LKKBD is not set ++# CONFIG_KEYBOARD_XTKBD is not set ++# CONFIG_KEYBOARD_NEWTON is not set ++# CONFIG_KEYBOARD_STOWAWAY is not set ++# CONFIG_INPUT_MOUSE is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++# CONFIG_INPUT_TOUCHSCREEN is not set ++# CONFIG_INPUT_MISC is not set ++ ++# ++# Hardware I/O ports ++# ++CONFIG_SERIO=y ++CONFIG_SERIO_SERPORT=y ++# CONFIG_SERIO_PCIPS2 is not set ++# CONFIG_SERIO_RAW is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_VT=y ++CONFIG_CONSOLE_TRANSLATIONS=y ++CONFIG_VT_CONSOLE=y ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++CONFIG_DEVKMEM=y ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_NOZOMI is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_COLDFIRE_IRDA is not set ++# CONFIG_SERIAL_COLDFIRE_EDMA is not set ++CONFIG_SERIAL_MCF=y ++CONFIG_SERIAL_MCF_BAUDRATE=115200 ++CONFIG_SERIAL_MCF_CONSOLE=y ++# CONFIG_SERIAL_JSM is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_GEN_RTC is not set ++# CONFIG_R3964 is not set ++# CONFIG_APPLICOM is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_CHARDEV is not set ++CONFIG_I2C_HELPER_AUTO=y ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# PC SMBus host controller drivers ++# ++# CONFIG_I2C_ALI1535 is not set ++# CONFIG_I2C_ALI1563 is not set ++# CONFIG_I2C_ALI15X3 is not set ++# CONFIG_I2C_AMD756 is not set ++# CONFIG_I2C_AMD8111 is not set ++# CONFIG_I2C_I801 is not set ++# CONFIG_I2C_ISCH is not set ++# CONFIG_I2C_PIIX4 is not set ++# CONFIG_I2C_NFORCE2 is not set ++# CONFIG_I2C_SIS5595 is not set ++# CONFIG_I2C_SIS630 is not set ++# CONFIG_I2C_SIS96X is not set ++# CONFIG_I2C_VIA is not set ++# CONFIG_I2C_VIAPRO is not set ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++CONFIG_I2C_MCF=y ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_SIMTEC is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_TAOS_EVM is not set ++ ++# ++# Graphics adapter I2C/DDC channel drivers ++# ++# CONFIG_I2C_VOODOO3 is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_STUB is not set ++ ++# ++# Miscellaneous I2C Chip support ++# ++# CONFIG_DS1682 is not set ++# CONFIG_SENSORS_PCF8574 is not set ++# CONFIG_PCF8575 is not set ++# CONFIG_SENSORS_PCA9539 is not set ++# CONFIG_SENSORS_PCF8591 is not set ++# CONFIG_SENSORS_MAX6875 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++# CONFIG_I2C_DEBUG_CHIP is not set ++# CONFIG_SPI is not set ++# CONFIG_W1 is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++# CONFIG_THERMAL_HWMON is not set ++# CONFIG_WATCHDOG is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_REGULATOR is not set ++ ++# ++# Multimedia devices ++# ++ ++# ++# Multimedia core support ++# ++# CONFIG_VIDEO_DEV is not set ++# CONFIG_DVB_CORE is not set ++# CONFIG_VIDEO_MEDIA is not set ++ ++# ++# Multimedia drivers ++# ++CONFIG_DAB=y ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++# CONFIG_VGASTATE is not set ++CONFIG_VIDEO_OUTPUT_CONTROL=m ++# CONFIG_FB is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++ ++# ++# Display device support ++# ++# CONFIG_DISPLAY_SUPPORT is not set ++ ++# ++# Console display driver support ++# ++CONFIG_DUMMY_CONSOLE=y ++# CONFIG_SOUND is not set ++# CONFIG_HID_SUPPORT is not set ++# CONFIG_USB_SUPPORT is not set ++# CONFIG_UWB is not set ++# CONFIG_MMC is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++# CONFIG_INFINIBAND is not set ++# CONFIG_RTC_CLASS is not set ++# CONFIG_DMADEVICES is not set ++# CONFIG_UIO is not set ++# CONFIG_STAGING is not set ++ ++# ++# Character devices ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++CONFIG_GENERIC_CLOCKEVENTS_BUILD=y ++ ++# ++# File systems ++# ++CONFIG_EXT2_FS=y ++# CONFIG_EXT2_FS_XATTR is not set ++# CONFIG_EXT2_FS_XIP is not set ++CONFIG_EXT3_FS=y ++CONFIG_EXT3_FS_XATTR=y ++# CONFIG_EXT3_FS_POSIX_ACL is not set ++# CONFIG_EXT3_FS_SECURITY is not set ++# CONFIG_EXT4_FS is not set ++CONFIG_JBD=y ++CONFIG_FS_MBCACHE=y ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_FS_POSIX_ACL is not set ++CONFIG_FILE_LOCKING=y ++# CONFIG_XFS_FS is not set ++# CONFIG_GFS2_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++CONFIG_DNOTIFY=y ++# CONFIG_INOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_AUTOFS_FS is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=y ++CONFIG_MSDOS_FS=y ++CONFIG_VFAT_FS=y ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++CONFIG_NTFS_FS=y ++# CONFIG_NTFS_DEBUG is not set ++CONFIG_NTFS_RW=y ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++# CONFIG_PROC_KCORE is not set ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++# CONFIG_TMPFS_POSIX_ACL is not set ++# CONFIG_HUGETLB_PAGE is not set ++# CONFIG_CONFIGFS_FS is not set ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++# CONFIG_JFFS2_FS is not set ++# CONFIG_CRAMFS is not set ++# CONFIG_SQUASHFS is not set ++# CONFIG_VXFS_FS is not set ++CONFIG_MINIX_FS=y ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++CONFIG_ROMFS_FS=y ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=y ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++CONFIG_ROOT_NFS=y ++# CONFIG_NFSD is not set ++CONFIG_LOCKD=y ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=y ++# CONFIG_SUNRPC_REGISTER_V4 is not set ++# CONFIG_RPCSEC_GSS_KRB5 is not set ++# CONFIG_RPCSEC_GSS_SPKM3 is not set ++# CONFIG_SMB_FS is not set ++# CONFIG_CIFS is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++ ++# ++# Partition Types ++# ++CONFIG_PARTITION_ADVANCED=y ++# CONFIG_ACORN_PARTITION is not set ++# CONFIG_OSF_PARTITION is not set ++# CONFIG_AMIGA_PARTITION is not set ++# CONFIG_ATARI_PARTITION is not set ++# CONFIG_MAC_PARTITION is not set ++CONFIG_MSDOS_PARTITION=y ++# CONFIG_BSD_DISKLABEL is not set ++# CONFIG_MINIX_SUBPARTITION is not set ++# CONFIG_SOLARIS_X86_PARTITION is not set ++# CONFIG_UNIXWARE_DISKLABEL is not set ++# CONFIG_LDM_PARTITION is not set ++# CONFIG_SGI_PARTITION is not set ++# CONFIG_ULTRIX_PARTITION is not set ++# CONFIG_SUN_PARTITION is not set ++# CONFIG_KARMA_PARTITION is not set ++# CONFIG_EFI_PARTITION is not set ++# CONFIG_SYSV68_PARTITION is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++CONFIG_NLS_UTF8=y ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++# CONFIG_ENABLE_MUST_CHECK is not set ++CONFIG_FRAME_WARN=1024 ++# CONFIG_MAGIC_SYSRQ is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_DEBUG_FS is not set ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_KERNEL is not set ++CONFIG_DEBUG_BUGVERBOSE=y ++CONFIG_DEBUG_MEMORY_INIT=y ++# CONFIG_RCU_CPU_STALL_DETECTOR is not set ++# CONFIG_SYSCTL_SYSCALL_CHECK is not set ++ ++# ++# Tracers ++# ++# CONFIG_DYNAMIC_PRINTK_DEBUG is not set ++# CONFIG_SAMPLES is not set ++# CONFIG_BOOTPARAM is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++# CONFIG_SECURITY_FILE_CAPABILITIES is not set ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++# CONFIG_CRYPTO_FIPS is not set ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_GF128MUL is not set ++# CONFIG_CRYPTO_NULL is not set ++# CONFIG_CRYPTO_CRYPTD is not set ++CONFIG_CRYPTO_AUTHENC=y ++CONFIG_CRYPTO_TEST=m ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_SEQIV is not set ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++# CONFIG_CRYPTO_CTR is not set ++# CONFIG_CRYPTO_CTS is not set ++# CONFIG_CRYPTO_ECB is not set ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++ ++# ++# Digest ++# ++CONFIG_CRYPTO_CRC32C=y ++# CONFIG_CRYPTO_MD4 is not set ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++CONFIG_CRYPTO_SHA1=y ++# CONFIG_CRYPTO_SHA256 is not set ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++# CONFIG_CRYPTO_AES is not set ++# CONFIG_CRYPTO_ANUBIS is not set ++# CONFIG_CRYPTO_ARC4 is not set ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++# CONFIG_CRYPTO_DEFLATE is not set ++# CONFIG_CRYPTO_LZO is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++ ++# ++# OCF Configuration ++# ++# CONFIG_OCF_OCF is not set ++ ++# ++# Talitos Driver ++# ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_GENERIC_FIND_LAST_BIT=y ++CONFIG_CRC_CCITT=y ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC7 is not set ++CONFIG_LIBCRC32C=y ++CONFIG_PLIST=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT=y ++CONFIG_HAS_DMA=y +--- /dev/null ++++ b/arch/m68k/configs/m5475evb_defconfig +@@ -0,0 +1,1324 @@ ++# ++# Automatically generated make config: don't edit ++# Linux kernel version: 2.6.29 ++# Tue Aug 24 15:41:10 2010 ++# ++CONFIG_M68K=y ++CONFIG_MMU=y ++CONFIG_GENERIC_TIME=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_RWSEM_GENERIC_SPINLOCK=y ++# CONFIG_ARCH_HAS_ILOG2_U32 is not set ++# CONFIG_ARCH_HAS_ILOG2_U64 is not set ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++# CONFIG_TIME_LOW_RES is not set ++CONFIG_GENERIC_IOMAP=y ++# CONFIG_NO_IOPORT is not set ++# CONFIG_NO_DMA is not set ++CONFIG_HZ=100 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++ ++# ++# General setup ++# ++CONFIG_EXPERIMENTAL=y ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_SWAP=y ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++# CONFIG_POSIX_MQUEUE is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++# CONFIG_AUDIT is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_CLASSIC_RCU=y ++# CONFIG_TREE_RCU is not set ++# CONFIG_PREEMPT_RCU is not set ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_PREEMPT_RCU_TRACE is not set ++CONFIG_IKCONFIG=y ++CONFIG_IKCONFIG_PROC=y ++CONFIG_LOG_BUF_SHIFT=17 ++CONFIG_GROUP_SCHED=y ++CONFIG_FAIR_GROUP_SCHED=y ++# CONFIG_RT_GROUP_SCHED is not set ++CONFIG_USER_SCHED=y ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUPS is not set ++CONFIG_SYSFS_DEPRECATED=y ++CONFIG_SYSFS_DEPRECATED_V2=y ++# CONFIG_RELAY is not set ++CONFIG_NAMESPACES=y ++# CONFIG_UTS_NS is not set ++# CONFIG_IPC_NS is not set ++# CONFIG_USER_NS is not set ++# CONFIG_PID_NS is not set ++# CONFIG_NET_NS is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++# CONFIG_EMBEDDED is not set ++CONFIG_UID16=y ++CONFIG_SYSCTL_SYSCALL=y ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_EXTRA_PASS=y ++CONFIG_HOTPLUG=y ++CONFIG_PRINTK=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++CONFIG_VM_EVENT_COUNTERS=y ++CONFIG_PCI_QUIRKS=y ++CONFIG_COMPAT_BRK=y ++CONFIG_SLAB=y ++# CONFIG_SLUB is not set ++# CONFIG_SLOB is not set ++# CONFIG_PROFILING is not set ++# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set ++CONFIG_SLABINFO=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=0 ++CONFIG_MODULES=y ++# CONFIG_MODULE_FORCE_LOAD is not set ++CONFIG_MODULE_UNLOAD=y ++CONFIG_MODULE_FORCE_UNLOAD=y ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++CONFIG_BLOCK=y ++CONFIG_LBD=y ++# CONFIG_BLK_DEV_IO_TRACE is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_AS=y ++CONFIG_IOSCHED_DEADLINE=y ++CONFIG_IOSCHED_CFQ=y ++# CONFIG_DEFAULT_AS is not set ++# CONFIG_DEFAULT_DEADLINE is not set ++CONFIG_DEFAULT_CFQ=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="cfq" ++# CONFIG_FREEZER is not set ++ ++# ++# Platform dependent setup ++# ++CONFIG_COLDFIRE=y ++CONFIG_CFV4E=y ++# CONFIG_FPU is not set ++CONFIG_MCD_DMA=y ++# CONFIG_AMIGA is not set ++# CONFIG_ATARI is not set ++CONFIG_PCI=y ++# CONFIG_MAC is not set ++# CONFIG_APOLLO is not set ++# CONFIG_VME is not set ++# CONFIG_HP300 is not set ++# CONFIG_SUN3X is not set ++# CONFIG_Q40 is not set ++# CONFIG_SUN3 is not set ++ ++# ++# Processor type ++# ++# CONFIG_M68020 is not set ++# CONFIG_M68030 is not set ++# CONFIG_M68040 is not set ++# CONFIG_M68060 is not set ++# CONFIG_M5445X is not set ++# CONFIG_HAVE_FSL_USB_DR is not set ++CONFIG_M547X_8X=y ++CONFIG_M547X=y ++# CONFIG_M548X is not set ++# CONFIG_M5474LITE is not set ++# CONFIG_M5475AFE is not set ++# CONFIG_M5475BFE is not set ++CONFIG_M5475CFE=y ++# CONFIG_M5475DFE is not set ++# CONFIG_M5475EFE is not set ++# CONFIG_M5475FFE is not set ++# CONFIG_M5484LITE is not set ++# CONFIG_M5485AFE is not set ++# CONFIG_M5485BFE is not set ++# CONFIG_M5485CFE is not set ++# CONFIG_M5485DFE is not set ++# CONFIG_M5485EFE is not set ++# CONFIG_M5485FFE is not set ++# CONFIG_M5441X is not set ++CONFIG_MCFCLK=266000000 ++# CONFIG_MCF_USER_HALT is not set ++CONFIG_MMU_CFV4E=y ++CONFIG_SDRAM_BASE=0x00000000 ++CONFIG_SDRAM_SIZE=0x04000000 ++CONFIG_NOR_FLASH_BASE=0xE0000000 ++CONFIG_DMA_BASE=0xef000000 ++CONFIG_DMA_SIZE=0x800000 ++CONFIG_VDSO=y ++# CONFIG_M68KFPU_EMU is not set ++CONFIG_ADVANCED=y ++# CONFIG_RMW_INSNS is not set ++CONFIG_SINGLE_MEMORY_CHUNK=y ++# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set ++CONFIG_SELECT_MEMORY_MODEL=y ++CONFIG_FLATMEM_MANUAL=y ++# CONFIG_DISCONTIGMEM_MANUAL is not set ++# CONFIG_SPARSEMEM_MANUAL is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_NEED_MULTIPLE_NODES=y ++CONFIG_PAGEFLAGS_EXTENDED=y ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++CONFIG_ZONE_DMA_FLAG=1 ++CONFIG_BOUNCE=y ++CONFIG_VIRT_TO_BUS=y ++CONFIG_UNEVICTABLE_LRU=y ++ ++# ++# General setup ++# ++CONFIG_BINFMT_ELF=y ++# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set ++CONFIG_HAVE_AOUT=y ++# CONFIG_BINFMT_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_PROC_HARDWARE=y ++CONFIG_ZONE_DMA=y ++# CONFIG_ARCH_SUPPORTS_MSI is not set ++CONFIG_PCI_LEGACY=y ++# CONFIG_PCI_STUB is not set ++ ++# ++# Power management options ++# ++CONFIG_PM=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_COMPAT_NET_DEV_OPS=y ++CONFIG_PACKET=y ++# CONFIG_PACKET_MMAP is not set ++CONFIG_UNIX=y ++CONFIG_XFRM=y ++# CONFIG_XFRM_USER is not set ++# CONFIG_XFRM_SUB_POLICY is not set ++# CONFIG_XFRM_MIGRATE is not set ++# CONFIG_XFRM_STATISTICS is not set ++CONFIG_NET_KEY=y ++# CONFIG_NET_KEY_MIGRATE is not set ++CONFIG_INET=y ++# CONFIG_IP_MULTICAST is not set ++CONFIG_IP_ADVANCED_ROUTER=y ++CONFIG_ASK_IP_FIB_HASH=y ++# CONFIG_IP_FIB_TRIE is not set ++CONFIG_IP_FIB_HASH=y ++# CONFIG_IP_MULTIPLE_TABLES is not set ++# CONFIG_IP_ROUTE_MULTIPATH is not set ++# CONFIG_IP_ROUTE_VERBOSE is not set ++CONFIG_IP_PNP=y ++# CONFIG_IP_PNP_DHCP is not set ++# CONFIG_IP_PNP_BOOTP is not set ++# CONFIG_IP_PNP_RARP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE is not set ++# CONFIG_ARPD is not set ++# CONFIG_SYN_COOKIES is not set ++CONFIG_INET_AH=y ++CONFIG_INET_ESP=y ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_LRO is not set ++CONFIG_INET_DIAG=y ++CONFIG_INET_TCP_DIAG=y ++# CONFIG_TCP_CONG_ADVANCED is not set ++CONFIG_TCP_CONG_CUBIC=y ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_BRIDGE is not set ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_ECONET is not set ++# CONFIG_WAN_ROUTER is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++CONFIG_CAN=y ++CONFIG_CAN_RAW=y ++# CONFIG_CAN_BCM is not set ++ ++# ++# CAN Device Drivers ++# ++# CONFIG_CAN_VCAN is not set ++# CONFIG_CAN_DEV is not set ++# CONFIG_CAN_FLEXCAN is not set ++# CONFIG_CAN_DEBUG_DEVICES is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_PHONET is not set ++CONFIG_WIRELESS=y ++# CONFIG_CFG80211 is not set ++CONFIG_WIRELESS_OLD_REGULATORY=y ++# CONFIG_WIRELESS_EXT is not set ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_KLIPS is not set ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ++# CONFIG_STANDALONE is not set ++CONFIG_PREVENT_FIRMWARE_BUILD=y ++CONFIG_FW_LOADER=y ++CONFIG_FIRMWARE_IN_KERNEL=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++# CONFIG_MTD_DEBUG is not set ++# CONFIG_MTD_CONCAT is not set ++CONFIG_MTD_PARTITIONS=y ++# CONFIG_MTD_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++# CONFIG_MTD_CHAR is not set ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_MTD_OOPS is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++CONFIG_MTD_CFI=y ++CONFIG_MTD_JEDECPROBE=y ++CONFIG_MTD_GEN_PROBE=y ++# CONFIG_MTD_CFI_ADV_OPTIONS is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_CFI_INTELEXT=y ++CONFIG_MTD_CFI_AMDSTD=y ++# CONFIG_MTD_CFI_STAA is not set ++CONFIG_MTD_CFI_UTIL=y ++CONFIG_MTD_RAM=y ++CONFIG_MTD_ROM=y ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP=y ++CONFIG_MTD_PHYSMAP_COMPAT=y ++CONFIG_MTD_PHYSMAP_START=0xe0000000 ++CONFIG_MTD_PHYSMAP_LEN=0x1000000 ++CONFIG_MTD_PHYSMAP_BANKWIDTH=2 ++# CONFIG_MTD_INTEL_VR_NOR is not set ++# CONFIG_MTD_PLATRAM is not set ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_PMC551 is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOC2000 is not set ++# CONFIG_MTD_DOC2001 is not set ++# CONFIG_MTD_DOC2001PLUS is not set ++# CONFIG_MTD_NAND is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR flash memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++ ++# ++# UBI - Unsorted block images ++# ++# CONFIG_MTD_UBI is not set ++# CONFIG_PARPORT is not set ++CONFIG_BLK_DEV=y ++# CONFIG_BLK_CPQ_DA is not set ++# CONFIG_BLK_CPQ_CISS_DA is not set ++# CONFIG_BLK_DEV_DAC960 is not set ++# CONFIG_BLK_DEV_UMEM is not set ++# CONFIG_BLK_DEV_COW_COMMON is not set ++CONFIG_BLK_DEV_LOOP=y ++# CONFIG_BLK_DEV_CRYPTOLOOP is not set ++# CONFIG_BLK_DEV_NBD is not set ++# CONFIG_BLK_DEV_SX8 is not set ++# CONFIG_BLK_DEV_UB is not set ++CONFIG_BLK_DEV_RAM=y ++CONFIG_BLK_DEV_RAM_COUNT=16 ++CONFIG_BLK_DEV_RAM_SIZE=64000 ++# CONFIG_BLK_DEV_XIP is not set ++# CONFIG_CDROM_PKTCDVD is not set ++# CONFIG_ATA_OVER_ETH is not set ++# CONFIG_BLK_DEV_HD is not set ++CONFIG_MISC_DEVICES=y ++# CONFIG_PHANTOM is not set ++# CONFIG_SGI_IOC4 is not set ++# CONFIG_TIFM_CORE is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_HP_ILO is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++# CONFIG_EEPROM_AT24 is not set ++# CONFIG_EEPROM_LEGACY is not set ++# CONFIG_EEPROM_93CX6 is not set ++CONFIG_HAVE_IDE=y ++# CONFIG_IDE is not set ++ ++# ++# SCSI device support ++# ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_TGT is not set ++# CONFIG_SCSI_NETLINK is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++ ++# ++# Some SCSI devices (e.g. CD jukebox) support multiple LUNs ++# ++CONFIG_SCSI_MULTI_LUN=y ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++CONFIG_SCSI_WAIT_SCAN=m ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++# CONFIG_SCSI_LOWLEVEL is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_FUSION is not set ++ ++# ++# IEEE 1394 (FireWire) support ++# ++ ++# ++# Enable only one of the two stacks, unless you know what you are doing ++# ++# CONFIG_FIREWIRE is not set ++# CONFIG_IEEE1394 is not set ++# CONFIG_I2O is not set ++CONFIG_NETDEVICES=y ++# CONFIG_DUMMY is not set ++# CONFIG_BONDING is not set ++# CONFIG_MACVLAN is not set ++# CONFIG_EQUALIZER is not set ++# CONFIG_TUN is not set ++# CONFIG_VETH is not set ++# CONFIG_ARCNET is not set ++CONFIG_PHYLIB=y ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++CONFIG_BROADCOM5222_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_NATIONAL8364x_PHY is not set ++# CONFIG_NATIONAL8384x_PHY is not set ++# CONFIG_MicrelKSZ8041_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_FIXED_PHY is not set ++# CONFIG_MDIO_BITBANG is not set ++CONFIG_NET_ETHERNET=y ++CONFIG_MII=y ++# CONFIG_HAPPYMEAL is not set ++# CONFIG_SUNGEM is not set ++# CONFIG_CASSINI is not set ++# CONFIG_NET_VENDOR_3COM is not set ++# CONFIG_DNET is not set ++# CONFIG_NET_TULIP is not set ++# CONFIG_HP100 is not set ++# CONFIG_IBM_NEW_EMAC_ZMII is not set ++# CONFIG_IBM_NEW_EMAC_RGMII is not set ++# CONFIG_IBM_NEW_EMAC_TAH is not set ++# CONFIG_IBM_NEW_EMAC_EMAC4 is not set ++# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set ++# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set ++# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set ++# CONFIG_NET_PCI is not set ++# CONFIG_B44 is not set ++CONFIG_FEC_548x=y ++CONFIG_FEC_548x_ENABLE_FEC2=y ++CONFIG_FEC_548x_SHARED_PHY=y ++# CONFIG_ATL2 is not set ++# CONFIG_NETDEV_1000 is not set ++# CONFIG_NETDEV_10000 is not set ++# CONFIG_TR is not set ++ ++# ++# Wireless LAN ++# ++# CONFIG_WLAN_PRE80211 is not set ++# CONFIG_WLAN_80211 is not set ++# CONFIG_IWLWIFI_LEDS is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++ ++# ++# USB Network Adapters ++# ++# CONFIG_USB_CATC is not set ++# CONFIG_USB_KAWETH is not set ++# CONFIG_USB_PEGASUS is not set ++# CONFIG_USB_RTL8150 is not set ++# CONFIG_USB_USBNET is not set ++# CONFIG_WAN is not set ++# CONFIG_FDDI is not set ++# CONFIG_HIPPI is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++# CONFIG_NET_FC is not set ++# CONFIG_NETCONSOLE is not set ++# CONFIG_NETPOLL is not set ++# CONFIG_NET_POLL_CONTROLLER is not set ++# CONFIG_ISDN is not set ++# CONFIG_PHONE is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++# CONFIG_INPUT_MOUSEDEV_PSAUX is not set ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 ++# CONFIG_INPUT_JOYDEV is not set ++CONFIG_INPUT_EVDEV=y ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++CONFIG_INPUT_KEYBOARD=y ++# CONFIG_KEYBOARD_ATKBD is not set ++# CONFIG_KEYBOARD_SUNKBD is not set ++# CONFIG_KEYBOARD_LKKBD is not set ++# CONFIG_KEYBOARD_XTKBD is not set ++# CONFIG_KEYBOARD_NEWTON is not set ++# CONFIG_KEYBOARD_STOWAWAY is not set ++# CONFIG_INPUT_MOUSE is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++# CONFIG_INPUT_TOUCHSCREEN is not set ++# CONFIG_INPUT_MISC is not set ++ ++# ++# Hardware I/O ports ++# ++CONFIG_SERIO=y ++CONFIG_SERIO_SERPORT=y ++# CONFIG_SERIO_PCIPS2 is not set ++# CONFIG_SERIO_RAW is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_VT=y ++CONFIG_CONSOLE_TRANSLATIONS=y ++CONFIG_VT_CONSOLE=y ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++CONFIG_DEVKMEM=y ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_NOZOMI is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_COLDFIRE_IRDA is not set ++# CONFIG_SERIAL_COLDFIRE_EDMA is not set ++CONFIG_SERIAL_MCF=y ++CONFIG_SERIAL_MCF_BAUDRATE=115200 ++CONFIG_SERIAL_MCF_CONSOLE=y ++# CONFIG_SERIAL_JSM is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_APPLICOM is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++CONFIG_I2C_CHARDEV=y ++CONFIG_I2C_HELPER_AUTO=y ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# PC SMBus host controller drivers ++# ++# CONFIG_I2C_ALI1535 is not set ++# CONFIG_I2C_ALI1563 is not set ++# CONFIG_I2C_ALI15X3 is not set ++# CONFIG_I2C_AMD756 is not set ++# CONFIG_I2C_AMD8111 is not set ++# CONFIG_I2C_I801 is not set ++# CONFIG_I2C_ISCH is not set ++# CONFIG_I2C_PIIX4 is not set ++# CONFIG_I2C_NFORCE2 is not set ++# CONFIG_I2C_SIS5595 is not set ++# CONFIG_I2C_SIS630 is not set ++# CONFIG_I2C_SIS96X is not set ++# CONFIG_I2C_VIA is not set ++# CONFIG_I2C_VIAPRO is not set ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++CONFIG_I2C_MCF=y ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_SIMTEC is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Graphics adapter I2C/DDC channel drivers ++# ++# CONFIG_I2C_VOODOO3 is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_STUB is not set ++ ++# ++# Miscellaneous I2C Chip support ++# ++# CONFIG_DS1682 is not set ++# CONFIG_SENSORS_PCF8574 is not set ++# CONFIG_PCF8575 is not set ++# CONFIG_SENSORS_PCA9539 is not set ++# CONFIG_SENSORS_PCF8591 is not set ++# CONFIG_SENSORS_MAX6875 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++# CONFIG_I2C_DEBUG_CHIP is not set ++# CONFIG_SPI is not set ++# CONFIG_W1 is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++# CONFIG_THERMAL_HWMON is not set ++CONFIG_WATCHDOG=y ++# CONFIG_WATCHDOG_NOWAYOUT is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_ALIM7101_WDT is not set ++CONFIG_COLDFIRE_WATCHDOG=y ++ ++# ++# PCI-based Watchdog Cards ++# ++# CONFIG_PCIPCWATCHDOG is not set ++# CONFIG_WDTPCI is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_REGULATOR is not set ++ ++# ++# Multimedia devices ++# ++ ++# ++# Multimedia core support ++# ++# CONFIG_VIDEO_DEV is not set ++# CONFIG_DVB_CORE is not set ++# CONFIG_VIDEO_MEDIA is not set ++ ++# ++# Multimedia drivers ++# ++CONFIG_DAB=y ++# CONFIG_USB_DABUSB is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++# CONFIG_VGASTATE is not set ++CONFIG_VIDEO_OUTPUT_CONTROL=m ++# CONFIG_FB is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++ ++# ++# Display device support ++# ++# CONFIG_DISPLAY_SUPPORT is not set ++ ++# ++# Console display driver support ++# ++CONFIG_DUMMY_CONSOLE=y ++# CONFIG_SOUND is not set ++# CONFIG_HID_SUPPORT is not set ++CONFIG_USB_SUPPORT=y ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB_ARCH_HAS_OHCI=y ++CONFIG_USB_ARCH_HAS_EHCI=y ++CONFIG_USB=y ++# CONFIG_USB_DEBUG is not set ++# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set ++ ++# ++# Miscellaneous USB options ++# ++# CONFIG_USB_DEVICEFS is not set ++CONFIG_USB_DEVICE_CLASS=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_SUSPEND is not set ++# CONFIG_USB_OTG is not set ++CONFIG_USB_MON=y ++# CONFIG_USB_WUSB is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++CONFIG_USB_EHCI_HCD=y ++# CONFIG_USB_EHCI_ROOT_HUB_TT is not set ++# CONFIG_USB_EHCI_TT_NEWSCHED is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1760_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_UHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_WHCI_HCD is not set ++# CONFIG_USB_HWA_HCD is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; ++# ++ ++# ++# see USB_STORAGE Help for more information ++# ++CONFIG_USB_STORAGE=y ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_LIBUSUAL is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_BERRY_CHARGE is not set ++# CONFIG_USB_LED is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_PHIDGET is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_VST is not set ++# CONFIG_USB_GADGET is not set ++ ++# ++# OTG and related infrastructure ++# ++# CONFIG_UWB is not set ++# CONFIG_MMC is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++# CONFIG_INFINIBAND is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++CONFIG_RTC_DRV_RS5C372=y ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++ ++# ++# SPI RTC drivers ++# ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_MCF is not set ++# CONFIG_RTC_M5441X is not set ++# CONFIG_DMADEVICES is not set ++# CONFIG_UIO is not set ++# CONFIG_STAGING is not set ++ ++# ++# Character devices ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++CONFIG_GENERIC_CLOCKEVENTS_BUILD=y ++ ++# ++# File systems ++# ++CONFIG_EXT2_FS=y ++# CONFIG_EXT2_FS_XATTR is not set ++# CONFIG_EXT2_FS_XIP is not set ++CONFIG_EXT3_FS=y ++CONFIG_EXT3_FS_XATTR=y ++# CONFIG_EXT3_FS_POSIX_ACL is not set ++# CONFIG_EXT3_FS_SECURITY is not set ++# CONFIG_EXT4_FS is not set ++CONFIG_JBD=y ++CONFIG_FS_MBCACHE=y ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_FS_POSIX_ACL is not set ++CONFIG_FILE_LOCKING=y ++# CONFIG_XFS_FS is not set ++# CONFIG_GFS2_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++CONFIG_DNOTIFY=y ++# CONFIG_INOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_AUTOFS_FS is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=y ++CONFIG_MSDOS_FS=y ++CONFIG_VFAT_FS=y ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++CONFIG_NTFS_FS=y ++# CONFIG_NTFS_DEBUG is not set ++CONFIG_NTFS_RW=y ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++# CONFIG_PROC_KCORE is not set ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++# CONFIG_TMPFS_POSIX_ACL is not set ++# CONFIG_HUGETLB_PAGE is not set ++# CONFIG_CONFIGFS_FS is not set ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++CONFIG_JFFS2_FS_WRITEBUFFER=y ++# CONFIG_JFFS2_FS_WBUF_VERIFY is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++# CONFIG_CRAMFS is not set ++# CONFIG_SQUASHFS is not set ++# CONFIG_VXFS_FS is not set ++CONFIG_MINIX_FS=y ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++CONFIG_ROMFS_FS=y ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=y ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++CONFIG_ROOT_NFS=y ++# CONFIG_NFSD is not set ++CONFIG_LOCKD=y ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=y ++# CONFIG_SUNRPC_REGISTER_V4 is not set ++# CONFIG_RPCSEC_GSS_KRB5 is not set ++# CONFIG_RPCSEC_GSS_SPKM3 is not set ++# CONFIG_SMB_FS is not set ++# CONFIG_CIFS is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++ ++# ++# Partition Types ++# ++CONFIG_PARTITION_ADVANCED=y ++# CONFIG_ACORN_PARTITION is not set ++# CONFIG_OSF_PARTITION is not set ++# CONFIG_AMIGA_PARTITION is not set ++# CONFIG_ATARI_PARTITION is not set ++# CONFIG_MAC_PARTITION is not set ++CONFIG_MSDOS_PARTITION=y ++# CONFIG_BSD_DISKLABEL is not set ++# CONFIG_MINIX_SUBPARTITION is not set ++# CONFIG_SOLARIS_X86_PARTITION is not set ++# CONFIG_UNIXWARE_DISKLABEL is not set ++# CONFIG_LDM_PARTITION is not set ++# CONFIG_SGI_PARTITION is not set ++# CONFIG_ULTRIX_PARTITION is not set ++# CONFIG_SUN_PARTITION is not set ++# CONFIG_KARMA_PARTITION is not set ++# CONFIG_EFI_PARTITION is not set ++# CONFIG_SYSV68_PARTITION is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++CONFIG_NLS_UTF8=y ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++# CONFIG_ENABLE_MUST_CHECK is not set ++CONFIG_FRAME_WARN=1024 ++# CONFIG_MAGIC_SYSRQ is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_DEBUG_FS is not set ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_KERNEL is not set ++CONFIG_DEBUG_BUGVERBOSE=y ++CONFIG_DEBUG_MEMORY_INIT=y ++# CONFIG_RCU_CPU_STALL_DETECTOR is not set ++# CONFIG_SYSCTL_SYSCALL_CHECK is not set ++ ++# ++# Tracers ++# ++# CONFIG_DYNAMIC_PRINTK_DEBUG is not set ++# CONFIG_SAMPLES is not set ++# CONFIG_BOOTPARAM is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++# CONFIG_SECURITY_FILE_CAPABILITIES is not set ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++# CONFIG_CRYPTO_FIPS is not set ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_GF128MUL is not set ++# CONFIG_CRYPTO_NULL is not set ++# CONFIG_CRYPTO_CRYPTD is not set ++CONFIG_CRYPTO_AUTHENC=y ++CONFIG_CRYPTO_TEST=m ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_SEQIV is not set ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++# CONFIG_CRYPTO_CTR is not set ++# CONFIG_CRYPTO_CTS is not set ++# CONFIG_CRYPTO_ECB is not set ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++ ++# ++# Digest ++# ++CONFIG_CRYPTO_CRC32C=y ++# CONFIG_CRYPTO_MD4 is not set ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++CONFIG_CRYPTO_SHA1=y ++# CONFIG_CRYPTO_SHA256 is not set ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++# CONFIG_CRYPTO_AES is not set ++# CONFIG_CRYPTO_ANUBIS is not set ++# CONFIG_CRYPTO_ARC4 is not set ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++# CONFIG_CRYPTO_DEFLATE is not set ++# CONFIG_CRYPTO_LZO is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++ ++# ++# OCF Configuration ++# ++# CONFIG_OCF_OCF is not set ++ ++# ++# Talitos Driver ++# ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_GENERIC_FIND_LAST_BIT=y ++CONFIG_CRC_CCITT=y ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC7 is not set ++CONFIG_LIBCRC32C=y ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_PLIST=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT=y ++CONFIG_HAS_DMA=y +--- /dev/null ++++ b/arch/m68k/configs/m5485evb_defconfig +@@ -0,0 +1,1582 @@ ++# ++# Automatically generated make config: don't edit ++# Linux kernel version: 2.6.29 ++# Tue Aug 24 16:19:05 2010 ++# ++CONFIG_M68K=y ++CONFIG_MMU=y ++CONFIG_GENERIC_TIME=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_RWSEM_GENERIC_SPINLOCK=y ++# CONFIG_ARCH_HAS_ILOG2_U32 is not set ++# CONFIG_ARCH_HAS_ILOG2_U64 is not set ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++# CONFIG_TIME_LOW_RES is not set ++CONFIG_GENERIC_IOMAP=y ++# CONFIG_NO_IOPORT is not set ++# CONFIG_NO_DMA is not set ++CONFIG_HZ=100 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++ ++# ++# General setup ++# ++CONFIG_EXPERIMENTAL=y ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_SWAP=y ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++# CONFIG_POSIX_MQUEUE is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++# CONFIG_AUDIT is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_CLASSIC_RCU=y ++# CONFIG_TREE_RCU is not set ++# CONFIG_PREEMPT_RCU is not set ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_PREEMPT_RCU_TRACE is not set ++CONFIG_IKCONFIG=y ++CONFIG_IKCONFIG_PROC=y ++CONFIG_LOG_BUF_SHIFT=17 ++CONFIG_GROUP_SCHED=y ++CONFIG_FAIR_GROUP_SCHED=y ++# CONFIG_RT_GROUP_SCHED is not set ++CONFIG_USER_SCHED=y ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUPS is not set ++CONFIG_SYSFS_DEPRECATED=y ++CONFIG_SYSFS_DEPRECATED_V2=y ++# CONFIG_RELAY is not set ++CONFIG_NAMESPACES=y ++# CONFIG_UTS_NS is not set ++# CONFIG_IPC_NS is not set ++# CONFIG_USER_NS is not set ++# CONFIG_PID_NS is not set ++# CONFIG_NET_NS is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++# CONFIG_EMBEDDED is not set ++CONFIG_UID16=y ++CONFIG_SYSCTL_SYSCALL=y ++CONFIG_KALLSYMS=y ++# CONFIG_KALLSYMS_EXTRA_PASS is not set ++CONFIG_HOTPLUG=y ++CONFIG_PRINTK=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++CONFIG_VM_EVENT_COUNTERS=y ++CONFIG_PCI_QUIRKS=y ++CONFIG_COMPAT_BRK=y ++CONFIG_SLAB=y ++# CONFIG_SLUB is not set ++# CONFIG_SLOB is not set ++# CONFIG_PROFILING is not set ++# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set ++CONFIG_SLABINFO=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=0 ++CONFIG_MODULES=y ++# CONFIG_MODULE_FORCE_LOAD is not set ++CONFIG_MODULE_UNLOAD=y ++CONFIG_MODULE_FORCE_UNLOAD=y ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++CONFIG_BLOCK=y ++CONFIG_LBD=y ++# CONFIG_BLK_DEV_IO_TRACE is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_AS=y ++CONFIG_IOSCHED_DEADLINE=y ++CONFIG_IOSCHED_CFQ=y ++# CONFIG_DEFAULT_AS is not set ++# CONFIG_DEFAULT_DEADLINE is not set ++CONFIG_DEFAULT_CFQ=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="cfq" ++# CONFIG_FREEZER is not set ++ ++# ++# Platform dependent setup ++# ++CONFIG_COLDFIRE=y ++CONFIG_CFV4E=y ++# CONFIG_FPU is not set ++CONFIG_MCD_DMA=y ++# CONFIG_AMIGA is not set ++# CONFIG_ATARI is not set ++CONFIG_PCI=y ++# CONFIG_MAC is not set ++# CONFIG_APOLLO is not set ++# CONFIG_VME is not set ++# CONFIG_HP300 is not set ++# CONFIG_SUN3X is not set ++# CONFIG_Q40 is not set ++# CONFIG_SUN3 is not set ++ ++# ++# Processor type ++# ++# CONFIG_M68020 is not set ++# CONFIG_M68030 is not set ++# CONFIG_M68040 is not set ++# CONFIG_M68060 is not set ++# CONFIG_M5445X is not set ++# CONFIG_HAVE_FSL_USB_DR is not set ++CONFIG_M547X_8X=y ++# CONFIG_M547X is not set ++CONFIG_M548X=y ++# CONFIG_M5474LITE is not set ++# CONFIG_M5475AFE is not set ++# CONFIG_M5475BFE is not set ++# CONFIG_M5475CFE is not set ++# CONFIG_M5475DFE is not set ++# CONFIG_M5475EFE is not set ++# CONFIG_M5475FFE is not set ++# CONFIG_M5484LITE is not set ++# CONFIG_M5485AFE is not set ++# CONFIG_M5485BFE is not set ++CONFIG_M5485CFE=y ++# CONFIG_M5485DFE is not set ++# CONFIG_M5485EFE is not set ++# CONFIG_M5485FFE is not set ++# CONFIG_M5441X is not set ++CONFIG_MCFCLK=200000000 ++# CONFIG_MCF_USER_HALT is not set ++CONFIG_MMU_CFV4E=y ++CONFIG_SDRAM_BASE=0x00000000 ++CONFIG_SDRAM_SIZE=0x04000000 ++CONFIG_NOR_FLASH_BASE=0xE0000000 ++CONFIG_DMA_BASE=0xef000000 ++CONFIG_DMA_SIZE=0x800000 ++CONFIG_VDSO=y ++# CONFIG_M68KFPU_EMU is not set ++CONFIG_ADVANCED=y ++# CONFIG_RMW_INSNS is not set ++CONFIG_SINGLE_MEMORY_CHUNK=y ++# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set ++CONFIG_SELECT_MEMORY_MODEL=y ++CONFIG_FLATMEM_MANUAL=y ++# CONFIG_DISCONTIGMEM_MANUAL is not set ++# CONFIG_SPARSEMEM_MANUAL is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_NEED_MULTIPLE_NODES=y ++CONFIG_PAGEFLAGS_EXTENDED=y ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++CONFIG_ZONE_DMA_FLAG=1 ++CONFIG_BOUNCE=y ++CONFIG_VIRT_TO_BUS=y ++CONFIG_UNEVICTABLE_LRU=y ++ ++# ++# General setup ++# ++CONFIG_BINFMT_ELF=y ++# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set ++CONFIG_HAVE_AOUT=y ++# CONFIG_BINFMT_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_PROC_HARDWARE=y ++CONFIG_ZONE_DMA=y ++# CONFIG_ARCH_SUPPORTS_MSI is not set ++CONFIG_PCI_LEGACY=y ++# CONFIG_PCI_STUB is not set ++ ++# ++# Power management options ++# ++CONFIG_PM=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_COMPAT_NET_DEV_OPS=y ++CONFIG_PACKET=y ++# CONFIG_PACKET_MMAP is not set ++CONFIG_UNIX=y ++CONFIG_XFRM=y ++# CONFIG_XFRM_USER is not set ++# CONFIG_XFRM_SUB_POLICY is not set ++# CONFIG_XFRM_MIGRATE is not set ++# CONFIG_XFRM_STATISTICS is not set ++CONFIG_NET_KEY=y ++# CONFIG_NET_KEY_MIGRATE is not set ++CONFIG_INET=y ++# CONFIG_IP_MULTICAST is not set ++CONFIG_IP_ADVANCED_ROUTER=y ++CONFIG_ASK_IP_FIB_HASH=y ++# CONFIG_IP_FIB_TRIE is not set ++CONFIG_IP_FIB_HASH=y ++# CONFIG_IP_MULTIPLE_TABLES is not set ++# CONFIG_IP_ROUTE_MULTIPATH is not set ++# CONFIG_IP_ROUTE_VERBOSE is not set ++CONFIG_IP_PNP=y ++# CONFIG_IP_PNP_DHCP is not set ++# CONFIG_IP_PNP_BOOTP is not set ++# CONFIG_IP_PNP_RARP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE is not set ++# CONFIG_ARPD is not set ++# CONFIG_SYN_COOKIES is not set ++CONFIG_INET_AH=y ++CONFIG_INET_ESP=y ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_LRO is not set ++CONFIG_INET_DIAG=y ++CONFIG_INET_TCP_DIAG=y ++# CONFIG_TCP_CONG_ADVANCED is not set ++CONFIG_TCP_CONG_CUBIC=y ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_BRIDGE is not set ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_ECONET is not set ++# CONFIG_WAN_ROUTER is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++CONFIG_CAN=y ++CONFIG_CAN_RAW=y ++# CONFIG_CAN_BCM is not set ++ ++# ++# CAN Device Drivers ++# ++# CONFIG_CAN_VCAN is not set ++CONFIG_CAN_DEV=y ++CONFIG_CAN_CALC_BITTIMING=y ++CONFIG_CAN_FLEXCAN=y ++CONFIG_CAN_MCF=y ++# CONFIG_CAN_DEBUG_DEVICES is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_PHONET is not set ++CONFIG_WIRELESS=y ++# CONFIG_CFG80211 is not set ++CONFIG_WIRELESS_OLD_REGULATORY=y ++# CONFIG_WIRELESS_EXT is not set ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_KLIPS is not set ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ++# CONFIG_STANDALONE is not set ++CONFIG_PREVENT_FIRMWARE_BUILD=y ++CONFIG_FW_LOADER=y ++CONFIG_FIRMWARE_IN_KERNEL=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++# CONFIG_MTD_DEBUG is not set ++CONFIG_MTD_CONCAT=y ++CONFIG_MTD_PARTITIONS=y ++# CONFIG_MTD_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_CHAR=y ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_MTD_OOPS is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++CONFIG_MTD_CFI=y ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_GEN_PROBE=y ++# CONFIG_MTD_CFI_ADV_OPTIONS is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_CFI_INTELEXT=y ++CONFIG_MTD_CFI_AMDSTD=y ++# CONFIG_MTD_CFI_STAA is not set ++CONFIG_MTD_CFI_UTIL=y ++CONFIG_MTD_RAM=y ++CONFIG_MTD_ROM=y ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP=y ++CONFIG_MTD_PHYSMAP_COMPAT=y ++CONFIG_MTD_PHYSMAP_START=0xE0000000 ++CONFIG_MTD_PHYSMAP_LEN=0x1000000 ++CONFIG_MTD_PHYSMAP_BANKWIDTH=2 ++# CONFIG_MTD_INTEL_VR_NOR is not set ++# CONFIG_MTD_PLATRAM is not set ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_PMC551 is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOC2000 is not set ++# CONFIG_MTD_DOC2001 is not set ++# CONFIG_MTD_DOC2001PLUS is not set ++# CONFIG_MTD_NAND is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR flash memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++ ++# ++# UBI - Unsorted block images ++# ++# CONFIG_MTD_UBI is not set ++# CONFIG_PARPORT is not set ++CONFIG_BLK_DEV=y ++# CONFIG_BLK_CPQ_DA is not set ++# CONFIG_BLK_CPQ_CISS_DA is not set ++# CONFIG_BLK_DEV_DAC960 is not set ++# CONFIG_BLK_DEV_UMEM is not set ++# CONFIG_BLK_DEV_COW_COMMON is not set ++CONFIG_BLK_DEV_LOOP=y ++# CONFIG_BLK_DEV_CRYPTOLOOP is not set ++# CONFIG_BLK_DEV_NBD is not set ++# CONFIG_BLK_DEV_SX8 is not set ++# CONFIG_BLK_DEV_UB is not set ++CONFIG_BLK_DEV_RAM=y ++CONFIG_BLK_DEV_RAM_COUNT=16 ++CONFIG_BLK_DEV_RAM_SIZE=64000 ++# CONFIG_BLK_DEV_XIP is not set ++# CONFIG_CDROM_PKTCDVD is not set ++# CONFIG_ATA_OVER_ETH is not set ++# CONFIG_BLK_DEV_HD is not set ++CONFIG_MISC_DEVICES=y ++# CONFIG_PHANTOM is not set ++# CONFIG_SGI_IOC4 is not set ++# CONFIG_TIFM_CORE is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_HP_ILO is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++# CONFIG_EEPROM_AT24 is not set ++# CONFIG_EEPROM_LEGACY is not set ++# CONFIG_EEPROM_93CX6 is not set ++CONFIG_HAVE_IDE=y ++CONFIG_IDE=y ++ ++# ++# Please see Documentation/ide/ide.txt for help/info on IDE drives ++# ++# CONFIG_BLK_DEV_IDE_SATA is not set ++CONFIG_IDE_GD=y ++CONFIG_IDE_GD_ATA=y ++# CONFIG_IDE_GD_ATAPI is not set ++# CONFIG_BLK_DEV_IDECD is not set ++# CONFIG_BLK_DEV_IDETAPE is not set ++# CONFIG_IDE_TASK_IOCTL is not set ++CONFIG_IDE_PROC_FS=y ++ ++# ++# IDE chipset support/bugfixes ++# ++# CONFIG_BLK_DEV_PLATFORM is not set ++ ++# ++# PCI IDE chipsets support ++# ++# CONFIG_BLK_DEV_GENERIC is not set ++# CONFIG_BLK_DEV_OPTI621 is not set ++# CONFIG_BLK_DEV_AEC62XX is not set ++# CONFIG_BLK_DEV_ALI15X3 is not set ++# CONFIG_BLK_DEV_AMD74XX is not set ++# CONFIG_BLK_DEV_CMD64X is not set ++# CONFIG_BLK_DEV_TRIFLEX is not set ++# CONFIG_BLK_DEV_CS5520 is not set ++# CONFIG_BLK_DEV_CS5530 is not set ++# CONFIG_BLK_DEV_HPT366 is not set ++# CONFIG_BLK_DEV_JMICRON is not set ++# CONFIG_BLK_DEV_SC1200 is not set ++# CONFIG_BLK_DEV_PIIX is not set ++# CONFIG_BLK_DEV_IT8172 is not set ++# CONFIG_BLK_DEV_IT8213 is not set ++# CONFIG_BLK_DEV_IT821X is not set ++# CONFIG_BLK_DEV_NS87415 is not set ++# CONFIG_BLK_DEV_PDC202XX_OLD is not set ++# CONFIG_BLK_DEV_PDC202XX_NEW is not set ++# CONFIG_BLK_DEV_SVWKS is not set ++# CONFIG_BLK_DEV_SIIMAGE is not set ++# CONFIG_BLK_DEV_SLC90E66 is not set ++# CONFIG_BLK_DEV_TRM290 is not set ++# CONFIG_BLK_DEV_VIA82CXXX is not set ++# CONFIG_BLK_DEV_TC86C001 is not set ++# CONFIG_BLK_DEV_IDEDMA is not set ++ ++# ++# SCSI device support ++# ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_TGT is not set ++# CONFIG_SCSI_NETLINK is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++ ++# ++# Some SCSI devices (e.g. CD jukebox) support multiple LUNs ++# ++CONFIG_SCSI_MULTI_LUN=y ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++CONFIG_SCSI_WAIT_SCAN=m ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++# CONFIG_SCSI_LOWLEVEL is not set ++# CONFIG_SCSI_DH is not set ++CONFIG_ATA=y ++# CONFIG_ATA_NONSTANDARD is not set ++CONFIG_SATA_PMP=y ++# CONFIG_SATA_AHCI is not set ++CONFIG_SATA_SIL24=y ++CONFIG_ATA_SFF=y ++# CONFIG_SATA_SVW is not set ++# CONFIG_ATA_PIIX is not set ++# CONFIG_SATA_MV is not set ++# CONFIG_SATA_NV is not set ++# CONFIG_PDC_ADMA is not set ++# CONFIG_SATA_QSTOR is not set ++# CONFIG_SATA_PROMISE is not set ++# CONFIG_SATA_SX4 is not set ++CONFIG_SATA_SIL=y ++# CONFIG_SATA_SIS is not set ++# CONFIG_SATA_ULI is not set ++# CONFIG_SATA_VIA is not set ++# CONFIG_SATA_VITESSE is not set ++# CONFIG_SATA_INIC162X is not set ++# CONFIG_PATA_ALI is not set ++# CONFIG_PATA_AMD is not set ++# CONFIG_PATA_ARTOP is not set ++# CONFIG_PATA_ATIIXP is not set ++# CONFIG_PATA_CMD640_PCI is not set ++# CONFIG_PATA_CMD64X is not set ++# CONFIG_PATA_CS5520 is not set ++# CONFIG_PATA_CS5530 is not set ++# CONFIG_PATA_CYPRESS is not set ++# CONFIG_PATA_EFAR is not set ++# CONFIG_ATA_GENERIC is not set ++# CONFIG_PATA_HPT366 is not set ++# CONFIG_PATA_HPT37X is not set ++# CONFIG_PATA_HPT3X2N is not set ++# CONFIG_PATA_HPT3X3 is not set ++# CONFIG_PATA_IT821X is not set ++# CONFIG_PATA_IT8213 is not set ++# CONFIG_PATA_JMICRON is not set ++# CONFIG_PATA_TRIFLEX is not set ++# CONFIG_PATA_MARVELL is not set ++# CONFIG_PATA_MPIIX is not set ++# CONFIG_PATA_OLDPIIX is not set ++# CONFIG_PATA_NETCELL is not set ++# CONFIG_PATA_NINJA32 is not set ++# CONFIG_PATA_NS87410 is not set ++# CONFIG_PATA_NS87415 is not set ++# CONFIG_PATA_OPTI is not set ++# CONFIG_PATA_OPTIDMA is not set ++# CONFIG_PATA_PDC_OLD is not set ++# CONFIG_PATA_RADISYS is not set ++# CONFIG_PATA_RZ1000 is not set ++# CONFIG_PATA_SC1200 is not set ++# CONFIG_PATA_SERVERWORKS is not set ++# CONFIG_PATA_PDC2027X is not set ++# CONFIG_PATA_SIL680 is not set ++# CONFIG_PATA_SIS is not set ++# CONFIG_PATA_VIA is not set ++# CONFIG_PATA_WINBOND is not set ++# CONFIG_PATA_SCH is not set ++# CONFIG_MD is not set ++# CONFIG_FUSION is not set ++ ++# ++# IEEE 1394 (FireWire) support ++# ++ ++# ++# Enable only one of the two stacks, unless you know what you are doing ++# ++# CONFIG_FIREWIRE is not set ++# CONFIG_IEEE1394 is not set ++# CONFIG_I2O is not set ++CONFIG_NETDEVICES=y ++# CONFIG_DUMMY is not set ++# CONFIG_BONDING is not set ++# CONFIG_MACVLAN is not set ++# CONFIG_EQUALIZER is not set ++# CONFIG_TUN is not set ++# CONFIG_VETH is not set ++# CONFIG_ARCNET is not set ++CONFIG_PHYLIB=y ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++CONFIG_BROADCOM5222_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_NATIONAL8364x_PHY is not set ++# CONFIG_NATIONAL8384x_PHY is not set ++# CONFIG_MicrelKSZ8041_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_FIXED_PHY is not set ++# CONFIG_MDIO_BITBANG is not set ++CONFIG_NET_ETHERNET=y ++CONFIG_MII=y ++# CONFIG_HAPPYMEAL is not set ++# CONFIG_SUNGEM is not set ++# CONFIG_CASSINI is not set ++# CONFIG_NET_VENDOR_3COM is not set ++# CONFIG_DNET is not set ++# CONFIG_NET_TULIP is not set ++# CONFIG_HP100 is not set ++# CONFIG_IBM_NEW_EMAC_ZMII is not set ++# CONFIG_IBM_NEW_EMAC_RGMII is not set ++# CONFIG_IBM_NEW_EMAC_TAH is not set ++# CONFIG_IBM_NEW_EMAC_EMAC4 is not set ++# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set ++# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set ++# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set ++CONFIG_NET_PCI=y ++# CONFIG_PCNET32 is not set ++# CONFIG_AMD8111_ETH is not set ++# CONFIG_ADAPTEC_STARFIRE is not set ++# CONFIG_B44 is not set ++# CONFIG_FORCEDETH is not set ++CONFIG_E100=y ++# CONFIG_FEALNX is not set ++# CONFIG_NATSEMI is not set ++CONFIG_NE2K_PCI=y ++CONFIG_8139CP=y ++CONFIG_8139TOO=y ++CONFIG_8139TOO_PIO=y ++# CONFIG_8139TOO_TUNE_TWISTER is not set ++# CONFIG_8139TOO_8129 is not set ++# CONFIG_8139_OLD_RX_RESET is not set ++# CONFIG_R6040 is not set ++# CONFIG_SIS900 is not set ++# CONFIG_EPIC100 is not set ++# CONFIG_SMSC9420 is not set ++# CONFIG_SUNDANCE is not set ++# CONFIG_TLAN is not set ++# CONFIG_VIA_RHINE is not set ++# CONFIG_SC92031 is not set ++CONFIG_FEC_548x=y ++CONFIG_FEC_548x_ENABLE_FEC2=y ++CONFIG_FEC_548x_SHARED_PHY=y ++# CONFIG_ATL2 is not set ++CONFIG_NETDEV_1000=y ++# CONFIG_ACENIC is not set ++# CONFIG_DL2K is not set ++CONFIG_E1000=y ++# CONFIG_E1000E is not set ++# CONFIG_IP1000 is not set ++# CONFIG_IGB is not set ++# CONFIG_NS83820 is not set ++# CONFIG_HAMACHI is not set ++# CONFIG_YELLOWFIN is not set ++CONFIG_R8169=y ++# CONFIG_SIS190 is not set ++# CONFIG_SKGE is not set ++# CONFIG_SKY2 is not set ++# CONFIG_VIA_VELOCITY is not set ++# CONFIG_TIGON3 is not set ++# CONFIG_BNX2 is not set ++# CONFIG_QLA3XXX is not set ++# CONFIG_ATL1 is not set ++# CONFIG_ATL1E is not set ++# CONFIG_ATL1C is not set ++# CONFIG_JME is not set ++# CONFIG_NETDEV_10000 is not set ++# CONFIG_TR is not set ++ ++# ++# Wireless LAN ++# ++# CONFIG_WLAN_PRE80211 is not set ++# CONFIG_WLAN_80211 is not set ++# CONFIG_IWLWIFI_LEDS is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++ ++# ++# USB Network Adapters ++# ++# CONFIG_USB_CATC is not set ++# CONFIG_USB_KAWETH is not set ++# CONFIG_USB_PEGASUS is not set ++# CONFIG_USB_RTL8150 is not set ++# CONFIG_USB_USBNET is not set ++# CONFIG_WAN is not set ++# CONFIG_FDDI is not set ++# CONFIG_HIPPI is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++# CONFIG_NET_FC is not set ++# CONFIG_NETCONSOLE is not set ++# CONFIG_NETPOLL is not set ++# CONFIG_NET_POLL_CONTROLLER is not set ++# CONFIG_ISDN is not set ++# CONFIG_PHONE is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++# CONFIG_INPUT_MOUSEDEV_PSAUX is not set ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 ++# CONFIG_INPUT_JOYDEV is not set ++CONFIG_INPUT_EVDEV=y ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++CONFIG_INPUT_KEYBOARD=y ++# CONFIG_KEYBOARD_ATKBD is not set ++# CONFIG_KEYBOARD_SUNKBD is not set ++# CONFIG_KEYBOARD_LKKBD is not set ++# CONFIG_KEYBOARD_XTKBD is not set ++# CONFIG_KEYBOARD_NEWTON is not set ++# CONFIG_KEYBOARD_STOWAWAY is not set ++# CONFIG_INPUT_MOUSE is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++# CONFIG_INPUT_TOUCHSCREEN is not set ++# CONFIG_INPUT_MISC is not set ++ ++# ++# Hardware I/O ports ++# ++CONFIG_SERIO=y ++CONFIG_SERIO_SERPORT=y ++# CONFIG_SERIO_PCIPS2 is not set ++# CONFIG_SERIO_RAW is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_VT=y ++CONFIG_CONSOLE_TRANSLATIONS=y ++CONFIG_VT_CONSOLE=y ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++CONFIG_DEVKMEM=y ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_NOZOMI is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_COLDFIRE_IRDA is not set ++# CONFIG_SERIAL_COLDFIRE_EDMA is not set ++CONFIG_SERIAL_MCF=y ++CONFIG_SERIAL_MCF_BAUDRATE=115200 ++CONFIG_SERIAL_MCF_CONSOLE=y ++# CONFIG_SERIAL_JSM is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_APPLICOM is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++CONFIG_I2C_CHARDEV=y ++CONFIG_I2C_HELPER_AUTO=y ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# PC SMBus host controller drivers ++# ++# CONFIG_I2C_ALI1535 is not set ++# CONFIG_I2C_ALI1563 is not set ++# CONFIG_I2C_ALI15X3 is not set ++# CONFIG_I2C_AMD756 is not set ++# CONFIG_I2C_AMD8111 is not set ++# CONFIG_I2C_I801 is not set ++# CONFIG_I2C_ISCH is not set ++# CONFIG_I2C_PIIX4 is not set ++# CONFIG_I2C_NFORCE2 is not set ++# CONFIG_I2C_SIS5595 is not set ++# CONFIG_I2C_SIS630 is not set ++# CONFIG_I2C_SIS96X is not set ++# CONFIG_I2C_VIA is not set ++# CONFIG_I2C_VIAPRO is not set ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++CONFIG_I2C_MCF=y ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_SIMTEC is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Graphics adapter I2C/DDC channel drivers ++# ++# CONFIG_I2C_VOODOO3 is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_STUB is not set ++ ++# ++# Miscellaneous I2C Chip support ++# ++# CONFIG_DS1682 is not set ++# CONFIG_SENSORS_PCF8574 is not set ++# CONFIG_PCF8575 is not set ++# CONFIG_SENSORS_PCA9539 is not set ++# CONFIG_SENSORS_PCF8591 is not set ++# CONFIG_SENSORS_MAX6875 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++# CONFIG_I2C_DEBUG_CHIP is not set ++# CONFIG_SPI is not set ++# CONFIG_W1 is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++# CONFIG_THERMAL_HWMON is not set ++CONFIG_WATCHDOG=y ++# CONFIG_WATCHDOG_NOWAYOUT is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_ALIM7101_WDT is not set ++CONFIG_COLDFIRE_WATCHDOG=y ++ ++# ++# PCI-based Watchdog Cards ++# ++# CONFIG_PCIPCWATCHDOG is not set ++# CONFIG_WDTPCI is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_REGULATOR is not set ++ ++# ++# Multimedia devices ++# ++ ++# ++# Multimedia core support ++# ++# CONFIG_VIDEO_DEV is not set ++# CONFIG_DVB_CORE is not set ++# CONFIG_VIDEO_MEDIA is not set ++ ++# ++# Multimedia drivers ++# ++CONFIG_DAB=y ++# CONFIG_USB_DABUSB is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++# CONFIG_VGASTATE is not set ++CONFIG_VIDEO_OUTPUT_CONTROL=m ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++CONFIG_FB_CFB_FILLRECT=y ++CONFIG_FB_CFB_COPYAREA=y ++CONFIG_FB_CFB_IMAGEBLIT=y ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++CONFIG_FB_DEFERRED_IO=y ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++CONFIG_FB_SMI=y ++# CONFIG_FB_CIRRUS is not set ++# CONFIG_FB_PM2 is not set ++# CONFIG_FB_CYBER2000 is not set ++# CONFIG_FB_ASILIANT is not set ++# CONFIG_FB_IMSTT is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_NVIDIA is not set ++# CONFIG_FB_RIVA is not set ++# CONFIG_FB_MATROX is not set ++# CONFIG_FB_RADEON is not set ++# CONFIG_FB_ATY128 is not set ++# CONFIG_FB_ATY is not set ++# CONFIG_FB_S3 is not set ++# CONFIG_FB_SAVAGE is not set ++# CONFIG_FB_SIS is not set ++# CONFIG_FB_VIA is not set ++# CONFIG_FB_NEOMAGIC is not set ++# CONFIG_FB_KYRO is not set ++# CONFIG_FB_3DFX is not set ++# CONFIG_FB_VOODOO1 is not set ++# CONFIG_FB_VT8623 is not set ++# CONFIG_FB_TRIDENT is not set ++# CONFIG_FB_ARK is not set ++# CONFIG_FB_PM3 is not set ++# CONFIG_FB_CARMINE is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_MB862XX is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++ ++# ++# Display device support ++# ++# CONFIG_DISPLAY_SUPPORT is not set ++ ++# ++# Console display driver support ++# ++CONFIG_DUMMY_CONSOLE=y ++CONFIG_FRAMEBUFFER_CONSOLE=y ++# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set ++# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set ++CONFIG_FONTS=y ++CONFIG_FONT_8x8=y ++CONFIG_FONT_8x16=y ++CONFIG_FONT_6x11=y ++# CONFIG_FONT_7x14 is not set ++CONFIG_FONT_PEARL_8x8=y ++CONFIG_FONT_ACORN_8x8=y ++CONFIG_FONT_MINI_4x6=y ++CONFIG_FONT_SUN8x16=y ++CONFIG_FONT_SUN12x22=y ++CONFIG_FONT_10x18=y ++CONFIG_LOGO=y ++CONFIG_LOGO_LINUX_MONO=y ++CONFIG_LOGO_LINUX_VGA16=y ++CONFIG_LOGO_LINUX_CLUT224=y ++# CONFIG_SOUND is not set ++CONFIG_HID_SUPPORT=y ++CONFIG_HID=y ++CONFIG_HID_DEBUG=y ++# CONFIG_HIDRAW is not set ++ ++# ++# USB Input Devices ++# ++CONFIG_USB_HID=y ++# CONFIG_HID_PID is not set ++# CONFIG_USB_HIDDEV is not set ++ ++# ++# Special HID drivers ++# ++CONFIG_HID_COMPAT=y ++CONFIG_HID_A4TECH=y ++CONFIG_HID_APPLE=y ++CONFIG_HID_BELKIN=y ++CONFIG_HID_CHERRY=y ++CONFIG_HID_CHICONY=y ++CONFIG_HID_CYPRESS=y ++CONFIG_HID_EZKEY=y ++CONFIG_HID_GYRATION=y ++CONFIG_HID_LOGITECH=y ++# CONFIG_LOGITECH_FF is not set ++# CONFIG_LOGIRUMBLEPAD2_FF is not set ++CONFIG_HID_MICROSOFT=y ++CONFIG_HID_MONTEREY=y ++CONFIG_HID_NTRIG=y ++CONFIG_HID_PANTHERLORD=y ++# CONFIG_PANTHERLORD_FF is not set ++CONFIG_HID_PETALYNX=y ++CONFIG_HID_SAMSUNG=y ++CONFIG_HID_SONY=y ++CONFIG_HID_SUNPLUS=y ++# CONFIG_GREENASIA_FF is not set ++CONFIG_HID_TOPSEED=y ++# CONFIG_THRUSTMASTER_FF is not set ++# CONFIG_ZEROPLUS_FF is not set ++CONFIG_USB_SUPPORT=y ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB_ARCH_HAS_OHCI=y ++CONFIG_USB_ARCH_HAS_EHCI=y ++CONFIG_USB=y ++# CONFIG_USB_DEBUG is not set ++# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEVICEFS=y ++# CONFIG_USB_DEVICE_CLASS is not set ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_SUSPEND is not set ++# CONFIG_USB_OTG is not set ++CONFIG_USB_MON=y ++# CONFIG_USB_WUSB is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++# CONFIG_USB_EHCI_TT_NEWSCHED is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1760_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_UHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_WHCI_HCD is not set ++# CONFIG_USB_HWA_HCD is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; ++# ++ ++# ++# see USB_STORAGE Help for more information ++# ++CONFIG_USB_STORAGE=y ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_LIBUSUAL is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_BERRY_CHARGE is not set ++# CONFIG_USB_LED is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_PHIDGET is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_VST is not set ++# CONFIG_USB_GADGET is not set ++ ++# ++# OTG and related infrastructure ++# ++# CONFIG_UWB is not set ++# CONFIG_MMC is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++# CONFIG_INFINIBAND is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++CONFIG_RTC_DRV_RS5C372=y ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++ ++# ++# SPI RTC drivers ++# ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_MCF is not set ++# CONFIG_RTC_M5441X is not set ++# CONFIG_DMADEVICES is not set ++# CONFIG_UIO is not set ++# CONFIG_STAGING is not set ++ ++# ++# Character devices ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++CONFIG_GENERIC_CLOCKEVENTS_BUILD=y ++ ++# ++# File systems ++# ++CONFIG_EXT2_FS=y ++# CONFIG_EXT2_FS_XATTR is not set ++# CONFIG_EXT2_FS_XIP is not set ++CONFIG_EXT3_FS=y ++CONFIG_EXT3_FS_XATTR=y ++# CONFIG_EXT3_FS_POSIX_ACL is not set ++# CONFIG_EXT3_FS_SECURITY is not set ++# CONFIG_EXT4_FS is not set ++CONFIG_JBD=y ++CONFIG_FS_MBCACHE=y ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_FS_POSIX_ACL is not set ++CONFIG_FILE_LOCKING=y ++# CONFIG_XFS_FS is not set ++# CONFIG_GFS2_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++CONFIG_DNOTIFY=y ++# CONFIG_INOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_AUTOFS_FS is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=y ++CONFIG_MSDOS_FS=y ++CONFIG_VFAT_FS=y ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++CONFIG_NTFS_FS=y ++# CONFIG_NTFS_DEBUG is not set ++CONFIG_NTFS_RW=y ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++# CONFIG_PROC_KCORE is not set ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++# CONFIG_TMPFS_POSIX_ACL is not set ++# CONFIG_HUGETLB_PAGE is not set ++# CONFIG_CONFIGFS_FS is not set ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++CONFIG_JFFS2_FS_WRITEBUFFER=y ++# CONFIG_JFFS2_FS_WBUF_VERIFY is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++# CONFIG_CRAMFS is not set ++# CONFIG_SQUASHFS is not set ++# CONFIG_VXFS_FS is not set ++CONFIG_MINIX_FS=y ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++CONFIG_ROMFS_FS=y ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=y ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++CONFIG_ROOT_NFS=y ++# CONFIG_NFSD is not set ++CONFIG_LOCKD=y ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=y ++# CONFIG_SUNRPC_REGISTER_V4 is not set ++# CONFIG_RPCSEC_GSS_KRB5 is not set ++# CONFIG_RPCSEC_GSS_SPKM3 is not set ++# CONFIG_SMB_FS is not set ++# CONFIG_CIFS is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++ ++# ++# Partition Types ++# ++CONFIG_PARTITION_ADVANCED=y ++# CONFIG_ACORN_PARTITION is not set ++# CONFIG_OSF_PARTITION is not set ++# CONFIG_AMIGA_PARTITION is not set ++# CONFIG_ATARI_PARTITION is not set ++# CONFIG_MAC_PARTITION is not set ++CONFIG_MSDOS_PARTITION=y ++# CONFIG_BSD_DISKLABEL is not set ++# CONFIG_MINIX_SUBPARTITION is not set ++# CONFIG_SOLARIS_X86_PARTITION is not set ++# CONFIG_UNIXWARE_DISKLABEL is not set ++# CONFIG_LDM_PARTITION is not set ++# CONFIG_SGI_PARTITION is not set ++# CONFIG_ULTRIX_PARTITION is not set ++# CONFIG_SUN_PARTITION is not set ++# CONFIG_KARMA_PARTITION is not set ++# CONFIG_EFI_PARTITION is not set ++# CONFIG_SYSV68_PARTITION is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++CONFIG_NLS_UTF8=y ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++# CONFIG_ENABLE_MUST_CHECK is not set ++CONFIG_FRAME_WARN=1024 ++# CONFIG_MAGIC_SYSRQ is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_DEBUG_FS is not set ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_KERNEL is not set ++CONFIG_DEBUG_BUGVERBOSE=y ++CONFIG_DEBUG_MEMORY_INIT=y ++# CONFIG_RCU_CPU_STALL_DETECTOR is not set ++# CONFIG_SYSCTL_SYSCALL_CHECK is not set ++ ++# ++# Tracers ++# ++# CONFIG_DYNAMIC_PRINTK_DEBUG is not set ++# CONFIG_SAMPLES is not set ++# CONFIG_BOOTPARAM is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++# CONFIG_SECURITY_FILE_CAPABILITIES is not set ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++# CONFIG_CRYPTO_FIPS is not set ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_GF128MUL is not set ++# CONFIG_CRYPTO_NULL is not set ++# CONFIG_CRYPTO_CRYPTD is not set ++CONFIG_CRYPTO_AUTHENC=y ++CONFIG_CRYPTO_TEST=m ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_SEQIV is not set ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++# CONFIG_CRYPTO_CTR is not set ++# CONFIG_CRYPTO_CTS is not set ++# CONFIG_CRYPTO_ECB is not set ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++ ++# ++# Digest ++# ++CONFIG_CRYPTO_CRC32C=y ++# CONFIG_CRYPTO_MD4 is not set ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++CONFIG_CRYPTO_SHA1=y ++# CONFIG_CRYPTO_SHA256 is not set ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++# CONFIG_CRYPTO_AES is not set ++# CONFIG_CRYPTO_ANUBIS is not set ++# CONFIG_CRYPTO_ARC4 is not set ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++# CONFIG_CRYPTO_DEFLATE is not set ++# CONFIG_CRYPTO_LZO is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++ ++# ++# OCF Configuration ++# ++# CONFIG_OCF_OCF is not set ++ ++# ++# Talitos Driver ++# ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_GENERIC_FIND_LAST_BIT=y ++CONFIG_CRC_CCITT=y ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC7 is not set ++CONFIG_LIBCRC32C=y ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_PLIST=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT=y ++CONFIG_HAS_DMA=y +--- /dev/null ++++ b/arch/m68k/include/asm/cf_548x_cacheflush.h +@@ -0,0 +1,262 @@ ++/* ++ * arch/m68k/include/asm/cf_548x_cacheflush.h - Coldfire 547x/548x Cache ++ * ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Kurt Mahan kmahan@freescale.com ++ * Shrek Wu b16972@freescale.com ++ * ++ * Based on include/asm-m68k/cacheflush.h ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++#ifndef M68K_CF_548x_CACHEFLUSH_H ++#define M68K_CF_548x_CACHEFLUSH_H ++ ++#include <asm/cfcache.h> ++/* ++ * Cache handling functions ++ */ ++ ++#define flush_icache() \ ++({ \ ++ unsigned long set; \ ++ unsigned long start_set; \ ++ unsigned long end_set; \ ++ \ ++ start_set = 0; \ ++ end_set = (unsigned long)LAST_DCACHE_ADDR; \ ++ \ ++ for (set = start_set; set <= end_set; set += (0x10 - 3)) {\ ++ asm volatile("cpushl %%ic,(%0)\n" \ ++ "\taddq%.l #1,%0\n" \ ++ "\tcpushl %%ic,(%0)\n" \ ++ "\taddq%.l #1,%0\n" \ ++ "\tcpushl %%ic,(%0)\n" \ ++ "\taddq%.l #1,%0\n" \ ++ "\tcpushl %%ic,(%0)" : "=a" (set) : "a" (set)); \ ++ } \ ++}) ++ ++#define flush_dcache() \ ++({ \ ++ unsigned long set; \ ++ unsigned long start_set; \ ++ unsigned long end_set; \ ++ \ ++ start_set = 0; \ ++ end_set = (unsigned long)LAST_DCACHE_ADDR; \ ++ \ ++ for (set = start_set; set <= end_set; set += (0x10 - 3)) { \ ++ asm volatile("cpushl %%dc,(%0)\n" \ ++ "\taddq%.l #1,%0\n" \ ++ "\tcpushl %%dc,(%0)\n" \ ++ "\taddq%.l #1,%0\n" \ ++ "\tcpushl %%dc,(%0)\n" \ ++ "\taddq%.l #1,%0\n" \ ++ "\tcpushl %%dc,(%0)" : "=a" (set) : "a" (set)); \ ++ } \ ++}) ++ ++#define flush_bcache() \ ++({ \ ++ unsigned long set; \ ++ unsigned long start_set; \ ++ unsigned long end_set; \ ++ \ ++ start_set = 0; \ ++ end_set = (unsigned long)LAST_DCACHE_ADDR; \ ++ \ ++ for (set = start_set; set <= end_set; set += (0x10 - 3)) { \ ++ asm volatile("cpushl %%bc,(%0)\n" \ ++ "\taddq%.l #1,%0\n" \ ++ "\tcpushl %%bc,(%0)\n" \ ++ "\taddq%.l #1,%0\n" \ ++ "\tcpushl %%bc,(%0)\n" \ ++ "\taddq%.l #1,%0\n" \ ++ "\tcpushl %%bc,(%0)" : "=a" (set) : "a" (set)); \ ++ } \ ++}) ++ ++/* ++ * invalidate the cache for the specified memory range. ++ * It starts at the physical address specified for ++ * the given number of bytes. ++ */ ++extern void cache_clear(unsigned long paddr, int len); ++/* ++ * push any dirty cache in the specified memory range. ++ * It starts at the physical address specified for ++ * the given number of bytes. ++ */ ++extern void cache_push(unsigned long paddr, int len); ++ ++/* ++ * push and invalidate pages in the specified user virtual ++ * memory range. ++ */ ++extern void cache_push_v(unsigned long vaddr, int len); ++ ++/* This is needed whenever the virtual mapping of the current ++ process changes. */ ++ ++/** ++ * flush_cache_mm - Flush an mm_struct ++ * @mm: mm_struct to flush ++ */ ++static inline void flush_cache_mm(struct mm_struct *mm) ++{ ++ if (mm == current->mm) ++ flush_bcache(); ++} ++ ++#define flush_cache_dup_mm(mm) flush_cache_mm(mm) ++ ++#define flush_cache_all() flush_bcache() ++ ++/** ++ * flush_cache_range - Flush a cache range ++ * @vma: vma struct ++ * @start: Starting address ++ * @end: Ending address ++ * ++ * flush_cache_range must be a macro to avoid a dependency on ++ * linux/mm.h which includes this file. ++ */ ++static inline void flush_cache_range(struct vm_area_struct *vma, ++ unsigned long start, unsigned long end) ++{ ++ if (vma->vm_mm == current->mm) ++ flush_bcache(); ++/*cf_cache_flush_range(start, end);*/ ++} ++ ++/** ++ * flush_cache_page - Flush a page of the cache ++ * @vma: vma struct ++ * @vmaddr: ++ * @pfn: page numer ++ * ++ * flush_cache_page must be a macro to avoid a dependency on ++ * linux/mm.h which includes this file. ++ */ ++static inline void flush_cache_page(struct vm_area_struct *vma, ++ unsigned long vmaddr, unsigned long pfn) ++{ ++ if (vma->vm_mm == current->mm) ++ flush_bcache(); ++/*cf_cache_flush_range(vmaddr, vmaddr+PAGE_SIZE);*/ ++} ++ ++/* Push the page at kernel virtual address and clear the icache */ ++/* RZ: use cpush %bc instead of cpush %dc, cinv %ic */ ++#define flush_page_to_ram(page) __flush_page_to_ram((void *) page_address(page)) ++extern inline void __flush_page_to_ram(void *address) ++{ ++ unsigned long set; ++ unsigned long start_set; ++ unsigned long end_set; ++ unsigned long addr = (unsigned long) address; ++ ++ addr &= ~(PAGE_SIZE - 1); ++ /* round down to page start address */ ++ ++ start_set = addr & _ICACHE_SET_MASK; ++ end_set = (addr + PAGE_SIZE-1) & _ICACHE_SET_MASK; ++ ++ if (start_set > end_set) { ++ /* from the begining to the lowest address */ ++ for (set = 0; set <= end_set; set += (0x10 - 3)) { ++ asm volatile("cpushl %%bc,(%0)\n" ++ "\taddq%.l #1,%0\n" ++ "\tcpushl %%bc,(%0)\n" ++ "\taddq%.l #1,%0\n" ++ "\tcpushl %%bc,(%0)\n" ++ "\taddq%.l #1,%0\n" ++ "\tcpushl %%bc,(%0)" : "=a" (set) : "a" (set)); ++ } ++ /* next loop will finish the cache ie pass the hole */ ++ end_set = LAST_ICACHE_ADDR; ++ } ++ ++ for (set = start_set; set <= end_set; set += (0x10 - 3)) { ++ asm volatile("cpushl %%bc,(%0)\n" ++ "\taddq%.l #1,%0\n" ++ "\tcpushl %%bc,(%0)\n" ++ "\taddq%.l #1,%0\n" ++ "\tcpushl %%bc,(%0)\n" ++ "\taddq%.l #1,%0\n" ++ "\tcpushl %%bc,(%0)" : "=a" (set) : "a" (set)); ++ } ++} ++ ++/* Use __flush_page_to_ram() for flush_dcache_page all values are same - MW */ ++#define flush_dcache_page(page) \ ++ __flush_page_to_ram((void *) page_address(page)) ++#define flush_icache_page(vma, pg) \ ++ __flush_page_to_ram((void *) page_address(pg)) ++#define flush_icache_user_range(adr, len) \ ++ do { } while (0) ++/* NL */ ++#define flush_icache_user_page(vma, page, addr, len) \ ++ do { } while (0) ++ ++/* Push n pages at kernel virtual address and clear the icache */ ++/* RZ: use cpush %bc instead of cpush %dc, cinv %ic */ ++extern inline void flush_icache_range(unsigned long address, ++ unsigned long endaddr) ++{ ++ unsigned long set; ++ unsigned long start_set; ++ unsigned long end_set; ++ ++ start_set = address & _ICACHE_SET_MASK; ++ end_set = endaddr & _ICACHE_SET_MASK; ++ ++ if (start_set > end_set) { ++ /* from the begining to the lowest address */ ++ for (set = 0; set <= end_set; set += (0x10 - 3)) { ++ asm volatile("cpushl %%ic,(%0)\n" ++ "\taddq%.l #1,%0\n" ++ "\tcpushl %%ic,(%0)\n" ++ "\taddq%.l #1,%0\n" ++ "\tcpushl %%ic,(%0)\n" ++ "\taddq%.l #1,%0\n" ++ "\tcpushl %%ic,(%0)" : "=a" (set) : "a" (set)); ++ } ++ /* next loop will finish the cache ie pass the hole */ ++ end_set = LAST_ICACHE_ADDR; ++ } ++ for (set = start_set; set <= end_set; set += (0x10 - 3)) { ++ asm volatile("cpushl %%ic,(%0)\n" ++ "\taddq%.l #1,%0\n" ++ "\tcpushl %%ic,(%0)\n" ++ "\taddq%.l #1,%0\n" ++ "\tcpushl %%ic,(%0)\n" ++ "\taddq%.l #1,%0\n" ++ "\tcpushl %%ic,(%0)" : "=a" (set) : "a" (set)); ++ } ++} ++ ++static inline void copy_to_user_page(struct vm_area_struct *vma, ++ struct page *page, unsigned long vaddr, ++ void *dst, void *src, int len) ++{ ++ memcpy(dst, src, len); ++ flush_icache_user_page(vma, page, vaddr, len); ++} ++static inline void copy_from_user_page(struct vm_area_struct *vma, ++ struct page *page, unsigned long vaddr, ++ void *dst, void *src, int len) ++{ ++ memcpy(dst, src, len); ++} ++ ++#define flush_cache_vmap(start, end) flush_cache_all() ++#define flush_cache_vunmap(start, end) flush_cache_all() ++#define flush_dcache_mmap_lock(mapping) do { } while (0) ++#define flush_dcache_mmap_unlock(mapping) do { } while (0) ++ ++#endif /* M68K_CF_548x_CACHEFLUSH_H */ +--- /dev/null ++++ b/arch/m68k/include/asm/m5485dma.h +@@ -0,0 +1,98 @@ ++/* ++ * m5485dma.h -- ColdFire 547x/548x DMA controller support. ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ */ ++#ifndef __MCF548X_DMA_H__ ++#define __MCF548X_DMA_H__ ++ ++ ++/* Register read/write macros */ ++#define MCF_DMA_DIPR MCF_REG32(0x008014) ++#define MCF_DMA_DIMR MCF_REG32(0x008018) ++#define MCF_DMA_IMCR MCF_REG32(0x00805C) ++ ++/* Bit definitions and macros for MCF_DMA_DIPR */ ++#define MCF_DMA_DIPR_TASK0 (0x00000001) ++#define MCF_DMA_DIPR_TASK1 (0x00000002) ++#define MCF_DMA_DIPR_TASK2 (0x00000004) ++#define MCF_DMA_DIPR_TASK3 (0x00000008) ++#define MCF_DMA_DIPR_TASK4 (0x00000010) ++#define MCF_DMA_DIPR_TASK5 (0x00000020) ++#define MCF_DMA_DIPR_TASK6 (0x00000040) ++#define MCF_DMA_DIPR_TASK7 (0x00000080) ++#define MCF_DMA_DIPR_TASK8 (0x00000100) ++#define MCF_DMA_DIPR_TASK9 (0x00000200) ++#define MCF_DMA_DIPR_TASK10 (0x00000400) ++#define MCF_DMA_DIPR_TASK11 (0x00000800) ++#define MCF_DMA_DIPR_TASK12 (0x00001000) ++#define MCF_DMA_DIPR_TASK13 (0x00002000) ++#define MCF_DMA_DIPR_TASK14 (0x00004000) ++#define MCF_DMA_DIPR_TASK15 (0x00008000) ++ ++/* Bit definitions and macros for MCF_DMA_DIMR */ ++#define MCF_DMA_DIMR_TASK0 (0x00000001) ++#define MCF_DMA_DIMR_TASK1 (0x00000002) ++#define MCF_DMA_DIMR_TASK2 (0x00000004) ++#define MCF_DMA_DIMR_TASK3 (0x00000008) ++#define MCF_DMA_DIMR_TASK4 (0x00000010) ++#define MCF_DMA_DIMR_TASK5 (0x00000020) ++#define MCF_DMA_DIMR_TASK6 (0x00000040) ++#define MCF_DMA_DIMR_TASK7 (0x00000080) ++#define MCF_DMA_DIMR_TASK8 (0x00000100) ++#define MCF_DMA_DIMR_TASK9 (0x00000200) ++#define MCF_DMA_DIMR_TASK10 (0x00000400) ++#define MCF_DMA_DIMR_TASK11 (0x00000800) ++#define MCF_DMA_DIMR_TASK12 (0x00001000) ++#define MCF_DMA_DIMR_TASK13 (0x00002000) ++#define MCF_DMA_DIMR_TASK14 (0x00004000) ++#define MCF_DMA_DIMR_TASK15 (0x00008000) ++ ++/* Bit definitions and macros for MCF_DMA_IMCR */ ++#define MCF_DMA_IMCR_SRC16(x) (((x)&0x00000003)<<0) ++#define MCF_DMA_IMCR_SRC17(x) (((x)&0x00000003)<<2) ++#define MCF_DMA_IMCR_SRC18(x) (((x)&0x00000003)<<4) ++#define MCF_DMA_IMCR_SRC19(x) (((x)&0x00000003)<<6) ++#define MCF_DMA_IMCR_SRC20(x) (((x)&0x00000003)<<8) ++#define MCF_DMA_IMCR_SRC21(x) (((x)&0x00000003)<<10) ++#define MCF_DMA_IMCR_SRC22(x) (((x)&0x00000003)<<12) ++#define MCF_DMA_IMCR_SRC23(x) (((x)&0x00000003)<<14) ++#define MCF_DMA_IMCR_SRC24(x) (((x)&0x00000003)<<16) ++#define MCF_DMA_IMCR_SRC25(x) (((x)&0x00000003)<<18) ++#define MCF_DMA_IMCR_SRC26(x) (((x)&0x00000003)<<20) ++#define MCF_DMA_IMCR_SRC27(x) (((x)&0x00000003)<<22) ++#define MCF_DMA_IMCR_SRC28(x) (((x)&0x00000003)<<24) ++#define MCF_DMA_IMCR_SRC29(x) (((x)&0x00000003)<<26) ++#define MCF_DMA_IMCR_SRC30(x) (((x)&0x00000003)<<28) ++#define MCF_DMA_IMCR_SRC31(x) (((x)&0x00000003)<<30) ++#define MCF_DMA_IMCR_SRC16_FEC0RX (0x00000000) ++#define MCF_DMA_IMCR_SRC17_FEC0TX (0x00000000) ++#define MCF_DMA_IMCR_SRC18_FEC0RX (0x00000020) ++#define MCF_DMA_IMCR_SRC19_FEC0TX (0x00000080) ++#define MCF_DMA_IMCR_SRC20_FEC1RX (0x00000100) ++#define MCF_DMA_IMCR_SRC21_DREQ1 (0x00000000) ++#define MCF_DMA_IMCR_SRC21_FEC1TX (0x00000400) ++#define MCF_DMA_IMCR_SRC22_FEC0RX (0x00001000) ++#define MCF_DMA_IMCR_SRC23_FEC0TX (0x00004000) ++#define MCF_DMA_IMCR_SRC24_CTM0 (0x00010000) ++#define MCF_DMA_IMCR_SRC24_FEC1RX (0x00020000) ++#define MCF_DMA_IMCR_SRC25_CTM1 (0x00040000) ++#define MCF_DMA_IMCR_SRC25_FEC1TX (0x00080000) ++#define MCF_DMA_IMCR_SRC26_USBEP4 (0x00000000) ++#define MCF_DMA_IMCR_SRC26_CTM2 (0x00200000) ++#define MCF_DMA_IMCR_SRC27_USBEP5 (0x00000000) ++#define MCF_DMA_IMCR_SRC27_CTM3 (0x00800000) ++#define MCF_DMA_IMCR_SRC28_USBEP6 (0x00000000) ++#define MCF_DMA_IMCR_SRC28_CTM4 (0x01000000) ++#define MCF_DMA_IMCR_SRC28_DREQ1 (0x02000000) ++#define MCF_DMA_IMCR_SRC28_PSC2RX (0x03000000) ++#define MCF_DMA_IMCR_SRC29_DREQ1 (0x04000000) ++#define MCF_DMA_IMCR_SRC29_CTM5 (0x08000000) ++#define MCF_DMA_IMCR_SRC29_PSC2TX (0x0C000000) ++#define MCF_DMA_IMCR_SRC30_FEC1RX (0x00000000) ++#define MCF_DMA_IMCR_SRC30_CTM6 (0x10000000) ++#define MCF_DMA_IMCR_SRC30_PSC3RX (0x30000000) ++#define MCF_DMA_IMCR_SRC31_FEC1TX (0x00000000) ++#define MCF_DMA_IMCR_SRC31_CTM7 (0x80000000) ++#define MCF_DMA_IMCR_SRC31_PSC3TX (0xC0000000) ++ ++#endif /* __MCF548X_DMA_H__ */ +--- /dev/null ++++ b/arch/m68k/include/asm/m5485dspi.h +@@ -0,0 +1,146 @@ ++/* ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * File: mcf548x_dspi.h ++ * Purpose: Register and bit definitions for the MCF548X ++ * ++ * Notes: ++ * ++ */ ++ ++#ifndef _M5485DSPI_H_ ++#define _M5485DSPI_H_ ++ ++/* ++ * ++ * DMA Serial Peripheral Interface (DSPI) ++ * ++ */ ++ ++/* Register read/write macros */ ++#define MCF_DSPI_DMCR MCF_REG32(0x008A00) ++#define MCF_DSPI_DTCR MCF_REG32(0x008A08) ++#define MCF_DSPI_DCTAR0 MCF_REG32(0x008A0C) ++#define MCF_DSPI_DCTAR1 MCF_REG32(0x008A10) ++#define MCF_DSPI_DCTAR2 MCF_REG32(0x008A14) ++#define MCF_DSPI_DCTAR3 MCF_REG32(0x008A18) ++#define MCF_DSPI_DCTAR4 MCF_REG32(0x008A1C) ++#define MCF_DSPI_DCTAR5 MCF_REG32(0x008A20) ++#define MCF_DSPI_DCTAR6 MCF_REG32(0x008A24) ++#define MCF_DSPI_DCTAR7 MCF_REG32(0x008A28) ++#define MCF_DSPI_DCTARn(x) MCF_REG32(0x008A0C+(x*4)) ++#define MCF_DSPI_DSR MCF_REG32(0x008A2C) ++#define MCF_DSPI_DRSER MCF_REG32(0x008A30) ++#define MCF_DSPI_DTFR MCF_REG32(0x008A34) ++#define MCF_DSPI_DRFR MCF_REG32(0x008A38) ++#define MCF_DSPI_DTFDR0 MCF_REG32(0x008A3C) ++#define MCF_DSPI_DTFDR1 MCF_REG32(0x008A40) ++#define MCF_DSPI_DTFDR2 MCF_REG32(0x008A44) ++#define MCF_DSPI_DTFDR3 MCF_REG32(0x008A48) ++#define MCF_DSPI_DTFDRn(x) MCF_REG32(0x008A3C+(x*4)) ++#define MCF_DSPI_DRFDR0 MCF_REG32(0x008A7C) ++#define MCF_DSPI_DRFDR1 MCF_REG32(0x008A80) ++#define MCF_DSPI_DRFDR2 MCF_REG32(0x008A84) ++#define MCF_DSPI_DRFDR3 MCF_REG32(0x008A88) ++#define MCF_DSPI_DRFDRn(x) MCF_REG32(0x008A7C+(x*4)) ++ ++/* Bit definitions and macros for MCF_DSPI_DMCR */ ++#define MCF_DSPI_DMCR_HALT (0x00000001) ++#define MCF_DSPI_DMCR_SMPL_PT(x) (((x)&0x00000003)<<8) ++#define MCF_DSPI_DMCR_CRXF (0x00000400) ++#define MCF_DSPI_DMCR_CTXF (0x00000800) ++#define MCF_DSPI_DMCR_DRXF (0x00001000) ++#define MCF_DSPI_DMCR_DTXF (0x00002000) ++#define MCF_DSPI_DMCR_CSIS0 (0x00010000) ++#define MCF_DSPI_DMCR_CSIS2 (0x00040000) ++#define MCF_DSPI_DMCR_CSIS3 (0x00080000) ++#define MCF_DSPI_DMCR_CSIS5 (0x00200000) ++#define MCF_DSPI_DMCR_ROOE (0x01000000) ++#define MCF_DSPI_DMCR_PCSSE (0x02000000) ++#define MCF_DSPI_DMCR_MTFE (0x04000000) ++#define MCF_DSPI_DMCR_FRZ (0x08000000) ++#define MCF_DSPI_DMCR_DCONF(x) (((x)&0x00000003)<<28) ++#define MCF_DSPI_DMCR_CSCK (0x40000000) ++#define MCF_DSPI_DMCR_MSTR (0x80000000) ++ ++/* Bit definitions and macros for MCF_DSPI_DTCR */ ++#define MCF_DSPI_DTCR_SPI_TCNT(x) (((x)&0x0000FFFF)<<16) ++ ++/* Bit definitions and macros for MCF_DSPI_DCTARn */ ++#define MCF_DSPI_DCTAR_BR(x) (((x)&0x0000000F)<<0) ++#define MCF_DSPI_DCTAR_DT(x) (((x)&0x0000000F)<<4) ++#define MCF_DSPI_DCTAR_ASC(x) (((x)&0x0000000F)<<8) ++#define MCF_DSPI_DCTAR_CSSCK(x) (((x)&0x0000000F)<<12) ++#define MCF_DSPI_DCTAR_PBR(x) (((x)&0x00000003)<<16) ++#define MCF_DSPI_DCTAR_PDT(x) (((x)&0x00000003)<<18) ++#define MCF_DSPI_DCTAR_PASC(x) (((x)&0x00000003)<<20) ++#define MCF_DSPI_DCTAR_PCSSCK(x) (((x)&0x00000003)<<22) ++#define MCF_DSPI_DCTAR_LSBFE (0x01000000) ++#define MCF_DSPI_DCTAR_CPHA (0x02000000) ++#define MCF_DSPI_DCTAR_CPOL (0x04000000) ++/* #define MCF_DSPI_DCTAR_TRSZ(x) (((x)&0x0000000F)<<27) */ ++#define MCF_DSPI_DCTAR_FMSZ(x) (((x)&0x0000000F)<<27) ++#define MCF_DSPI_DCTAR_PCSSCK_1CLK (0x00000000) ++#define MCF_DSPI_DCTAR_PCSSCK_3CLK (0x00400000) ++#define MCF_DSPI_DCTAR_PCSSCK_5CLK (0x00800000) ++#define MCF_DSPI_DCTAR_PCSSCK_7CLK (0x00A00000) ++#define MCF_DSPI_DCTAR_PASC_1CLK (0x00000000) ++#define MCF_DSPI_DCTAR_PASC_3CLK (0x00100000) ++#define MCF_DSPI_DCTAR_PASC_5CLK (0x00200000) ++#define MCF_DSPI_DCTAR_PASC_7CLK (0x00300000) ++#define MCF_DSPI_DCTAR_PDT_1CLK (0x00000000) ++#define MCF_DSPI_DCTAR_PDT_3CLK (0x00040000) ++#define MCF_DSPI_DCTAR_PDT_5CLK (0x00080000) ++#define MCF_DSPI_DCTAR_PDT_7CLK (0x000A0000) ++#define MCF_DSPI_DCTAR_PBR_1CLK (0x00000000) ++#define MCF_DSPI_DCTAR_PBR_3CLK (0x00010000) ++#define MCF_DSPI_DCTAR_PBR_5CLK (0x00020000) ++#define MCF_DSPI_DCTAR_PBR_7CLK (0x00030000) ++ ++/* Bit definitions and macros for MCF_DSPI_DSR */ ++#define MCF_DSPI_DSR_RXPTR(x) (((x)&0x0000000F)<<0) ++#define MCF_DSPI_DSR_RXCTR(x) (((x)&0x0000000F)<<4) ++#define MCF_DSPI_DSR_TXPTR(x) (((x)&0x0000000F)<<8) ++#define MCF_DSPI_DSR_TXCTR(x) (((x)&0x0000000F)<<12) ++#define MCF_DSPI_DSR_RFDF (0x00020000) ++#define MCF_DSPI_DSR_RFOF (0x00080000) ++#define MCF_DSPI_DSR_TFFF (0x02000000) ++#define MCF_DSPI_DSR_TFUF (0x08000000) ++#define MCF_DSPI_DSR_EOQF (0x10000000) ++#define MCF_DSPI_DSR_TXRXS (0x40000000) ++#define MCF_DSPI_DSR_TCF (0x80000000) ++ ++/* Bit definitions and macros for MCF_DSPI_DRSER */ ++#define MCF_DSPI_DRSER_RFDFS (0x00010000) ++#define MCF_DSPI_DRSER_RFDFE (0x00020000) ++#define MCF_DSPI_DRSER_RFOFE (0x00080000) ++#define MCF_DSPI_DRSER_TFFFS (0x01000000) ++#define MCF_DSPI_DRSER_TFFFE (0x02000000) ++#define MCF_DSPI_DRSER_TFUFE (0x08000000) ++#define MCF_DSPI_DRSER_EOQFE (0x10000000) ++#define MCF_DSPI_DRSER_TCFE (0x80000000) ++ ++/* Bit definitions and macros for MCF_DSPI_DTFR */ ++#define MCF_DSPI_DTFR_TXDATA(x) (((x)&0x0000FFFF)<<0) ++#define MCF_DSPI_DTFR_CS0 (0x00010000) ++#define MCF_DSPI_DTFR_CS2 (0x00040000) ++#define MCF_DSPI_DTFR_CS3 (0x00080000) ++#define MCF_DSPI_DTFR_CS5 (0x00200000) ++#define MCF_DSPI_DTFR_CTCNT (0x04000000) ++#define MCF_DSPI_DTFR_EOQ (0x08000000) ++#define MCF_DSPI_DTFR_CTAS(x) (((x)&0x00000007)<<28) ++#define MCF_DSPI_DTFR_CONT (0x80000000) ++ ++/* Bit definitions and macros for MCF_DSPI_DRFR */ ++#define MCF_DSPI_DRFR_RXDATA(x) (((x)&0x0000FFFF)<<0) ++ ++/* Bit definitions and macros for MCF_DSPI_DTFDRn */ ++#define MCF_DSPI_DTFDRn_TXDATA(x) (((x)&0x0000FFFF)<<0) ++#define MCF_DSPI_DTFDRn_TXCMD(x) (((x)&0x0000FFFF)<<16) ++ ++/* Bit definitions and macros for MCF_DSPI_DRFDRn */ ++#define MCF_DSPI_DRFDRn_RXDATA(x) (((x)&0x0000FFFF)<<0) ++ ++/********************************************************************/ ++ ++#endif /* _M5485DSPI_H_ */ +--- /dev/null ++++ b/arch/m68k/include/asm/m5485gpio.h +@@ -0,0 +1,695 @@ ++/* ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * File: mcf548x_gpio.h ++ * Purpose: Register and bit definitions for the MCF548X ++ * ++ * Notes: ++ * ++ */ ++ ++#ifndef _M5485GPIO_H_ ++#define _M5485GPIO_H_ ++ ++/********************************************************************* ++* ++* General Purpose I/O (GPIO) ++* ++*********************************************************************/ ++ ++/* Register read/write macros */ ++#define MCF_GPIO_PODR_FBCTL MCF_REG08(0x000A00) ++#define MCF_GPIO_PODR_FBCS MCF_REG08(0x000A01) ++#define MCF_GPIO_PODR_DMA MCF_REG08(0x000A02) ++#define MCF_GPIO_PODR_FEC0H MCF_REG08(0x000A04) ++#define MCF_GPIO_PODR_FEC0L MCF_REG08(0x000A05) ++#define MCF_GPIO_PODR_FEC1H MCF_REG08(0x000A06) ++#define MCF_GPIO_PODR_FEC1L MCF_REG08(0x000A07) ++#define MCF_GPIO_PODR_FECI2C MCF_REG08(0x000A08) ++#define MCF_GPIO_PODR_PCIBG MCF_REG08(0x000A09) ++#define MCF_GPIO_PODR_PCIBR MCF_REG08(0x000A0A) ++#define MCF_GPIO_PODR_PSC3PSC2 MCF_REG08(0x000A0C) ++#define MCF_GPIO_PODR_PSC1PSC0 MCF_REG08(0x000A0D) ++#define MCF_GPIO_PODR_DSPI MCF_REG08(0x000A0E) ++#define MCF_GPIO_PDDR_FBCTL MCF_REG08(0x000A10) ++#define MCF_GPIO_PDDR_FBCS MCF_REG08(0x000A11) ++#define MCF_GPIO_PDDR_DMA MCF_REG08(0x000A12) ++#define MCF_GPIO_PDDR_FEC0H MCF_REG08(0x000A14) ++#define MCF_GPIO_PDDR_FEC0L MCF_REG08(0x000A15) ++#define MCF_GPIO_PDDR_FEC1H MCF_REG08(0x000A16) ++#define MCF_GPIO_PDDR_FEC1L MCF_REG08(0x000A17) ++#define MCF_GPIO_PDDR_FECI2C MCF_REG08(0x000A18) ++#define MCF_GPIO_PDDR_PCIBG MCF_REG08(0x000A19) ++#define MCF_GPIO_PDDR_PCIBR MCF_REG08(0x000A1A) ++#define MCF_GPIO_PDDR_PSC3PSC2 MCF_REG08(0x000A1C) ++#define MCF_GPIO_PDDR_PSC1PSC0 MCF_REG08(0x000A1D) ++#define MCF_GPIO_PDDR_DSPI MCF_REG08(0x000A1E) ++#define MCF_GPIO_PPDSDR_FBCTL MCF_REG08(0x000A20) ++#define MCF_GPIO_PPDSDR_FBCS MCF_REG08(0x000A21) ++#define MCF_GPIO_PPDSDR_DMA MCF_REG08(0x000A22) ++#define MCF_GPIO_PPDSDR_FEC0H MCF_REG08(0x000A24) ++#define MCF_GPIO_PPDSDR_FEC0L MCF_REG08(0x000A25) ++#define MCF_GPIO_PPDSDR_FEC1H MCF_REG08(0x000A26) ++#define MCF_GPIO_PPDSDR_FEC1L MCF_REG08(0x000A27) ++#define MCF_GPIO_PPDSDR_FECI2C MCF_REG08(0x000A28) ++#define MCF_GPIO_PPDSDR_PCIBG MCF_REG08(0x000A29) ++#define MCF_GPIO_PPDSDR_PCIBR MCF_REG08(0x000A2A) ++#define MCF_GPIO_PPDSDR_PSC3PSC2 MCF_REG08(0x000A2C) ++#define MCF_GPIO_PPDSDR_PSC1PSC0 MCF_REG08(0x000A2D) ++#define MCF_GPIO_PPDSDR_DSPI MCF_REG08(0x000A2E) ++#define MCF_GPIO_PCLRR_FBCTL MCF_REG08(0x000A30) ++#define MCF_GPIO_PCLRR_FBCS MCF_REG08(0x000A31) ++#define MCF_GPIO_PCLRR_DMA MCF_REG08(0x000A32) ++#define MCF_GPIO_PCLRR_FEC0H MCF_REG08(0x000A34) ++#define MCF_GPIO_PCLRR_FEC0L MCF_REG08(0x000A35) ++#define MCF_GPIO_PCLRR_FEC1H MCF_REG08(0x000A36) ++#define MCF_GPIO_PCLRR_FEC1L MCF_REG08(0x000A37) ++#define MCF_GPIO_PCLRR_FECI2C MCF_REG08(0x000A38) ++#define MCF_GPIO_PCLRR_PCIBG MCF_REG08(0x000A39) ++#define MCF_GPIO_PCLRR_PCIBR MCF_REG08(0x000A3A) ++#define MCF_GPIO_PCLRR_PSC3PSC2 MCF_REG08(0x000A3C) ++#define MCF_GPIO_PCLRR_PSC1PSC0 MCF_REG08(0x000A3D) ++#define MCF_GPIO_PCLRR_DSPI MCF_REG08(0x000A3E) ++#define MCF_GPIO_PAR_FBCTL MCF_REG16(0x000A40) ++#define MCF_GPIO_PAR_FBCS MCF_REG08(0x000A42) ++#define MCF_GPIO_PAR_DMA MCF_REG08(0x000A43) ++#define MCF_GPIO_PAR_FECI2CIRQ MCF_REG16(0x000A44) ++#define MCF_GPIO_PAR_PCIBG MCF_REG16(0x000A48) ++#define MCF_GPIO_PAR_PCIBR MCF_REG16(0x000A4A) ++#define MCF_GPIO_PAR_PSC3 MCF_REG08(0x000A4C) ++#define MCF_GPIO_PAR_PSC2 MCF_REG08(0x000A4D) ++#define MCF_GPIO_PAR_PSC1 MCF_REG08(0x000A4E) ++#define MCF_GPIO_PAR_PSC0 MCF_REG08(0x000A4F) ++#define MCF_GPIO_PAR_DSPI MCF_REG16(0x000A50) ++#define MCF_GPIO_PAR_TIMER MCF_REG08(0x000A52) ++ ++/* Bit definitions and macros for MCF_GPIO_PODR_FBCTL */ ++#define MCF_GPIO_PODR_FBCTL_PODRFBCTL0 (0x01) ++#define MCF_GPIO_PODR_FBCTL_PODRFBCTL1 (0x02) ++#define MCF_GPIO_PODR_FBCTL_PODRFBCTL2 (0x04) ++#define MCF_GPIO_PODR_FBCTL_PODRFBCTL3 (0x08) ++#define MCF_GPIO_PODR_FBCTL_PODRFBCTL4 (0x10) ++#define MCF_GPIO_PODR_FBCTL_PODRFBCTL5 (0x20) ++#define MCF_GPIO_PODR_FBCTL_PODRFBCTL6 (0x40) ++#define MCF_GPIO_PODR_FBCTL_PODRFBCTL7 (0x80) ++ ++/* Bit definitions and macros for MCF_GPIO_PODR_FBCS */ ++#define MCF_GPIO_PODR_FBCS_PODRFBCS1 (0x02) ++#define MCF_GPIO_PODR_FBCS_PODRFBCS2 (0x04) ++#define MCF_GPIO_PODR_FBCS_PODRFBCS3 (0x08) ++#define MCF_GPIO_PODR_FBCS_PODRFBCS4 (0x10) ++#define MCF_GPIO_PODR_FBCS_PODRFBCS5 (0x20) ++ ++/* Bit definitions and macros for MCF_GPIO_PODR_DMA */ ++#define MCF_GPIO_PODR_DMA_PODRDMA0 (0x01) ++#define MCF_GPIO_PODR_DMA_PODRDMA1 (0x02) ++#define MCF_GPIO_PODR_DMA_PODRDMA2 (0x04) ++#define MCF_GPIO_PODR_DMA_PODRDMA3 (0x08) ++ ++/* Bit definitions and macros for MCF_GPIO_PODR_FEC0H */ ++#define MCF_GPIO_PODR_FEC0H_PODRFEC0H0 (0x01) ++#define MCF_GPIO_PODR_FEC0H_PODRFEC0H1 (0x02) ++#define MCF_GPIO_PODR_FEC0H_PODRFEC0H2 (0x04) ++#define MCF_GPIO_PODR_FEC0H_PODRFEC0H3 (0x08) ++#define MCF_GPIO_PODR_FEC0H_PODRFEC0H4 (0x10) ++#define MCF_GPIO_PODR_FEC0H_PODRFEC0H5 (0x20) ++#define MCF_GPIO_PODR_FEC0H_PODRFEC0H6 (0x40) ++#define MCF_GPIO_PODR_FEC0H_PODRFEC0H7 (0x80) ++ ++/* Bit definitions and macros for MCF_GPIO_PODR_FEC0L */ ++#define MCF_GPIO_PODR_FEC0L_PODRFEC0L0 (0x01) ++#define MCF_GPIO_PODR_FEC0L_PODRFEC0L1 (0x02) ++#define MCF_GPIO_PODR_FEC0L_PODRFEC0L2 (0x04) ++#define MCF_GPIO_PODR_FEC0L_PODRFEC0L3 (0x08) ++#define MCF_GPIO_PODR_FEC0L_PODRFEC0L4 (0x10) ++#define MCF_GPIO_PODR_FEC0L_PODRFEC0L5 (0x20) ++#define MCF_GPIO_PODR_FEC0L_PODRFEC0L6 (0x40) ++#define MCF_GPIO_PODR_FEC0L_PODRFEC0L7 (0x80) ++ ++/* Bit definitions and macros for MCF_GPIO_PODR_FEC1H */ ++#define MCF_GPIO_PODR_FEC1H_PODRFEC1H0 (0x01) ++#define MCF_GPIO_PODR_FEC1H_PODRFEC1H1 (0x02) ++#define MCF_GPIO_PODR_FEC1H_PODRFEC1H2 (0x04) ++#define MCF_GPIO_PODR_FEC1H_PODRFEC1H3 (0x08) ++#define MCF_GPIO_PODR_FEC1H_PODRFEC1H4 (0x10) ++#define MCF_GPIO_PODR_FEC1H_PODRFEC1H5 (0x20) ++#define MCF_GPIO_PODR_FEC1H_PODRFEC1H6 (0x40) ++#define MCF_GPIO_PODR_FEC1H_PODRFEC1H7 (0x80) ++ ++/* Bit definitions and macros for MCF_GPIO_PODR_FEC1L */ ++#define MCF_GPIO_PODR_FEC1L_PODRFEC1L0 (0x01) ++#define MCF_GPIO_PODR_FEC1L_PODRFEC1L1 (0x02) ++#define MCF_GPIO_PODR_FEC1L_PODRFEC1L2 (0x04) ++#define MCF_GPIO_PODR_FEC1L_PODRFEC1L3 (0x08) ++#define MCF_GPIO_PODR_FEC1L_PODRFEC1L4 (0x10) ++#define MCF_GPIO_PODR_FEC1L_PODRFEC1L5 (0x20) ++#define MCF_GPIO_PODR_FEC1L_PODRFEC1L6 (0x40) ++#define MCF_GPIO_PODR_FEC1L_PODRFEC1L7 (0x80) ++ ++/* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */ ++#define MCF_GPIO_PODR_FECI2C_PODRFECI2C0 (0x01) ++#define MCF_GPIO_PODR_FECI2C_PODRFECI2C1 (0x02) ++#define MCF_GPIO_PODR_FECI2C_PODRFECI2C2 (0x04) ++#define MCF_GPIO_PODR_FECI2C_PODRFECI2C3 (0x08) ++ ++/* Bit definitions and macros for MCF_GPIO_PODR_PCIBG */ ++#define MCF_GPIO_PODR_PCIBG_PODRPCIBG0 (0x01) ++#define MCF_GPIO_PODR_PCIBG_PODRPCIBG1 (0x02) ++#define MCF_GPIO_PODR_PCIBG_PODRPCIBG2 (0x04) ++#define MCF_GPIO_PODR_PCIBG_PODRPCIBG3 (0x08) ++#define MCF_GPIO_PODR_PCIBG_PODRPCIBG4 (0x10) ++ ++/* Bit definitions and macros for MCF_GPIO_PODR_PCIBR */ ++#define MCF_GPIO_PODR_PCIBR_PODRPCIBR0 (0x01) ++#define MCF_GPIO_PODR_PCIBR_PODRPCIBR1 (0x02) ++#define MCF_GPIO_PODR_PCIBR_PODRPCIBR2 (0x04) ++#define MCF_GPIO_PODR_PCIBR_PODRPCIBR3 (0x08) ++#define MCF_GPIO_PODR_PCIBR_PODRPCIBR4 (0x10) ++ ++/* Bit definitions and macros for MCF_GPIO_PODR_PSC3PSC2 */ ++#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC20 (0x01) ++#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC21 (0x02) ++#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC22 (0x04) ++#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC23 (0x08) ++#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC24 (0x10) ++#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC25 (0x20) ++#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC26 (0x40) ++#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC27 (0x80) ++ ++/* Bit definitions and macros for MCF_GPIO_PODR_PSC1PSC0 */ ++#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC00 (0x01) ++#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC01 (0x02) ++#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC02 (0x04) ++#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC03 (0x08) ++#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC04 (0x10) ++#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC05 (0x20) ++#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC06 (0x40) ++#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC07 (0x80) ++ ++/* Bit definitions and macros for MCF_GPIO_PODR_DSPI */ ++#define MCF_GPIO_PODR_DSPI_PODRDSPI0 (0x01) ++#define MCF_GPIO_PODR_DSPI_PODRDSPI1 (0x02) ++#define MCF_GPIO_PODR_DSPI_PODRDSPI2 (0x04) ++#define MCF_GPIO_PODR_DSPI_PODRDSPI3 (0x08) ++#define MCF_GPIO_PODR_DSPI_PODRDSPI4 (0x10) ++#define MCF_GPIO_PODR_DSPI_PODRDSPI5 (0x20) ++#define MCF_GPIO_PODR_DSPI_PODRDSPI6 (0x40) ++ ++/* Bit definitions and macros for MCF_GPIO_PDDR_FBCTL */ ++#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL0 (0x01) ++#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL1 (0x02) ++#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL2 (0x04) ++#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL3 (0x08) ++#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL4 (0x10) ++#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL5 (0x20) ++#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL6 (0x40) ++#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL7 (0x80) ++ ++/* Bit definitions and macros for MCF_GPIO_PDDR_FBCS */ ++#define MCF_GPIO_PDDR_FBCS_PDDRFBCS1 (0x02) ++#define MCF_GPIO_PDDR_FBCS_PDDRFBCS2 (0x04) ++#define MCF_GPIO_PDDR_FBCS_PDDRFBCS3 (0x08) ++#define MCF_GPIO_PDDR_FBCS_PDDRFBCS4 (0x10) ++#define MCF_GPIO_PDDR_FBCS_PDDRFBCS5 (0x20) ++ ++/* Bit definitions and macros for MCF_GPIO_PDDR_DMA */ ++#define MCF_GPIO_PDDR_DMA_PDDRDMA0 (0x01) ++#define MCF_GPIO_PDDR_DMA_PDDRDMA1 (0x02) ++#define MCF_GPIO_PDDR_DMA_PDDRDMA2 (0x04) ++#define MCF_GPIO_PDDR_DMA_PDDRDMA3 (0x08) ++ ++/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0H */ ++#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H0 (0x01) ++#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H1 (0x02) ++#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H2 (0x04) ++#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H3 (0x08) ++#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H4 (0x10) ++#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H5 (0x20) ++#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H6 (0x40) ++#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H7 (0x80) ++ ++/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0L */ ++#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L0 (0x01) ++#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L1 (0x02) ++#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L2 (0x04) ++#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L3 (0x08) ++#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L4 (0x10) ++#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L5 (0x20) ++#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L6 (0x40) ++#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L7 (0x80) ++ ++/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1H */ ++#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H0 (0x01) ++#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H1 (0x02) ++#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H2 (0x04) ++#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H3 (0x08) ++#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H4 (0x10) ++#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H5 (0x20) ++#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H6 (0x40) ++#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H7 (0x80) ++ ++/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1L */ ++#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L0 (0x01) ++#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L1 (0x02) ++#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L2 (0x04) ++#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L3 (0x08) ++#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L4 (0x10) ++#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L5 (0x20) ++#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L6 (0x40) ++#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L7 (0x80) ++ ++/* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */ ++#define MCF_GPIO_PDDR_FECI2C_PDDRFECI2C0 (0x01) ++#define MCF_GPIO_PDDR_FECI2C_PDDRFECI2C1 (0x02) ++#define MCF_GPIO_PDDR_FECI2C_PDDRFECI2C2 (0x04) ++#define MCF_GPIO_PDDR_FECI2C_PDDRFECI2C3 (0x08) ++ ++/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBG */ ++#define MCF_GPIO_PDDR_PCIBG_PDDRPCIBG0 (0x01) ++#define MCF_GPIO_PDDR_PCIBG_PDDRPCIBG1 (0x02) ++#define MCF_GPIO_PDDR_PCIBG_PDDRPCIBG2 (0x04) ++#define MCF_GPIO_PDDR_PCIBG_PDDRPCIBG3 (0x08) ++#define MCF_GPIO_PDDR_PCIBG_PDDRPCIBG4 (0x10) ++ ++/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBR */ ++#define MCF_GPIO_PDDR_PCIBR_PDDRPCIBR0 (0x01) ++#define MCF_GPIO_PDDR_PCIBR_PDDRPCIBR1 (0x02) ++#define MCF_GPIO_PDDR_PCIBR_PDDRPCIBR2 (0x04) ++#define MCF_GPIO_PDDR_PCIBR_PDDRPCIBR3 (0x08) ++#define MCF_GPIO_PDDR_PCIBR_PDDRPCIBR4 (0x10) ++ ++/* Bit definitions and macros for MCF_GPIO_PDDR_PSC3PSC2 */ ++#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC20 (0x01) ++#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC21 (0x02) ++#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC22 (0x04) ++#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC23 (0x08) ++#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC24 (0x10) ++#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC25 (0x20) ++#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC26 (0x40) ++#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC27 (0x80) ++ ++/* Bit definitions and macros for MCF_GPIO_PDDR_PSC1PSC0 */ ++#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC00 (0x01) ++#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC01 (0x02) ++#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC02 (0x04) ++#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC03 (0x08) ++#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC04 (0x10) ++#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC05 (0x20) ++#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC06 (0x40) ++#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC07 (0x80) ++ ++/* Bit definitions and macros for MCF_GPIO_PDDR_DSPI */ ++#define MCF_GPIO_PDDR_DSPI_PDDRDSPI0 (0x01) ++#define MCF_GPIO_PDDR_DSPI_PDDRDSPI1 (0x02) ++#define MCF_GPIO_PDDR_DSPI_PDDRDSPI2 (0x04) ++#define MCF_GPIO_PDDR_DSPI_PDDRDSPI3 (0x08) ++#define MCF_GPIO_PDDR_DSPI_PDDRDSPI4 (0x10) ++#define MCF_GPIO_PDDR_DSPI_PDDRDSPI5 (0x20) ++#define MCF_GPIO_PDDR_DSPI_PDDRDSPI6 (0x40) ++ ++/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCTL */ ++#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL0 (0x01) ++#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL1 (0x02) ++#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL2 (0x04) ++#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL3 (0x08) ++#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL4 (0x10) ++#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL5 (0x20) ++#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL6 (0x40) ++#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL7 (0x80) ++ ++/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCS */ ++#define MCF_GPIO_PPDSDR_FBCS_PPDSDRFBCS1 (0x02) ++#define MCF_GPIO_PPDSDR_FBCS_PPDSDRFBCS2 (0x04) ++#define MCF_GPIO_PPDSDR_FBCS_PPDSDRFBCS3 (0x08) ++#define MCF_GPIO_PPDSDR_FBCS_PPDSDRFBCS4 (0x10) ++#define MCF_GPIO_PPDSDR_FBCS_PPDSDRFBCS5 (0x20) ++ ++/* Bit definitions and macros for MCF_GPIO_PPDSDR_DMA */ ++#define MCF_GPIO_PPDSDR_DMA_PPDSDRDMA0 (0x01) ++#define MCF_GPIO_PPDSDR_DMA_PPDSDRDMA1 (0x02) ++#define MCF_GPIO_PPDSDR_DMA_PPDSDRDMA2 (0x04) ++#define MCF_GPIO_PPDSDR_DMA_PPDSDRDMA3 (0x08) ++ ++/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0H */ ++#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H0 (0x01) ++#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H1 (0x02) ++#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H2 (0x04) ++#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H3 (0x08) ++#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H4 (0x10) ++#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H5 (0x20) ++#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H6 (0x40) ++#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H7 (0x80) ++ ++/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0L */ ++#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L0 (0x01) ++#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L1 (0x02) ++#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L2 (0x04) ++#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L3 (0x08) ++#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L4 (0x10) ++#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L5 (0x20) ++#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L6 (0x40) ++#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L7 (0x80) ++ ++/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1H */ ++#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H0 (0x01) ++#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H1 (0x02) ++#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H2 (0x04) ++#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H3 (0x08) ++#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H4 (0x10) ++#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H5 (0x20) ++#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H6 (0x40) ++#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H7 (0x80) ++ ++/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1L */ ++#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L0 (0x01) ++#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L1 (0x02) ++#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L2 (0x04) ++#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L3 (0x08) ++#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L4 (0x10) ++#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L5 (0x20) ++#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L6 (0x40) ++#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L7 (0x80) ++ ++/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */ ++#define MCF_GPIO_PPDSDR_FECI2C_PPDSDRFECI2C0 (0x01) ++#define MCF_GPIO_PPDSDR_FECI2C_PPDSDRFECI2C1 (0x02) ++#define MCF_GPIO_PPDSDR_FECI2C_PPDSDRFECI2C2 (0x04) ++#define MCF_GPIO_PPDSDR_FECI2C_PPDSDRFECI2C3 (0x08) ++ ++/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBG */ ++#define MCF_GPIO_PPDSDR_PCIBG_PPDSDRPCIBG0 (0x01) ++#define MCF_GPIO_PPDSDR_PCIBG_PPDSDRPCIBG1 (0x02) ++#define MCF_GPIO_PPDSDR_PCIBG_PPDSDRPCIBG2 (0x04) ++#define MCF_GPIO_PPDSDR_PCIBG_PPDSDRPCIBG3 (0x08) ++#define MCF_GPIO_PPDSDR_PCIBG_PPDSDRPCIBG4 (0x10) ++ ++/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBR */ ++#define MCF_GPIO_PPDSDR_PCIBR_PPDSDRPCIBR0 (0x01) ++#define MCF_GPIO_PPDSDR_PCIBR_PPDSDRPCIBR1 (0x02) ++#define MCF_GPIO_PPDSDR_PCIBR_PPDSDRPCIBR2 (0x04) ++#define MCF_GPIO_PPDSDR_PCIBR_PPDSDRPCIBR3 (0x08) ++#define MCF_GPIO_PPDSDR_PCIBR_PPDSDRPCIBR4 (0x10) ++ ++/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC3PSC2 */ ++#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDRPSC3PSC20 (0x01) ++#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDRPSC3PSC21 (0x02) ++#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDRPSC3PSC22 (0x04) ++#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDRPSC3PSC23 (0x08) ++#define MCF_GPIO_PPDSDR_PSC3PSC2_PDDRPSC3PSC24 (0x10) ++#define MCF_GPIO_PPDSDR_PSC3PSC2_PDDRPSC3PSC25 (0x20) ++#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDRPSC3PSC26 (0x40) ++#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDRPSC3PSC27 (0x80) ++ ++/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC1PSC0 */ ++#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDRPSC1PSC00 (0x01) ++#define MCF_GPIO_PPDSDR_PSC1PSC0_PDDRPSC1PSC01 (0x02) ++#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDRPSC1PSC02 (0x04) ++#define MCF_GPIO_PPDSDR_PSC1PSC0_PDDRPSC1PSC03 (0x08) ++#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDRPSC1PSC04 (0x10) ++#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDRPSC1PSC05 (0x20) ++#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDRPSC1PSC06 (0x40) ++#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDRPSC1PSC07 (0x80) ++ ++/* Bit definitions and macros for MCF_GPIO_PPDSDR_DSPI */ ++#define MCF_GPIO_PPDSDR_DSPI_PPDSDRDSPI0 (0x01) ++#define MCF_GPIO_PPDSDR_DSPI_PPDSDRDSPI1 (0x02) ++#define MCF_GPIO_PPDSDR_DSPI_PPDSDRDSPI2 (0x04) ++#define MCF_GPIO_PPDSDR_DSPI_PPDSDRDSPI3 (0x08) ++#define MCF_GPIO_PPDSDR_DSPI_PDDRDSPI4 (0x10) ++#define MCF_GPIO_PPDSDR_DSPI_PPDSDRDSPI5 (0x20) ++#define MCF_GPIO_PPDSDR_DSPI_PPDSDRDSPI6 (0x40) ++ ++/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCTL */ ++#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL0 (0x01) ++#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL1 (0x02) ++#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL2 (0x04) ++#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL3 (0x08) ++#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL4 (0x10) ++#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL5 (0x20) ++#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL6 (0x40) ++#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL7 (0x80) ++ ++/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCS */ ++#define MCF_GPIO_PCLRR_FBCS_PCLRRFBCS1 (0x02) ++#define MCF_GPIO_PCLRR_FBCS_PCLRRFBCS2 (0x04) ++#define MCF_GPIO_PCLRR_FBCS_PCLRRFBCS3 (0x08) ++#define MCF_GPIO_PCLRR_FBCS_PCLRRFBCS4 (0x10) ++#define MCF_GPIO_PCLRR_FBCS_PCLRRFBCS5 (0x20) ++ ++/* Bit definitions and macros for MCF_GPIO_PCLRR_DMA */ ++#define MCF_GPIO_PCLRR_DMA_PCLRRDMA0 (0x01) ++#define MCF_GPIO_PCLRR_DMA_PCLRRDMA1 (0x02) ++#define MCF_GPIO_PCLRR_DMA_PCLRRDMA2 (0x04) ++#define MCF_GPIO_PCLRR_DMA_PCLRRDMA3 (0x08) ++ ++/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0H */ ++#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H0 (0x01) ++#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H1 (0x02) ++#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H2 (0x04) ++#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H3 (0x08) ++#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H4 (0x10) ++#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H5 (0x20) ++#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H6 (0x40) ++#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H7 (0x80) ++ ++/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0L */ ++#define MCF_GPIO_PCLRR_FEC0L_PCLRRFEC0L0 (0x01) ++#define MCF_GPIO_PCLRR_FEC0L_PODRFEC0L1 (0x02) ++#define MCF_GPIO_PCLRR_FEC0L_PCLRRFEC0L2 (0x04) ++#define MCF_GPIO_PCLRR_FEC0L_PCLRRFEC0L3 (0x08) ++#define MCF_GPIO_PCLRR_FEC0L_PODRFEC0L4 (0x10) ++#define MCF_GPIO_PCLRR_FEC0L_PODRFEC0L5 (0x20) ++#define MCF_GPIO_PCLRR_FEC0L_PODRFEC0L6 (0x40) ++#define MCF_GPIO_PCLRR_FEC0L_PCLRRFEC0L7 (0x80) ++ ++/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1H */ ++#define MCF_GPIO_PCLRR_FEC1H_PCLRRFEC1H0 (0x01) ++#define MCF_GPIO_PCLRR_FEC1H_PCLRRFEC1H1 (0x02) ++#define MCF_GPIO_PCLRR_FEC1H_PCLRRFEC1H2 (0x04) ++#define MCF_GPIO_PCLRR_FEC1H_PODRFEC1H3 (0x08) ++#define MCF_GPIO_PCLRR_FEC1H_PODRFEC1H4 (0x10) ++#define MCF_GPIO_PCLRR_FEC1H_PCLRRFEC1H5 (0x20) ++#define MCF_GPIO_PCLRR_FEC1H_PCLRRFEC1H6 (0x40) ++#define MCF_GPIO_PCLRR_FEC1H_PCLRRFEC1H7 (0x80) ++ ++/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1L */ ++#define MCF_GPIO_PCLRR_FEC1L_PCLRRFEC1L0 (0x01) ++#define MCF_GPIO_PCLRR_FEC1L_PCLRRFEC1L1 (0x02) ++#define MCF_GPIO_PCLRR_FEC1L_PCLRRFEC1L2 (0x04) ++#define MCF_GPIO_PCLRR_FEC1L_PCLRRFEC1L3 (0x08) ++#define MCF_GPIO_PCLRR_FEC1L_PODRFEC1L4 (0x10) ++#define MCF_GPIO_PCLRR_FEC1L_PCLRRFEC1L5 (0x20) ++#define MCF_GPIO_PCLRR_FEC1L_PCLRRFEC1L6 (0x40) ++#define MCF_GPIO_PCLRR_FEC1L_PCLRRFEC1L7 (0x80) ++ ++/* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */ ++#define MCF_GPIO_PCLRR_FECI2C_PCLRRFECI2C0 (0x01) ++#define MCF_GPIO_PCLRR_FECI2C_PCLRRFECI2C1 (0x02) ++#define MCF_GPIO_PCLRR_FECI2C_PODRFECI2C2 (0x04) ++#define MCF_GPIO_PCLRR_FECI2C_PCLRRFECI2C3 (0x08) ++ ++/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBG */ ++#define MCF_GPIO_PCLRR_PCIBG_PODRPCIBG0 (0x01) ++#define MCF_GPIO_PCLRR_PCIBG_PODRPCIBG1 (0x02) ++#define MCF_GPIO_PCLRR_PCIBG_PODRPCIBG2 (0x04) ++#define MCF_GPIO_PCLRR_PCIBG_PCLRRPCIBG3 (0x08) ++#define MCF_GPIO_PCLRR_PCIBG_PCLRRPCIBG4 (0x10) ++ ++/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBR */ ++#define MCF_GPIO_PCLRR_PCIBR_PCLRRPCIBR0 (0x01) ++#define MCF_GPIO_PCLRR_PCIBR_PCLRRPCIBR1 (0x02) ++#define MCF_GPIO_PCLRR_PCIBR_PCLRRPCIBR2 (0x04) ++#define MCF_GPIO_PCLRR_PCIBR_PODRPCIBR3 (0x08) ++#define MCF_GPIO_PCLRR_PCIBR_PODRPCIBR4 (0x10) ++ ++/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC3PSC2 */ ++#define MCF_GPIO_PCLRR_PSC3PSC2_PODRPSC3PSC20 (0x01) ++#define MCF_GPIO_PCLRR_PSC3PSC2_PODRPSC3PSC21 (0x02) ++#define MCF_GPIO_PCLRR_PSC3PSC2_PCLRRPSC3PSC22 (0x04) ++#define MCF_GPIO_PCLRR_PSC3PSC2_PCLRRPSC3PSC23 (0x08) ++#define MCF_GPIO_PCLRR_PSC3PSC2_PCLRRPSC3PSC24 (0x10) ++#define MCF_GPIO_PCLRR_PSC3PSC2_PODRPSC3PSC25 (0x20) ++#define MCF_GPIO_PCLRR_PSC3PSC2_PODRPSC3PSC26 (0x40) ++#define MCF_GPIO_PCLRR_PSC3PSC2_PCLRRPSC3PSC27 (0x80) ++ ++/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC1PSC0 */ ++#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRRPSC1PSC00 (0x01) ++#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRRPSC1PSC01 (0x02) ++#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRRPSC1PSC02 (0x04) ++#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRRPSC1PSC03 (0x08) ++#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRRPSC1PSC04 (0x10) ++#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRRPSC1PSC05 (0x20) ++#define MCF_GPIO_PCLRR_PSC1PSC0_PODRPSC1PSC06 (0x40) ++#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRRPSC1PSC07 (0x80) ++ ++/* Bit definitions and macros for MCF_GPIO_PCLRR_DSPI */ ++#define MCF_GPIO_PCLRR_DSPI_PCLRRDSPI0 (0x01) ++#define MCF_GPIO_PCLRR_DSPI_PCLRRDSPI1 (0x02) ++#define MCF_GPIO_PCLRR_DSPI_PCLRRDSPI2 (0x04) ++#define MCF_GPIO_PCLRR_DSPI_PCLRRDSPI3 (0x08) ++#define MCF_GPIO_PCLRR_DSPI_PCLRRDSPI4 (0x10) ++#define MCF_GPIO_PCLRR_DSPI_PCLRRDSPI5 (0x20) ++#define MCF_GPIO_PCLRR_DSPI_PCLRRDSPI6 (0x40) ++ ++/* Bit definitions and macros for MCF_GPIO_PAR_FBCTL */ ++#define MCF_GPIO_PAR_FBCTL_PAR_TS(x) (((x)&0x0003)<<0) ++#define MCF_GPIO_PAR_FBCTL_PAR_TA (0x0004) ++#define MCF_GPIO_PAR_FBCTL_PAR_RWB (0x0010) ++#define MCF_GPIO_PAR_FBCTL_PAR_OE (0x0040) ++#define MCF_GPIO_PAR_FBCTL_PAR_BWE0 (0x0100) ++#define MCF_GPIO_PAR_FBCTL_PAR_BWE1 (0x0400) ++#define MCF_GPIO_PAR_FBCTL_PAR_BWE2 (0x1000) ++#define MCF_GPIO_PAR_FBCTL_PAR_BWE3 (0x4000) ++#define MCF_GPIO_PAR_FBCTL_PAR_TS_GPIO (0) ++#define MCF_GPIO_PAR_FBCTL_PAR_TS_TBST (2) ++#define MCF_GPIO_PAR_FBCTL_PAR_TS_TS (3) ++ ++/* Bit definitions and macros for MCF_GPIO_PAR_FBCS */ ++#define MCF_GPIO_PAR_FBCS_PAR_CS1 (0x02) ++#define MCF_GPIO_PAR_FBCS_PAR_CS2 (0x04) ++#define MCF_GPIO_PAR_FBCS_PAR_CS3 (0x08) ++#define MCF_GPIO_PAR_FBCS_PAR_CS4 (0x10) ++#define MCF_GPIO_PAR_FBCS_PAR_CS5 (0x20) ++ ++/* Bit definitions and macros for MCF_GPIO_PAR_DMA */ ++#define MCF_GPIO_PAR_DMA_PAR_DREQ0(x) (((x)&0x03)<<0) ++#define MCF_GPIO_PAR_DMA_PAR_DREQ1(x) (((x)&0x03)<<2) ++#define MCF_GPIO_PAR_DMA_PAR_DACK0(x) (((x)&0x03)<<4) ++#define MCF_GPIO_PAR_DMA_PAR_DACK1(x) (((x)&0x03)<<6) ++#define MCF_GPIO_PAR_DMA_PAR_DACKx_GPIO (0) ++#define MCF_GPIO_PAR_DMA_PAR_DACKx_TOUT (2) ++#define MCF_GPIO_PAR_DMA_PAR_DACKx_DACK (3) ++#define MCF_GPIO_PAR_DMA_PAR_DREQx_GPIO (0) ++#define MCF_GPIO_PAR_DMA_PAR_DREQx_TIN (2) ++#define MCF_GPIO_PAR_DMA_PAR_DREQx_DREQ (3) ++ ++/* Bit definitions and macros for MCF_GPIO_PAR_FECI2CIRQ */ ++#define MCF_GPIO_PAR_FECI2CIRQ_PAR_IRQ5 (0x0001) ++#define MCF_GPIO_PAR_FECI2CIRQ_PAR_IRQ6 (0x0002) ++#define MCF_GPIO_PAR_FECI2CIRQ_PAR_SCL (0x0004) ++#define MCF_GPIO_PAR_FECI2CIRQ_PAR_SDA (0x0008) ++#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC(x) (((x)&0x0003)<<6) ++#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO(x) (((x)&0x0003)<<8) ++#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MII (0x0400) ++#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E17 (0x0800) ++#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MDC (0x1000) ++#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MDIO (0x2000) ++#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MII (0x4000) ++#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E07 (0x8000) ++#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_CANRX (0x0000) ++#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_SDA (0x0200) ++#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_EMDIO (0x0300) ++#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_CANTX (0x0000) ++#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_SCL (0x0080) ++#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_EMDC (0x00C0) ++ ++/* Bit definitions and macros for MCF_GPIO_PAR_PCIBG */ ++#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG0(x) (((x)&0x0003)<<0) ++#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG1(x) (((x)&0x0003)<<2) ++#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG2(x) (((x)&0x0003)<<4) ++#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG3(x) (((x)&0x0003)<<6) ++#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG4(x) (((x)&0x0003)<<8) ++ ++/* Bit definitions and macros for MCF_GPIO_PAR_PCIBR */ ++#define MCF_GPIO_PAR_PCIBR_PAR_PCIBG0(x) (((x)&0x0003)<<0) ++#define MCF_GPIO_PAR_PCIBR_PAR_PCIBG1(x) (((x)&0x0003)<<2) ++#define MCF_GPIO_PAR_PCIBR_PAR_PCIBG2(x) (((x)&0x0003)<<4) ++#define MCF_GPIO_PAR_PCIBR_PAR_PCIBG3(x) (((x)&0x0003)<<6) ++#define MCF_GPIO_PAR_PCIBR_PAR_PCIBR4(x) (((x)&0x0003)<<8) ++ ++/* Bit definitions and macros for MCF_GPIO_PAR_PSC3 */ ++#define MCF_GPIO_PAR_PSC3_PAR_TXD3 (0x04) ++#define MCF_GPIO_PAR_PSC3_PAR_RXD3 (0x08) ++#define MCF_GPIO_PAR_PSC3_PAR_RTS3(x) (((x)&0x03)<<4) ++#define MCF_GPIO_PAR_PSC3_PAR_CTS3(x) (((x)&0x03)<<6) ++#define MCF_GPIO_PAR_PSC3_PAR_CTS3_GPIO (0x00) ++#define MCF_GPIO_PAR_PSC3_PAR_CTS3_BCLK (0x80) ++#define MCF_GPIO_PAR_PSC3_PAR_CTS3_CTS (0xC0) ++#define MCF_GPIO_PAR_PSC3_PAR_RTS3_GPIO (0x00) ++#define MCF_GPIO_PAR_PSC3_PAR_RTS3_FSYNC (0x20) ++#define MCF_GPIO_PAR_PSC3_PAR_RTS3_RTS (0x30) ++#define MCF_GPIO_PAR_PSC3_PAR_CTS2_CANRX (0x40) ++ ++/* Bit definitions and macros for MCF_GPIO_PAR_PSC2 */ ++#define MCF_GPIO_PAR_PSC2_PAR_TXD2 (0x04) ++#define MCF_GPIO_PAR_PSC2_PAR_RXD2 (0x08) ++#define MCF_GPIO_PAR_PSC2_PAR_RTS2(x) (((x)&0x03)<<4) ++#define MCF_GPIO_PAR_PSC2_PAR_CTS2(x) (((x)&0x03)<<6) ++#define MCF_GPIO_PAR_PSC2_PAR_CTS2_GPIO (0x00) ++#define MCF_GPIO_PAR_PSC2_PAR_CTS2_BCLK (0x80) ++#define MCF_GPIO_PAR_PSC2_PAR_CTS2_CTS (0xC0) ++#define MCF_GPIO_PAR_PSC2_PAR_RTS2_GPIO (0x00) ++#define MCF_GPIO_PAR_PSC2_PAR_RTS2_CANTX (0x10) ++#define MCF_GPIO_PAR_PSC2_PAR_RTS2_FSYNC (0x20) ++#define MCF_GPIO_PAR_PSC2_PAR_RTS2_RTS (0x30) ++#define MCF_GPIO_PAR_PSC2_PAR_RTS2_CANRX (0x40) ++ ++/* Bit definitions and macros for MCF_GPIO_PAR_PSC1 */ ++#define MCF_GPIO_PAR_PSC1_PAR_TXD1 (0x04) ++#define MCF_GPIO_PAR_PSC1_PAR_RXD1 (0x08) ++#define MCF_GPIO_PAR_PSC1_PAR_RTS1(x) (((x)&0x03)<<4) ++#define MCF_GPIO_PAR_PSC1_PAR_CTS1(x) (((x)&0x03)<<6) ++#define MCF_GPIO_PAR_PSC1_PAR_CTS1_GPIO (0x00) ++#define MCF_GPIO_PAR_PSC1_PAR_CTS1_BCLK (0x80) ++#define MCF_GPIO_PAR_PSC1_PAR_CTS1_CTS (0xC0) ++#define MCF_GPIO_PAR_PSC1_PAR_RTS1_GPIO (0x00) ++#define MCF_GPIO_PAR_PSC1_PAR_RTS1_FSYNC (0x20) ++#define MCF_GPIO_PAR_PSC1_PAR_RTS1_RTS (0x30) ++ ++/* Bit definitions and macros for MCF_GPIO_PAR_PSC0 */ ++#define MCF_GPIO_PAR_PSC0_PAR_TXD0 (0x04) ++#define MCF_GPIO_PAR_PSC0_PAR_RXD0 (0x08) ++#define MCF_GPIO_PAR_PSC0_PAR_RTS0(x) (((x)&0x03)<<4) ++#define MCF_GPIO_PAR_PSC0_PAR_CTS0(x) (((x)&0x03)<<6) ++#define MCF_GPIO_PAR_PSC0_PAR_CTS0_GPIO (0x00) ++#define MCF_GPIO_PAR_PSC0_PAR_CTS0_BCLK (0x80) ++#define MCF_GPIO_PAR_PSC0_PAR_CTS0_CTS (0xC0) ++#define MCF_GPIO_PAR_PSC0_PAR_RTS0_GPIO (0x00) ++#define MCF_GPIO_PAR_PSC0_PAR_RTS0_FSYNC (0x20) ++#define MCF_GPIO_PAR_PSC0_PAR_RTS0_RTS (0x30) ++ ++/* Bit definitions and macros for MCF_GPIO_PAR_DSPI */ ++#define MCF_GPIO_PAR_DSPI_PAR_SOUT(x) (((x)&0x0003)<<0) ++#define MCF_GPIO_PAR_DSPI_PAR_SIN(x) (((x)&0x0003)<<2) ++#define MCF_GPIO_PAR_DSPI_PAR_SCK(x) (((x)&0x0003)<<4) ++#define MCF_GPIO_PAR_DSPI_PAR_CS0(x) (((x)&0x0003)<<6) ++#define MCF_GPIO_PAR_DSPI_PAR_CS2(x) (((x)&0x0003)<<8) ++#define MCF_GPIO_PAR_DSPI_PAR_CS3(x) (((x)&0x0003)<<10) ++#define MCF_GPIO_PAR_DSPI_PAR_CS5 (0x1000) ++#define MCF_GPIO_PAR_DSPI_PAR_CS3_GPIO (0x0000) ++#define MCF_GPIO_PAR_DSPI_PAR_CS3_CANTX (0x0400) ++#define MCF_GPIO_PAR_DSPI_PAR_CS3_TOUT (0x0800) ++#define MCF_GPIO_PAR_DSPI_PAR_CS3_DSPICS (0x0C00) ++#define MCF_GPIO_PAR_DSPI_PAR_CS2_GPIO (0x0000) ++#define MCF_GPIO_PAR_DSPI_PAR_CS2_CANTX (0x0100) ++#define MCF_GPIO_PAR_DSPI_PAR_CS2_TOUT (0x0200) ++#define MCF_GPIO_PAR_DSPI_PAR_CS2_DSPICS (0x0300) ++#define MCF_GPIO_PAR_DSPI_PAR_CS0_GPIO (0x0000) ++#define MCF_GPIO_PAR_DSPI_PAR_CS0_FSYNC (0x0040) ++#define MCF_GPIO_PAR_DSPI_PAR_CS0_RTS (0x0080) ++#define MCF_GPIO_PAR_DSPI_PAR_CS0_DSPICS (0x00C0) ++#define MCF_GPIO_PAR_DSPI_PAR_SCK_GPIO (0x0000) ++#define MCF_GPIO_PAR_DSPI_PAR_SCK_BCLK (0x0010) ++#define MCF_GPIO_PAR_DSPI_PAR_SCK_CTS (0x0020) ++#define MCF_GPIO_PAR_DSPI_PAR_SCK_SCK (0x0030) ++#define MCF_GPIO_PAR_DSPI_PAR_SIN_GPIO (0x0000) ++#define MCF_GPIO_PAR_DSPI_PAR_SIN_RXD (0x0008) ++#define MCF_GPIO_PAR_DSPI_PAR_SIN_SIN (0x000C) ++#define MCF_GPIO_PAR_DSPI_PAR_SOUT_GPIO (0x0000) ++#define MCF_GPIO_PAR_DSPI_PAR_SOUT_TXD (0x0002) ++#define MCF_GPIO_PAR_DSPI_PAR_SOUT_SOUT (0x0003) ++ ++/* Bit definitions and macros for MCF_GPIO_PAR_TIMER */ ++#define MCF_GPIO_PAR_TIMER_PAR_TOUT2 (0x01) ++#define MCF_GPIO_PAR_TIMER_PAR_TIN2(x) (((x)&0x03)<<1) ++#define MCF_GPIO_PAR_TIMER_PAR_TOUT3 (0x08) ++#define MCF_GPIO_PAR_TIMER_PAR_TIN3(x) (((x)&0x03)<<4) ++#define MCF_GPIO_PAR_TIMER_PAR_TIN3_CANRX (0x00) ++#define MCF_GPIO_PAR_TIMER_PAR_TIN3_IRQ (0x20) ++#define MCF_GPIO_PAR_TIMER_PAR_TIN3_TIN (0x30) ++#define MCF_GPIO_PAR_TIMER_PAR_TIN2_CANRX (0x00) ++#define MCF_GPIO_PAR_TIMER_PAR_TIN2_IRQ (0x04) ++#define MCF_GPIO_PAR_TIMER_PAR_TIN2_TIN (0x06) ++ ++/********************************************************************/ ++ ++#endif /* _M5485GPIO_H_ */ +--- /dev/null ++++ b/arch/m68k/include/asm/m5485gpt.h +@@ -0,0 +1,90 @@ ++/* ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * File: mcf548x_gpt.h ++ * Purpose: Register and bit definitions for the MCF548X ++ * ++ * Notes: ++ * ++ */ ++ ++#ifndef __MCF548X_GPT_H__ ++#define __MCF548X_GPT_H__ ++ ++/********************************************************************* ++* ++* General Purpose Timers (GPT) ++* ++*********************************************************************/ ++ ++/* Register read/write macros */ ++#define MCF_GPT_GMS0 MCF_REG32(0x000800) ++#define MCF_GPT_GCIR0 MCF_REG32(0x000804) ++#define MCF_GPT_GPWM0 MCF_REG32(0x000808) ++#define MCF_GPT_GSR0 MCF_REG32(0x00080C) ++#define MCF_GPT_GMS1 MCF_REG32(0x000810) ++#define MCF_GPT_GCIR1 MCF_REG32(0x000814) ++#define MCF_GPT_GPWM1 MCF_REG32(0x000818) ++#define MCF_GPT_GSR1 MCF_REG32(0x00081C) ++#define MCF_GPT_GMS2 MCF_REG32(0x000820) ++#define MCF_GPT_GCIR2 MCF_REG32(0x000824) ++#define MCF_GPT_GPWM2 MCF_REG32(0x000828) ++#define MCF_GPT_GSR2 MCF_REG32(0x00082C) ++#define MCF_GPT_GMS3 MCF_REG32(0x000830) ++#define MCF_GPT_GCIR3 MCF_REG32(0x000834) ++#define MCF_GPT_GPWM3 MCF_REG32(0x000838) ++#define MCF_GPT_GSR3 MCF_REG32(0x00083C) ++#define MCF_GPT_GMS(x) MCF_REG32(0x000800+((x)*0x010)) ++#define MCF_GPT_GCIR(x) MCF_REG32(0x000804+((x)*0x010)) ++#define MCF_GPT_GPWM(x) MCF_REG32(0x000808+((x)*0x010)) ++#define MCF_GPT_GSR(x) MCF_REG32(0x00080C+((x)*0x010)) ++ ++/* Bit definitions and macros for MCF_GPT_GMS */ ++#define MCF_GPT_GMS_TMS(x) (((x)&0x00000007)<<0) ++#define MCF_GPT_GMS_GPIO(x) (((x)&0x00000003)<<4) ++#define MCF_GPT_GMS_IEN (0x00000100) ++#define MCF_GPT_GMS_OD (0x00000200) ++#define MCF_GPT_GMS_SC (0x00000400) ++#define MCF_GPT_GMS_CE (0x00001000) ++#define MCF_GPT_GMS_WDEN (0x00008000) ++#define MCF_GPT_GMS_ICT(x) (((x)&0x00000003)<<16) ++#define MCF_GPT_GMS_OCT(x) (((x)&0x00000003)<<20) ++#define MCF_GPT_GMS_OCPW(x) (((x)&0x000000FF)<<24) ++#define MCF_GPT_GMS_OCT_FRCLOW (0x00000000) ++#define MCF_GPT_GMS_OCT_PULSEHI (0x00100000) ++#define MCF_GPT_GMS_OCT_PULSELO (0x00200000) ++#define MCF_GPT_GMS_OCT_TOGGLE (0x00300000) ++#define MCF_GPT_GMS_ICT_ANY (0x00000000) ++#define MCF_GPT_GMS_ICT_RISE (0x00010000) ++#define MCF_GPT_GMS_ICT_FALL (0x00020000) ++#define MCF_GPT_GMS_ICT_PULSE (0x00030000) ++#define MCF_GPT_GMS_GPIO_INPUT (0x00000000) ++#define MCF_GPT_GMS_GPIO_OUTLO (0x00000020) ++#define MCF_GPT_GMS_GPIO_OUTHI (0x00000030) ++#define MCF_GPT_GMS_TMS_DISABLE (0x00000000) ++#define MCF_GPT_GMS_TMS_INCAPT (0x00000001) ++#define MCF_GPT_GMS_TMS_OUTCAPT (0x00000002) ++#define MCF_GPT_GMS_TMS_PWM (0x00000003) ++#define MCF_GPT_GMS_TMS_GPIO (0x00000004) ++ ++/* Bit definitions and macros for MCF_GPT_GCIR */ ++#define MCF_GPT_GCIR_CNT(x) (((x)&0x0000FFFF)<<0) ++#define MCF_GPT_GCIR_PRE(x) (((x)&0x0000FFFF)<<16) ++ ++/* Bit definitions and macros for MCF_GPT_GPWM */ ++#define MCF_GPT_GPWM_LOAD (0x00000001) ++#define MCF_GPT_GPWM_PWMOP (0x00000100) ++#define MCF_GPT_GPWM_WIDTH(x) (((x)&0x0000FFFF)<<16) ++ ++/* Bit definitions and macros for MCF_GPT_GSR */ ++#define MCF_GPT_GSR_CAPT (0x00000001) ++#define MCF_GPT_GSR_COMP (0x00000002) ++#define MCF_GPT_GSR_PWMP (0x00000004) ++#define MCF_GPT_GSR_TEXP (0x00000008) ++#define MCF_GPT_GSR_PIN (0x00000100) ++#define MCF_GPT_GSR_OVF(x) (((x)&0x00000007)<<12) ++#define MCF_GPT_GSR_CAPTURE(x) (((x)&0x0000FFFF)<<16) ++ ++#define MCF_GPT_MAX_TIMEOUT 30 ++/********************************************************************/ ++ ++#endif /* __MCF548X_GPT_H__ */ +--- /dev/null ++++ b/arch/m68k/include/asm/m5485pci.h +@@ -0,0 +1,380 @@ ++/* ++ * m5485pci.h -- ColdFire 547x/548x PCI controller support. ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ */ ++#ifndef __MCF548X_PCI_H__ ++#define __MCF548X_PCI_H__ ++ ++ ++/* PCI Type 0 Configuration Registers */ ++#define MCF_PCIIDR MCF_REG32(0x000B00) ++/* PCI Device ID/Vendor ID */ ++#define MCF_PCISCR MCF_REG32(0x000B04) ++/* PCI Status/Command */ ++#define MCF_PCICCRIR MCF_REG32(0x000B08) ++/* PCI Class Code / Revision ID */ ++#define MCF_PCICR1 MCF_REG32(0x000B0C) ++/* PCI Configuration 1 Register */ ++#define MCF_PCIBAR0 MCF_REG32(0x000B10) ++/* PCI Base Address Register 0 */ ++#define MCF_PCIBAR1 MCF_REG32(0x000B14) ++/* PCI Base Address Register 1 */ ++#define MCF_PCICCPR MCF_REG32(0x000B28) ++/* PCI Cardbus CIS Pointer */ ++#define MCF_PCISID MCF_REG32(0x000B2C) ++/* Subsystem ID/Subsystem Vendor ID*/ ++#define MCF_PCIERBAR MCF_REG32(0x000B30) ++/* PCI Expansion ROM */ ++#define MCF_PCICPR MCF_REG32(0x000B30) ++/* PCI Capabilities Pointer */ ++#define MCF_PCICR2 MCF_REG32(0x000B3C) ++/* PCI Configuration Register 2 */ ++ ++/* General Control/Status Registers */ ++#define MCF_PCIGSCR MCF_REG32(0x000B60) ++/* Global Status/Control Register */ ++#define MCF_PCITBATR0 MCF_REG32(0x000B64) ++/* Target Base Address Translation 0*/ ++#define MCF_PCITBATR1 MCF_REG32(0x000B68) ++/* Target Base Address Translation 1*/ ++#define MCF_PCITCR MCF_REG32(0x000B6C) ++/* Target Control Register */ ++#define MCF_PCIIW0BTAR MCF_REG32(0x000B70) ++/* Initiator Window 0 Base Address */ ++#define MCF_PCIIW1BTAR MCF_REG32(0x000B74) ++/* Initiator Window 1 Base Address */ ++#define MCF_PCIIW2BTAR MCF_REG32(0x000B78) ++/* Initiator Window 2 Base Address */ ++#define MCF_PCIIWCR MCF_REG32(0x000B80) ++/* Initiator Window Configuration */ ++#define MCF_PCIICR MCF_REG32(0x000B84) ++/* Initiator Control Register */ ++#define MCF_PCIISR MCF_REG32(0x000B88) ++/* Initiator Status Register */ ++#define MCF_PCICAR MCF_REG32(0x000BF8) ++/* Configuration Address Register */ ++ ++/* CommBus FIFO Transmit Interface Registers */ ++#define MCF_PCITPSR MCF_REG32(0x008400) ++/* Tx Packet Size Register */ ++#define MCF_PCITSAR MCF_REG32(0x008404) ++/* Tx Start Address Register */ ++#define MCF_PCITTCR MCF_REG32(0x008408) ++/* Tx Transaction Control Register */ ++#define MCF_PCITER MCF_REG32(0x00840C) ++/* Tx Enables Register */ ++#define MCF_PCITNAR MCF_REG32(0x008410) ++/* Tx Next Address Register */ ++#define MCF_PCITLWR MCF_REG32(0x008414) ++/* Tx Last Word Register */ ++#define MCF_PCITDCR MCF_REG32(0x008418) ++/* Tx Done Counts Register */ ++#define MCF_PCITSR MCF_REG32(0x00841C) ++/* Tx Status Register */ ++#define MCF_PCITFDR MCF_REG32(0x008440) ++/* Tx FIFO Data Register */ ++#define MCF_PCITFSR MCF_REG32(0x008444) ++/* Tx FIFO Status Register */ ++#define MCF_PCITFCR MCF_REG32(0x008448) ++/* Tx FIFO Control Register */ ++#define MCF_PCITFAR MCF_REG32(0x00844C) ++/* Tx FIFO Alarm Register */ ++#define MCF_PCITFRPR MCF_REG32(0x008450) ++/* Tx FIFO Read Pointer Register */ ++#define MCF_PCITFWPR MCF_REG32(0x008454) ++/* Tx FIFO Write Pointer Register */ ++ ++/* CommBus FIFO Receive Interface Registers */ ++#define MCF_PCIRPSR MCF_REG32(0x008480) ++/* Tx Packet Size Register */ ++#define MCF_PCIRSAR MCF_REG32(0x008484) ++/* Tx Start Address Register */ ++#define MCF_PCIRTCR MCF_REG32(0x008488) ++/* Tx Transaction Control Register */ ++#define MCF_PCIRER MCF_REG32(0x00848C) ++/* Tx Enables Register */ ++#define MCF_PCIRNAR MCF_REG32(0x008490) ++/* Tx Next Address Register */ ++#define MCF_PCIRDCR MCF_REG32(0x008498) ++/* Tx Done Counts Register */ ++#define MCF_PCIRSR MCF_REG32(0x00849C) ++/* Tx Status Register */ ++#define MCF_PCIRFDR MCF_REG32(0x0084C0) ++/* Tx FIFO Data Register */ ++#define MCF_PCIRFSR MCF_REG32(0x0084C4) ++/* Tx FIFO Status Register */ ++#define MCF_PCIRFCR MCF_REG32(0x0084C8) ++/* Tx FIFO Control Register */ ++#define MCF_PCIRFAR MCF_REG32(0x0084CC) ++/* Tx FIFO Alarm Register */ ++#define MCF_PCIRFRPR MCF_REG32(0x0084D0) ++/* Tx FIFO Read Pointer Register */ ++#define MCF_PCIRFWPR MCF_REG32(0x0084D4) ++/* Tx FIFO Write Pointer Register */ ++ ++/* PCI Arbiter Registers */ ++#define MCF_PCIARB_PACR MCF_REG32(0x000C00) ++#define MCF_PCIARB_PASR MCF_REG32(0x000C04) ++ ++ ++/* Bit definitions and macros for MCF_PCIIDR */ ++#define MCF_PCIIDR_VENDORID(x) (((x)&0x0000FFFF)<<0) ++#define MCF_PCIIDR_DEVICEID(x) (((x)&0x0000FFFF)<<16) ++ ++/* Bit definitions and macros for MCF_PCISCR */ ++#define MCF_PCISCR_M (0x00000002) ++#define MCF_PCISCR_B (0x00000004) ++#define MCF_PCISCR_SP (0x00000008) ++#define MCF_PCISCR_MW (0x00000010) ++#define MCF_PCISCR_PER (0x00000040) ++#define MCF_PCISCR_S (0x00000100) ++#define MCF_PCISCR_F (0x00000200) ++#define MCF_PCISCR_C (0x00100000) ++#define MCF_PCISCR_66M (0x00200000) ++#define MCF_PCISCR_R (0x00400000) ++#define MCF_PCISCR_FC (0x00800000) ++#define MCF_PCISCR_DP (0x01000000) ++#define MCF_PCISCR_DT(x) (((x)&0x00000003)<<25) ++#define MCF_PCISCR_TS (0x08000000) ++#define MCF_PCISCR_TR (0x10000000) ++#define MCF_PCISCR_MA (0x20000000) ++#define MCF_PCISCR_SE (0x40000000) ++#define MCF_PCISCR_PE (0x80000000) ++ ++/* Bit definitions and macros for MCF_PCICCRIR */ ++#define MCF_PCICCRIR_REVID(x) (((x)&0x000000FF)<<0) ++#define MCF_PCICCRIR_CLASSCODE(x) (((x)&0x00FFFFFF)<<8) ++ ++/* Bit definitions and macros for MCF_PCICR1 */ ++#define MCF_PCICR1_CACHELINESIZE(x) (((x)&0x0000000F)<<0) ++#define MCF_PCICR1_LATTIMER(x) (((x)&0x000000FF)<<8) ++#define MCF_PCICR1_HEADERTYPE(x) (((x)&0x000000FF)<<16) ++#define MCF_PCICR1_BIST(x) (((x)&0x000000FF)<<24) ++ ++/* Bit definitions and macros for MCF_PCIBAR# */ ++#define MCF_PCIBAR0_ADDR(x) (((x)&0x00003FFF)<<18) ++#define MCF_PCIBAR1_ADDR(x) (((x)&0x00000003)<<30) ++ ++/* Bit definitions and macros for MCF_PCICR2 */ ++#define MCF_PCICR2_INTLINE(x) (((x)&0x000000FF)<<0) ++#define MCF_PCICR2_INTPIN(x) (((x)&0x000000FF)<<8) ++#define MCF_PCICR2_MINGNT(x) (((x)&0x000000FF)<<16) ++#define MCF_PCICR2_MAXLAT(x) (((x)&0x000000FF)<<24) ++ ++/* Bit definitions and macros for MCF_PCIGSCR */ ++#define MCF_PCIGSCR_PR (0x00000001) ++#define MCF_PCIGSCR_SEE (0x00001000) ++#define MCF_PCIGSCR_PEE (0x00002000) ++#define MCF_PCIGSCR_SE (0x10000000) ++#define MCF_PCIGSCR_PE (0x20000000) ++ ++/* Bit definitions and macros for MCF_PCITBATR0 */ ++#define MCF_PCITBATR0_EN (0x00000001) ++#define MCF_PCITBATR0_BAT0(x) (((x)&0x00003FFF)<<18) ++ ++/* Bit definitions and macros for MCF_PCITBATR1 */ ++#define MCF_PCITBATR1_EN (0x00000001) ++#define MCF_PCITBATR1_BAT1(x) (((x)&0x00000003)<<30) ++ ++/* Bit definitions and macros for MCF_PCITCR */ ++#define MCF_PCITCR_P (0x00010000) ++#define MCF_PCITCR_LD (0x01000000) ++ ++/* Bit definitions and macros for MCF_PCIIW0BTAR */ ++#define MCF_PCIIW0BTAR_WTA0(x) (((x)&0x000000FF)<<8) ++#define MCF_PCIIW0BTAR_WAM0(x) (((x)&0x000000FF)<<16) ++#define MCF_PCIIW0BTAR_WBA0(x) (((x)&0x000000FF)<<24) ++ ++/* Bit definitions and macros for MCF_PCIIW1BTAR */ ++#define MCF_PCIIW1BTAR_WTA1(x) (((x)&0x000000FF)<<8) ++#define MCF_PCIIW1BTAR_WAM1(x) (((x)&0x000000FF)<<16) ++#define MCF_PCIIW1BTAR_WBA1(x) (((x)&0x000000FF)<<24) ++ ++/* Bit definitions and macros for MCF_PCIIW2BTAR */ ++#define MCF_PCIIW2BTAR_WTA2(x) (((x)&0x000000FF)<<8) ++#define MCF_PCIIW2BTAR_WAM2(x) (((x)&0x000000FF)<<16) ++#define MCF_PCIIW2BTAR_WBA2(x) (((x)&0x000000FF)<<24) ++ ++/* Bit definitions and macros for MCF_PCIIWCR */ ++#define MCF_PCIIWCR_WINCTRL2(x) (((x)&0x0000000F)<<8) ++#define MCF_PCIIWCR_WINCTRL1(x) (((x)&0x0000000F)<<16) ++#define MCF_PCIIWCR_WINCTRL0(x) (((x)&0x0000000F)<<24) ++#define MCF_PCIIWCR_WINCTRL0_MEMREAD (0x01000000) ++#define MCF_PCIIWCR_WINCTRL0_MEMRDLINE (0x03000000) ++#define MCF_PCIIWCR_WINCTRL0_MEMRDMUL (0x05000000) ++#define MCF_PCIIWCR_WINCTRL0_IO (0x09000000) ++#define MCF_PCIIWCR_WINCTRL0_E (0x01000000) ++#define MCF_PCIIWCR_WINCTRL1_MEMREAD (0x00010000) ++#define MCF_PCIIWCR_WINCTRL1_MEMRDLINE (0x00030000) ++#define MCF_PCIIWCR_WINCTRL1_MEMRDMUL (0x00050000) ++#define MCF_PCIIWCR_WINCTRL1_IO (0x00090000) ++#define MCF_PCIIWCR_WINCTRL1_E (0x00010000) ++#define MCF_PCIIWCR_WINCTRL2_MEMREAD (0x00000100) ++#define MCF_PCIIWCR_WINCTRL2_MEMRDLINE (0x00000300) ++#define MCF_PCIIWCR_WINCTRL2_MEMRDMUL (0x00000500) ++#define MCF_PCIIWCR_WINCTRL2_IO (0x00000900) ++#define MCF_PCIIWCR_WINCTRL2_E (0x00000100) ++ ++ ++/* Bit definitions and macros for MCF_PCIICR */ ++#define MCF_PCIICR_MAXRETRY(x) (((x)&0x000000FF)<<0) ++#define MCF_PCIICR_TAE (0x01000000) ++#define MCF_PCIICR_IAE (0x02000000) ++#define MCF_PCIICR_REE (0x04000000) ++ ++/* Bit definitions and macros for MCF_PCIISR */ ++#define MCF_PCIISR_TA (0x01000000) ++#define MCF_PCIISR_IA (0x02000000) ++#define MCF_PCIISR_RE (0x04000000) ++ ++/* Bit definitions and macros for MCF_PCICAR */ ++#define MCF_PCICAR_DWORD(x) (((x)&0x0000003F)<<2) ++#define MCF_PCICAR_FUNCNUM(x) (((x)&0x00000007)<<8) ++#define MCF_PCICAR_DEVNUM(x) (((x)&0x0000001F)<<11) ++#define MCF_PCICAR_BUSNUM(x) (((x)&0x000000FF)<<16) ++#define MCF_PCICAR_E (0x80000000) ++ ++/* Bit definitions and macros for MCF_PCITPSR */ ++#define MCF_PCITPSR_PKTSIZE(x) (((x)&0x0000FFFF)<<16) ++ ++/* Bit definitions and macros for MCF_PCITTCR */ ++#define MCF_PCITTCR_DI (0x00000001) ++#define MCF_PCITTCR_W (0x00000010) ++#define MCF_PCITTCR_MAXBEATS(x) (((x)&0x00000007)<<8) ++#define MCF_PCITTCR_MAXRETRY(x) (((x)&0x000000FF)<<16) ++#define MCF_PCITTCR_PCICMD(x) (((x)&0x0000000F)<<24) ++ ++/* Bit definitions and macros for MCF_PCITER */ ++#define MCF_PCITER_NE (0x00010000) ++#define MCF_PCITER_IAE (0x00020000) ++#define MCF_PCITER_TAE (0x00040000) ++#define MCF_PCITER_RE (0x00080000) ++#define MCF_PCITER_SE (0x00100000) ++#define MCF_PCITER_FEE (0x00200000) ++#define MCF_PCITER_ME (0x01000000) ++#define MCF_PCITER_BE (0x08000000) ++#define MCF_PCITER_CM (0x10000000) ++#define MCF_PCITER_RF (0x40000000) ++#define MCF_PCITER_RC (0x80000000) ++ ++/* Bit definitions and macros for MCF_PCITDCR */ ++#define MCF_PCITDCR_PKTSDONE(x) (((x)&0x0000FFFF)<<0) ++#define MCF_PCITDCR_BYTESDONE(x) (((x)&0x0000FFFF)<<16) ++ ++/* Bit definitions and macros for MCF_PCITSR */ ++#define MCF_PCITSR_IA (0x00010000) ++#define MCF_PCITSR_TA (0x00020000) ++#define MCF_PCITSR_RE (0x00040000) ++#define MCF_PCITSR_SE (0x00080000) ++#define MCF_PCITSR_FE (0x00100000) ++#define MCF_PCITSR_BE1 (0x00200000) ++#define MCF_PCITSR_BE2 (0x00400000) ++#define MCF_PCITSR_BE3 (0x00800000) ++#define MCF_PCITSR_NT (0x01000000) ++ ++/* Bit definitions and macros for MCF_PCITFSR */ ++#define MCF_PCITFSR_EMT (0x00010000) ++#define MCF_PCITFSR_ALARM (0x00020000) ++#define MCF_PCITFSR_FU (0x00040000) ++#define MCF_PCITFSR_FR (0x00080000) ++#define MCF_PCITFSR_OF (0x00100000) ++#define MCF_PCITFSR_UF (0x00200000) ++#define MCF_PCITFSR_RXW (0x00400000) ++ ++/* Bit definitions and macros for MCF_PCITFCR */ ++#define MCF_PCITFCR_OF_MSK (0x00080000) ++#define MCF_PCITFCR_UF_MSK (0x00100000) ++#define MCF_PCITFCR_RXW_MSK (0x00200000) ++#define MCF_PCITFCR_FAE_MSK (0x00400000) ++#define MCF_PCITFCR_IP_MSK (0x00800000) ++#define MCF_PCITFCR_GR(x) (((x)&0x00000007)<<24) ++ ++/* Bit definitions and macros for MCF_PCITFAR */ ++#define MCF_PCITFAR_ALARM(x) (((x)&0x0000007F)<<0) ++ ++/* Bit definitions and macros for MCF_PCITFRPR */ ++#define MCF_PCITFRPR_READ(x) (((x)&0x00000FFF)<<0) ++ ++/* Bit definitions and macros for MCF_PCITFWPR */ ++#define MCF_PCITFWPR_WRITE(x) (((x)&0x00000FFF)<<0) ++ ++/* Bit definitions and macros for MCF_PCIRPSR */ ++#define MCF_PCIRPSR_PKTSIZE(x) (((x)&0x0000FFFF)<<16) ++ ++/* Bit definitions and macros for MCF_PCIRTCR */ ++#define MCF_PCIRTCR_DI (0x00000001) ++#define MCF_PCIRTCR_W (0x00000010) ++#define MCF_PCIRTCR_MAXBEATS(x) (((x)&0x00000007)<<8) ++#define MCF_PCIRTCR_FB (0x00001000) ++#define MCF_PCIRTCR_MAXRETRY(x) (((x)&0x000000FF)<<16) ++#define MCF_PCIRTCR_PCICMD(x) (((x)&0x0000000F)<<24) ++ ++/* Bit definitions and macros for MCF_PCIRER */ ++#define MCF_PCIRER_NE (0x00010000) ++#define MCF_PCIRER_IAE (0x00020000) ++#define MCF_PCIRER_TAE (0x00040000) ++#define MCF_PCIRER_RE (0x00080000) ++#define MCF_PCIRER_SE (0x00100000) ++#define MCF_PCIRER_FEE (0x00200000) ++#define MCF_PCIRER_ME (0x01000000) ++#define MCF_PCIRER_BE (0x08000000) ++#define MCF_PCIRER_CM (0x10000000) ++#define MCF_PCIRER_FE (0x20000000) ++#define MCF_PCIRER_RF (0x40000000) ++#define MCF_PCIRER_RC (0x80000000) ++ ++/* Bit definitions and macros for MCF_PCIRDCR */ ++#define MCF_PCIRDCR_PKTSDONE(x) (((x)&0x0000FFFF)<<0) ++#define MCF_PCIRDCR_BYTESDONE(x) (((x)&0x0000FFFF)<<16) ++ ++/* Bit definitions and macros for MCF_PCIRSR */ ++#define MCF_PCIRSR_IA (0x00010000) ++#define MCF_PCIRSR_TA (0x00020000) ++#define MCF_PCIRSR_RE (0x00040000) ++#define MCF_PCIRSR_SE (0x00080000) ++#define MCF_PCIRSR_FE (0x00100000) ++#define MCF_PCIRSR_BE1 (0x00200000) ++#define MCF_PCIRSR_BE2 (0x00400000) ++#define MCF_PCIRSR_BE3 (0x00800000) ++#define MCF_PCIRSR_NT (0x01000000) ++ ++/* Bit definitions and macros for MCF_PCIRFSR */ ++#define MCF_PCIRFSR_EMT (0x00010000) ++#define MCF_PCIRFSR_ALARM (0x00020000) ++#define MCF_PCIRFSR_FU (0x00040000) ++#define MCF_PCIRFSR_FR (0x00080000) ++#define MCF_PCIRFSR_OF (0x00100000) ++#define MCF_PCIRFSR_UF (0x00200000) ++#define MCF_PCIRFSR_RXW (0x00400000) ++ ++/* Bit definitions and macros for MCF_PCIRFCR */ ++#define MCF_PCIRFCR_OF_MSK (0x00080000) ++#define MCF_PCIRFCR_UF_MSK (0x00100000) ++#define MCF_PCIRFCR_RXW_MSK (0x00200000) ++#define MCF_PCIRFCR_FAE_MSK (0x00400000) ++#define MCF_PCIRFCR_IP_MSK (0x00800000) ++#define MCF_PCIRFCR_GR(x) (((x)&0x00000007)<<24) ++ ++/* Bit definitions and macros for MCF_PCIRFAR */ ++#define MCF_PCIRFAR_ALARM(x) (((x)&0x0000007F)<<0) ++ ++/* Bit definitions and macros for MCF_PCIRFRPR */ ++#define MCF_PCIRFRPR_READ(x) (((x)&0x00000FFF)<<0) ++ ++/* Bit definitions and macros for MCF_PCIRFWPR */ ++#define MCF_PCIRFWPR_WRITE(x) (((x)&0x00000FFF)<<0) ++ ++ ++/* Bit definitions and macros for MCF_PCIARB_PACR */ ++#define MCF_PCIARB_PACR_INTMPRI (0x00000001) ++#define MCF_PCIARB_PACR_EXTMPRI(x) (((x)&0x0000001F)<<1) ++#define MCF_PCIARB_PACR_INTMINTEN (0x00010000) ++#define MCF_PCIARB_PACR_EXTMINTEN(x) (((x)&0x0000001F)<<17) ++#define MCF_PCIARB_PACR_PKMD (0x40000000) ++#define MCF_PCIARB_PACR_DS (0x80000000) ++ ++/* Bit definitions and macros for MCF_PCIARB_PASR */ ++#define MCF_PCIARB_PASR_ITLMBK (0x00010000) ++#define MCF_PCIARB_PASR_EXTMBK(x) (((x)&0x0000001F)<<17) ++ ++#endif /* __MCF548X_PCI_H__ */ +--- /dev/null ++++ b/arch/m68k/include/asm/m5485psc.h +@@ -0,0 +1,475 @@ ++/* ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * File: mcf548x_psc.h ++ * Purpose: Register and bit definitions for the MCF548X ++ * ++ * Notes ++ * ++ */ ++ ++#ifndef __MCF548X_PSC_H__ ++#define __MCF548X_PSC_H__ ++ ++/********************************************************************* ++* ++* Programmable Serial Controller (PSC) ++* ++*********************************************************************/ ++ ++/* Register read/write macros */ ++#define MCF_PSC_MR0 MCF_REG08(0x008600) ++#define MCF_PSC_SR0 MCF_REG16(0x008604) ++#define MCF_PSC_CSR0 MCF_REG08(0x008604) ++#define MCF_PSC_CR0 MCF_REG08(0x008608) ++#define MCF_PSC_RB0 MCF_REG32(0x00860C) ++#define MCF_PSC_TB0 MCF_REG32(0x00860C) ++#define MCF_PSC_TB_8BIT0 MCF_REG32(0x00860C) ++#define MCF_PSC_TB_16BIT0 MCF_REG32(0x00860C) ++#define MCF_PSC_TB_AC970 MCF_REG32(0x00860C) ++#define MCF_PSC_IPCR0 MCF_REG08(0x008610) ++#define MCF_PSC_ACR0 MCF_REG08(0x008610) ++#define MCF_PSC_ISR0 MCF_REG16(0x008614) ++#define MCF_PSC_IMR0 MCF_REG16(0x008614) ++#define MCF_PSC_CTUR0 MCF_REG08(0x008618) ++#define MCF_PSC_CTLR0 MCF_REG08(0x00861C) ++#define MCF_PSC_IP0 MCF_REG08(0x008634) ++#define MCF_PSC_OPSET0 MCF_REG08(0x008638) ++#define MCF_PSC_OPRESET0 MCF_REG08(0x00863C) ++#define MCF_PSC_SICR0 MCF_REG08(0x008640) ++#define MCF_PSC_IRCR10 MCF_REG08(0x008644) ++#define MCF_PSC_IRCR20 MCF_REG08(0x008648) ++#define MCF_PSC_IRSDR0 MCF_REG08(0x00864C) ++#define MCF_PSC_IRMDR0 MCF_REG08(0x008650) ++#define MCF_PSC_IRFDR0 MCF_REG08(0x008654) ++#define MCF_PSC_RFCNT0 MCF_REG16(0x008658) ++#define MCF_PSC_TFCNT0 MCF_REG16(0x00865C) ++#define MCF_PSC_RFSR0 MCF_REG16(0x008664) ++#define MCF_PSC_TFSR0 MCF_REG16(0x008684) ++#define MCF_PSC_RFCR0 MCF_REG32(0x008668) ++#define MCF_PSC_TFCR0 MCF_REG32(0x008688) ++#define MCF_PSC_RFAR0 MCF_REG16(0x00866E) ++#define MCF_PSC_TFAR0 MCF_REG16(0x00868E) ++#define MCF_PSC_RFRP0 MCF_REG16(0x008672) ++#define MCF_PSC_TFRP0 MCF_REG16(0x008692) ++#define MCF_PSC_RFWP0 MCF_REG16(0x008676) ++#define MCF_PSC_TFWP0 MCF_REG16(0x008696) ++#define MCF_PSC_RLRFP0 MCF_REG16(0x00867A) ++#define MCF_PSC_TLRFP0 MCF_REG16(0x00869A) ++#define MCF_PSC_RLWFP0 MCF_REG16(0x00867E) ++#define MCF_PSC_TLWFP0 MCF_REG16(0x00869E) ++#define MCF_PSC_MR1 MCF_REG08(0x008700) ++#define MCF_PSC_SR1 MCF_REG16(0x008704) ++#define MCF_PSC_CSR1 MCF_REG08(0x008704) ++#define MCF_PSC_CR1 MCF_REG08(0x008708) ++#define MCF_PSC_RB1 MCF_REG32(0x00870C) ++#define MCF_PSC_TB1 MCF_REG32(0x00870C) ++#define MCF_PSC_TB_8BIT1 MCF_REG32(0x00870C) ++#define MCF_PSC_TB_16BIT1 MCF_REG32(0x00870C) ++#define MCF_PSC_TB_AC971 MCF_REG32(0x00870C) ++#define MCF_PSC_IPCR1 MCF_REG08(0x008710) ++#define MCF_PSC_ACR1 MCF_REG08(0x008710) ++#define MCF_PSC_ISR1 MCF_REG16(0x008714) ++#define MCF_PSC_IMR1 MCF_REG16(0x008714) ++#define MCF_PSC_CTUR1 MCF_REG08(0x008718) ++#define MCF_PSC_CTLR1 MCF_REG08(0x00871C) ++#define MCF_PSC_IP1 MCF_REG08(0x008734) ++#define MCF_PSC_OPSET1 MCF_REG08(0x008738) ++#define MCF_PSC_OPRESET1 MCF_REG08(0x00873C) ++#define MCF_PSC_SICR1 MCF_REG08(0x008740) ++#define MCF_PSC_IRCR11 MCF_REG08(0x008744) ++#define MCF_PSC_IRCR21 MCF_REG08(0x008748) ++#define MCF_PSC_IRSDR1 MCF_REG08(0x00874C) ++#define MCF_PSC_IRMDR1 MCF_REG08(0x008750) ++#define MCF_PSC_IRFDR1 MCF_REG08(0x008754) ++#define MCF_PSC_RFCNT1 MCF_REG16(0x008758) ++#define MCF_PSC_TFCNT1 MCF_REG16(0x00875C) ++#define MCF_PSC_RFSR1 MCF_REG16(0x008764) ++#define MCF_PSC_TFSR1 MCF_REG16(0x008784) ++#define MCF_PSC_RFCR1 MCF_REG32(0x008768) ++#define MCF_PSC_TFCR1 MCF_REG32(0x008788) ++#define MCF_PSC_RFAR1 MCF_REG16(0x00876E) ++#define MCF_PSC_TFAR1 MCF_REG16(0x00878E) ++#define MCF_PSC_RFRP1 MCF_REG16(0x008772) ++#define MCF_PSC_TFRP1 MCF_REG16(0x008792) ++#define MCF_PSC_RFWP1 MCF_REG16(0x008776) ++#define MCF_PSC_TFWP1 MCF_REG16(0x008796) ++#define MCF_PSC_RLRFP1 MCF_REG16(0x00877A) ++#define MCF_PSC_TLRFP1 MCF_REG16(0x00879A) ++#define MCF_PSC_RLWFP1 MCF_REG16(0x00877E) ++#define MCF_PSC_TLWFP1 MCF_REG16(0x00879E) ++#define MCF_PSC_MR2 MCF_REG08(0x008800) ++#define MCF_PSC_SR2 MCF_REG16(0x008804) ++#define MCF_PSC_CSR2 MCF_REG08(0x008804) ++#define MCF_PSC_CR2 MCF_REG08(0x008808) ++#define MCF_PSC_RB2 MCF_REG32(0x00880C) ++#define MCF_PSC_TB2 MCF_REG32(0x00880C) ++#define MCF_PSC_TB_8BIT2 MCF_REG32(0x00880C) ++#define MCF_PSC_TB_16BIT2 MCF_REG32(0x00880C) ++#define MCF_PSC_TB_AC972 MCF_REG32(0x00880C) ++#define MCF_PSC_IPCR2 MCF_REG08(0x008810) ++#define MCF_PSC_ACR2 MCF_REG08(0x008810) ++#define MCF_PSC_ISR2 MCF_REG16(0x008814) ++#define MCF_PSC_IMR2 MCF_REG16(0x008814) ++#define MCF_PSC_CTUR2 MCF_REG08(0x008818) ++#define MCF_PSC_CTLR2 MCF_REG08(0x00881C) ++#define MCF_PSC_IP2 MCF_REG08(0x008834) ++#define MCF_PSC_OPSET2 MCF_REG08(0x008838) ++#define MCF_PSC_OPRESET2 MCF_REG08(0x00883C) ++#define MCF_PSC_SICR2 MCF_REG08(0x008840) ++#define MCF_PSC_IRCR12 MCF_REG08(0x008844) ++#define MCF_PSC_IRCR22 MCF_REG08(0x008848) ++#define MCF_PSC_IRSDR2 MCF_REG08(0x00884C) ++#define MCF_PSC_IRMDR2 MCF_REG08(0x008850) ++#define MCF_PSC_IRFDR2 MCF_REG08(0x008854) ++#define MCF_PSC_RFCNT2 MCF_REG16(0x008858) ++#define MCF_PSC_TFCNT2 MCF_REG16(0x00885C) ++#define MCF_PSC_RFSR2 MCF_REG16(0x008864) ++#define MCF_PSC_TFSR2 MCF_REG16(0x008884) ++#define MCF_PSC_RFCR2 MCF_REG32(0x008868) ++#define MCF_PSC_TFCR2 MCF_REG32(0x008888) ++#define MCF_PSC_RFAR2 MCF_REG16(0x00886E) ++#define MCF_PSC_TFAR2 MCF_REG16(0x00888E) ++#define MCF_PSC_RFRP2 MCF_REG16(0x008872) ++#define MCF_PSC_TFRP2 MCF_REG16(0x008892) ++#define MCF_PSC_RFWP2 MCF_REG16(0x008876) ++#define MCF_PSC_TFWP2 MCF_REG16(0x008896) ++#define MCF_PSC_RLRFP2 MCF_REG16(0x00887A) ++#define MCF_PSC_TLRFP2 MCF_REG16(0x00889A) ++#define MCF_PSC_RLWFP2 MCF_REG16(0x00887E) ++#define MCF_PSC_TLWFP2 MCF_REG16(0x00889E) ++#define MCF_PSC_MR3 MCF_REG08(0x008900) ++#define MCF_PSC_SR3 MCF_REG16(0x008904) ++#define MCF_PSC_CSR3 MCF_REG08(0x008904) ++#define MCF_PSC_CR3 MCF_REG08(0x008908) ++#define MCF_PSC_RB3 MCF_REG32(0x00890C) ++#define MCF_PSC_TB3 MCF_REG32(0x00890C) ++#define MCF_PSC_TB_8BIT3 MCF_REG32(0x00890C) ++#define MCF_PSC_TB_16BIT3 MCF_REG32(0x00890C) ++#define MCF_PSC_TB_AC973 MCF_REG32(0x00890C) ++#define MCF_PSC_IPCR3 MCF_REG08(0x008910) ++#define MCF_PSC_ACR3 MCF_REG08(0x008910) ++#define MCF_PSC_ISR3 MCF_REG16(0x008914) ++#define MCF_PSC_IMR3 MCF_REG16(0x008914) ++#define MCF_PSC_CTUR3 MCF_REG08(0x008918) ++#define MCF_PSC_CTLR3 MCF_REG08(0x00891C) ++#define MCF_PSC_IP3 MCF_REG08(0x008934) ++#define MCF_PSC_OPSET3 MCF_REG08(0x008938) ++#define MCF_PSC_OPRESET3 MCF_REG08(0x00893C) ++#define MCF_PSC_SICR3 MCF_REG08(0x008940) ++#define MCF_PSC_IRCR13 MCF_REG08(0x008944) ++#define MCF_PSC_IRCR23 MCF_REG08(0x008948) ++#define MCF_PSC_IRSDR3 MCF_REG08(0x00894C) ++#define MCF_PSC_IRMDR3 MCF_REG08(0x008950) ++#define MCF_PSC_IRFDR3 MCF_REG08(0x008954) ++#define MCF_PSC_RFCNT3 MCF_REG16(0x008958) ++#define MCF_PSC_TFCNT3 MCF_REG16(0x00895C) ++#define MCF_PSC_RFSR3 MCF_REG16(0x008964) ++#define MCF_PSC_TFSR3 MCF_REG16(0x008984) ++#define MCF_PSC_RFCR3 MCF_REG32(0x008968) ++#define MCF_PSC_TFCR3 MCF_REG32(0x008988) ++#define MCF_PSC_RFAR3 MCF_REG16(0x00896E) ++#define MCF_PSC_TFAR3 MCF_REG16(0x00898E) ++#define MCF_PSC_RFRP3 MCF_REG16(0x008972) ++#define MCF_PSC_TFRP3 MCF_REG16(0x008992) ++#define MCF_PSC_RFWP3 MCF_REG16(0x008976) ++#define MCF_PSC_TFWP3 MCF_REG16(0x008996) ++#define MCF_PSC_RLRFP3 MCF_REG16(0x00897A) ++#define MCF_PSC_TLRFP3 MCF_REG16(0x00899A) ++#define MCF_PSC_RLWFP3 MCF_REG16(0x00897E) ++#define MCF_PSC_TLWFP3 MCF_REG16(0x00899E) ++#define MCF_PSC_MR(x) MCF_REG08(0x008600+((x)*0x100)) ++#define MCF_PSC_SR(x) MCF_REG16(0x008604+((x)*0x100)) ++#define MCF_PSC_CSR(x) MCF_REG08(0x008604+((x)*0x100)) ++#define MCF_PSC_CR(x) MCF_REG08(0x008608+((x)*0x100)) ++#define MCF_PSC_RB(x) MCF_REG32(0x00860C+((x)*0x100)) ++#define MCF_PSC_TB(x) MCF_REG32(0x00860C+((x)*0x100)) ++#define MCF_PSC_TB_8BIT(x) MCF_REG32(0x00860C+((x)*0x100)) ++#define MCF_PSC_TB_16BIT(x) MCF_REG32(0x00860C+((x)*0x100)) ++#define MCF_PSC_TB_AC97(x) MCF_REG32(0x00860C+((x)*0x100)) ++#define MCF_PSC_IPCR(x) MCF_REG08(0x008610+((x)*0x100)) ++#define MCF_PSC_ACR(x) MCF_REG08(0x008610+((x)*0x100)) ++#define MCF_PSC_ISR(x) MCF_REG16(0x008614+((x)*0x100)) ++#define MCF_PSC_IMR(x) MCF_REG16(0x008614+((x)*0x100)) ++#define MCF_PSC_CTUR(x) MCF_REG08(0x008618+((x)*0x100)) ++#define MCF_PSC_CTLR(x) MCF_REG08(0x00861C+((x)*0x100)) ++#define MCF_PSC_IP(x) MCF_REG08(0x008634+((x)*0x100)) ++#define MCF_PSC_OPSET(x) MCF_REG08(0x008638+((x)*0x100)) ++#define MCF_PSC_OPRESET(x) MCF_REG08(0x00863C+((x)*0x100)) ++#define MCF_PSC_SICR(x) MCF_REG08(0x008640+((x)*0x100)) ++#define MCF_PSC_IRCR1(x) MCF_REG08(0x008644+((x)*0x100)) ++#define MCF_PSC_IRCR2(x) MCF_REG08(0x008648+((x)*0x100)) ++#define MCF_PSC_IRSDR(x) MCF_REG08(0x00864C+((x)*0x100)) ++#define MCF_PSC_IRMDR(x) MCF_REG08(0x008650+((x)*0x100)) ++#define MCF_PSC_IRFDR(x) MCF_REG08(0x008654+((x)*0x100)) ++#define MCF_PSC_RFCNT(x) MCF_REG16(0x008658+((x)*0x100)) ++#define MCF_PSC_TFCNT(x) MCF_REG16(0x00865C+((x)*0x100)) ++#define MCF_PSC_RFSR(x) MCF_REG16(0x008664+((x)*0x100)) ++#define MCF_PSC_TFSR(x) MCF_REG16(0x008684+((x)*0x100)) ++#define MCF_PSC_RFCR(x) MCF_REG32(0x008668+((x)*0x100)) ++#define MCF_PSC_TFCR(x) MCF_REG32(0x008688+((x)*0x100)) ++#define MCF_PSC_RFAR(x) MCF_REG16((0x00866E)+((x)*0x100)) ++#define MCF_PSC_TFAR(x) MCF_REG16((0x00868E)+((x)*0x100)) ++#define MCF_PSC_RFRP(x) MCF_REG16(0x008672+((x)*0x100)) ++#define MCF_PSC_TFRP(x) MCF_REG16(0x008692+((x)*0x100)) ++#define MCF_PSC_RFWP(x) MCF_REG16(0x008676+((x)*0x100)) ++#define MCF_PSC_TFWP(x) MCF_REG16(0x008696+((x)*0x100)) ++#define MCF_PSC_RLRFP(x) MCF_REG16(0x00867A+((x)*0x100)) ++#define MCF_PSC_TLRFP(x) MCF_REG16(0x00869A+((x)*0x100)) ++#define MCF_PSC_RLWFP(x) MCF_REG16(0x00867E+((x)*0x100)) ++#define MCF_PSC_TLWFP(x) MCF_REG16(0x00869E+((x)*0x100)) ++ ++/* Bit definitions and macros for MCF_PSC_MR */ ++#define MCF_PSC_MR_BC(x) (((x)&0x03)<<0) ++#define MCF_PSC_MR_PT (0x04) ++#define MCF_PSC_MR_PM(x) (((x)&0x03)<<3) ++#define MCF_PSC_MR_ERR (0x20) ++#define MCF_PSC_MR_RXIRQ (0x40) ++#define MCF_PSC_MR_RXRTS (0x80) ++#define MCF_PSC_MR_SB(x) (((x)&0x0F)<<0) ++#define MCF_PSC_MR_TXCTS (0x10) ++#define MCF_PSC_MR_TXRTS (0x20) ++#define MCF_PSC_MR_CM(x) (((x)&0x03)<<6) ++#define MCF_PSC_MR_PM_MULTI_ADDR (0x1C) ++#define MCF_PSC_MR_PM_MULTI_DATA (0x18) ++#define MCF_PSC_MR_PM_NONE (0x10) ++#define MCF_PSC_MR_PM_FORCE_HI (0x0C) ++#define MCF_PSC_MR_PM_FORCE_LO (0x08) ++#define MCF_PSC_MR_PM_ODD (0x04) ++#define MCF_PSC_MR_PM_EVEN (0x00) ++#define MCF_PSC_MR_BC_5 (0x00) ++#define MCF_PSC_MR_BC_6 (0x01) ++#define MCF_PSC_MR_BC_7 (0x02) ++#define MCF_PSC_MR_BC_8 (0x03) ++#define MCF_PSC_MR_CM_NORMAL (0x00) ++#define MCF_PSC_MR_CM_ECHO (0x40) ++#define MCF_PSC_MR_CM_LOCAL_LOOP (0x80) ++#define MCF_PSC_MR_CM_REMOTE_LOOP (0xC0) ++#define MCF_PSC_MR_SB_STOP_BITS_1 (0x07) ++#define MCF_PSC_MR_SB_STOP_BITS_15 (0x08) ++#define MCF_PSC_MR_SB_STOP_BITS_2 (0x0F) ++ ++/* Bit definitions and macros for MCF_PSC_SR */ ++#define MCF_PSC_SR_ERR (0x0040) ++#define MCF_PSC_SR_CDE_DEOF (0x0080) ++#define MCF_PSC_SR_RXRDY (0x0100) ++#define MCF_PSC_SR_FU (0x0200) ++#define MCF_PSC_SR_TXRDY (0x0400) ++#define MCF_PSC_SR_TXEMP_URERR (0x0800) ++#define MCF_PSC_SR_OE (0x1000) ++#define MCF_PSC_SR_PE_CRCERR (0x2000) ++#define MCF_PSC_SR_FE_PHYERR (0x4000) ++#define MCF_PSC_SR_RB_NEOF (0x8000) ++ ++/* Bit definitions and macros for MCF_PSC_CSR */ ++#define MCF_PSC_CSR_TCSEL(x) (((x)&0x0F)<<0) ++#define MCF_PSC_CSR_RCSEL(x) (((x)&0x0F)<<4) ++#define MCF_PSC_CSR_RCSEL_SYS_CLK (0xD0) ++#define MCF_PSC_CSR_RCSEL_CTM16 (0xE0) ++#define MCF_PSC_CSR_RCSEL_CTM (0xF0) ++#define MCF_PSC_CSR_TCSEL_SYS_CLK (0x0D) ++#define MCF_PSC_CSR_TCSEL_CTM16 (0x0E) ++#define MCF_PSC_CSR_TCSEL_CTM (0x0F) ++ ++/* Bit definitions and macros for MCF_PSC_CR */ ++#define MCF_PSC_CR_RXC(x) (((x)&0x03)<<0) ++#define MCF_PSC_CR_TXC(x) (((x)&0x03)<<2) ++#define MCF_PSC_CR_MISC(x) (((x)&0x07)<<4) ++#define MCF_PSC_CR_NONE (0x00) ++#define MCF_PSC_CR_STOP_BREAK (0x70) ++#define MCF_PSC_CR_START_BREAK (0x60) ++#define MCF_PSC_CR_BKCHGINT (0x50) ++#define MCF_PSC_CR_RESET_ERROR (0x40) ++#define MCF_PSC_CR_RESET_TX (0x30) ++#define MCF_PSC_CR_RESET_RX (0x20) ++#define MCF_PSC_CR_RESET_MR (0x10) ++#define MCF_PSC_CR_TX_DISABLED (0x08) ++#define MCF_PSC_CR_TX_ENABLED (0x04) ++#define MCF_PSC_CR_RX_DISABLED (0x02) ++#define MCF_PSC_CR_RX_ENABLED (0x01) ++ ++/* Bit definitions and macros for MCF_PSC_TB_8BIT */ ++#define MCF_PSC_TB_8BIT_TB3(x) (((x)&0x000000FF)<<0) ++#define MCF_PSC_TB_8BIT_TB2(x) (((x)&0x000000FF)<<8) ++#define MCF_PSC_TB_8BIT_TB1(x) (((x)&0x000000FF)<<16) ++#define MCF_PSC_TB_8BIT_TB0(x) (((x)&0x000000FF)<<24) ++ ++/* Bit definitions and macros for MCF_PSC_TB_16BIT */ ++#define MCF_PSC_TB_16BIT_TB1(x) (((x)&0x0000FFFF)<<0) ++#define MCF_PSC_TB_16BIT_TB0(x) (((x)&0x0000FFFF)<<16) ++ ++/* Bit definitions and macros for MCF_PSC_TB_AC97 */ ++#define MCF_PSC_TB_AC97_SOF (0x00000800) ++#define MCF_PSC_TB_AC97_TB(x) (((x)&0x000FFFFF)<<12) ++ ++/* Bit definitions and macros for MCF_PSC_IPCR */ ++#define MCF_PSC_IPCR_RESERVED (0x0C) ++#define MCF_PSC_IPCR_CTS (0x0D) ++#define MCF_PSC_IPCR_D_CTS (0x1C) ++#define MCF_PSC_IPCR_SYNC (0x8C) ++ ++/* Bit definitions and macros for MCF_PSC_ACR */ ++#define MCF_PSC_ACR_IEC0 (0x01) ++#define MCF_PSC_ACR_CTMS(x) (((x)&0x07)<<4) ++#define MCF_PSC_ACR_BRG (0x80) ++ ++/* Bit definitions and macros for MCF_PSC_ISR */ ++#define MCF_PSC_ISR_ERR (0x0040) ++#define MCF_PSC_ISR_DEOF (0x0080) ++#define MCF_PSC_ISR_TXRDY (0x0100) ++#define MCF_PSC_ISR_RXRDY_FU (0x0200) ++#define MCF_PSC_ISR_DB (0x0400) ++#define MCF_PSC_ISR_IPC (0x8000) ++ ++/* Bit definitions and macros for MCF_PSC_IMR */ ++#define MCF_PSC_IMR_ERR (0x0040) ++#define MCF_PSC_IMR_DEOF (0x0080) ++#define MCF_PSC_IMR_TXRDY (0x0100) ++#define MCF_PSC_IMR_RXRDY_FU (0x0200) ++#define MCF_PSC_IMR_DB (0x0400) ++#define MCF_PSC_IMR_IPC (0x8000) ++ ++/* Bit definitions and macros for MCF_PSC_IP */ ++#define MCF_PSC_IP_CTS (0x01) ++#define MCF_PSC_IP_TGL (0x40) ++#define MCF_PSC_IP_LWPR_B (0x80) ++ ++/* Bit definitions and macros for MCF_PSC_OPSET */ ++#define MCF_PSC_OPSET_RTS (0x01) ++ ++/* Bit definitions and macros for MCF_PSC_OPRESET */ ++#define MCF_PSC_OPRESET_RTS (0x01) ++ ++/* Bit definitions and macros for MCF_PSC_SICR */ ++#define MCF_PSC_SICR_SIM(x) (((x)&0x07)<<0) ++#define MCF_PSC_SICR_SHDIR (0x10) ++#define MCF_PSC_SICR_DTS (0x20) ++#define MCF_PSC_SICR_AWR (0x40) ++#define MCF_PSC_SICR_ACRB (0x80) ++#define MCF_PSC_SICR_SIM_UART (0x00) ++#define MCF_PSC_SICR_SIM_MODEM8 (0x01) ++#define MCF_PSC_SICR_SIM_MODEM16 (0x02) ++#define MCF_PSC_SICR_SIM_AC97 (0x03) ++#define MCF_PSC_SICR_SIM_SIR (0x04) ++#define MCF_PSC_SICR_SIM_MIR (0x05) ++#define MCF_PSC_SICR_SIM_FIR (0x06) ++ ++/* Bit definitions and macros for MCF_PSC_IRCR1 */ ++#define MCF_PSC_IRCR1_SPUL (0x01) ++#define MCF_PSC_IRCR1_SIPEN (0x02) ++#define MCF_PSC_IRCR1_FD (0x04) ++ ++/* Bit definitions and macros for MCF_PSC_IRCR2 */ ++#define MCF_PSC_IRCR2_NXTEOF (0x01) ++#define MCF_PSC_IRCR2_ABORT (0x02) ++#define MCF_PSC_IRCR2_SIPREQ (0x04) ++ ++/* Bit definitions and macros for MCF_PSC_IRMDR */ ++#define MCF_PSC_IRMDR_M_FDIV(x) (((x)&0x7F)<<0) ++#define MCF_PSC_IRMDR_FREQ (0x80) ++ ++/* Bit definitions and macros for MCF_PSC_IRFDR */ ++#define MCF_PSC_IRFDR_F_FDIV(x) (((x)&0x0F)<<0) ++ ++/* Bit definitions and macros for MCF_PSC_RFCNT */ ++#define MCF_PSC_RFCNT_CNT(x) (((x)&0x01FF)<<0) ++ ++/* Bit definitions and macros for MCF_PSC_TFCNT */ ++#define MCF_PSC_TFCNT_CNT(x) (((x)&0x01FF)<<0) ++ ++/* Bit definitions and macros for MCF_PSC_RFSR */ ++#define MCF_PSC_RFSR_EMT (0x0001) ++#define MCF_PSC_RFSR_ALARM (0x0002) ++#define MCF_PSC_RFSR_FU (0x0004) ++#define MCF_PSC_RFSR_FRMRY (0x0008) ++#define MCF_PSC_RFSR_OF (0x0010) ++#define MCF_PSC_RFSR_UF (0x0020) ++#define MCF_PSC_RFSR_RXW (0x0040) ++#define MCF_PSC_RFSR_FAE (0x0080) ++#define MCF_PSC_RFSR_FRM(x) (((x)&0x000F)<<8) ++#define MCF_PSC_RFSR_TAG (0x1000) ++#define MCF_PSC_RFSR_TXW (0x4000) ++#define MCF_PSC_RFSR_IP (0x8000) ++#define MCF_PSC_RFSR_FRM_BYTE0 (0x0800) ++#define MCF_PSC_RFSR_FRM_BYTE1 (0x0400) ++#define MCF_PSC_RFSR_FRM_BYTE2 (0x0200) ++#define MCF_PSC_RFSR_FRM_BYTE3 (0x0100) ++ ++/* Bit definitions and macros for MCF_PSC_TFSR */ ++#define MCF_PSC_TFSR_EMT (0x0001) ++#define MCF_PSC_TFSR_ALARM (0x0002) ++#define MCF_PSC_TFSR_FU (0x0004) ++#define MCF_PSC_TFSR_FRMRY (0x0008) ++#define MCF_PSC_TFSR_OF (0x0010) ++#define MCF_PSC_TFSR_UF (0x0020) ++#define MCF_PSC_TFSR_RXW (0x0040) ++#define MCF_PSC_TFSR_FAE (0x0080) ++#define MCF_PSC_TFSR_FRM(x) (((x)&0x000F)<<8) ++#define MCF_PSC_TFSR_TAG (0x1000) ++#define MCF_PSC_TFSR_TXW (0x4000) ++#define MCF_PSC_TFSR_IP (0x8000) ++#define MCF_PSC_TFSR_FRM_BYTE0 (0x0800) ++#define MCF_PSC_TFSR_FRM_BYTE1 (0x0400) ++#define MCF_PSC_TFSR_FRM_BYTE2 (0x0200) ++#define MCF_PSC_TFSR_FRM_BYTE3 (0x0100) ++ ++/* Bit definitions and macros for MCF_PSC_RFCR */ ++#define MCF_PSC_RFCR_CNTR(x) (((x)&0x0000FFFF)<<0) ++#define MCF_PSC_RFCR_TXW_MSK (0x00040000) ++#define MCF_PSC_RFCR_OF_MSK (0x00080000) ++#define MCF_PSC_RFCR_UF_MSK (0x00100000) ++#define MCF_PSC_RFCR_RXW_MSK (0x00200000) ++#define MCF_PSC_RFCR_FAE_MSK (0x00400000) ++#define MCF_PSC_RFCR_IP_MSK (0x00800000) ++#define MCF_PSC_RFCR_GR(x) (((x)&0x00000007)<<24) ++#define MCF_PSC_RFCR_FRMEN (0x08000000) ++#define MCF_PSC_RFCR_TIMER (0x10000000) ++#define MCF_PSC_RFCR_WRITETAG (0x20000000) ++#define MCF_PSC_RFCR_SHADOW (0x80000000) ++ ++/* Bit definitions and macros for MCF_PSC_TFCR */ ++#define MCF_PSC_TFCR_CNTR(x) (((x)&0x0000FFFF)<<0) ++#define MCF_PSC_TFCR_TXW_MSK (0x00040000) ++#define MCF_PSC_TFCR_OF_MSK (0x00080000) ++#define MCF_PSC_TFCR_UF_MSK (0x00100000) ++#define MCF_PSC_TFCR_RXW_MSK (0x00200000) ++#define MCF_PSC_TFCR_FAE_MSK (0x00400000) ++#define MCF_PSC_TFCR_IP_MSK (0x00800000) ++#define MCF_PSC_TFCR_GR(x) (((x)&0x00000007)<<24) ++#define MCF_PSC_TFCR_FRMEN (0x08000000) ++#define MCF_PSC_TFCR_TIMER (0x10000000) ++#define MCF_PSC_TFCR_WRITETAG (0x20000000) ++#define MCF_PSC_TFCR_SHADOW (0x80000000) ++ ++/* Bit definitions and macros for MCF_PSC_RFAR */ ++#define MCF_PSC_RFAR_ALARM(x) (((x)&0x01FF)<<0) ++ ++/* Bit definitions and macros for MCF_PSC_TFAR */ ++#define MCF_PSC_TFAR_ALARM(x) (((x)&0x01FF)<<0) ++ ++/* Bit definitions and macros for MCF_PSC_RFRP */ ++#define MCF_PSC_RFRP_READ(x) (((x)&0x01FF)<<0) ++ ++/* Bit definitions and macros for MCF_PSC_TFRP */ ++#define MCF_PSC_TFRP_READ(x) (((x)&0x01FF)<<0) ++ ++/* Bit definitions and macros for MCF_PSC_RFWP */ ++#define MCF_PSC_RFWP_WRITE(x) (((x)&0x01FF)<<0) ++ ++/* Bit definitions and macros for MCF_PSC_TFWP */ ++#define MCF_PSC_TFWP_WRITE(x) (((x)&0x01FF)<<0) ++ ++/* Bit definitions and macros for MCF_PSC_RLRFP */ ++#define MCF_PSC_RLRFP_LFP(x) (((x)&0x01FF)<<0) ++ ++/* Bit definitions and macros for MCF_PSC_TLRFP */ ++#define MCF_PSC_TLRFP_LFP(x) (((x)&0x01FF)<<0) ++ ++/* Bit definitions and macros for MCF_PSC_RLWFP */ ++#define MCF_PSC_RLWFP_LFP(x) (((x)&0x01FF)<<0) ++ ++/* Bit definitions and macros for MCF_PSC_TLWFP */ ++#define MCF_PSC_TLWFP_LFP(x) (((x)&0x01FF)<<0) ++ ++/********************************************************************/ ++ ++#endif /* __MCF548X_PSC_H__ */ +--- /dev/null ++++ b/arch/m68k/include/asm/m5485sec.h +@@ -0,0 +1,177 @@ ++/* ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ */ ++ ++#ifndef M5485SEC_H ++#define M5484SEC_H ++ ++#define SEC_EUACR_U MCF_REG32(0x21000) ++#define SEC_EUACR_L MCF_REG32(0x21004) ++#define SEC_EUASR_U MCF_REG32(0x21028) ++#define SEC_EUASR_L MCF_REG32(0x2102C) ++#define SEC_SMCR MCF_REG32(0x21030) ++#define SEC_SISR_U MCF_REG32(0x21010) ++#define SEC_SISR_L MCF_REG32(0x21014) ++#define SEC_SICR_U MCF_REG32(0x21018) ++#define SEC_SICR_L MCF_REG32(0x2101C) ++#define SEC_SIMR_U MCF_REG32(0x21008) ++#define SEC_SIMR_L MCF_REG32(0x2100C) ++#define SEC_SID MCF_REG32(0x21020) ++ ++#define SEC_SMCR_RESET 0x01000000 ++#define SEC_SIMR_MASK_U 0x00000000 ++#define SEC_SIMR_MASK_L 0x03333340 ++ ++#define SEC_CC0_FR MCF_REG32(0x2204C) ++#define SEC_CC0_CR MCF_REG32(0x2200C) ++#define SEC_CC0_CDPR MCF_REG32(0x22044) ++#define SEC_CC0_PSR_U MCF_REG32(0x22010) ++#define SEC_CC0_PSR_L MCF_REG32(0x22014) ++#define SEC_CC1_FR MCF_REG32(0x2304C) ++#define SEC_CC1_CR MCF_REG32(0x2300C) ++#define SEC_CC1_CDPR MCF_REG32(0x23044) ++#define SEC_CC1_PSR_U MCF_REG32(0x23010) ++#define SEC_CC1_PSR_L MCF_REG32(0x23014) ++ ++#define SEC_CC_CR_RESET 0x00000001 ++#define SEC_CC_CR_CONFIGURATION 0x0000001E ++#define SEC_CC_PSR_U_ERR_CH0 0x20000000 ++#define SEC_CC_PSR_U_ERR_CH1 0x80000000 ++#define SEC_CC_PSR_U_DN_CH0 0x10000000 ++#define SEC_CC_PSR_U_DN_CH1 0x40000000 ++ ++#define SEC_DEU_DRCR MCF_REG32(0x2A018) ++#define SEC_DEU_DSR MCF_REG32(0x2A028) ++#define SEC_DEU_DISR MCF_REG32(0x2A030) ++#define SEC_DEU_DIMR MCF_REG32(0x2A038) ++ ++#define SEC_DEU_DRCR_RESET 0x01000000 ++#define SEC_DEU_DSR_RD 0x01000000 ++#define SEC_DEU_DIMR_MASK 0xF63F0000 ++ ++#define SEC_AFEU_AFRCR MCF_REG32(0x28018) ++#define SEC_AFEU_AFSR MCF_REG32(0x28028) ++#define SEC_AFEU_AFISR MCF_REG32(0x28030) ++#define SEC_AFEU_AFIMR MCF_REG32(0x28038) ++ ++#define SEC_AFEU_AFRCR_RESET 0x01000000 ++#define SEC_AFEU_AFSR_RD 0x01000000 ++#define SEC_AFEU_AFIMR_MASK 0xF61F0000 ++ ++ ++#define SEC_MDEU_MDRCR MCF_REG32(0x2C018) ++#define SEC_MDEU_MDSR MCF_REG32(0x2C028) ++#define SEC_MDEU_MDISR MCF_REG32(0x2C030) ++#define SEC_MDEU_MDIMR MCF_REG32(0x2C038) ++ ++#define SEC_MDEU_MDRCR_RESET 0x01000000 ++#define SEC_MDEU_MDSR_RD 0x01000000 ++#define SEC_MDEU_MDIMR_MASK 0xC41F0000 ++ ++ ++#define SEC_RNG_RNGRCR MCF_REG32(0x2E018) ++#define SEC_RNG_RNGSR MCF_REG32(0x2E028) ++#define SEC_RNG_RNGISR MCF_REG32(0x2E030) ++#define SEC_RNG_RNGIMR MCF_REG32(0x2E038) ++ ++#define SEC_RNG_RNGRCR_RESET 0x01000000 ++#define SEC_RNG_RNGSR_RD 0x01000000 ++#define SEC_RNG_RNGIMR_MASK 0xC2100000 ++ ++#define SEC_AESU_AESRCR MCF_REG32(0x32018) ++#define SEC_AESU_AESSR MCF_REG32(0x32028) ++#define SEC_AESU_AESISR MCF_REG32(0x32030) ++#define SEC_AESU_AESIMR MCF_REG32(0x32038) ++ ++#define SEC_AESU_AESRCR_RESET 0x01000000 ++#define SEC_AESU_AESSR_RD 0x01000000 ++#define SEC_AESU_AESIMR_MASK 0xF61F0000 ++ ++ ++#define SEC_DESC_NUM 20 ++#define SEC_CHANNEL_NUMBER 2 ++#define SEC_MAX_BUF_SIZE (32 * 1024) ++#define SEC_INIT_TIMEOUT (1 * HZ) ++#define SEC_INTERRUPT 37 ++ ++/* Header descriptor values*/ ++#define SEC_ALG_ENCR_DES_ECB_SINGLE 0x20100010 ++#define SEC_ALG_DECR_DES_ECB_SINGLE 0x20000010 ++#define SEC_ALG_ENCR_DES_ECB_TRIPLE 0x20300010 ++#define SEC_ALG_DECR_DES_ECB_TRIPLE 0x20200010 ++#define SEC_ALG_ENCR_DES_CBC_SINGLE 0x20500010 ++#define SEC_ALG_DECR_DES_CBC_SINGLE 0x20400010 ++#define SEC_ALG_ENCR_DES_CBC_TRIPLE 0x20700010 ++#define SEC_ALG_DECR_DES_CBC_TRIPLE 0x20600010 ++ ++#define SEC_ALG_MDEU_SHA256 0x30500010 ++#define SEC_ALG_MDEU_MD5 0x30600010 ++#define SEC_ALG_MDEU_SHA 0x30400010 ++#define SEC_ALG_MDEU_SHA256_HMAC 0x31D00010 ++#define SEC_ALG_MDEU_MD5_HMAC 0x31E00010 ++#define SEC_ALG_MDEU_SHA_HMAC 0x31C00010 ++ ++#define SEC_ALG_RNG 0x40000010 ++ ++ ++#define SEC_ALG_AFEU_KEY 0x10200050 ++#define SEC_ALG_AFEU_CONTEXT 0x10700050 ++ ++#define SEC_ALG_ENCR_AESU_CBC 0x60300010 ++#define SEC_ALG_DECR_AESU_CBC 0x60200010 ++#define SEC_ALG_ENCR_AESU_ECB 0x60100010 ++#define SEC_ALG_DECR_AESU_ECB 0x60000010 ++#define SEC_ALG_AESU_CTR 0x60600010 ++ ++ ++ ++#define SEC_DESCHEAD_ERROR 0xFE000000 ++#define SEC_DESCHEAD_COMPLETED 0xFF000000 ++ ++#define SEC_DEVICE_NAME "cfsec" ++ ++/*!!! This number must be changed*/ ++#define SEC_MAJOR 130 ++ ++#define SEC_DEV_BUF 1024 ++#define SEC_DEV_KEY_LEN 64 ++#define SEC_DEV_VECTOR_LEN 259 ++ ++#define SEC_AES_BLCK_LEN 16 ++#define SEC_DES_BLCK_LEN 8 ++ ++ ++/* Descriptor structure of SEC*/ ++struct sec_descriptor { ++ volatile unsigned long secdesc_header; ++ unsigned long secdesc_len1; ++ void *secdesc_ptr1; ++ unsigned long secdesc_iv_in_len; ++ void *secdesc_iv_in_ptr; ++ unsigned long secdesc_key_len; ++ void *secdesc_key_ptr; ++ unsigned long secdesc_data_in_len; ++ void *secdesc_data_in_ptr; ++ unsigned long secdesc_data_out_len; ++ void *secdesc_data_out_ptr; ++ unsigned long secdesc_iv_out_len; ++ void *secdesc_iv_out_ptr; ++ unsigned long secdesc_len7; ++ void *secdesc_ptr7; ++ void *secdesc_ptrnext; ++}; ++ ++struct sec_device_data { ++ unsigned char secdev_inbuf[SEC_DEV_BUF]; ++ unsigned char secdev_outbuf[SEC_DEV_BUF]; ++ unsigned char secdev_key[SEC_DEV_KEY_LEN]; ++ unsigned char secdev_iv[SEC_DEV_VECTOR_LEN]; ++ unsigned char secdev_ov[SEC_DEV_VECTOR_LEN]; ++ struct sec_descriptor *secdev_desc; ++}; ++ ++struct sec_descriptor *sec_desc_alloc(void); ++inline void sec_desc_free(struct sec_descriptor *desc); ++int sec_execute(int channel, struct sec_descriptor *desc, int timeout); ++int sec_nonblock_execute(struct sec_descriptor *desc); ++#endif +--- /dev/null ++++ b/arch/m68k/include/asm/m5485sim.h +@@ -0,0 +1,346 @@ ++/* ++ * m5485sim.h -- ColdFire 547x/548x System Integration Unit support. ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ */ ++#ifndef m5485sim_h ++#define m5485sim_h ++/* ++ * System Integration Unit Registers ++ */ ++#define MCF_SDRAMDS MCF_REG32(0x000004) ++/* SDRAM Drive Strength */ ++#define MCF_SBCR MCF_REG32(0x000010) ++/* System Breakpoint Control */ ++#define MCF_CSnCFG(x) MCF_REG32(0x000020+(x*4)) ++/* SDRAM Chip Select X */ ++#define MCF_SECSACR MCF_REG32(0x000038) ++/* Sequential Access Control */ ++#define MCF_RSR MCF_REG32(0x000044) ++/* Reset Status */ ++#define MCF_JTAGID MCF_REG32(0x000050) ++/* JTAG Device Identification */ ++#define MCF_XARB_PRIEN MCF_REG32(0x000264) ++/* Arbiter master pri enable */ ++#define MCF_XARB_PRI MCF_REG32(0x000268) ++/* Arbiter master pri levels */ ++#define MCF_SPCR MCF_REG32(0x000300) ++ ++/* ++ * FlexBus Chip Selects Registers ++ */ ++#define MCF_CSARn(x) MCF_REG32(0x000500+(x*0xC)) ++#define MCF_CSMRn(x) MCF_REG32(0x000504+(x*0xC)) ++#define MCF_CSCRn(x) MCF_REG32(0x000508+(x*0xC)) ++ ++/* ++ * Interrupt Controller Registers ++ */ ++#define MCF_IPRH MCF_REG32(0x000700) ++#define MCF_IPRL MCF_REG32(0x000704) ++#define MCF_IMRH MCF_REG32(0x000708) ++#define MCF_IMRL MCF_REG32(0x00070C) ++#define MCF_INTFRCH MCF_REG32(0x000710) ++#define MCF_INTFRCL MCF_REG32(0x000714) ++#define MCF_IRLR MCF_REG08(0x000718) ++#define MCF_IACKLPR MCF_REG08(0x000719) ++#define MCF_SWIACK MCF_REG08(0x0007E0) ++#define MCF_LnIACK(x) MCF_REG08(0x0007E4+((x)*0x004)) ++#define MCF_ICR(x) MCF_REG08(0x000740+((x)*0x001)) ++ ++/* ++ * Slice Timers Registers ++ */ ++#define MCF_SLTCNT(x) MCF_REG32(0x000900+((x)*0x010)) ++#define MCF_SCR(x) MCF_REG32(0x000904+((x)*0x010)) ++#define MCF_SCNT(x) MCF_REG32(0x000908+((x)*0x010)) ++#define MCF_SSR(x) MCF_REG32(0x00090C+((x)*0x010)) ++ ++/* ++ * Interrupt sources ++ */ ++#define ISC_EPORT_Fn(x) (x) ++/* EPORT Interrupts */ ++#define ISC_USB_EPn(x) (15+(x)) ++/* USB Endopint */ ++#define ISC_USB_ISR (22) ++/* USB General source */ ++#define ISC_USB_AISR (22) ++/* USB core source */ ++#define ISC_DSPI_OVRFW (25) ++/* DSPI overflow */ ++#define ISC_DSPI_RFOF (26) ++#define ISC_DSPI_RFDF (27) ++#define ISC_DSPI_TFUF (28) ++#define ISC_DSPI_TCF (29) ++#define ISC_DSPI_TFFF (30) ++#define ISC_DSPI_EOQF (31) ++#define ISC_PSCn(x) (35-(x)) ++#define ISC_COMM_TIM (36) ++#define ISC_SEC (37) ++#define ISC_FEC1 (38) ++#define ISC_FEC0 (39) ++#define ISC_I2C (40) ++#define ISC_PCI_ARB (41) ++#define ISC_PCI_CB (42) ++#define ISC_PCI_XLB (43) ++#define ISC_DMA (48) ++#define ISC_CANn_ERR(x) (49+(6*(x))) ++#define ISC_CANn_BUSOFF(x) (50+(6*(x))) ++#define ISC_CANn_MBOR(x) (51+(6*(x))) ++#define ISC_CAN0_WAKEIN (52) ++#define ISC_SLTn(x) (54-(x)) ++#define ISC_GPTn(x) (62-(x)) ++ ++/* ++ * Interrupt level and priorities ++ */ ++#define ILP_TOP (MCF_ICR_IL(5) | MCF_ICR_IP(3)) ++#define ILP_SLT0 (MCF_ICR_IL(5) | MCF_ICR_IP(2)) ++#define ILP_SLT1 (MCF_ICR_IL(5) | MCF_ICR_IP(1)) ++#define ILP_DMA (MCF_ICR_IL(5) | MCF_ICR_IP(0)) ++#define ILP_SEC (MCF_ICR_IL(4) | MCF_ICR_IP(7)) ++#define ILP_FEC0 (MCF_ICR_IL(4) | MCF_ICR_IP(6)) ++#define ILP_FEC1 (MCF_ICR_IL(4) | MCF_ICR_IP(5)) ++#define ILP_PCI_XLB (MCF_ICR_IL(4) | MCF_ICR_IP(4)) ++#define ILP_PCI_ARB (MCF_ICR_IL(4) | MCF_ICR_IP(3)) ++#define ILP_PCI_CB (MCF_ICR_IL(4) | MCF_ICR_IP(2)) ++#define ILP_I2C (MCF_ICR_IL(4) | MCF_ICR_IP(1)) ++ ++#define ILP_USB_EPn(x) (MCF_ICR_IL(3) | MCF_ICR_IP(7-(x))) ++#define ILP_USB_EP0 (MCF_ICR_IL(3) | MCF_ICR_IP(7)) ++#define ILP_USB_EP1 (MCF_ICR_IL(3) | MCF_ICR_IP(6)) ++#define ILP_USB_EP2 (MCF_ICR_IL(3) | MCF_ICR_IP(5)) ++#define ILP_USB_EP3 (MCF_ICR_IL(3) | MCF_ICR_IP(4)) ++#define ILP_USB_EP4 (MCF_ICR_IL(3) | MCF_ICR_IP(3)) ++#define ILP_USB_EP5 (MCF_ICR_IL(3) | MCF_ICR_IP(2)) ++#define ILP_USB_EP6 (MCF_ICR_IL(3) | MCF_ICR_IP(1)) ++#define ILP_USB_ISR (MCF_ICR_IL(3) | MCF_ICR_IP(0)) ++ ++#define ILP_USB_AISR (MCF_ICR_IL(2) | MCF_ICR_IP(7)) ++#define ILP_DSPI_OVRFW (MCF_ICR_IL(2) | MCF_ICR_IP(6)) ++#define ILP_DSPI_RFOF (MCF_ICR_IL(2) | MCF_ICR_IP(5)) ++#define ILP_DSPI_RFDF (MCF_ICR_IL(2) | MCF_ICR_IP(4)) ++#define ILP_DSPI_TFUF (MCF_ICR_IL(2) | MCF_ICR_IP(3)) ++#define ILP_DSPI_TCF (MCF_ICR_IL(2) | MCF_ICR_IP(2)) ++#define ILP_DSPI_TFFF (MCF_ICR_IL(2) | MCF_ICR_IP(1)) ++#define ILP_DSPI_EOQF (MCF_ICR_IL(2) | MCF_ICR_IP(0)) ++ ++#define ILP_COMM_TIM (MCF_ICR_IL(1) | MCF_ICR_IP(7)) ++#define ILP_PSCn(x) (MCF_ICR_IL(1) | MCF_ICR_IP(3-((x)&3))) ++#define ILP_PSC0 (MCF_ICR_IL(1) | MCF_ICR_IP(3)) ++#define ILP_PSC1 (MCF_ICR_IL(1) | MCF_ICR_IP(2)) ++#define ILP_PSC2 (MCF_ICR_IL(1) | MCF_ICR_IP(1)) ++#define ILP_PSC3 (MCF_ICR_IL(1) | MCF_ICR_IP(0)) ++ ++ ++ ++ ++ ++/********************************************************************/ ++ ++/* ++ * System Integration Unit Bitfields ++ */ ++ ++/* SBCR */ ++#define MCF_SBCR_PIN2DSPI (0x08000000) ++#define MCF_SBCR_DMA2CPU (0x10000000) ++#define MCF_SBCR_CPU2DMA (0x20000000) ++#define MCF_SBCR_PIN2DMA (0x40000000) ++#define MCF_SBCR_PIN2CPU (0x80000000) ++ ++/* SECSACR */ ++#define MCF_SECSACR_SEQEN (0x00000001) ++ ++/* RSR */ ++#define MCF_RSR_RST (0x00000001) ++#define MCF_RSR_RSTWD (0x00000002) ++#define MCF_RSR_RSTJTG (0x00000008) ++ ++/* JTAGID */ ++#define MCF_JTAGID_REV (0xF0000000) ++#define MCF_JTAGID_PROCESSOR (0x0FFFFFFF) ++#define MCF_JTAGID_MCF5485 (0x0800C01D) ++#define MCF_JTAGID_MCF5484 (0x0800D01D) ++#define MCF_JTAGID_MCF5483 (0x0800E01D) ++#define MCF_JTAGID_MCF5482 (0x0800F01D) ++#define MCF_JTAGID_MCF5481 (0x0801001D) ++#define MCF_JTAGID_MCF5480 (0x0801101D) ++#define MCF_JTAGID_MCF5475 (0x0801201D) ++#define MCF_JTAGID_MCF5474 (0x0801301D) ++#define MCF_JTAGID_MCF5473 (0x0801401D) ++#define MCF_JTAGID_MCF5472 (0x0801501D) ++#define MCF_JTAGID_MCF5471 (0x0801601D) ++#define MCF_JTAGID_MCF5470 (0x0801701D) ++ ++ ++/* ++ * Interrupt Controller Bitfields ++ */ ++#define MCF_IRLR_IRQ(x) (((x)&0x7F)<<1) ++#define MCF_IACKLPR_PRI(x) (((x)&0x0F)<<0) ++#define MCF_IACKLPR_LEVEL(x) (((x)&0x07)<<4) ++#define MCF_ICR_IP(x) (((x)&0x07)<<0) ++#define MCF_ICR_IL(x) (((x)&0x07)<<3) ++ ++/* ++ * Slice Timers Bitfields ++ */ ++#define MCF_SCR_TEN (0x01000000) ++#define MCF_SCR_IEN (0x02000000) ++#define MCF_SCR_RUN (0x04000000) ++#define MCF_SSR_ST (0x01000000) ++#define MCF_SSR_BE (0x02000000) ++ ++ ++/* ++ * Some needed coldfire registers ++ */ ++#define MCF_PAR_PCIBG MCF_REG16(0x000A48) ++#define MCF_PAR_PCIBR MCF_REG16(0x000A4A) ++#define MCF_PAR_PSCn(x) MCF_REG08(0x000A4F-((x)&0x3)) ++#define MCF_PAR_FECI2CIRQ MCF_REG16(0x000A44) ++#define MCF_PAR_DSPI MCF_REG16(0x000A50) ++#define MCF_PAR_TIMER MCF_REG08(0X000A52) ++#define MCF_EPPAR MCF_REG16(0x000F00) ++#define MCF_EPDDR MCF_REG08(0x000F04) ++#define MCF_EPIER MCF_REG08(0x000F05) ++#define MCF_EPFR MCF_REG08(0x000F0C) ++ ++/* ++ * Some GPIO bitfields ++ */ ++#define MCF_PAR_SDA (0x0008) ++#define MCF_PAR_SCL (0x0004) ++#define MCF_PAR_PSC_TXD (0x04) ++#define MCF_PAR_PSC_RXD (0x08) ++#define MCF_PAR_PSC_RTS(x) (((x)&0x03)<<4) ++#define MCF_PAR_PSC_CTS(x) (((x)&0x03)<<6) ++#define MCF_PAR_PSC_CTS_GPIO (0x00) ++#define MCF_PAR_PSC_CTS_BCLK (0x80) ++#define MCF_PAR_PSC_CTS_CTS (0xC0) ++#define MCF_PAR_PSC_RTS_GPIO (0x00) ++#define MCF_PAR_PSC_RTS_FSYNC (0x20) ++#define MCF_PAR_PSC_RTS_RTS (0x30) ++#define MCF_PAR_PSC_CANRX (0x40) ++ ++/* ++ * FlexCAN Module Configuration Register ++ */ ++#define CANMCR_MDIS (0x80000000) ++#define CANMCR_FRZ (0x40000000) ++#define CANMCR_HALT (0x10000000) ++#define CANMCR_SOFTRST (0x02000000) ++#define CANMCR_NOTRDY (0x08000000) ++#define CANMCR_FRZACK (0x01000000) ++#define CANMCR_SUPV (0x00800000) ++#define CANMCR_MAXMB (0x0F) ++/* ++ * FlexCAN Control Register ++ */ ++#define CANCTRL_PRESDIV(x) (((x)&0xFF)<<24) ++#define CANCTRL_RJW(x) (((x)&0x03)<<22) ++#define CANCTRL_PSEG1(x) (((x)&0x07)<<19) ++#define CANCTRL_PSEG2(x) (((x)&0x07)<<16) ++#define CANCTRL_BOFFMSK (0x00008000) ++#define CANCTRL_ERRMSK (0x00004000) ++#define CANCTRL_CLKSRC (0x00002000) ++#define CANCTRL_LPB (0x00001000) ++#define CANCTRL_SAMP(x) (((x)&0x01)<<7) ++#define CANCTRL_BOFFREC (0x00000040) ++#define CANCTRL_TSYNC (0x00000020) ++#define CANCTRL_LBUF (0x00000010) ++#define CANCTRL_LOM (0x00000008) ++#define CANCTRL_PROPSEG(x) ((x)&0x07) ++ ++/* ++ * FlexCAN Error Counter Register ++ */ ++#define ERRCNT_RXECTR(x) (((x)&0xFF)<<8) ++#define ERRCNT_TXECTR(x) ((x)&0xFF) ++ ++/* ++ * FlexCAN Error and Status Register ++ */ ++#define ERRSTAT_BITERR(x) (((x)&0x03)<<14) ++#define ERRSTAT_ACKERR (0x00002000) ++#define ERRSTAT_CRCERR (0x00001000) ++#define ERRSTAT_FRMERR (0x00000800) ++#define ERRSTAT_STFERR (0x00000400) ++#define ERRSTAT_TXWRN (0x00000200) ++#define ERRSTAT_RXWRN (0x00000100) ++#define ERRSTAT_IDLE (0x00000080) ++#define ERRSTAT_TXRX (0x00000040) ++#define ERRSTAT_FLTCONF(x) (((x)&0x03)<<4) ++#define ERRSTAT_BOFFINT (0x00000004) ++#define ERRSTAT_ERRINT (0x00000002) ++ ++/* ++ * Interrupt Mask Register ++ */ ++#define IMASK_BUF15M (0x8000) ++#define IMASK_BUF14M (0x4000) ++#define IMASK_BUF13M (0x2000) ++#define IMASK_BUF12M (0x1000) ++#define IMASK_BUF11M (0x0800) ++#define IMASK_BUF10M (0x0400) ++#define IMASK_BUF9M (0x0200) ++#define IMASK_BUF8M (0x0100) ++#define IMASK_BUF7M (0x0080) ++#define IMASK_BUF6M (0x0040) ++#define IMASK_BUF5M (0x0020) ++#define IMASK_BUF4M (0x0010) ++#define IMASK_BUF3M (0x0008) ++#define IMASK_BUF2M (0x0004) ++#define IMASK_BUF1M (0x0002) ++#define IMASK_BUF0M (0x0001) ++#define IMASK_BUFnM(x) (0x1<<(x)) ++#define IMASK_BUFF_ENABLE_ALL (0xFFFF) ++#define IMASK_BUFF_DISABLE_ALL (0x0000) ++ ++/* ++ * Interrupt Flag Register ++ */ ++#define IFLAG_BUF15M (0x8000) ++#define IFLAG_BUF14M (0x4000) ++#define IFLAG_BUF13M (0x2000) ++#define IFLAG_BUF12M (0x1000) ++#define IFLAG_BUF11M (0x0800) ++#define IFLAG_BUF10M (0x0400) ++#define IFLAG_BUF9M (0x0200) ++#define IFLAG_BUF8M (0x0100) ++#define IFLAG_BUF7M (0x0080) ++#define IFLAG_BUF6M (0x0040) ++#define IFLAG_BUF5M (0x0020) ++#define IFLAG_BUF4M (0x0010) ++#define IFLAG_BUF3M (0x0008) ++#define IFLAG_BUF2M (0x0004) ++#define IFLAG_BUF1M (0x0002) ++#define IFLAG_BUF0M (0x0001) ++#define IFLAG_BUFF_SET_ALL (0xFFFF) ++#define IFLAG_BUFF_CLEAR_ALL (0x0000) ++#define IFLAG_BUFnM(x) (0x1<<(x)) ++ ++/* ++ * Message Buffers ++ */ ++#define MB_CNT_CODE(x) (((x)&0x0F)<<24) ++#define MB_CNT_SRR (0x00400000) ++#define MB_CNT_IDE (0x00200000) ++#define MB_CNT_RTR (0x00100000) ++#define MB_CNT_TIMESTAMP(x) ((x)&0xFFFF) ++#define MB_ID_STD (0x07FF) ++#define MB_ID_EXT (0x1FFFFFFF) ++#define MB_CODE_MASK (0xF0FFFFFF) ++#define CAN_MB 16 ++#define PDEV_MAX 2 ++ ++/* ++ * Some used coldfire values ++ */ ++#define MCF_EPIER_EPIE(x) (0x01 << (x)) ++#define MCF_EPPAR_EPPAx_FALLING (2) ++#define MCF_EPPAR_EPPA(n, x) (((x)&0x0003) << (2*n)) ++ ++ ++#endif /* m5485sim_h */ +--- /dev/null ++++ b/arch/m68k/include/asm/m5485sram.h +@@ -0,0 +1,12 @@ ++#ifndef SYS_SRAM_H ++#define SYS_SRAM_H ++ ++ ++#define SYS_SRAM_DMA_START (MCF_MBAR + 0x10000) ++#define SYS_SRAM_DMA_SIZE 8192 ++#define SYS_SRAM_FEC_START (SYS_SRAM_DMA_START + SYS_SRAM_DMA_SIZE) ++#define SYS_SRAM_FEC_SIZE 2048 ++#define SYS_SRAM_SEC_START (SYS_SRAM_FEC_START + SYS_SRAM_FEC_SIZE) ++#define SYS_SRAM_SEC_SIZE 1280 ++ ++#endif /* SYS_SRAM_H */ |