diff options
Diffstat (limited to 'target/linux/coldfire/patches/002-MCF54451-and-MCF54455-support-in-Linux-2.6.38.patch')
| -rw-r--r-- | target/linux/coldfire/patches/002-MCF54451-and-MCF54455-support-in-Linux-2.6.38.patch | 10546 |
1 files changed, 10546 insertions, 0 deletions
diff --git a/target/linux/coldfire/patches/002-MCF54451-and-MCF54455-support-in-Linux-2.6.38.patch b/target/linux/coldfire/patches/002-MCF54451-and-MCF54455-support-in-Linux-2.6.38.patch new file mode 100644 index 000000000..82fc1eda7 --- /dev/null +++ b/target/linux/coldfire/patches/002-MCF54451-and-MCF54455-support-in-Linux-2.6.38.patch @@ -0,0 +1,10546 @@ +From f46a96f02d74535e928710eaebffe6c8b201b76a Mon Sep 17 00:00:00 2001 +From: Alison Wang <b18965@freescale.com> +Date: Thu, 4 Aug 2011 09:59:37 +0800 +Subject: [PATCH 02/52] MCF54451 and MCF54455 support in Linux 2.6.38 + +Add MCF54451 and MCF54455 support in Linux 2.6.38. + +Signed-off-by: Alison Wang <b18965@freescale.com> +--- + arch/m68k/coldfire/m5445x/Makefile | 20 + + arch/m68k/coldfire/m5445x/config.c | 599 ++++++++++ + arch/m68k/coldfire/m5445x/devices.c | 527 +++++++++ + arch/m68k/configs/m54451evb_defconfig | 1412 +++++++++++++++++++++++ + arch/m68k/configs/m54455evb_defconfig | 1597 +++++++++++++++++++++++++++ + arch/m68k/include/asm/cf_5445x_cacheflush.h | 534 +++++++++ + arch/m68k/include/asm/mcf5445x_ccm.h | 206 ++++ + arch/m68k/include/asm/mcf5445x_dspi.h | 665 +++++++++++ + arch/m68k/include/asm/mcf5445x_dtim.h | 96 ++ + arch/m68k/include/asm/mcf5445x_edma.h | 1472 ++++++++++++++++++++++++ + arch/m68k/include/asm/mcf5445x_eport.h | 117 ++ + arch/m68k/include/asm/mcf5445x_fbcs.h | 200 ++++ + arch/m68k/include/asm/mcf5445x_gpio.h | 1411 +++++++++++++++++++++++ + arch/m68k/include/asm/mcf5445x_intc.h | 724 ++++++++++++ + arch/m68k/include/asm/mcf5445x_pci.h | 238 ++++ + arch/m68k/include/asm/mcf5445x_pciarb.h | 40 + + arch/m68k/include/asm/mcf5445x_rtc.h | 114 ++ + arch/m68k/include/asm/mcf5445x_scm.h | 48 + + arch/m68k/include/asm/mcf5445x_sdramc.h | 142 +++ + arch/m68k/include/asm/mcf5445x_ssi.h | 187 ++++ + arch/m68k/include/asm/mcf5445x_xbs.h | 81 ++ + 21 files changed, 10430 insertions(+), 0 deletions(-) + create mode 100644 arch/m68k/coldfire/m5445x/Makefile + create mode 100644 arch/m68k/coldfire/m5445x/config.c + create mode 100644 arch/m68k/coldfire/m5445x/devices.c + create mode 100644 arch/m68k/configs/m54451evb_defconfig + create mode 100644 arch/m68k/configs/m54455evb_defconfig + create mode 100644 arch/m68k/include/asm/cf_5445x_cacheflush.h + create mode 100644 arch/m68k/include/asm/mcf5445x_ccm.h + create mode 100644 arch/m68k/include/asm/mcf5445x_dspi.h + create mode 100644 arch/m68k/include/asm/mcf5445x_dtim.h + create mode 100644 arch/m68k/include/asm/mcf5445x_edma.h + create mode 100644 arch/m68k/include/asm/mcf5445x_eport.h + create mode 100644 arch/m68k/include/asm/mcf5445x_fbcs.h + create mode 100644 arch/m68k/include/asm/mcf5445x_gpio.h + create mode 100644 arch/m68k/include/asm/mcf5445x_intc.h + create mode 100644 arch/m68k/include/asm/mcf5445x_pci.h + create mode 100644 arch/m68k/include/asm/mcf5445x_pciarb.h + create mode 100644 arch/m68k/include/asm/mcf5445x_rtc.h + create mode 100644 arch/m68k/include/asm/mcf5445x_scm.h + create mode 100644 arch/m68k/include/asm/mcf5445x_sdramc.h + create mode 100644 arch/m68k/include/asm/mcf5445x_ssi.h + create mode 100644 arch/m68k/include/asm/mcf5445x_xbs.h + +--- /dev/null ++++ b/arch/m68k/coldfire/m5445x/Makefile +@@ -0,0 +1,20 @@ ++# ++# Makefile for Linux arch/m68k/coldfire/m5445x source directory ++# ++ ++obj-$(CONFIG_M5445X) += devices.o config.o ++ ++ifneq ($(strip $(CONFIG_USB) $(CONFIG_USB_GADGET_FSL_USB2)),) ++ obj-y += usb.o ++endif ++ifneq ($(strip $(CONFIG_USB_GADGET_FSL_USB2) $(CONFIG_USB_EHCI_HCD)),) ++ obj-y += usb_dr.o ++endif ++ifneq ($(strip $(CONFIG_USB) $(CONFIG_USB_GADGET_FSL_USB2)),) ++ obj-y += xcvr.o ++endif ++ ++obj-$(CONFIG_PCI) += pci.o mcf5445x-pci.o ++ifneq ($(CONFIG_FEC),) ++obj-y += fec.o ++endif +--- /dev/null ++++ b/arch/m68k/coldfire/m5445x/config.c +@@ -0,0 +1,599 @@ ++/* ++ * linux/arch/m68k/coldfire/config_m5445x.c ++ * ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Author: ++ * Kurt Mahan kmahan@freescale.com ++ * Matt Waddel Matt.Waddel@freescale.com ++ * Jason Jin Jason.Jin@freescale.com ++ * Shrek Wu B16972@freescale.com ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++ ++#include <linux/module.h> ++#include <linux/init.h> ++#include <linux/string.h> ++#include <linux/kernel.h> ++#include <linux/console.h> ++#include <linux/bootmem.h> ++#include <linux/mm.h> ++#include <linux/sched.h> ++#include <linux/clockchips.h> ++#include <linux/delay.h> ++#include <asm/bootinfo.h> ++#include <asm/machdep.h> ++#include <asm/coldfire.h> ++#include <asm/cfcache.h> ++#include <asm/cacheflush.h> ++#include <asm/io.h> ++#include <asm/cfmmu.h> ++#include <asm/setup.h> ++#include <asm/irq.h> ++#include <asm/traps.h> ++#include <asm/movs.h> ++#include <asm/movs.h> ++#include <asm/page.h> ++#include <asm/pgalloc.h> ++#include <asm/cf-sram.h> ++ ++#include <asm/mcfsim.h> ++ ++#define UBOOT_EXTRA_CLOCKS ++#include <asm/bootinfo.h> ++ ++#include <asm/mcf5445x_intc.h> ++#include <asm/mcf5445x_sdramc.h> ++#include <asm/mcf5445x_fbcs.h> ++#include <asm/mcf5445x_dtim.h> ++#include <asm/mcf5445x_xbs.h> ++ ++extern int get_irq_list(struct seq_file *p, void *v); ++extern char _text, _end; ++extern char _etext, _edata, __init_begin, __init_end; ++extern struct console mcfrs_console; ++extern char m68k_command_line[CL_SIZE]; ++extern unsigned long availmem; ++extern unsigned long shadow_cacr; ++EXPORT_SYMBOL(shadow_cacr); ++extern struct mem_info m68k_ramdisk; ++ ++static int irq_enable[NR_IRQS]; ++unsigned long num_pages; ++ ++/* cf dma physical addresses */ ++unsigned long cf_dma_base; ++EXPORT_SYMBOL(cf_dma_base); ++unsigned long cf_dma_end; ++EXPORT_SYMBOL(cf_dma_end); ++unsigned long cf_dma_size; ++EXPORT_SYMBOL(cf_dma_size); ++ ++/* ethernet mac addresses from uboot */ ++unsigned char uboot_enet0[6]; ++unsigned char uboot_enet1[6]; ++ ++void coldfire_sort_memrec(void) ++{ ++ int i, j; ++ ++ /* Sort the m68k_memory records by address */ ++ for (i = 0; i < m68k_num_memory; ++i) { ++ for (j = i + 1; j < m68k_num_memory; ++j) { ++ if (m68k_memory[i].addr > m68k_memory[j].addr) { ++ struct mem_info tmp; ++ tmp = m68k_memory[i]; ++ m68k_memory[i] = m68k_memory[j]; ++ m68k_memory[j] = tmp; ++ } ++ } ++ } ++ /* Trim off discontiguous bits */ ++ for (i = 1; i < m68k_num_memory; ++i) { ++ if ((m68k_memory[i-1].addr + m68k_memory[i-1].size) != ++ m68k_memory[i].addr) { ++ printk(KERN_DEBUG "m68k_parse_bootinfo: " ++ "addr gap between 0x%lx & 0x%lx\n", ++ m68k_memory[i-1].addr+m68k_memory[i-1].size, ++ m68k_memory[i].addr); ++ m68k_num_memory = i; ++ break; ++ } ++ } ++} ++ ++/* ++ * UBoot Handler ++ */ ++int __init uboot_commandline(char *bootargs) ++{ ++ int len = 0, cmd_line_len; ++ static struct uboot_record uboot_info; ++ u32 offset = PAGE_OFFSET_RAW - PHYS_OFFSET; ++ ++ extern unsigned long uboot_info_stk; ++ ++ /* validate address */ ++ if ((uboot_info_stk < PAGE_OFFSET_RAW) || ++ (uboot_info_stk >= (PAGE_OFFSET_RAW + CONFIG_SDRAM_SIZE))) ++ return 0; ++ ++ /* Add offset to get post-remapped kernel memory location */ ++ uboot_info.bdi = (struct bd_info *) ++ ((*(u32 *)(uboot_info_stk)) + offset); ++ uboot_info.initrd_start = (*(u32 *)(uboot_info_stk+4)) + offset; ++ uboot_info.initrd_end = (*(u32 *)(uboot_info_stk+8)) + offset; ++ uboot_info.cmd_line_start = (*(u32 *)(uboot_info_stk+12)) + offset; ++ uboot_info.cmd_line_stop = (*(u32 *)(uboot_info_stk+16)) + offset; ++ ++#if defined(CONFIG_BLK_DEV_INITRD) ++ m68k_ramdisk.addr = uboot_info.initrd_start; ++ m68k_ramdisk.size = (uboot_info.initrd_end - uboot_info.initrd_start) ? ++ (uboot_info.initrd_end - uboot_info.initrd_start + 1) : 0; ++#endif ++ ++ /* copy over mac addresses */ ++ memcpy(uboot_enet0, uboot_info.bdi->bi_enet0addr, 6); ++ memcpy(uboot_enet1, uboot_info.bdi->bi_enet1addr, 6); ++ ++ /* copy command line */ ++ cmd_line_len = uboot_info.cmd_line_stop - uboot_info.cmd_line_start; ++ if ((cmd_line_len > 0) && (cmd_line_len < CL_SIZE-1)) ++ len = (int)strncpy(bootargs, (char *)uboot_info.cmd_line_start,\ ++ cmd_line_len); ++ ++ return len; ++} ++ ++#if defined(CONFIG_M54451) ++#define DEFAULT_COMMAND_LINE \ ++ "debug root=/dev/nfs rw \ ++ nfsroot=172.27.155.1:/tftpboot/redstripe/rootfs/ \ ++ ip=172.27.155.51:172.27.155.1" ++#elif defined(CONFIG_M54455) ++#define MTD_DEFAULT_COMMAND_LINE \ ++ "root=/dev/mtdblock1 rw rootfstype=jffs2 \ ++ ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)" ++#define DEFAULT_COMMAND_LINE \ ++ "debug root=/dev/nfs rw \ ++ nfsroot=172.27.155.1:/tftpboot/redstripe/rootfs/ \ ++ ip=172.27.155.55:172.27.155.1" ++#endif ++ ++ ++/* ++ * Early Coldfire Initialization. ++ */ ++asmlinkage void __init cf_early_init(void) ++{ ++ SET_VBR((void *)MCF_RAMBAR1); ++ ++ /* Mask all interrupts */ ++ MCF_INTC0_IMRL = 0xFFFFFFFF; ++ MCF_INTC0_IMRH = 0xFFFFFFFF; ++ MCF_INTC1_IMRL = 0xFFFFFFFF; ++ MCF_INTC1_IMRH = 0xFFFFFFFF; ++ ++#if defined(CONFIG_NOR_FLASH_BASE) ++ MCF_FBCS_CSAR(1) = CONFIG_NOR_FLASH_BASE; ++#else ++ MCF_FBCS_CSAR(1) = 0x00000000; ++#endif ++ ++#if CONFIG_SDRAM_SIZE > (256*1024*1024) ++ /* Init optional SDRAM chip select */ ++ MCF_SDRAMC_SDCS(1) = (256*1024*1024) | 0x1B; ++#endif ++ ++ MCF_XBS_CRS2 = 0x100; ++ /* Setup SDRAM crossbar(XBS) priorities */ ++ MCF_XBS_PRS2 = (MCF_XBS_PRS_M0(MCF_XBS_PRI_2) | /*CPU*/ ++ MCF_XBS_PRS_M1(MCF_XBS_PRI_3) | /*eDMA*/ ++ MCF_XBS_PRS_M2(MCF_XBS_PRI_1) | /*FEC0*/ ++ MCF_XBS_PRS_M3(MCF_XBS_PRI_5) | /*FEC1*/ ++ MCF_XBS_PRS_M5(MCF_XBS_PRI_6) | /*PCI*/ ++ MCF_XBS_PRS_M6(MCF_XBS_PRI_4) | /*USB*/ ++ MCF_XBS_PRS_M7(MCF_XBS_PRI_7)); /*SBF*/ ++ ++ m68k_machtype = MACH_CFMMU; ++ m68k_fputype = FPU_CFV4E; ++ m68k_mmutype = MMU_CFV4E; ++ m68k_cputype = CPU_CFV4E; ++ ++ /* initialize PHYSRAM */ ++ m68k_num_memory = 0; ++ m68k_memory[m68k_num_memory].addr = CONFIG_SDRAM_BASE; /* phys */ ++ m68k_memory[m68k_num_memory++].size = CONFIG_SDRAM_SIZE; ++ ++ if (!uboot_commandline(m68k_command_line)) { ++#if defined(CONFIG_BOOTPARAM) ++ strncpy(m68k_command_line, CONFIG_BOOTPARAM_STRING, CL_SIZE-1); ++#else ++ strcpy(m68k_command_line, DEFAULT_COMMAND_LINE); ++#endif ++ } ++ ++ /* Invalidate caches via CACR */ ++ flush_bcache(); ++ cacr_set(CACHE_DISABLE_MODE); ++ ++ /* Turn on caches via CACR, enable EUSP */ ++ cacr_set(CACHE_INITIAL_MODE); ++} ++ ++/* Assembler routines */ ++asmlinkage void buserr(void); ++asmlinkage void trap(void); ++asmlinkage void system_call(void); ++asmlinkage void inthandler(void); ++ ++void __init coldfire_trap_init(void) ++{ ++ int i = 0; ++ e_vector *vectors; ++ ++ vectors = (e_vector *)MCF_RAMBAR1; ++ /* ++ * There is a common trap handler and common interrupt ++ * handler that handle almost every vector. We treat ++ * the system call and bus error special, they get their ++ * own first level handlers. ++ */ ++ for (i = 3; (i <= 23); i++) ++ vectors[i] = trap; ++ for (i = 33; (i <= 63); i++) ++ vectors[i] = trap; ++ for (i = 24; (i <= 31); i++) ++ vectors[i] = inthandler; ++ for (i = 64; (i < 255); i++) ++ vectors[i] = inthandler; ++ ++ vectors[255] = 0; ++ vectors[2] = buserr; ++ vectors[32] = system_call; ++} ++ ++void settimericr(unsigned int timer, unsigned int level) ++{ ++ volatile unsigned char *icrp; ++ unsigned int icr = 0; ++ unsigned char irq = 0; ++ ++ if (timer <= 3) { ++ switch (timer) { ++ case 0: ++ irq = 32; ++ icr = MCFSIM_ICR_TIMER0; ++ break; ++ case 1: ++ irq = 33; ++ icr = MCFSIM_ICR_TIMER1; ++ break; ++ case 2: ++ irq = 34; ++ icr = MCFSIM_ICR_TIMER2; ++ break; ++ case 3: ++ irq = 35; ++ icr = MCFSIM_ICR_TIMER3; ++ break; ++ } ++ ++ icrp = (volatile unsigned char *) (icr); ++ *icrp = level; ++ coldfire_enable_irq0(irq); ++ } ++} ++ ++void coldfire_sched_clk_init(void); ++ ++void coldfire_tick(void) ++{ ++ /* Reset the ColdFire timer */ ++ __raw_writeb(MCF_DTIM_DTER_CAP | MCF_DTIM_DTER_REF, MCF_DTIM0_DTER); ++} ++ ++void __init coldfire_sched_init(irq_handler_t handler) ++{ ++ unsigned int mcf_timerlevel = 5; ++ unsigned int mcf_timervector = 64+32; ++ ++ __raw_writew(MCF_DTIM_DTMR_RST_RST, MCF_DTIM0_DTMR); ++ __raw_writel(((MCF_BUSCLK / 16) / HZ), MCF_DTIM0_DTRR); ++ __raw_writew(MCF_DTIM_DTMR_ORRI | MCF_DTIM_DTMR_CLK_DIV16 | ++ MCF_DTIM_DTMR_FRR | MCF_DTIM_DTMR_RST_EN, \ ++ MCF_DTIM0_DTMR); ++ ++ request_irq(mcf_timervector, handler, IRQF_DISABLED, \ ++ "timer", (void *)MCF_DTIM0_DTMR); ++ ++ settimericr(0, mcf_timerlevel); ++ ++ /* initialize the fast clock */ ++ coldfire_sched_clk_init(); ++} ++ ++int timerirqpending(int timer) ++{ ++ unsigned int imr = 0; ++ unsigned ret = 0; ++ ++ switch (timer) { ++ case 1: ++ imr = 0x1; ++ break; ++ case 2: ++ imr = 0x2; ++ break; ++ default: ++ break; ++ } ++ ++ ret = getiprh() & imr; ++ return ret; ++} ++ ++unsigned long coldfire_gettimeoffset(void) ++{ ++ volatile unsigned long trr, tcn, offset; ++ ++ tcn = __raw_readw(MCF_DTIM0_DTCN); ++ trr = __raw_readl(MCF_DTIM0_DTRR); ++ offset = (tcn * (1000000 / HZ)) / trr; ++ ++ /* Check if we just wrapped the counters and maybe missed a tick */ ++ if ((offset < (1000000 / HZ / 2)) && timerirqpending(1)) ++ offset += 1000000 / HZ; ++ return offset; ++} ++ ++/* sched_clock support */ ++ ++static unsigned long long sched_clk_val; ++ ++static irqreturn_t coldfire_sched_clk_irq(int irq, void *dev) ++{ ++ __raw_writeb(MCF_DTIM_DTER_CAP | MCF_DTIM_DTER_REF, MCF_DTIM3_DTER); ++ sched_clk_val += 0x100000000LL; ++ ++ return IRQ_HANDLED; ++} ++ ++/* ++ * Setup DTIM3 as the 5445x sched_clock() implementation. The ++ * input frequency to the clock is the internal bus clock (MCF_BUSCLK) ++ * which is the system clock (MCF_CLK) / 2. ++ * ++ * On a system running at 266Mhz: ++ * MCF_CLK = 266Mhz (266000000) ++ * MCF_BUSCLK = 133Mhz (133000000) ++ * DTIM3 Tick = 133Mhz (133000000) ++ * Tick Resolution = 7.5ns (round to 8ns/Tick) ++ * ++ * On a system running at 240Mhz: ++ * MCF_CLK = 240Mhz (240000000) ++ * MCF_BUSCLK = 120Mhz (120000000) ++ * DTIM3 Tick = 120Mhz (120000000) ++ * Tick Resolution = 8.4ns (round to 8ns/Tick) ++ */ ++void __init coldfire_sched_clk_init(void) ++{ ++ unsigned int mcf_timerlevel = 5; ++ unsigned int mcf_timervector = 64+32+3; /* DTIM3 */ ++ ++ printk(KERN_INFO "Initializing DTIM3 for sched_clock\n"); ++ __raw_writew(MCF_DTIM_DTMR_RST_RST, MCF_DTIM3_DTMR); ++ __raw_writel(0xffffffff, MCF_DTIM3_DTRR); ++ __raw_writew(MCF_DTIM_DTMR_ORRI | MCF_DTIM_DTMR_CLK_DIV1 | \ ++ MCF_DTIM_DTMR_RST_EN, MCF_DTIM3_DTMR); ++ ++ sched_clk_val = 0; ++ request_irq(mcf_timervector, coldfire_sched_clk_irq, IRQF_DISABLED, \ ++ "timer", (void *)MCF_DTIM3_DTMR); ++ ++ settimericr(3, mcf_timerlevel); ++} ++ ++#ifndef CONFIG_GENERIC_CLOCKEVENTS ++/* get highres timer */ ++unsigned long long sched_clock(void) ++{ ++ unsigned long long ret = 0; ++ ret = sched_clk_val | (unsigned long long)(MCF_REG32(MCF_DTIM3_DTCN)); ++ ret = ret << 3; ++ return ret; ++} ++ ++#else /*CONFIG_GENERIC_CLOCKEVENTS*/ ++ ++static unsigned long long sched_dtim_clk_val; ++ ++unsigned long long sched_clock(void) ++{ ++ unsigned long flags; ++ unsigned long long tcn, cycles; ++ ++ local_irq_save(flags); ++ tcn = ((unsigned long long)(MCF_REG32(MCF_DTIM2_DTCN))); ++ cycles = sched_dtim_clk_val; ++ local_irq_restore(flags); ++ return cycles + tcn; ++} ++ ++unsigned long long sys_dtim2_read(void) ++{ ++ unsigned long flags; ++ unsigned long long tcn, cycles; ++ ++ local_irq_save(flags); ++ tcn = ((unsigned long long)(MCF_REG32(MCF_DTIM2_DTCN))); ++ cycles = sched_dtim_clk_val; ++ local_irq_restore(flags); ++ ++ return cycles + tcn; ++} ++ ++static irqreturn_t coldfire_dtim_clk_irq(int irq, void *dev) ++{ ++ struct clock_event_device *evt = (struct clock_event_device *)dev; ++ ++ __raw_writeb(MCF_DTIM_DTER_CAP | MCF_DTIM_DTER_REF, MCF_DTIM2_DTER); ++ sched_dtim_clk_val += (MCF_BUSCLK / 16) / HZ; ++ evt->event_handler(evt); ++ return IRQ_HANDLED; ++} ++ ++void sys_dtim2_init(struct clock_event_device *evt) ++{ ++ unsigned int mcf_timerlevel = 5; ++ unsigned int mcf_timervector = 64+32+2; /* DTIM2 */ ++ ++ printk(KERN_INFO "Initializing DTIM2 for sched_clock\n"); ++ __raw_writew(MCF_DTIM_DTMR_RST_RST, MCF_DTIM2_DTMR); ++ __raw_writel(((MCF_BUSCLK / 16) / HZ)-1, MCF_DTIM2_DTRR); ++ __raw_writew(MCF_DTIM_DTMR_ORRI | MCF_DTIM_DTMR_CLK_DIV16 | ++ MCF_DTIM_DTMR_FRR | MCF_DTIM_DTMR_RST_EN, \ ++ MCF_DTIM2_DTMR); ++ ++ request_irq(mcf_timervector, coldfire_dtim_clk_irq, IRQF_DISABLED, \ ++ "timer2", (void *)evt); ++ ++ settimericr(3, mcf_timerlevel); ++ return; ++} ++ ++#endif ++ ++void coldfire_reboot(void) ++{ ++ /* disable interrupts and do a software reset */ ++ asm("movew #0x2700, %%sr\n\t" ++ "moveb #0x40, %%d0\n\t" ++ "moveb %%d0, 0xfc0a0000\n\t" ++ : : : "%d0"); ++ ++ mdelay(10); ++ ++ asm("moveb #0xc0, %%d0\n\t" ++ "moveb %%d0, 0xfc0a0000\n\t" ++ : : : "%d0"); ++} ++ ++static void coldfire_get_model(char *model) ++{ ++ sprintf(model, "Version 4 ColdFire"); ++} ++ ++/* ++ * Setup the nodes and the boot memory. ++ * ++ * memory_start and memory_end are VIRTUAL addresses ++ */ ++static void __init ++coldfire_bootmem_alloc(unsigned long memory_start, unsigned long memory_end) ++{ ++ unsigned long base_pfn; ++ ++ /* compute total pages in system */ ++ num_pages = PAGE_ALIGN(memory_end - PAGE_OFFSET) >> PAGE_SHIFT; ++ ++ /* align start/end to page boundries */ ++ memory_start = PAGE_ALIGN(memory_start); ++ memory_end = memory_end & PAGE_MASK; ++ ++ /* page numbers */ ++ base_pfn = __pa(PAGE_OFFSET) >> PAGE_SHIFT; ++ min_low_pfn = __pa(memory_start) >> PAGE_SHIFT; ++ max_low_pfn = __pa(memory_end) >> PAGE_SHIFT; ++ ++ high_memory = (void *)memory_end; ++ availmem = memory_start; ++ ++ /* setup bootmem data */ ++ m68k_setup_node(0); ++ availmem += init_bootmem_node(NODE_DATA(0), min_low_pfn, ++ base_pfn, max_low_pfn); ++ availmem = PAGE_ALIGN(availmem); ++ ++ printk(KERN_INFO "** availmem=0x%lx pa(am)=0x%lx\n", ++ availmem, __pa(availmem)); ++ printk(KERN_INFO "** mstart=0x%lx mend=0x%lx\n", ++ memory_start, memory_end); ++ printk(KERN_INFO "bpfn=0x%lx minpfn=0x%lx maxpfn=0x%lx\n", ++ base_pfn, min_low_pfn, max_low_pfn); ++ ++ /* turn over physram */ ++ free_bootmem(__pa(availmem), memory_end - availmem); ++ ++ /* configure physical dma area */ ++ cf_dma_base = __pa(PAGE_ALIGN(memory_start)); ++ cf_dma_size = CONFIG_DMA_SIZE; ++ cf_dma_end = CONFIG_SDRAM_BASE + cf_dma_size - 1; ++ ++ printk(KERN_INFO "dma: phys base=0x%lx phys end=0x%lx virt base=0x%x\n", ++ cf_dma_base, cf_dma_end, CONFIG_DMA_BASE); ++ ++ printk(KERN_INFO "mdma=0x%x pa(mdma)=0x%lx\n", ++ MAX_DMA_ADDRESS, __pa(MAX_DMA_ADDRESS)); ++} ++ ++/* ++ * Architecture setup for Coldfire ++ */ ++void __init config_coldfire(void) ++{ ++ unsigned long endmem, startmem; ++ ++ /* ++ * Calculate endmem from m68k_memory[0] assuming that a single ++ * chunk of ram is being configured. ++ */ ++ startmem = ((((int) &_end) + (PAGE_SIZE - 1)) & PAGE_MASK); ++ endmem = PAGE_OFFSET + m68k_memory[0].size; ++ ++ /* set virt to node shift to be the high nibble byte */ ++ m68k_virt_to_node_shift = 28; ++ ++ printk(KERN_INFO "starting up linux startmem 0x%lx, endmem 0x%lx, \ ++ size %luMB\n", startmem, endmem, (endmem - startmem) >> 20); ++ ++ memset(irq_enable, 0, sizeof(irq_enable)); ++ ++ /* ++ * Setup coldfire mach-specific handlers ++ */ ++ mach_max_dma_address = 0xffffffff; ++ mach_sched_init = coldfire_sched_init; ++ mach_tick = coldfire_tick; ++ mach_gettimeoffset = coldfire_gettimeoffset; ++ mach_reset = coldfire_reboot; ++ mach_get_model = coldfire_get_model; ++ ++ coldfire_bootmem_alloc(startmem, endmem-1); ++ ++#if defined(CONFIG_DUMMY_CONSOLE) || defined(CONFIG_FRAMEBUFFER_CONSOLE) ++ conswitchp = &dummy_con; ++#endif ++ ++#if defined(CONFIG_SERIAL_COLDFIRE) ++ /* ++ * This causes trouble when it is re-registered later. ++ * Currently this is fixed by conditionally commenting ++ * out the register_console in mcf_serial.c ++ */ ++/*JKM -- moved earlier*/ ++ register_console(&mcfrs_console); ++#endif ++} ++ ++#ifdef CONFIG_SRAM ++static int __init setup_sram_pool(void) ++{ ++ declare_sram_pool((void *)CONFIG_SRAM_BASE, CONFIG_SRAM_SIZE); ++ return 0; ++} ++postcore_initcall(setup_sram_pool); ++#endif +--- /dev/null ++++ b/arch/m68k/coldfire/m5445x/devices.c +@@ -0,0 +1,527 @@ ++/* ++ * arch/m68k/coldfire/mcf5445x-devices.c ++ * ++ * Coldfire M5445x Platform Device Configuration ++ * ++ * Based on the Freescale MXC devices.c ++ * ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Kurt Mahan <kmahan@freescale.com> ++ * Jason Jin Jason.Jin@freescale.com ++ * Shrek Wu B16972@freescale.com ++ * ++ */ ++#include <linux/module.h> ++#include <linux/kernel.h> ++#include <linux/init.h> ++#include <linux/platform_device.h> ++#include <linux/fsl_devices.h> ++#include <linux/spi/spi.h> ++ ++#include <linux/interrupt.h> ++#include <linux/init.h> ++#ifdef CONFIG_MMC_SPI ++#include <linux/mmc/host.h> ++#include <linux/spi/mmc_spi.h> ++#endif ++ ++#include <asm/coldfire.h> ++#include <asm/mcfsim.h> ++#include <asm/mcfuart.h> ++#include <asm/mcfqspi.h> ++#include <asm/mcfdspi.h> ++#include <asm/cf_io.h> ++ ++/* ATA Interrupt */ ++#define IRQ_ATA (64 + 64 + 54) ++ ++/* ATA Base */ ++void __iomem *io_ata_map; ++unsigned long io_ata_mapsize = 16 * 1024 * 1024; ++#define BASE_IO_ATA ((unsigned int)(io_ata_map)) ++#define BASE_IO_ATA_PHY 0x90000000 ++#define IO_ATA_MAP_OFFSET (BASE_IO_ATA-BASE_IO_ATA_PHY) ++ ++/* conversion function between virtual address and physical address */ ++unsigned int io_ata_virt2phys(void *x) ++{ ++ return (unsigned int)x - IO_ATA_MAP_OFFSET; ++} ++ ++void *io_ata_phys2virt(unsigned int x) ++{ ++ return (void *)(x + IO_ATA_MAP_OFFSET); ++} ++ ++#define ATA_IER MCF_REG08(BASE_IO_ATA+0x2c) /* int enable reg */ ++#define ATA_ICR MCF_REG08(BASE_IO_ATA+0x30) /* int clear reg */ ++ ++/* DSPI */ ++#define M5445X_DSPI_MCR 0xfc05c000 /* base */ ++ ++#define M5445X_DSPI_IRQ_SOURCE (31) ++#define M5445X_DSPI_IRQ_VECTOR (64 + M5445X_DSPI_IRQ_SOURCE) ++ ++#define M5445X_AUDIO_IRQ_SOURCE (49) /* SSI interrupt */ ++#define M5445X_AUDIO_IRQ_VECTOR (128+M5445X_AUDIO_IRQ_SOURCE) ++#define M5445X_AUDIO_IRQ_LEVEL (4) ++ ++/* number of supported SPI selects */ ++#define SPI_NUM_CHIPSELECTS 8 ++ ++#define M5445X_SPI_PAR_VAL (MCF_GPIO_PAR_DSPI_SCK | \ ++ MCF_GPIO_PAR_DSPI_SOUT | \ ++ MCF_GPIO_PAR_DSPI_SIN | \ ++ MCF_GPIO_PAR_DSPI_PCS5_PCS5 | \ ++ MCF_GPIO_PAR_DSPI_PCS1_PCS1 | \ ++ MCF_GPIO_PAR_DSPI_PCS0_PCS0) ++ ++#ifdef CONFIG_SPI ++/* ++ * DSPI ++ */ ++ ++#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) ++static struct coldfire_dspi_chip spidev_chip_info = { ++ .bits_per_word = 8, ++}; ++#endif ++ ++#if defined(CONFIG_SND_COLDFIRE) || defined(CONFIG_SND_COLDFIRE_MODULE) ++static struct coldfire_dspi_chip codec_spi_chip_info = { ++ .mode = SPI_MODE_0, ++ .bits_per_word = 16, ++ .void_write_data = 0, ++ .dbr = 0, ++ .pbr = 2, ++ .br = 8, ++ .pcssck = 1, ++ .pasc = 1, ++ .pdt = 1, ++ .cssck = 0, ++ .asc = 1, ++ .dt = 1, ++}; ++#endif ++ ++#if defined(CONFIG_MMC_SPI) ++int mmc_spi_init(struct device *mmc_spi_device, ++ irqreturn_t mmc_spi_irq_handler(int irq, void *private), ++ void *irq_privatedata) ++{ ++#if 0 ++ MCF_GPIO_PAR_IRQ = MCF_GPIO_PAR_IRQ | MCF_GPIO_PAR_IRQ_IRQ4_GPIO; ++ /* Set trailing edge for PCI interrupts */ ++ MCF_EPORT_EPPAR &= ~MCF_EPORT_EPPAR_EPPA4(3); ++ MCF_EPORT_EPPAR |= MCF_EPORT_EPPAR_EPPA4_LEVEL; ++ /* Turn on irq line in eport */ ++ MCF_EPORT_EPIER = MCF_EPORT_EPIER | MCF_EPORT_EPIER_EPIE4; ++#endif ++ MCF_EPORT_EPPAR &= ~MCF_EPORT_EPPAR_EPPA7(3); ++ MCF_EPORT_EPPAR |= MCF_EPORT_EPPAR_EPPA7_BOTH; ++ MCF_EPORT_EPIER = MCF_EPORT_EPIER | MCF_EPORT_EPIER_EPIE7; ++#if defined(CONFIG_M54451_SD_HW_DETECT) ++ MCF_INTC0_ICR7 = 2; ++ if (request_irq(64 + 7, mmc_spi_irq_handler, ++ IRQF_DISABLED, "mmc_spi_irq", irq_privatedata)) { ++ printk(KERN_INFO "Cannot allocate " ++ "eport_irq_lines[%d] IRQ\n", 7); ++ return -EBUSY; ++ } ++ printk(KERN_INFO " extern irq7 as sd card detect\n"); ++#endif ++ return 0; ++} ++ ++static struct coldfire_dspi_chip dspi_sd_chip_info = { ++ .mode = SPI_MODE_0, ++ .bits_per_word = 8, ++ .void_write_data = 0xff, ++ .dbr = 0, ++ .pbr = 1, ++ .br = 1, ++ .pcssck = 2, ++ .pasc = 2, ++ .pdt = 2, ++ .cssck = 5, ++ .asc = 5, ++ .dt = 5, ++}; ++ ++static struct mmc_spi_platform_data mcf54451_mmc_pdata = { ++ .ocr_mask = MMC_VDD_33_34, ++ .init = mmc_spi_init, ++}; ++#endif ++ ++#if defined(CONFIG_VOIP_FXS) || defined(CONFIG_VOIP_FXS_MODULE) ++static struct coldfire_dspi_chip fxs_chip_info = { ++ .mode = SPI_MODE_3, ++ .bits_per_word = 8, ++ .void_write_data = 0, ++ .dbr = 0, ++ .pbr = 1, ++ .br = 1, ++ .pcssck = 0, ++ .pasc = 0, ++ .pdt = 0, ++ .cssck = 0, ++ .asc = 0, ++ .dt = 0, ++}; ++#endif ++ ++#if defined(CONFIG_VOIP_FXO) || defined(CONFIG_VOIP_FXO_MODULE) ++static struct coldfire_dspi_chip fxo_chip_info = { ++ .mode = SPI_MODE_3, ++ .bits_per_word = 8, ++ .void_write_data = 0, ++ .dbr = 0, ++ .pbr = 1, ++ .br = 1, ++ .pcssck = 0, ++ .pasc = 0, ++ .pdt = 0, ++ .cssck = 0, ++ .asc = 0, ++ .dt = 0, ++}; ++#endif ++ ++static struct spi_board_info spi_board_info[] = { ++#if defined(CONFIG_SND_COLDFIRE) || defined(CONFIG_SND_COLDFIRE_MODULE) ++ { ++ .modalias = "mcf_codec_spi", ++ .max_speed_hz = 300000, ++ .bus_num = 1, ++ .chip_select = 5, ++ .irq = M5445X_AUDIO_IRQ_VECTOR, ++ .platform_data = NULL, ++ .controller_data = &codec_spi_chip_info ++ }, ++#endif ++ ++#if defined(CONFIG_VOIP_FXS) || defined(CONFIG_VOIP_FXS_MODULE) ++ { ++ .modalias = "spi_fxs", ++ .max_speed_hz = 10000000, /* max spi clock in HZ */ ++ .bus_num = 1, ++ .chip_select = 2, ++ .controller_data = &fxs_chip_info ++ }, ++#endif ++ ++#if defined(CONFIG_VOIP_FXO) || defined(CONFIG_VOIP_FXO_MODULE) ++ { ++ .modalias = "spi_fxo", ++ .max_speed_hz = 10000000, /* max spi clock in HZ */ ++ .bus_num = 1, ++ .chip_select = 3, ++ .controller_data = &fxo_chip_info ++ }, ++#endif ++ ++#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) ++ { ++ .modalias = "spidev", ++ .max_speed_hz = 16000000, /* max clk (SCK) speed in HZ */ ++ .bus_num = 1, ++ .chip_select = 0, /* CS0 */ ++ .controller_data = &spidev_chip_info, ++ }, ++#endif ++ ++#if defined(CONFIG_MMC_SPI) ++ { ++ .modalias = "mmc_spi", ++ .max_speed_hz = 25000000, ++ .bus_num = 1, ++ .chip_select = 0, ++ .platform_data = &mcf54451_mmc_pdata, ++ .controller_data = &dspi_sd_chip_info, ++ }, ++#endif ++}; ++ ++ ++static struct coldfire_spi_master coldfire_master_info = { ++ .bus_num = 1, ++ .num_chipselect = SPI_NUM_CHIPSELECTS, ++ .irq_list = 0, /* not used */ ++ .irq_source = M5445X_DSPI_IRQ_SOURCE, ++ .irq_vector = M5445X_DSPI_IRQ_VECTOR, ++ .irq_mask = (1 << M5445X_DSPI_IRQ_SOURCE), ++ .irq_lp = 0x2, /* irq level */ ++ .par_val = M5445X_SPI_PAR_VAL, ++ .cs_control = NULL, ++}; ++ ++static struct resource coldfire_spi_resources[] = { ++ [0] = { ++ .name = "spi-par", ++ .start = (u32)&MCF_GPIO_PAR_DSPI, /* PAR_DSPI */ ++ .end = (u32)&MCF_GPIO_PAR_DSPI, /* PAR_DSPI */ ++ .flags = IORESOURCE_MEM ++ }, ++ ++ [1] = { ++ .name = "spi-module", ++ .start = M5445X_DSPI_MCR, /* DSPI MCR Base */ ++ .end = M5445X_DSPI_MCR + 0xc0, /* DSPI mem map end */ ++ .flags = IORESOURCE_MEM ++ }, ++ ++ [2] = { ++ .name = "spi-int-level", ++ .start = (u32)&MCF_INTC0_ICR31, /* ICR start */ ++ .end = (u32)&MCF_INTC0_ICR31, /* ICR end */ ++ .flags = IORESOURCE_MEM ++ }, ++ ++ [3] = { ++ .name = "spi-int-mask", ++ .start = (u32)&MCF_INTC0_IMRL, /* IMRL */ ++ .end = (u32)&MCF_INTC0_IMRL, /* IMRL */ ++ .flags = IORESOURCE_MEM ++ } ++}; ++ ++static struct platform_device coldfire_spi = { ++ .name = "spi_coldfire", ++ .id = -1, ++ .resource = coldfire_spi_resources, ++ .num_resources = ARRAY_SIZE(coldfire_spi_resources), ++ .dev = { ++ .platform_data = &coldfire_master_info, ++ } ++}; ++ ++/** ++ * m5445x_spi_init - Initialize SPI ++ */ ++static int __init m5445x_spi_init(void) ++{ ++ int retval; ++ ++ /* register device */ ++ retval = platform_device_register(&coldfire_spi); ++ if (retval < 0) ++ goto out; ++ ++ /* register board info */ ++ if (ARRAY_SIZE(spi_board_info)) ++ retval = spi_register_board_info(spi_board_info, ++ ARRAY_SIZE(spi_board_info)); ++ ++out: ++ return retval; ++} ++#endif ++ ++/* ++ * On-chip PATA ++ */ ++#if defined(CONFIG_PATA_FSL) || defined(CONFIG_PATA_FSL_MODULE) ++static int ata_init(struct platform_device *pdev) ++{ ++ /* clear ints */ ++ ATA_IER = 0x00; ++ ATA_ICR = 0xff; ++ ++ /* setup shared pins */ ++ MCF_GPIO_PAR_FEC = (MCF_GPIO_PAR_FEC & MCF_GPIO_PAR_FEC_FEC1_MASK) | ++ MCF_GPIO_PAR_FEC_FEC1_ATA; ++ ++ MCF_GPIO_PAR_FECI2C = (MCF_GPIO_PAR_FECI2C & ++ (MCF_GPIO_PAR_FECI2C_MDC1_MASK & ++ MCF_GPIO_PAR_FECI2C_MDIO1_MASK)) | ++ MCF_GPIO_PAR_FECI2C_MDC1_ATA_DIOR | ++ MCF_GPIO_PAR_FECI2C_MDIO1_ATA_DIOW; ++ ++ MCF_GPIO_PAR_ATA = MCF_GPIO_PAR_ATA_BUFEN | ++ MCF_GPIO_PAR_ATA_CS1 | ++ MCF_GPIO_PAR_ATA_CS0 | ++ MCF_GPIO_PAR_ATA_DA2 | ++ MCF_GPIO_PAR_ATA_DA1 | ++ MCF_GPIO_PAR_ATA_DA0 | ++ MCF_GPIO_PAR_ATA_RESET_RESET | ++ MCF_GPIO_PAR_ATA_DMARQ_DMARQ | ++ MCF_GPIO_PAR_ATA_IORDY_IORDY; ++ ++ MCF_GPIO_PAR_PCI = (MCF_GPIO_PAR_PCI & ++ (MCF_GPIO_PAR_PCI_GNT3_MASK & ++ MCF_GPIO_PAR_PCI_REQ3_MASK)) | ++ MCF_GPIO_PAR_PCI_GNT3_ATA_DMACK | ++ MCF_GPIO_PAR_PCI_REQ3_ATA_INTRQ; ++ ++ return 0; ++} ++ ++static void ata_exit(void) ++{ ++ printk(KERN_INFO "** ata_exit\n"); ++} ++ ++static int ata_get_clk_rate(void) ++{ ++ return MCF_BUSCLK; ++} ++ ++ ++static struct fsl_ata_platform_data ata_data = { ++ .init = ata_init, ++ .exit = ata_exit, ++ .get_clk_rate = ata_get_clk_rate, ++}; ++ ++static struct resource pata_fsl_resources[] = { ++ [0] = { /* I/O */ ++ .flags = IORESOURCE_MEM, ++ }, ++ [2] = { /* IRQ */ ++ .start = IRQ_ATA, ++ .end = IRQ_ATA, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static struct platform_device pata_fsl_device = { ++ .name = "pata_fsl", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(pata_fsl_resources), ++ .resource = pata_fsl_resources, ++ .dev = { ++ .platform_data = &ata_data, ++ .coherent_dma_mask = ~0, /* $$$ REVISIT */ ++ }, ++}; ++ ++static inline void mcf5445x_init_pata(void) ++{ ++ io_ata_map = ioremap(BASE_IO_ATA_PHY, io_ata_mapsize); ++ if (!io_ata_map) { ++ printk(KERN_ERR "IO ATA map failed by ioremap!\n"); ++ return; ++ } ++ printk(KERN_INFO "BASE_IO_ATA value is 0x%x\n", BASE_IO_ATA); ++ ++ pata_fsl_resources[0].start = BASE_IO_ATA; ++ pata_fsl_resources[0].end = BASE_IO_ATA + 0x000000d8; ++ ++ (void)platform_device_register(&pata_fsl_device); ++} ++#endif ++ ++/* ++ * I2C ++ */ ++#if defined(CONFIG_I2C) ++static struct resource coldfire_i2c_resources[] = { ++ { /* I/O */ ++ .start = 0xFC058000, ++ .end = 0xFC058010, ++ .flags = IORESOURCE_MEM, ++ }, ++ { /* IRQ */ ++ .start = (64 + 30), ++ .end = (64 + 30), ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static struct platform_device coldfire_i2c_device = { ++ .name = "mcf-i2c", ++ .id = 0, /*bus number*/ ++ .num_resources = ARRAY_SIZE(coldfire_i2c_resources), ++ .resource = coldfire_i2c_resources, ++}; ++ ++static void mcf5445x_init_i2c(void) ++{ ++ platform_device_register(&coldfire_i2c_device); ++} ++#endif ++ ++static int __init mcf5445x_init_devices(void) ++{ ++ printk(KERN_INFO "mcf5445x_init_devices: %s.\n", __func__); ++#ifdef CONFIG_SPI ++ m5445x_spi_init(); ++#endif ++ ++#if defined(CONFIG_PATA_FSL) || defined(CONFIG_PATA_FSL_MODULE) ++ mcf5445x_init_pata(); ++#endif ++ ++#if defined(CONFIG_I2C) ++ mcf5445x_init_i2c(); ++#endif ++ return 0; ++} ++arch_initcall(mcf5445x_init_devices); ++ ++/***************************************************************************/ ++static struct mcf_platform_uart m5445x_uart_platform[] = { ++ { ++ .mapbase = MCFUART_BASE1, ++ .irq = MCFINT_VECBASE + MCFINT_UART0, ++ }, ++#ifdef CONFIG_M54455 ++ { ++ .mapbase = MCFUART_BASE2, ++ .irq = MCFINT_VECBASE + MCFINT_UART1, ++ }, ++#endif ++ { }, ++}; ++ ++static struct platform_device m5445x_uart = { ++ .name = "mcfuart", ++ .id = 0, ++ .dev.platform_data = m5445x_uart_platform, ++}; ++ ++#if defined(CONFIG_RTC_MCF) || defined(CONFIG_RTC_MCF_MODULE) ++static struct platform_device rtc_device = { ++ .name = "mcf-rtc", ++ .id = -1, ++}; ++#endif ++ ++static struct platform_device *m5445x_devices[] __initdata = { ++ &m5445x_uart, ++#if defined(CONFIG_RTC_MCF) || defined(CONFIG_RTC_MCF_MODULE) ++ &rtc_device, ++#endif ++}; ++ ++ ++static void m5445x_uart_init_line(int line, int irq) ++{ ++ if (line == 0) ++ MCF_GPIO_PAR_UART = (0 | 0x000F); ++ else if (line == 1) ++ MCF_GPIO_PAR_UART |= (0 | 0x0FF0); ++} ++ ++void m5445x_uarts_init(void) ++{ ++ const int nrlines = ARRAY_SIZE(m5445x_uart_platform); ++ int line; ++ ++ for (line = 0; (line < nrlines); line++) ++ m5445x_uart_init_line(line, m5445x_uart_platform[line].irq); ++} ++/****************************************************************************/ ++/***************************************************************************/ ++ ++static int __init init_BSP(void) ++{ ++ m5445x_uarts_init(); ++ platform_add_devices(m5445x_devices, ARRAY_SIZE(m5445x_devices)); ++ return 0; ++} ++ ++arch_initcall(init_BSP); ++ ++ +--- /dev/null ++++ b/arch/m68k/configs/m54451evb_defconfig +@@ -0,0 +1,1412 @@ ++# ++# Automatically generated make config: don't edit ++# Linux kernel version: 2.6.29 ++# Tue Aug 24 16:14:20 2010 ++# ++CONFIG_M68K=y ++CONFIG_MMU=y ++CONFIG_GENERIC_TIME=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_RWSEM_GENERIC_SPINLOCK=y ++# CONFIG_ARCH_HAS_ILOG2_U32 is not set ++# CONFIG_ARCH_HAS_ILOG2_U64 is not set ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++# CONFIG_TIME_LOW_RES is not set ++CONFIG_GENERIC_IOMAP=y ++# CONFIG_NO_IOPORT is not set ++# CONFIG_NO_DMA is not set ++CONFIG_HZ=100 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++ ++# ++# General setup ++# ++CONFIG_EXPERIMENTAL=y ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_SWAP=y ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++# CONFIG_POSIX_MQUEUE is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++# CONFIG_AUDIT is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_CLASSIC_RCU=y ++# CONFIG_TREE_RCU is not set ++# CONFIG_PREEMPT_RCU is not set ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_PREEMPT_RCU_TRACE is not set ++CONFIG_IKCONFIG=y ++CONFIG_IKCONFIG_PROC=y ++CONFIG_LOG_BUF_SHIFT=17 ++CONFIG_GROUP_SCHED=y ++CONFIG_FAIR_GROUP_SCHED=y ++# CONFIG_RT_GROUP_SCHED is not set ++CONFIG_USER_SCHED=y ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUPS is not set ++CONFIG_SYSFS_DEPRECATED=y ++CONFIG_SYSFS_DEPRECATED_V2=y ++# CONFIG_RELAY is not set ++CONFIG_NAMESPACES=y ++# CONFIG_UTS_NS is not set ++# CONFIG_IPC_NS is not set ++# CONFIG_USER_NS is not set ++# CONFIG_PID_NS is not set ++# CONFIG_NET_NS is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_EMBEDDED=y ++CONFIG_UID16=y ++CONFIG_SYSCTL_SYSCALL=y ++CONFIG_KALLSYMS=y ++# CONFIG_KALLSYMS_EXTRA_PASS is not set ++CONFIG_HOTPLUG=y ++CONFIG_PRINTK=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++CONFIG_VM_EVENT_COUNTERS=y ++CONFIG_COMPAT_BRK=y ++CONFIG_SLAB=y ++# CONFIG_SLUB is not set ++# CONFIG_SLOB is not set ++# CONFIG_PROFILING is not set ++# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set ++CONFIG_SLABINFO=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=0 ++CONFIG_MODULES=y ++# CONFIG_MODULE_FORCE_LOAD is not set ++CONFIG_MODULE_UNLOAD=y ++CONFIG_MODULE_FORCE_UNLOAD=y ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++CONFIG_BLOCK=y ++CONFIG_LBD=y ++# CONFIG_BLK_DEV_IO_TRACE is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_AS=y ++CONFIG_IOSCHED_DEADLINE=y ++CONFIG_IOSCHED_CFQ=y ++# CONFIG_DEFAULT_AS is not set ++# CONFIG_DEFAULT_DEADLINE is not set ++CONFIG_DEFAULT_CFQ=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="cfq" ++# CONFIG_FREEZER is not set ++ ++# ++# Platform dependent setup ++# ++CONFIG_COLDFIRE=y ++CONFIG_CFV4E=y ++# CONFIG_FPU is not set ++# CONFIG_AMIGA is not set ++# CONFIG_ATARI is not set ++# CONFIG_MAC is not set ++# CONFIG_APOLLO is not set ++# CONFIG_VME is not set ++# CONFIG_HP300 is not set ++# CONFIG_SUN3X is not set ++# CONFIG_Q40 is not set ++# CONFIG_SUN3 is not set ++ ++# ++# Processor type ++# ++# CONFIG_M68020 is not set ++# CONFIG_M68030 is not set ++# CONFIG_M68040 is not set ++# CONFIG_M68060 is not set ++CONFIG_M5445X=y ++CONFIG_M54451=y ++# CONFIG_M54455 is not set ++CONFIG_M54451EVB=y ++# CONFIG_M54455EVB is not set ++CONFIG_HAVE_FSL_USB_DR=y ++# CONFIG_M547X_8X is not set ++# CONFIG_M5441X is not set ++CONFIG_MCFCLK=240000000 ++# CONFIG_MCF_USER_HALT is not set ++CONFIG_MMU_CFV4E=y ++CONFIG_SDRAM_BASE=0x40000000 ++CONFIG_SDRAM_SIZE=0x08000000 ++CONFIG_NOR_FLASH_BASE=0x00000000 ++CONFIG_DMA_BASE=0xef000000 ++CONFIG_DMA_SIZE=0x1000000 ++CONFIG_SRAM=y ++CONFIG_SRAM_BASE=0x8ff00000 ++CONFIG_SRAM_SIZE=0x8000 ++CONFIG_SRAM_ALLOC_GRANULARITY=0x200 ++CONFIG_VDSO=y ++# CONFIG_M68KFPU_EMU is not set ++CONFIG_ADVANCED=y ++# CONFIG_RMW_INSNS is not set ++CONFIG_SINGLE_MEMORY_CHUNK=y ++# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set ++CONFIG_SELECT_MEMORY_MODEL=y ++CONFIG_FLATMEM_MANUAL=y ++# CONFIG_DISCONTIGMEM_MANUAL is not set ++# CONFIG_SPARSEMEM_MANUAL is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_NEED_MULTIPLE_NODES=y ++CONFIG_PAGEFLAGS_EXTENDED=y ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++CONFIG_ZONE_DMA_FLAG=1 ++CONFIG_BOUNCE=y ++CONFIG_VIRT_TO_BUS=y ++CONFIG_UNEVICTABLE_LRU=y ++ ++# ++# General setup ++# ++CONFIG_BINFMT_ELF=y ++# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set ++CONFIG_HAVE_AOUT=y ++# CONFIG_BINFMT_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_PROC_HARDWARE=y ++CONFIG_ZONE_DMA=y ++# CONFIG_ARCH_SUPPORTS_MSI is not set ++ ++# ++# Power management options ++# ++CONFIG_PM=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_COMPAT_NET_DEV_OPS=y ++CONFIG_PACKET=y ++# CONFIG_PACKET_MMAP is not set ++CONFIG_UNIX=y ++CONFIG_XFRM=y ++# CONFIG_XFRM_USER is not set ++# CONFIG_XFRM_SUB_POLICY is not set ++# CONFIG_XFRM_MIGRATE is not set ++# CONFIG_XFRM_STATISTICS is not set ++CONFIG_NET_KEY=y ++# CONFIG_NET_KEY_MIGRATE is not set ++CONFIG_INET=y ++# CONFIG_IP_MULTICAST is not set ++CONFIG_IP_ADVANCED_ROUTER=y ++CONFIG_ASK_IP_FIB_HASH=y ++# CONFIG_IP_FIB_TRIE is not set ++CONFIG_IP_FIB_HASH=y ++# CONFIG_IP_MULTIPLE_TABLES is not set ++# CONFIG_IP_ROUTE_MULTIPATH is not set ++# CONFIG_IP_ROUTE_VERBOSE is not set ++CONFIG_IP_PNP=y ++# CONFIG_IP_PNP_DHCP is not set ++# CONFIG_IP_PNP_BOOTP is not set ++# CONFIG_IP_PNP_RARP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE is not set ++# CONFIG_ARPD is not set ++# CONFIG_SYN_COOKIES is not set ++CONFIG_INET_AH=y ++CONFIG_INET_ESP=y ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_LRO is not set ++CONFIG_INET_DIAG=y ++CONFIG_INET_TCP_DIAG=y ++# CONFIG_TCP_CONG_ADVANCED is not set ++CONFIG_TCP_CONG_CUBIC=y ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_BRIDGE is not set ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_ECONET is not set ++# CONFIG_WAN_ROUTER is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_PHONET is not set ++CONFIG_WIRELESS=y ++# CONFIG_CFG80211 is not set ++CONFIG_WIRELESS_OLD_REGULATORY=y ++# CONFIG_WIRELESS_EXT is not set ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_KLIPS is not set ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ++# CONFIG_STANDALONE is not set ++CONFIG_PREVENT_FIRMWARE_BUILD=y ++CONFIG_FW_LOADER=y ++CONFIG_FIRMWARE_IN_KERNEL=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++# CONFIG_MTD_DEBUG is not set ++CONFIG_MTD_CONCAT=y ++CONFIG_MTD_PARTITIONS=y ++# CONFIG_MTD_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_CHAR=y ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_MTD_OOPS is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++CONFIG_MTD_CFI=y ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_GEN_PROBE=y ++CONFIG_MTD_CFI_ADV_OPTIONS=y ++CONFIG_MTD_CFI_NOSWAP=y ++# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set ++# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set ++CONFIG_MTD_CFI_GEOMETRY=y ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++# CONFIG_MTD_OTP is not set ++CONFIG_MTD_CFI_INTELEXT=y ++CONFIG_MTD_CFI_AMDSTD=y ++CONFIG_MTD_CFI_STAA=y ++CONFIG_MTD_CFI_UTIL=y ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP=y ++CONFIG_MTD_PHYSMAP_COMPAT=y ++CONFIG_MTD_PHYSMAP_START=0x0 ++CONFIG_MTD_PHYSMAP_LEN=0x01000000 ++CONFIG_MTD_PHYSMAP_BANKWIDTH=2 ++# CONFIG_MTD_PLATRAM is not set ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_M25P80 is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOC2000 is not set ++# CONFIG_MTD_DOC2001 is not set ++# CONFIG_MTD_DOC2001PLUS is not set ++# CONFIG_MTD_NAND is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR flash memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++ ++# ++# UBI - Unsorted block images ++# ++# CONFIG_MTD_UBI is not set ++# CONFIG_PARPORT is not set ++CONFIG_BLK_DEV=y ++# CONFIG_BLK_DEV_COW_COMMON is not set ++CONFIG_BLK_DEV_LOOP=y ++# CONFIG_BLK_DEV_CRYPTOLOOP is not set ++# CONFIG_BLK_DEV_NBD is not set ++# CONFIG_BLK_DEV_UB is not set ++CONFIG_BLK_DEV_RAM=y ++CONFIG_BLK_DEV_RAM_COUNT=16 ++CONFIG_BLK_DEV_RAM_SIZE=64000 ++# CONFIG_BLK_DEV_XIP is not set ++# CONFIG_CDROM_PKTCDVD is not set ++# CONFIG_ATA_OVER_ETH is not set ++# CONFIG_BLK_DEV_HD is not set ++CONFIG_MISC_DEVICES=y ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++# CONFIG_EEPROM_AT24 is not set ++# CONFIG_EEPROM_AT25 is not set ++# CONFIG_EEPROM_LEGACY is not set ++# CONFIG_EEPROM_93CX6 is not set ++CONFIG_HAVE_IDE=y ++# CONFIG_IDE is not set ++ ++# ++# SCSI device support ++# ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_TGT is not set ++# CONFIG_SCSI_NETLINK is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++ ++# ++# Some SCSI devices (e.g. CD jukebox) support multiple LUNs ++# ++CONFIG_SCSI_MULTI_LUN=y ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++CONFIG_SCSI_WAIT_SCAN=m ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_LIBFC is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++CONFIG_NETDEVICES=y ++# CONFIG_DUMMY is not set ++# CONFIG_BONDING is not set ++# CONFIG_MACVLAN is not set ++# CONFIG_EQUALIZER is not set ++# CONFIG_TUN is not set ++# CONFIG_VETH is not set ++CONFIG_PHYLIB=y ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_BROADCOM5222_PHY is not set ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_NATIONAL8364x_PHY is not set ++# CONFIG_NATIONAL8384x_PHY is not set ++CONFIG_MicrelKSZ8041_PHY=y ++# CONFIG_STE10XP is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_FIXED_PHY is not set ++# CONFIG_MDIO_BITBANG is not set ++CONFIG_NET_ETHERNET=y ++CONFIG_MII=y ++# CONFIG_ENC28J60 is not set ++# CONFIG_DNET is not set ++# CONFIG_IBM_NEW_EMAC_ZMII is not set ++# CONFIG_IBM_NEW_EMAC_RGMII is not set ++# CONFIG_IBM_NEW_EMAC_TAH is not set ++# CONFIG_IBM_NEW_EMAC_EMAC4 is not set ++# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set ++# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set ++# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set ++# CONFIG_B44 is not set ++CONFIG_FEC=y ++# CONFIG_NETDEV_1000 is not set ++# CONFIG_NETDEV_10000 is not set ++ ++# ++# Wireless LAN ++# ++# CONFIG_WLAN_PRE80211 is not set ++# CONFIG_WLAN_80211 is not set ++# CONFIG_IWLWIFI_LEDS is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++ ++# ++# USB Network Adapters ++# ++# CONFIG_USB_CATC is not set ++# CONFIG_USB_KAWETH is not set ++CONFIG_USB_PEGASUS=m ++CONFIG_USB_RTL8150=m ++CONFIG_USB_USBNET=m ++CONFIG_USB_NET_AX8817X=m ++CONFIG_USB_NET_CDCETHER=m ++# CONFIG_USB_NET_DM9601 is not set ++# CONFIG_USB_NET_SMSC95XX is not set ++# CONFIG_USB_NET_GL620A is not set ++# CONFIG_USB_NET_NET1080 is not set ++# CONFIG_USB_NET_PLUSB is not set ++# CONFIG_USB_NET_MCS7830 is not set ++# CONFIG_USB_NET_RNDIS_HOST is not set ++# CONFIG_USB_NET_CDC_SUBSET is not set ++# CONFIG_USB_NET_ZAURUS is not set ++# CONFIG_WAN is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++# CONFIG_NETCONSOLE is not set ++# CONFIG_NETPOLL is not set ++# CONFIG_NET_POLL_CONTROLLER is not set ++# CONFIG_ISDN is not set ++# CONFIG_PHONE is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++# CONFIG_INPUT_MOUSEDEV_PSAUX is not set ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 ++# CONFIG_INPUT_JOYDEV is not set ++CONFIG_INPUT_EVDEV=y ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++CONFIG_INPUT_KEYBOARD=y ++# CONFIG_KEYBOARD_ATKBD is not set ++# CONFIG_KEYBOARD_SUNKBD is not set ++# CONFIG_KEYBOARD_LKKBD is not set ++# CONFIG_KEYBOARD_XTKBD is not set ++# CONFIG_KEYBOARD_NEWTON is not set ++# CONFIG_KEYBOARD_STOWAWAY is not set ++# CONFIG_INPUT_MOUSE is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++# CONFIG_INPUT_TOUCHSCREEN is not set ++# CONFIG_INPUT_MISC is not set ++ ++# ++# Hardware I/O ports ++# ++CONFIG_SERIO=y ++CONFIG_SERIO_SERPORT=y ++# CONFIG_SERIO_LIBPS2 is not set ++# CONFIG_SERIO_RAW is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_VT=y ++CONFIG_CONSOLE_TRANSLATIONS=y ++CONFIG_VT_CONSOLE=y ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++CONFIG_DEVKMEM=y ++CONFIG_DEVSRAM=m ++# CONFIG_SERIAL_NONSTANDARD is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_COLDFIRE_IRDA is not set ++# CONFIG_SERIAL_COLDFIRE_EDMA is not set ++CONFIG_SERIAL_MCF=y ++CONFIG_SERIAL_MCF_BAUDRATE=115200 ++CONFIG_SERIAL_MCF_CONSOLE=y ++CONFIG_UNIX98_PTYS=y ++# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++CONFIG_I2C_CHARDEV=y ++CONFIG_I2C_HELPER_AUTO=y ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++CONFIG_I2C_MCF=y ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_SIMTEC is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_STUB is not set ++ ++# ++# Miscellaneous I2C Chip support ++# ++# CONFIG_DS1682 is not set ++# CONFIG_SENSORS_PCF8574 is not set ++# CONFIG_PCF8575 is not set ++# CONFIG_SENSORS_PCA9539 is not set ++# CONFIG_SENSORS_PCF8591 is not set ++# CONFIG_SENSORS_MAX6875 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++# CONFIG_I2C_DEBUG_CHIP is not set ++CONFIG_SPI=y ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_BITBANG is not set ++CONFIG_SPI_DSPI=y ++CONFIG_SPI_COLDFIRE_DSPI_EDMA=y ++# CONFIG_VOIP_FXS is not set ++# CONFIG_VOIP_FXO is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_W1 is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++# CONFIG_THERMAL_HWMON is not set ++CONFIG_WATCHDOG=y ++# CONFIG_WATCHDOG_NOWAYOUT is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++CONFIG_COLDFIRE_WATCHDOG=y ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_REGULATOR is not set ++ ++# ++# Multimedia devices ++# ++ ++# ++# Multimedia core support ++# ++# CONFIG_VIDEO_DEV is not set ++# CONFIG_DVB_CORE is not set ++# CONFIG_VIDEO_MEDIA is not set ++ ++# ++# Multimedia drivers ++# ++CONFIG_DAB=y ++# CONFIG_USB_DABUSB is not set ++ ++# ++# Graphics support ++# ++# CONFIG_VGASTATE is not set ++CONFIG_VIDEO_OUTPUT_CONTROL=m ++# CONFIG_FB is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++ ++# ++# Display device support ++# ++# CONFIG_DISPLAY_SUPPORT is not set ++ ++# ++# Console display driver support ++# ++CONFIG_DUMMY_CONSOLE=y ++CONFIG_SOUND=y ++CONFIG_SOUND_OSS_CORE=y ++CONFIG_SND=y ++CONFIG_SND_TIMER=y ++CONFIG_SND_PCM=y ++# CONFIG_SND_SEQUENCER is not set ++CONFIG_SND_OSSEMUL=y ++# CONFIG_SND_MIXER_OSS is not set ++CONFIG_SND_PCM_OSS=y ++CONFIG_SND_PCM_OSS_PLUGINS=y ++# CONFIG_SND_HRTIMER is not set ++# CONFIG_SND_DYNAMIC_MINORS is not set ++CONFIG_SND_SUPPORT_OLD_API=y ++CONFIG_SND_VERBOSE_PROCFS=y ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++CONFIG_SND_DRIVERS=y ++# CONFIG_SND_DUMMY is not set ++# CONFIG_SND_MTPAV is not set ++# CONFIG_SND_SERIAL_U16550 is not set ++# CONFIG_SND_MPU401 is not set ++ ++# ++# ALSA for Coldfire ++# ++CONFIG_SND_COLDFIRE=y ++CONFIG_SND_SPI=y ++CONFIG_SND_USB=y ++# CONFIG_SND_USB_AUDIO is not set ++# CONFIG_SND_USB_CAIAQ is not set ++# CONFIG_SND_SOC is not set ++# CONFIG_SOUND_PRIME is not set ++CONFIG_HID_SUPPORT=y ++CONFIG_HID=y ++# CONFIG_HID_DEBUG is not set ++# CONFIG_HIDRAW is not set ++ ++# ++# USB Input Devices ++# ++CONFIG_USB_HID=y ++# CONFIG_HID_PID is not set ++# CONFIG_USB_HIDDEV is not set ++ ++# ++# Special HID drivers ++# ++CONFIG_HID_COMPAT=y ++# CONFIG_HID_A4TECH is not set ++# CONFIG_HID_APPLE is not set ++# CONFIG_HID_BELKIN is not set ++# CONFIG_HID_CHERRY is not set ++# CONFIG_HID_CHICONY is not set ++# CONFIG_HID_CYPRESS is not set ++# CONFIG_HID_EZKEY is not set ++# CONFIG_HID_GYRATION is not set ++# CONFIG_HID_LOGITECH is not set ++# CONFIG_HID_MICROSOFT is not set ++# CONFIG_HID_MONTEREY is not set ++# CONFIG_HID_NTRIG is not set ++# CONFIG_HID_PANTHERLORD is not set ++# CONFIG_HID_PETALYNX is not set ++# CONFIG_HID_SAMSUNG is not set ++# CONFIG_HID_SONY is not set ++# CONFIG_HID_SUNPLUS is not set ++# CONFIG_GREENASIA_FF is not set ++# CONFIG_HID_TOPSEED is not set ++# CONFIG_THRUSTMASTER_FF is not set ++# CONFIG_ZEROPLUS_FF is not set ++CONFIG_USB_SUPPORT=y ++CONFIG_USB_ARCH_HAS_HCD=y ++# CONFIG_USB_ARCH_HAS_OHCI is not set ++CONFIG_USB_ARCH_HAS_EHCI=y ++CONFIG_USB=y ++# CONFIG_USB_DEBUG is not set ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEVICEFS=y ++# CONFIG_USB_DEVICE_CLASS is not set ++# CONFIG_USB_DYNAMIC_MINORS is not set ++CONFIG_USB_SUSPEND=y ++CONFIG_USB_OTG=y ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++# CONFIG_USB_EHCI_TT_NEWSCHED is not set ++CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y ++CONFIG_USB_EHCI_BIG_ENDIAN_DESC=y ++CONFIG_USB_EHCI_FSL=y ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HWA_HCD is not set ++CONFIG_USB_M5445X_ULPI=y ++# CONFIG_USB_M5445X_FSLS is not set ++# CONFIG_USB_M5441X_ULPI is not set ++# CONFIG_USB_M5441X_FSLS is not set ++# CONFIG_USB_GADGET_MUSB_HDRC is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; ++# ++ ++# ++# see USB_STORAGE Help for more information ++# ++CONFIG_USB_STORAGE=y ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_LIBUSUAL is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_BERRY_CHARGE is not set ++# CONFIG_USB_LED is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_PHIDGET is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_VST is not set ++CONFIG_USB_GADGET=m ++# CONFIG_USB_GADGET_DEBUG_FILES is not set ++CONFIG_USB_GADGET_VBUS_DRAW=2 ++CONFIG_USB_GADGET_SELECTED=y ++# CONFIG_USB_GADGET_AT91 is not set ++# CONFIG_USB_GADGET_ATMEL_USBA is not set ++CONFIG_USB_GADGET_FSL_USB2=y ++CONFIG_USB_FSL_USB2=m ++# CONFIG_USB_GADGET_LH7A40X is not set ++# CONFIG_USB_GADGET_OMAP is not set ++# CONFIG_USB_GADGET_PXA25X is not set ++# CONFIG_USB_GADGET_PXA27X is not set ++# CONFIG_USB_GADGET_S3C2410 is not set ++# CONFIG_USB_GADGET_IMX is not set ++# CONFIG_USB_GADGET_M66592 is not set ++# CONFIG_USB_GADGET_AMD5536UDC is not set ++# CONFIG_USB_GADGET_FSL_QE is not set ++# CONFIG_USB_GADGET_CI13XXX is not set ++# CONFIG_USB_GADGET_NET2280 is not set ++# CONFIG_USB_GADGET_GOKU is not set ++# CONFIG_USB_GADGET_DUMMY_HCD is not set ++CONFIG_USB_GADGET_DUALSPEED=y ++# CONFIG_USB_ZERO is not set ++CONFIG_USB_ETH=m ++CONFIG_USB_ETH_RNDIS=y ++# CONFIG_USB_GADGETFS is not set ++CONFIG_USB_FILE_STORAGE=m ++# CONFIG_USB_FILE_STORAGE_TEST is not set ++# CONFIG_USB_G_SERIAL is not set ++# CONFIG_USB_MIDI_GADGET is not set ++# CONFIG_USB_G_PRINTER is not set ++# CONFIG_USB_CDC_COMPOSITE is not set ++ ++# ++# OTG and related infrastructure ++# ++CONFIG_MMC=y ++# CONFIG_MMC_DEBUG is not set ++# CONFIG_MMC_UNSAFE_RESUME is not set ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=y ++CONFIG_MMC_BLOCK_BOUNCE=y ++CONFIG_SDIO_UART=y ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++CONFIG_MMC_SPI=y ++CONFIG_M54451_SD_HW_DETECT=y ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_DS3234 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++ ++# ++# on-CPU RTC drivers ++# ++CONFIG_RTC_MCF=y ++# CONFIG_RTC_M5441X is not set ++CONFIG_DMADEVICES=y ++ ++# ++# DMA Devices ++# ++CONFIG_COLDFIRE_EDMA=y ++CONFIG_COLDFIRE_EDMA_TEST=m ++# CONFIG_UIO is not set ++# CONFIG_STAGING is not set ++ ++# ++# Character devices ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++CONFIG_GENERIC_CLOCKEVENTS_BUILD=y ++ ++# ++# File systems ++# ++CONFIG_EXT2_FS=y ++# CONFIG_EXT2_FS_XATTR is not set ++# CONFIG_EXT2_FS_XIP is not set ++CONFIG_EXT3_FS=y ++CONFIG_EXT3_FS_XATTR=y ++# CONFIG_EXT3_FS_POSIX_ACL is not set ++# CONFIG_EXT3_FS_SECURITY is not set ++# CONFIG_EXT4_FS is not set ++CONFIG_JBD=y ++CONFIG_FS_MBCACHE=y ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_FS_POSIX_ACL is not set ++CONFIG_FILE_LOCKING=y ++# CONFIG_XFS_FS is not set ++# CONFIG_GFS2_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_QUOTA is not set ++# CONFIG_AUTOFS_FS is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++CONFIG_ISO9660_FS=y ++# CONFIG_JOLIET is not set ++# CONFIG_ZISOFS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=y ++CONFIG_MSDOS_FS=y ++CONFIG_VFAT_FS=y ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++CONFIG_NTFS_FS=y ++# CONFIG_NTFS_DEBUG is not set ++CONFIG_NTFS_RW=y ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++# CONFIG_PROC_KCORE is not set ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++# CONFIG_TMPFS_POSIX_ACL is not set ++# CONFIG_HUGETLB_PAGE is not set ++# CONFIG_CONFIGFS_FS is not set ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++CONFIG_JFFS2_FS_WRITEBUFFER=y ++# CONFIG_JFFS2_FS_WBUF_VERIFY is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++# CONFIG_CRAMFS is not set ++# CONFIG_SQUASHFS is not set ++# CONFIG_VXFS_FS is not set ++CONFIG_MINIX_FS=y ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=y ++CONFIG_NFS_V3=y ++# CONFIG_NFS_V3_ACL is not set ++# CONFIG_NFS_V4 is not set ++CONFIG_ROOT_NFS=y ++# CONFIG_NFSD is not set ++CONFIG_LOCKD=y ++CONFIG_LOCKD_V4=y ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=y ++# CONFIG_SUNRPC_REGISTER_V4 is not set ++# CONFIG_RPCSEC_GSS_KRB5 is not set ++# CONFIG_RPCSEC_GSS_SPKM3 is not set ++# CONFIG_SMB_FS is not set ++# CONFIG_CIFS is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++ ++# ++# Partition Types ++# ++CONFIG_PARTITION_ADVANCED=y ++# CONFIG_ACORN_PARTITION is not set ++# CONFIG_OSF_PARTITION is not set ++# CONFIG_AMIGA_PARTITION is not set ++# CONFIG_ATARI_PARTITION is not set ++# CONFIG_MAC_PARTITION is not set ++CONFIG_MSDOS_PARTITION=y ++# CONFIG_BSD_DISKLABEL is not set ++# CONFIG_MINIX_SUBPARTITION is not set ++# CONFIG_SOLARIS_X86_PARTITION is not set ++# CONFIG_UNIXWARE_DISKLABEL is not set ++# CONFIG_LDM_PARTITION is not set ++# CONFIG_SGI_PARTITION is not set ++# CONFIG_ULTRIX_PARTITION is not set ++# CONFIG_SUN_PARTITION is not set ++# CONFIG_KARMA_PARTITION is not set ++# CONFIG_EFI_PARTITION is not set ++# CONFIG_SYSV68_PARTITION is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++CONFIG_NLS_UTF8=y ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++# CONFIG_ENABLE_MUST_CHECK is not set ++CONFIG_FRAME_WARN=1024 ++# CONFIG_MAGIC_SYSRQ is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_DEBUG_FS is not set ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_KERNEL is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_RCU_CPU_STALL_DETECTOR is not set ++# CONFIG_SYSCTL_SYSCALL_CHECK is not set ++ ++# ++# Tracers ++# ++# CONFIG_DYNAMIC_PRINTK_DEBUG is not set ++# CONFIG_SAMPLES is not set ++# CONFIG_BOOTPARAM is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++# CONFIG_SECURITY_FILE_CAPABILITIES is not set ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++# CONFIG_CRYPTO_FIPS is not set ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_GF128MUL is not set ++# CONFIG_CRYPTO_NULL is not set ++# CONFIG_CRYPTO_CRYPTD is not set ++CONFIG_CRYPTO_AUTHENC=y ++CONFIG_CRYPTO_TEST=m ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_SEQIV is not set ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++# CONFIG_CRYPTO_CTR is not set ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++CONFIG_CRYPTO_PCBC=m ++# CONFIG_CRYPTO_XTS is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++ ++# ++# Digest ++# ++CONFIG_CRYPTO_CRC32C=y ++# CONFIG_CRYPTO_MD4 is not set ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++CONFIG_CRYPTO_SHA1=y ++# CONFIG_CRYPTO_SHA256 is not set ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++# CONFIG_CRYPTO_DEFLATE is not set ++# CONFIG_CRYPTO_LZO is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++ ++# ++# OCF Configuration ++# ++ ++# ++# Talitos Driver ++# ++CONFIG_CRYPTO_HW=y ++CONFIG_CRYPTO_DEV_MCFCAU=y ++CONFIG_CRYPTO_DEV_MCFCAU_DES=y ++CONFIG_CRYPTO_DEV_MCFCAU_AES=y ++CONFIG_CRYPTO_DEV_MCFCAU_MD5=y ++CONFIG_CRYPTO_DEV_MCFCAU_SHA1=y ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_GENERIC_FIND_LAST_BIT=y ++CONFIG_CRC_CCITT=y ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++CONFIG_CRC_ITU_T=y ++CONFIG_CRC32=y ++CONFIG_CRC7=y ++CONFIG_LIBCRC32C=y ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_PLIST=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT=y ++CONFIG_HAS_DMA=y +--- /dev/null ++++ b/arch/m68k/configs/m54455evb_defconfig +@@ -0,0 +1,1597 @@ ++# ++# Automatically generated make config: don't edit ++# Linux kernel version: 2.6.29 ++# Tue Aug 24 16:16:14 2010 ++# ++CONFIG_M68K=y ++CONFIG_MMU=y ++CONFIG_GENERIC_TIME=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_RWSEM_GENERIC_SPINLOCK=y ++# CONFIG_ARCH_HAS_ILOG2_U32 is not set ++# CONFIG_ARCH_HAS_ILOG2_U64 is not set ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++# CONFIG_TIME_LOW_RES is not set ++CONFIG_GENERIC_IOMAP=y ++# CONFIG_NO_IOPORT is not set ++# CONFIG_NO_DMA is not set ++CONFIG_HZ=100 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++ ++# ++# General setup ++# ++CONFIG_EXPERIMENTAL=y ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_SWAP=y ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++# CONFIG_POSIX_MQUEUE is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++# CONFIG_AUDIT is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_CLASSIC_RCU=y ++# CONFIG_TREE_RCU is not set ++# CONFIG_PREEMPT_RCU is not set ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_PREEMPT_RCU_TRACE is not set ++CONFIG_IKCONFIG=y ++CONFIG_IKCONFIG_PROC=y ++CONFIG_LOG_BUF_SHIFT=17 ++CONFIG_GROUP_SCHED=y ++CONFIG_FAIR_GROUP_SCHED=y ++# CONFIG_RT_GROUP_SCHED is not set ++CONFIG_USER_SCHED=y ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUPS is not set ++CONFIG_SYSFS_DEPRECATED=y ++CONFIG_SYSFS_DEPRECATED_V2=y ++# CONFIG_RELAY is not set ++CONFIG_NAMESPACES=y ++# CONFIG_UTS_NS is not set ++# CONFIG_IPC_NS is not set ++# CONFIG_USER_NS is not set ++# CONFIG_PID_NS is not set ++# CONFIG_NET_NS is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_EMBEDDED=y ++CONFIG_UID16=y ++CONFIG_SYSCTL_SYSCALL=y ++CONFIG_KALLSYMS=y ++# CONFIG_KALLSYMS_EXTRA_PASS is not set ++CONFIG_HOTPLUG=y ++CONFIG_PRINTK=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++CONFIG_VM_EVENT_COUNTERS=y ++CONFIG_PCI_QUIRKS=y ++CONFIG_COMPAT_BRK=y ++CONFIG_SLAB=y ++# CONFIG_SLUB is not set ++# CONFIG_SLOB is not set ++# CONFIG_PROFILING is not set ++# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set ++CONFIG_SLABINFO=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=0 ++CONFIG_MODULES=y ++# CONFIG_MODULE_FORCE_LOAD is not set ++CONFIG_MODULE_UNLOAD=y ++CONFIG_MODULE_FORCE_UNLOAD=y ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++CONFIG_BLOCK=y ++CONFIG_LBD=y ++# CONFIG_BLK_DEV_IO_TRACE is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_AS=y ++CONFIG_IOSCHED_DEADLINE=y ++CONFIG_IOSCHED_CFQ=y ++# CONFIG_DEFAULT_AS is not set ++# CONFIG_DEFAULT_DEADLINE is not set ++CONFIG_DEFAULT_CFQ=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="cfq" ++# CONFIG_FREEZER is not set ++ ++# ++# Platform dependent setup ++# ++CONFIG_COLDFIRE=y ++CONFIG_CFV4E=y ++# CONFIG_FPU is not set ++# CONFIG_AMIGA is not set ++# CONFIG_ATARI is not set ++CONFIG_PCI=y ++# CONFIG_MAC is not set ++# CONFIG_APOLLO is not set ++# CONFIG_VME is not set ++# CONFIG_HP300 is not set ++# CONFIG_SUN3X is not set ++# CONFIG_Q40 is not set ++# CONFIG_SUN3 is not set ++ ++# ++# Processor type ++# ++# CONFIG_M68020 is not set ++# CONFIG_M68030 is not set ++# CONFIG_M68040 is not set ++# CONFIG_M68060 is not set ++CONFIG_M5445X=y ++# CONFIG_M54451 is not set ++CONFIG_M54455=y ++# CONFIG_M54451EVB is not set ++CONFIG_M54455EVB=y ++CONFIG_HAVE_FSL_USB_DR=y ++# CONFIG_M547X_8X is not set ++# CONFIG_M5441X is not set ++CONFIG_MCFCLK=266666666 ++# CONFIG_MCF_USER_HALT is not set ++CONFIG_MMU_CFV4E=y ++CONFIG_SDRAM_BASE=0x40000000 ++CONFIG_SDRAM_SIZE=0x10000000 ++CONFIG_NOR_FLASH_BASE=0x00000000 ++CONFIG_DMA_BASE=0xef000000 ++CONFIG_DMA_SIZE=0x1000000 ++CONFIG_SRAM=y ++CONFIG_SRAM_BASE=0x8ff00000 ++CONFIG_SRAM_SIZE=0x8000 ++CONFIG_SRAM_ALLOC_GRANULARITY=0x200 ++CONFIG_VDSO=y ++# CONFIG_M68KFPU_EMU is not set ++CONFIG_ADVANCED=y ++# CONFIG_RMW_INSNS is not set ++CONFIG_SINGLE_MEMORY_CHUNK=y ++# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set ++CONFIG_SELECT_MEMORY_MODEL=y ++CONFIG_FLATMEM_MANUAL=y ++# CONFIG_DISCONTIGMEM_MANUAL is not set ++# CONFIG_SPARSEMEM_MANUAL is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_NEED_MULTIPLE_NODES=y ++CONFIG_PAGEFLAGS_EXTENDED=y ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++CONFIG_ZONE_DMA_FLAG=1 ++CONFIG_BOUNCE=y ++CONFIG_VIRT_TO_BUS=y ++CONFIG_UNEVICTABLE_LRU=y ++ ++# ++# General setup ++# ++CONFIG_BINFMT_ELF=y ++# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set ++CONFIG_HAVE_AOUT=y ++# CONFIG_BINFMT_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_PROC_HARDWARE=y ++CONFIG_ZONE_DMA=y ++# CONFIG_ARCH_SUPPORTS_MSI is not set ++CONFIG_PCI_LEGACY=y ++# CONFIG_PCI_STUB is not set ++ ++# ++# Power management options ++# ++CONFIG_PM=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_COMPAT_NET_DEV_OPS=y ++CONFIG_PACKET=y ++# CONFIG_PACKET_MMAP is not set ++CONFIG_UNIX=y ++CONFIG_XFRM=y ++# CONFIG_XFRM_USER is not set ++# CONFIG_XFRM_SUB_POLICY is not set ++# CONFIG_XFRM_MIGRATE is not set ++# CONFIG_XFRM_STATISTICS is not set ++CONFIG_NET_KEY=y ++# CONFIG_NET_KEY_MIGRATE is not set ++CONFIG_INET=y ++# CONFIG_IP_MULTICAST is not set ++CONFIG_IP_ADVANCED_ROUTER=y ++CONFIG_ASK_IP_FIB_HASH=y ++# CONFIG_IP_FIB_TRIE is not set ++CONFIG_IP_FIB_HASH=y ++# CONFIG_IP_MULTIPLE_TABLES is not set ++# CONFIG_IP_ROUTE_MULTIPATH is not set ++# CONFIG_IP_ROUTE_VERBOSE is not set ++CONFIG_IP_PNP=y ++# CONFIG_IP_PNP_DHCP is not set ++# CONFIG_IP_PNP_BOOTP is not set ++# CONFIG_IP_PNP_RARP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE is not set ++# CONFIG_ARPD is not set ++# CONFIG_SYN_COOKIES is not set ++CONFIG_INET_AH=y ++CONFIG_INET_ESP=y ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_LRO is not set ++CONFIG_INET_DIAG=y ++CONFIG_INET_TCP_DIAG=y ++# CONFIG_TCP_CONG_ADVANCED is not set ++CONFIG_TCP_CONG_CUBIC=y ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_BRIDGE is not set ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_ECONET is not set ++# CONFIG_WAN_ROUTER is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_PHONET is not set ++CONFIG_WIRELESS=y ++# CONFIG_CFG80211 is not set ++CONFIG_WIRELESS_OLD_REGULATORY=y ++# CONFIG_WIRELESS_EXT is not set ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_KLIPS is not set ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ++# CONFIG_STANDALONE is not set ++CONFIG_PREVENT_FIRMWARE_BUILD=y ++CONFIG_FW_LOADER=y ++CONFIG_FIRMWARE_IN_KERNEL=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++# CONFIG_MTD_DEBUG is not set ++# CONFIG_MTD_CONCAT is not set ++CONFIG_MTD_PARTITIONS=y ++# CONFIG_MTD_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_CHAR=y ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_MTD_OOPS is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++CONFIG_MTD_CFI=y ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_GEN_PROBE=y ++# CONFIG_MTD_CFI_ADV_OPTIONS is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_CFI_INTELEXT=y ++CONFIG_MTD_CFI_AMDSTD=y ++# CONFIG_MTD_CFI_STAA is not set ++CONFIG_MTD_CFI_UTIL=y ++# CONFIG_MTD_RAM is not set ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP=y ++CONFIG_MTD_PHYSMAP_COMPAT=y ++CONFIG_MTD_PHYSMAP_START=0x0 ++CONFIG_MTD_PHYSMAP_LEN=0x01000000 ++CONFIG_MTD_PHYSMAP_BANKWIDTH=1 ++# CONFIG_MTD_INTEL_VR_NOR is not set ++# CONFIG_MTD_PLATRAM is not set ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_PMC551 is not set ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_M25P80 is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOC2000 is not set ++# CONFIG_MTD_DOC2001 is not set ++# CONFIG_MTD_DOC2001PLUS is not set ++# CONFIG_MTD_NAND is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR flash memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++ ++# ++# UBI - Unsorted block images ++# ++# CONFIG_MTD_UBI is not set ++# CONFIG_PARPORT is not set ++CONFIG_BLK_DEV=y ++# CONFIG_BLK_CPQ_DA is not set ++# CONFIG_BLK_CPQ_CISS_DA is not set ++# CONFIG_BLK_DEV_DAC960 is not set ++# CONFIG_BLK_DEV_UMEM is not set ++# CONFIG_BLK_DEV_COW_COMMON is not set ++CONFIG_BLK_DEV_LOOP=y ++# CONFIG_BLK_DEV_CRYPTOLOOP is not set ++# CONFIG_BLK_DEV_NBD is not set ++# CONFIG_BLK_DEV_SX8 is not set ++# CONFIG_BLK_DEV_UB is not set ++CONFIG_BLK_DEV_RAM=y ++CONFIG_BLK_DEV_RAM_COUNT=16 ++CONFIG_BLK_DEV_RAM_SIZE=64000 ++# CONFIG_BLK_DEV_XIP is not set ++# CONFIG_CDROM_PKTCDVD is not set ++# CONFIG_ATA_OVER_ETH is not set ++# CONFIG_BLK_DEV_HD is not set ++CONFIG_MISC_DEVICES=y ++# CONFIG_PHANTOM is not set ++# CONFIG_SGI_IOC4 is not set ++# CONFIG_TIFM_CORE is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_HP_ILO is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++# CONFIG_EEPROM_AT24 is not set ++# CONFIG_EEPROM_AT25 is not set ++# CONFIG_EEPROM_LEGACY is not set ++# CONFIG_EEPROM_93CX6 is not set ++CONFIG_HAVE_IDE=y ++# CONFIG_IDE is not set ++ ++# ++# SCSI device support ++# ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_TGT is not set ++# CONFIG_SCSI_NETLINK is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++CONFIG_CHR_DEV_SG=y ++# CONFIG_CHR_DEV_SCH is not set ++ ++# ++# Some SCSI devices (e.g. CD jukebox) support multiple LUNs ++# ++CONFIG_SCSI_MULTI_LUN=y ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++CONFIG_SCSI_WAIT_SCAN=m ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_BLK_DEV_3W_XXXX_RAID is not set ++# CONFIG_SCSI_3W_9XXX is not set ++# CONFIG_SCSI_ACARD is not set ++# CONFIG_SCSI_AACRAID is not set ++# CONFIG_SCSI_AIC7XXX is not set ++# CONFIG_SCSI_AIC7XXX_OLD is not set ++# CONFIG_SCSI_AIC79XX is not set ++# CONFIG_SCSI_AIC94XX is not set ++# CONFIG_SCSI_DPT_I2O is not set ++# CONFIG_SCSI_ADVANSYS is not set ++# CONFIG_SCSI_ARCMSR is not set ++# CONFIG_MEGARAID_NEWGEN is not set ++# CONFIG_MEGARAID_LEGACY is not set ++# CONFIG_MEGARAID_SAS is not set ++# CONFIG_SCSI_HPTIOP is not set ++# CONFIG_LIBFC is not set ++# CONFIG_FCOE is not set ++# CONFIG_SCSI_DMX3191D is not set ++# CONFIG_SCSI_FUTURE_DOMAIN is not set ++# CONFIG_SCSI_IPS is not set ++# CONFIG_SCSI_INITIO is not set ++# CONFIG_SCSI_INIA100 is not set ++# CONFIG_SCSI_MVSAS is not set ++# CONFIG_SCSI_STEX is not set ++# CONFIG_SCSI_SYM53C8XX_2 is not set ++# CONFIG_SCSI_IPR is not set ++# CONFIG_SCSI_QLOGIC_1280 is not set ++# CONFIG_SCSI_QLA_FC is not set ++# CONFIG_SCSI_QLA_ISCSI is not set ++# CONFIG_SCSI_LPFC is not set ++# CONFIG_SCSI_DC395x is not set ++# CONFIG_SCSI_DC390T is not set ++# CONFIG_SCSI_NSP32 is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_SRP is not set ++# CONFIG_SCSI_DH is not set ++CONFIG_ATA=y ++# CONFIG_ATA_NONSTANDARD is not set ++CONFIG_SATA_PMP=y ++# CONFIG_SATA_AHCI is not set ++# CONFIG_SATA_SIL24 is not set ++CONFIG_ATA_SFF=y ++# CONFIG_SATA_SVW is not set ++# CONFIG_ATA_PIIX is not set ++# CONFIG_SATA_MV is not set ++# CONFIG_SATA_NV is not set ++# CONFIG_PDC_ADMA is not set ++# CONFIG_SATA_QSTOR is not set ++# CONFIG_SATA_PROMISE is not set ++# CONFIG_SATA_SX4 is not set ++# CONFIG_SATA_SIL is not set ++# CONFIG_SATA_SIS is not set ++# CONFIG_SATA_ULI is not set ++# CONFIG_SATA_VIA is not set ++# CONFIG_SATA_VITESSE is not set ++# CONFIG_SATA_INIC162X is not set ++# CONFIG_PATA_ALI is not set ++# CONFIG_PATA_AMD is not set ++# CONFIG_PATA_ARTOP is not set ++# CONFIG_PATA_ATIIXP is not set ++# CONFIG_PATA_CMD640_PCI is not set ++# CONFIG_PATA_CMD64X is not set ++# CONFIG_PATA_CS5520 is not set ++# CONFIG_PATA_CS5530 is not set ++# CONFIG_PATA_CYPRESS is not set ++# CONFIG_PATA_EFAR is not set ++# CONFIG_ATA_GENERIC is not set ++# CONFIG_PATA_HPT366 is not set ++# CONFIG_PATA_HPT37X is not set ++# CONFIG_PATA_HPT3X2N is not set ++# CONFIG_PATA_HPT3X3 is not set ++# CONFIG_PATA_IT821X is not set ++# CONFIG_PATA_IT8213 is not set ++# CONFIG_PATA_JMICRON is not set ++# CONFIG_PATA_TRIFLEX is not set ++# CONFIG_PATA_MARVELL is not set ++# CONFIG_PATA_MPIIX is not set ++# CONFIG_PATA_OLDPIIX is not set ++# CONFIG_PATA_NETCELL is not set ++# CONFIG_PATA_NINJA32 is not set ++# CONFIG_PATA_NS87410 is not set ++# CONFIG_PATA_NS87415 is not set ++# CONFIG_PATA_OPTI is not set ++# CONFIG_PATA_OPTIDMA is not set ++# CONFIG_PATA_PDC_OLD is not set ++# CONFIG_PATA_RADISYS is not set ++# CONFIG_PATA_RZ1000 is not set ++# CONFIG_PATA_SC1200 is not set ++# CONFIG_PATA_SERVERWORKS is not set ++# CONFIG_PATA_PDC2027X is not set ++# CONFIG_PATA_SIL680 is not set ++# CONFIG_PATA_SIS is not set ++# CONFIG_PATA_VIA is not set ++# CONFIG_PATA_WINBOND is not set ++# CONFIG_PATA_PLATFORM is not set ++# CONFIG_PATA_SCH is not set ++CONFIG_PATA_FSL=y ++CONFIG_FSL_PATA_USE_DMA=y ++# CONFIG_MD is not set ++# CONFIG_FUSION is not set ++ ++# ++# IEEE 1394 (FireWire) support ++# ++ ++# ++# Enable only one of the two stacks, unless you know what you are doing ++# ++# CONFIG_FIREWIRE is not set ++# CONFIG_IEEE1394 is not set ++# CONFIG_I2O is not set ++CONFIG_NETDEVICES=y ++# CONFIG_DUMMY is not set ++# CONFIG_BONDING is not set ++# CONFIG_MACVLAN is not set ++# CONFIG_EQUALIZER is not set ++# CONFIG_TUN is not set ++# CONFIG_VETH is not set ++# CONFIG_ARCNET is not set ++CONFIG_PHYLIB=y ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_BROADCOM5222_PHY is not set ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_NATIONAL8364x_PHY is not set ++CONFIG_NATIONAL8384x_PHY=y ++# CONFIG_MicrelKSZ8041_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_FIXED_PHY is not set ++# CONFIG_MDIO_BITBANG is not set ++CONFIG_NET_ETHERNET=y ++CONFIG_MII=y ++# CONFIG_HAPPYMEAL is not set ++# CONFIG_SUNGEM is not set ++# CONFIG_CASSINI is not set ++# CONFIG_NET_VENDOR_3COM is not set ++# CONFIG_ENC28J60 is not set ++# CONFIG_DNET is not set ++# CONFIG_NET_TULIP is not set ++# CONFIG_HP100 is not set ++# CONFIG_IBM_NEW_EMAC_ZMII is not set ++# CONFIG_IBM_NEW_EMAC_RGMII is not set ++# CONFIG_IBM_NEW_EMAC_TAH is not set ++# CONFIG_IBM_NEW_EMAC_EMAC4 is not set ++# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set ++# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set ++# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set ++CONFIG_NET_PCI=y ++# CONFIG_PCNET32 is not set ++# CONFIG_AMD8111_ETH is not set ++# CONFIG_ADAPTEC_STARFIRE is not set ++# CONFIG_B44 is not set ++# CONFIG_FORCEDETH is not set ++CONFIG_E100=y ++# CONFIG_FEALNX is not set ++# CONFIG_NATSEMI is not set ++# CONFIG_NE2K_PCI is not set ++# CONFIG_8139CP is not set ++CONFIG_8139TOO=y ++# CONFIG_8139TOO_PIO is not set ++# CONFIG_8139TOO_TUNE_TWISTER is not set ++# CONFIG_8139TOO_8129 is not set ++# CONFIG_8139_OLD_RX_RESET is not set ++# CONFIG_R6040 is not set ++# CONFIG_SIS900 is not set ++# CONFIG_EPIC100 is not set ++# CONFIG_SMSC9420 is not set ++# CONFIG_SUNDANCE is not set ++# CONFIG_TLAN is not set ++# CONFIG_VIA_RHINE is not set ++# CONFIG_SC92031 is not set ++CONFIG_FEC=y ++# CONFIG_FEC2 is not set ++# CONFIG_ATL2 is not set ++CONFIG_NETDEV_1000=y ++# CONFIG_ACENIC is not set ++# CONFIG_DL2K is not set ++CONFIG_E1000=y ++# CONFIG_E1000E is not set ++# CONFIG_IP1000 is not set ++# CONFIG_IGB is not set ++# CONFIG_NS83820 is not set ++# CONFIG_HAMACHI is not set ++# CONFIG_YELLOWFIN is not set ++# CONFIG_R8169 is not set ++# CONFIG_SIS190 is not set ++# CONFIG_SKGE is not set ++# CONFIG_SKY2 is not set ++# CONFIG_VIA_VELOCITY is not set ++# CONFIG_TIGON3 is not set ++# CONFIG_BNX2 is not set ++# CONFIG_QLA3XXX is not set ++# CONFIG_ATL1 is not set ++# CONFIG_ATL1E is not set ++# CONFIG_ATL1C is not set ++# CONFIG_JME is not set ++# CONFIG_NETDEV_10000 is not set ++# CONFIG_TR is not set ++ ++# ++# Wireless LAN ++# ++# CONFIG_WLAN_PRE80211 is not set ++# CONFIG_WLAN_80211 is not set ++# CONFIG_IWLWIFI_LEDS is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++ ++# ++# USB Network Adapters ++# ++# CONFIG_USB_CATC is not set ++# CONFIG_USB_KAWETH is not set ++# CONFIG_USB_PEGASUS is not set ++CONFIG_USB_RTL8150=y ++# CONFIG_USB_USBNET is not set ++# CONFIG_WAN is not set ++# CONFIG_FDDI is not set ++# CONFIG_HIPPI is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++# CONFIG_NET_FC is not set ++# CONFIG_NETCONSOLE is not set ++# CONFIG_NETPOLL is not set ++# CONFIG_NET_POLL_CONTROLLER is not set ++# CONFIG_ISDN is not set ++# CONFIG_PHONE is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++# CONFIG_INPUT_MOUSEDEV_PSAUX is not set ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 ++# CONFIG_INPUT_JOYDEV is not set ++CONFIG_INPUT_EVDEV=y ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++CONFIG_INPUT_KEYBOARD=y ++# CONFIG_KEYBOARD_ATKBD is not set ++# CONFIG_KEYBOARD_SUNKBD is not set ++# CONFIG_KEYBOARD_LKKBD is not set ++# CONFIG_KEYBOARD_XTKBD is not set ++# CONFIG_KEYBOARD_NEWTON is not set ++# CONFIG_KEYBOARD_STOWAWAY is not set ++# CONFIG_INPUT_MOUSE is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++# CONFIG_INPUT_TOUCHSCREEN is not set ++# CONFIG_INPUT_MISC is not set ++ ++# ++# Hardware I/O ports ++# ++CONFIG_SERIO=y ++CONFIG_SERIO_SERPORT=y ++# CONFIG_SERIO_PCIPS2 is not set ++# CONFIG_SERIO_LIBPS2 is not set ++# CONFIG_SERIO_RAW is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_VT=y ++CONFIG_CONSOLE_TRANSLATIONS=y ++CONFIG_VT_CONSOLE=y ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++CONFIG_DEVKMEM=y ++CONFIG_DEVSRAM=m ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_NOZOMI is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_COLDFIRE_IRDA is not set ++# CONFIG_SERIAL_COLDFIRE_EDMA is not set ++CONFIG_SERIAL_MCF=y ++CONFIG_SERIAL_MCF_BAUDRATE=115200 ++CONFIG_SERIAL_MCF_CONSOLE=y ++# CONFIG_SERIAL_JSM is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_GEN_RTC is not set ++# CONFIG_R3964 is not set ++# CONFIG_APPLICOM is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++CONFIG_I2C_CHARDEV=y ++CONFIG_I2C_HELPER_AUTO=y ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# PC SMBus host controller drivers ++# ++# CONFIG_I2C_ALI1535 is not set ++# CONFIG_I2C_ALI1563 is not set ++# CONFIG_I2C_ALI15X3 is not set ++# CONFIG_I2C_AMD756 is not set ++# CONFIG_I2C_AMD8111 is not set ++# CONFIG_I2C_I801 is not set ++# CONFIG_I2C_ISCH is not set ++# CONFIG_I2C_PIIX4 is not set ++# CONFIG_I2C_NFORCE2 is not set ++# CONFIG_I2C_SIS5595 is not set ++# CONFIG_I2C_SIS630 is not set ++# CONFIG_I2C_SIS96X is not set ++# CONFIG_I2C_VIA is not set ++# CONFIG_I2C_VIAPRO is not set ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++CONFIG_I2C_MCF=y ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_SIMTEC is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Graphics adapter I2C/DDC channel drivers ++# ++# CONFIG_I2C_VOODOO3 is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_STUB is not set ++ ++# ++# Miscellaneous I2C Chip support ++# ++# CONFIG_DS1682 is not set ++# CONFIG_SENSORS_PCF8574 is not set ++# CONFIG_PCF8575 is not set ++# CONFIG_SENSORS_PCA9539 is not set ++# CONFIG_SENSORS_PCF8591 is not set ++# CONFIG_SENSORS_MAX6875 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++# CONFIG_I2C_DEBUG_CHIP is not set ++CONFIG_SPI=y ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_BITBANG is not set ++CONFIG_SPI_DSPI=y ++CONFIG_SPI_COLDFIRE_DSPI_EDMA=y ++# CONFIG_VOIP_FXS is not set ++# CONFIG_VOIP_FXO is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_W1 is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++# CONFIG_THERMAL_HWMON is not set ++CONFIG_WATCHDOG=y ++# CONFIG_WATCHDOG_NOWAYOUT is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_ALIM7101_WDT is not set ++CONFIG_COLDFIRE_WATCHDOG=y ++ ++# ++# PCI-based Watchdog Cards ++# ++# CONFIG_PCIPCWATCHDOG is not set ++# CONFIG_WDTPCI is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_REGULATOR is not set ++ ++# ++# Multimedia devices ++# ++ ++# ++# Multimedia core support ++# ++# CONFIG_VIDEO_DEV is not set ++# CONFIG_DVB_CORE is not set ++# CONFIG_VIDEO_MEDIA is not set ++ ++# ++# Multimedia drivers ++# ++CONFIG_DAB=y ++# CONFIG_USB_DABUSB is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++# CONFIG_VGASTATE is not set ++CONFIG_VIDEO_OUTPUT_CONTROL=m ++# CONFIG_FB is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++ ++# ++# Display device support ++# ++# CONFIG_DISPLAY_SUPPORT is not set ++ ++# ++# Console display driver support ++# ++CONFIG_DUMMY_CONSOLE=y ++CONFIG_SOUND=y ++CONFIG_SOUND_OSS_CORE=y ++CONFIG_SND=y ++CONFIG_SND_TIMER=y ++CONFIG_SND_PCM=y ++# CONFIG_SND_SEQUENCER is not set ++CONFIG_SND_OSSEMUL=y ++# CONFIG_SND_MIXER_OSS is not set ++CONFIG_SND_PCM_OSS=y ++CONFIG_SND_PCM_OSS_PLUGINS=y ++# CONFIG_SND_HRTIMER is not set ++# CONFIG_SND_DYNAMIC_MINORS is not set ++CONFIG_SND_SUPPORT_OLD_API=y ++CONFIG_SND_VERBOSE_PROCFS=y ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++CONFIG_SND_DRIVERS=y ++# CONFIG_SND_DUMMY is not set ++# CONFIG_SND_MTPAV is not set ++# CONFIG_SND_SERIAL_U16550 is not set ++# CONFIG_SND_MPU401 is not set ++CONFIG_SND_PCI=y ++# CONFIG_SND_AD1889 is not set ++# CONFIG_SND_ALS300 is not set ++# CONFIG_SND_ALI5451 is not set ++# CONFIG_SND_ATIIXP is not set ++# CONFIG_SND_ATIIXP_MODEM is not set ++# CONFIG_SND_AU8810 is not set ++# CONFIG_SND_AU8820 is not set ++# CONFIG_SND_AU8830 is not set ++# CONFIG_SND_AW2 is not set ++# CONFIG_SND_AZT3328 is not set ++# CONFIG_SND_BT87X is not set ++# CONFIG_SND_CA0106 is not set ++# CONFIG_SND_CMIPCI is not set ++# CONFIG_SND_OXYGEN is not set ++# CONFIG_SND_CS4281 is not set ++# CONFIG_SND_CS46XX is not set ++# CONFIG_SND_DARLA20 is not set ++# CONFIG_SND_GINA20 is not set ++# CONFIG_SND_LAYLA20 is not set ++# CONFIG_SND_DARLA24 is not set ++# CONFIG_SND_GINA24 is not set ++# CONFIG_SND_LAYLA24 is not set ++# CONFIG_SND_MONA is not set ++# CONFIG_SND_MIA is not set ++# CONFIG_SND_ECHO3G is not set ++# CONFIG_SND_INDIGO is not set ++# CONFIG_SND_INDIGOIO is not set ++# CONFIG_SND_INDIGODJ is not set ++# CONFIG_SND_EMU10K1 is not set ++# CONFIG_SND_EMU10K1X is not set ++# CONFIG_SND_ENS1370 is not set ++# CONFIG_SND_ENS1371 is not set ++# CONFIG_SND_ES1938 is not set ++# CONFIG_SND_ES1968 is not set ++# CONFIG_SND_FM801 is not set ++# CONFIG_SND_HDA_INTEL is not set ++# CONFIG_SND_HDSP is not set ++# CONFIG_SND_HDSPM is not set ++# CONFIG_SND_HIFIER is not set ++# CONFIG_SND_ICE1712 is not set ++# CONFIG_SND_ICE1724 is not set ++# CONFIG_SND_INTEL8X0 is not set ++# CONFIG_SND_INTEL8X0M is not set ++# CONFIG_SND_KORG1212 is not set ++# CONFIG_SND_MAESTRO3 is not set ++# CONFIG_SND_MIXART is not set ++# CONFIG_SND_NM256 is not set ++# CONFIG_SND_PCXHR is not set ++# CONFIG_SND_RIPTIDE is not set ++# CONFIG_SND_RME32 is not set ++# CONFIG_SND_RME96 is not set ++# CONFIG_SND_RME9652 is not set ++# CONFIG_SND_SONICVIBES is not set ++# CONFIG_SND_TRIDENT is not set ++# CONFIG_SND_VIA82XX is not set ++# CONFIG_SND_VIA82XX_MODEM is not set ++# CONFIG_SND_VIRTUOSO is not set ++# CONFIG_SND_VX222 is not set ++# CONFIG_SND_YMFPCI is not set ++ ++# ++# ALSA for Coldfire ++# ++CONFIG_SND_COLDFIRE=y ++CONFIG_SND_SPI=y ++CONFIG_SND_USB=y ++# CONFIG_SND_USB_AUDIO is not set ++# CONFIG_SND_USB_CAIAQ is not set ++# CONFIG_SND_SOC is not set ++# CONFIG_SOUND_PRIME is not set ++CONFIG_HID_SUPPORT=y ++CONFIG_HID=y ++CONFIG_HID_DEBUG=y ++# CONFIG_HIDRAW is not set ++ ++# ++# USB Input Devices ++# ++CONFIG_USB_HID=y ++# CONFIG_HID_PID is not set ++# CONFIG_USB_HIDDEV is not set ++ ++# ++# Special HID drivers ++# ++CONFIG_HID_COMPAT=y ++# CONFIG_HID_A4TECH is not set ++# CONFIG_HID_APPLE is not set ++# CONFIG_HID_BELKIN is not set ++# CONFIG_HID_CHERRY is not set ++# CONFIG_HID_CHICONY is not set ++# CONFIG_HID_CYPRESS is not set ++# CONFIG_HID_EZKEY is not set ++# CONFIG_HID_GYRATION is not set ++# CONFIG_HID_LOGITECH is not set ++# CONFIG_HID_MICROSOFT is not set ++# CONFIG_HID_MONTEREY is not set ++# CONFIG_HID_NTRIG is not set ++# CONFIG_HID_PANTHERLORD is not set ++# CONFIG_HID_PETALYNX is not set ++# CONFIG_HID_SAMSUNG is not set ++# CONFIG_HID_SONY is not set ++# CONFIG_HID_SUNPLUS is not set ++# CONFIG_GREENASIA_FF is not set ++# CONFIG_HID_TOPSEED is not set ++# CONFIG_THRUSTMASTER_FF is not set ++# CONFIG_ZEROPLUS_FF is not set ++CONFIG_USB_SUPPORT=y ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB_ARCH_HAS_OHCI=y ++CONFIG_USB_ARCH_HAS_EHCI=y ++CONFIG_USB=y ++# CONFIG_USB_DEBUG is not set ++# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEVICEFS=y ++# CONFIG_USB_DEVICE_CLASS is not set ++# CONFIG_USB_DYNAMIC_MINORS is not set ++CONFIG_USB_SUSPEND=y ++CONFIG_USB_OTG=y ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++# CONFIG_USB_EHCI_TT_NEWSCHED is not set ++CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y ++CONFIG_USB_EHCI_BIG_ENDIAN_DESC=y ++CONFIG_USB_EHCI_FSL=y ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1760_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_UHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_WHCI_HCD is not set ++# CONFIG_USB_HWA_HCD is not set ++CONFIG_USB_M5445X_ULPI=y ++# CONFIG_USB_M5445X_FSLS is not set ++# CONFIG_USB_M5441X_ULPI is not set ++# CONFIG_USB_M5441X_FSLS is not set ++# CONFIG_USB_GADGET_MUSB_HDRC is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; ++# ++ ++# ++# see USB_STORAGE Help for more information ++# ++CONFIG_USB_STORAGE=y ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_LIBUSUAL is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_BERRY_CHARGE is not set ++# CONFIG_USB_LED is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_PHIDGET is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_VST is not set ++CONFIG_USB_GADGET=m ++# CONFIG_USB_GADGET_DEBUG_FILES is not set ++CONFIG_USB_GADGET_VBUS_DRAW=2 ++CONFIG_USB_GADGET_SELECTED=y ++# CONFIG_USB_GADGET_AT91 is not set ++# CONFIG_USB_GADGET_ATMEL_USBA is not set ++CONFIG_USB_GADGET_FSL_USB2=y ++CONFIG_USB_FSL_USB2=m ++# CONFIG_USB_GADGET_LH7A40X is not set ++# CONFIG_USB_GADGET_OMAP is not set ++# CONFIG_USB_GADGET_PXA25X is not set ++# CONFIG_USB_GADGET_PXA27X is not set ++# CONFIG_USB_GADGET_S3C2410 is not set ++# CONFIG_USB_GADGET_IMX is not set ++# CONFIG_USB_GADGET_M66592 is not set ++# CONFIG_USB_GADGET_AMD5536UDC is not set ++# CONFIG_USB_GADGET_FSL_QE is not set ++# CONFIG_USB_GADGET_CI13XXX is not set ++# CONFIG_USB_GADGET_NET2280 is not set ++# CONFIG_USB_GADGET_GOKU is not set ++# CONFIG_USB_GADGET_DUMMY_HCD is not set ++CONFIG_USB_GADGET_DUALSPEED=y ++# CONFIG_USB_ZERO is not set ++CONFIG_USB_ETH=m ++CONFIG_USB_ETH_RNDIS=y ++# CONFIG_USB_GADGETFS is not set ++CONFIG_USB_FILE_STORAGE=m ++# CONFIG_USB_FILE_STORAGE_TEST is not set ++# CONFIG_USB_G_SERIAL is not set ++# CONFIG_USB_MIDI_GADGET is not set ++# CONFIG_USB_G_PRINTER is not set ++# CONFIG_USB_CDC_COMPOSITE is not set ++ ++# ++# OTG and related infrastructure ++# ++# CONFIG_UWB is not set ++# CONFIG_MMC is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++# CONFIG_INFINIBAND is not set ++# CONFIG_RTC_CLASS is not set ++CONFIG_DMADEVICES=y ++ ++# ++# DMA Devices ++# ++CONFIG_COLDFIRE_EDMA=y ++CONFIG_COLDFIRE_EDMA_TEST=m ++# CONFIG_UIO is not set ++# CONFIG_STAGING is not set ++ ++# ++# Character devices ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++CONFIG_GENERIC_CLOCKEVENTS_BUILD=y ++ ++# ++# File systems ++# ++CONFIG_EXT2_FS=y ++# CONFIG_EXT2_FS_XATTR is not set ++# CONFIG_EXT2_FS_XIP is not set ++CONFIG_EXT3_FS=y ++CONFIG_EXT3_FS_XATTR=y ++# CONFIG_EXT3_FS_POSIX_ACL is not set ++# CONFIG_EXT3_FS_SECURITY is not set ++# CONFIG_EXT4_FS is not set ++CONFIG_JBD=y ++CONFIG_FS_MBCACHE=y ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_FS_POSIX_ACL is not set ++CONFIG_FILE_LOCKING=y ++# CONFIG_XFS_FS is not set ++# CONFIG_GFS2_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_QUOTA is not set ++# CONFIG_AUTOFS_FS is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=y ++CONFIG_MSDOS_FS=y ++CONFIG_VFAT_FS=y ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++CONFIG_NTFS_FS=y ++# CONFIG_NTFS_DEBUG is not set ++CONFIG_NTFS_RW=y ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++# CONFIG_PROC_KCORE is not set ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++# CONFIG_TMPFS_POSIX_ACL is not set ++# CONFIG_HUGETLB_PAGE is not set ++# CONFIG_CONFIGFS_FS is not set ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++CONFIG_JFFS2_FS_WRITEBUFFER=y ++# CONFIG_JFFS2_FS_WBUF_VERIFY is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++# CONFIG_CRAMFS is not set ++# CONFIG_SQUASHFS is not set ++# CONFIG_VXFS_FS is not set ++CONFIG_MINIX_FS=y ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=y ++CONFIG_NFS_V3=y ++# CONFIG_NFS_V3_ACL is not set ++# CONFIG_NFS_V4 is not set ++CONFIG_ROOT_NFS=y ++# CONFIG_NFSD is not set ++CONFIG_LOCKD=y ++CONFIG_LOCKD_V4=y ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=y ++# CONFIG_SUNRPC_REGISTER_V4 is not set ++# CONFIG_RPCSEC_GSS_KRB5 is not set ++# CONFIG_RPCSEC_GSS_SPKM3 is not set ++# CONFIG_SMB_FS is not set ++# CONFIG_CIFS is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++ ++# ++# Partition Types ++# ++CONFIG_PARTITION_ADVANCED=y ++# CONFIG_ACORN_PARTITION is not set ++# CONFIG_OSF_PARTITION is not set ++# CONFIG_AMIGA_PARTITION is not set ++# CONFIG_ATARI_PARTITION is not set ++# CONFIG_MAC_PARTITION is not set ++CONFIG_MSDOS_PARTITION=y ++# CONFIG_BSD_DISKLABEL is not set ++# CONFIG_MINIX_SUBPARTITION is not set ++# CONFIG_SOLARIS_X86_PARTITION is not set ++# CONFIG_UNIXWARE_DISKLABEL is not set ++# CONFIG_LDM_PARTITION is not set ++# CONFIG_SGI_PARTITION is not set ++# CONFIG_ULTRIX_PARTITION is not set ++# CONFIG_SUN_PARTITION is not set ++# CONFIG_KARMA_PARTITION is not set ++# CONFIG_EFI_PARTITION is not set ++# CONFIG_SYSV68_PARTITION is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++CONFIG_NLS_UTF8=y ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++# CONFIG_ENABLE_MUST_CHECK is not set ++CONFIG_FRAME_WARN=1024 ++# CONFIG_MAGIC_SYSRQ is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_DEBUG_FS is not set ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_KERNEL is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_RCU_CPU_STALL_DETECTOR is not set ++# CONFIG_SYSCTL_SYSCALL_CHECK is not set ++ ++# ++# Tracers ++# ++# CONFIG_DYNAMIC_PRINTK_DEBUG is not set ++# CONFIG_SAMPLES is not set ++# CONFIG_BOOTPARAM is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++# CONFIG_SECURITY_FILE_CAPABILITIES is not set ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++# CONFIG_CRYPTO_FIPS is not set ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_GF128MUL is not set ++# CONFIG_CRYPTO_NULL is not set ++# CONFIG_CRYPTO_CRYPTD is not set ++CONFIG_CRYPTO_AUTHENC=y ++CONFIG_CRYPTO_TEST=m ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_SEQIV is not set ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++# CONFIG_CRYPTO_CTR is not set ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++CONFIG_CRYPTO_PCBC=m ++# CONFIG_CRYPTO_XTS is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++ ++# ++# Digest ++# ++CONFIG_CRYPTO_CRC32C=y ++# CONFIG_CRYPTO_MD4 is not set ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++CONFIG_CRYPTO_SHA1=y ++# CONFIG_CRYPTO_SHA256 is not set ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++# CONFIG_CRYPTO_DEFLATE is not set ++# CONFIG_CRYPTO_LZO is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++ ++# ++# OCF Configuration ++# ++ ++# ++# Talitos Driver ++# ++CONFIG_CRYPTO_HW=y ++CONFIG_CRYPTO_DEV_MCFCAU=y ++CONFIG_CRYPTO_DEV_MCFCAU_DES=y ++CONFIG_CRYPTO_DEV_MCFCAU_AES=y ++CONFIG_CRYPTO_DEV_MCFCAU_MD5=y ++CONFIG_CRYPTO_DEV_MCFCAU_SHA1=y ++# CONFIG_CRYPTO_DEV_HIFN_795X is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_GENERIC_FIND_LAST_BIT=y ++CONFIG_CRC_CCITT=y ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC7 is not set ++CONFIG_LIBCRC32C=y ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_PLIST=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT=y ++CONFIG_HAS_DMA=y +--- /dev/null ++++ b/arch/m68k/include/asm/cf_5445x_cacheflush.h +@@ -0,0 +1,534 @@ ++/* ++ * include/asm-m68k/cf_5445x_cacheflush.h - Coldfire 5445x Cache ++ * ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * Kurt Mahan kmahan@freescale.com ++ * ++ * Based on include/asm-m68k/cacheflush.h ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++#ifndef M68K_CF_5445x_CACHEFLUSH_H ++#define M68K_CF_5445x_CACHEFLUSH_H ++ ++#include <asm/cfcache.h> ++ ++/* ++ * Coldfire Cache Model ++ * ++ * The Coldfire processors use a Harvard architecture cache configured ++ * as four-way set associative. The cache does not implement bus snooping ++ * so cache coherency with other masters must be maintained in software. ++ * ++ * The cache is managed via the CPUSHL instruction in conjunction with ++ * bits set in the CACR (cache control register). Currently the code ++ * uses the CPUSHL enhancement which adds the ability to ++ * invalidate/clear/push a cacheline by physical address. This feature ++ * is designated in the Hardware Configuration Register [D1-CPES]. ++ * ++ * CACR Bits: ++ * DPI[28] cpushl invalidate disable for d-cache ++ * IDPI[12] cpushl invalidate disable for i-cache ++ * SPA[14] cpushl search by physical address ++ * IVO[20] cpushl invalidate only ++ * ++ * Random Terminology: ++ * * invalidate = reset the cache line's valid bit ++ * * push = generate a line-sized store of the data if its contents are ++ * marked as modifed (the modified flag is cleared after ++ * the store) ++ * * clear = push + invalidate ++ */ ++ ++/** ++ * flush_icache - Flush all of the instruction cache ++ */ ++static inline void flush_icache(void) ++{ ++ asm volatile("nop\n" ++ "moveq%.l #0,%%d0\n" ++ "moveq%.l #0,%%d1\n" ++ "move%.l %%d0,%%a0\n" ++ "1:\n" ++ "cpushl %%ic,(%%a0)\n" ++ "add%.l #0x0010,%%a0\n" ++ "addq%.l #1,%%d1\n" ++ "cmpi%.l %0,%%d1\n" ++ "bne 1b\n" ++ "moveq%.l #0,%%d1\n" ++ "addq%.l #1,%%d0\n" ++ "move%.l %%d0,%%a0\n" ++ "cmpi%.l #4,%%d0\n" ++ "bne 1b\n" ++ : : "i" (CACHE_SETS) ++ : "a0", "d0", "d1"); ++} ++ ++/** ++ * flush_dcache - Flush all of the data cache ++ */ ++static inline void flush_dcache(void) ++{ ++ asm volatile("nop\n" ++ "moveq%.l #0,%%d0\n" ++ "moveq%.l #0,%%d1\n" ++ "move%.l %%d0,%%a0\n" ++ "1:\n" ++ "cpushl %%dc,(%%a0)\n" ++ "add%.l #0x0010,%%a0\n" ++ "addq%.l #1,%%d1\n" ++ "cmpi%.l %0,%%d1\n" ++ "bne 1b\n" ++ "moveq%.l #0,%%d1\n" ++ "addq%.l #1,%%d0\n" ++ "move%.l %%d0,%%a0\n" ++ "cmpi%.l #4,%%d0\n" ++ "bne 1b\n" ++ : : "i" (CACHE_SETS) ++ : "a0", "d0", "d1"); ++} ++ ++/** ++ * flush_bcache - Flush all of both caches ++ */ ++static inline void flush_bcache(void) ++{ ++ asm volatile("nop\n" ++ "moveq%.l #0,%%d0\n" ++ "moveq%.l #0,%%d1\n" ++ "move%.l %%d0,%%a0\n" ++ "1:\n" ++ "cpushl %%bc,(%%a0)\n" ++ "add%.l #0x0010,%%a0\n" ++ "addq%.l #1,%%d1\n" ++ "cmpi%.l %0,%%d1\n" ++ "bne 1b\n" ++ "moveq%.l #0,%%d1\n" ++ "addq%.l #1,%%d0\n" ++ "move%.l %%d0,%%a0\n" ++ "cmpi%.l #4,%%d0\n" ++ "bne 1b\n" ++ : : "i" (CACHE_SETS) ++ : "a0", "d0", "d1"); ++} ++ ++/** ++ * cf_cache_clear - invalidate cache ++ * @paddr: starting physical address ++ * @len: number of bytes ++ * ++ * Invalidate cache lines starting at paddr for len bytes. ++ * Those lines are not pushed. ++ */ ++static inline void cf_cache_clear(unsigned long paddr, int len) ++{ ++ /* number of lines */ ++ len = (len + (CACHE_LINE_SIZE-1)) / CACHE_LINE_SIZE; ++ if (len == 0) ++ return; ++ ++ /* align on set boundary */ ++ paddr &= 0xfffffff0; ++ ++ asm volatile("nop\n" ++ "move%.l %2,%%d0\n" ++ "or%.l %3,%%d0\n" ++ "movec %%d0,%%cacr\n" ++ "move%.l %0,%%a0\n" ++ "move%.l %1,%%d0\n" ++ "1:\n" ++ "cpushl %%bc,(%%a0)\n" ++ "lea 0x10(%%a0),%%a0\n" ++ "subq%.l #1,%%d0\n" ++ "bne%.b 1b\n" ++ "movec %2,%%cacr\n" ++ : : "a" (paddr), "r" (len), ++ "r" (shadow_cacr), ++ "i" (CF_CACR_SPA+CF_CACR_IVO) ++ : "a0", "d0"); ++} ++ ++/** ++ * cf_cache_push - Push dirty cache out with no invalidate ++ * @paddr: starting physical address ++ * @len: number of bytes ++ * ++ * Push the any dirty lines starting at paddr for len bytes. ++ * Those lines are not invalidated. ++ */ ++static inline void cf_cache_push(unsigned long paddr, int len) ++{ ++ /* number of lines */ ++ len = (len + (CACHE_LINE_SIZE-1)) / CACHE_LINE_SIZE; ++ if (len == 0) ++ return; ++ ++ /* align on set boundary */ ++ paddr &= 0xfffffff0; ++ ++ asm volatile("nop\n" ++ "move%.l %2,%%d0\n" ++ "or%.l %3,%%d0\n" ++ "movec %%d0,%%cacr\n" ++ "move%.l %0,%%a0\n" ++ "move%.l %1,%%d0\n" ++ "1:\n" ++ "cpushl %%bc,(%%a0)\n" ++ "lea 0x10(%%a0),%%a0\n" ++ "subq%.l #1,%%d0\n" ++ "bne.b 1b\n" ++ "movec %2,%%cacr\n" ++ : : "a" (paddr), "r" (len), ++ "r" (shadow_cacr), ++ "i" (CF_CACR_SPA+CF_CACR_DPI+CF_CACR_IDPI) ++ : "a0", "d0"); ++} ++ ++/** ++ * cf_cache_flush - Push dirty cache out and invalidate ++ * @paddr: starting physical address ++ * @len: number of bytes ++ * ++ * Push the any dirty lines starting at paddr for len bytes and ++ * invalidate those lines. ++ */ ++static inline void cf_cache_flush(unsigned long paddr, int len) ++{ ++ /* number of lines */ ++ len = (len + (CACHE_LINE_SIZE-1)) / CACHE_LINE_SIZE; ++ if (len == 0) ++ return; ++ ++ /* align on set boundary */ ++ paddr &= 0xfffffff0; ++ ++ asm volatile("nop\n" ++ "move%.l %2,%%d0\n" ++ "or%.l %3,%%d0\n" ++ "movec %%d0,%%cacr\n" ++ "move%.l %0,%%a0\n" ++ "move%.l %1,%%d0\n" ++ "1:\n" ++ "cpushl %%bc,(%%a0)\n" ++ "lea 0x10(%%a0),%%a0\n" ++ "subq%.l #1,%%d0\n" ++ "bne.b 1b\n" ++ "movec %2,%%cacr\n" ++ : : "a" (paddr), "r" (len), ++ "r" (shadow_cacr), ++ "i" (CF_CACR_SPA) ++ : "a0", "d0"); ++} ++ ++/** ++ * cf_cache_flush_range - Push dirty data/inst cache in range out and invalidate ++ * @vstart - starting virtual address ++ * @vend: ending virtual address ++ * ++ * Push the any dirty data/instr lines starting at paddr for len bytes and ++ * invalidate those lines. ++ */ ++static inline void cf_cache_flush_range(unsigned long vstart, ++ unsigned long vend) ++{ ++ int len; ++ ++ /* align on set boundary */ ++ vstart &= 0xfffffff0; ++ vend = PAGE_ALIGN((vend + (CACHE_LINE_SIZE-1))) & 0xfffffff0; ++ len = vend - vstart; ++ if (len == 0) ++ return; ++ vstart = __pa(vstart); ++ vend = vstart + len; ++ ++ asm volatile("nop\n" ++ "move%.l %2,%%d0\n" ++ "or%.l %3,%%d0\n" ++ "movec %%d0,%%cacr\n" ++ "move%.l %0,%%a0\n" ++ "move%.l %1,%%a1\n" ++ "1:\n" ++ "cpushl %%bc,(%%a0)\n" ++ "lea 0x10(%%a0),%%a0\n" ++ "cmpa%.l %%a0,%%a1\n" ++ "bne.b 1b\n" ++ "movec %2,%%cacr\n" ++ : /* no return */ ++ : "a" (vstart), "a" (vend), ++ "r" (shadow_cacr), ++ "i" (CF_CACR_SPA) ++ : "a0", "a1", "d0"); ++} ++ ++/** ++ * cf_dcache_flush_range - Push dirty data cache in range out and invalidate ++ * @vstart - starting virtual address ++ * @vend: ending virtual address ++ * ++ * Push/Clear the virtual range *vstart* -> *vend* using the enhanced ++ * cpushl instruction to search by physical address. ++ * ++ * Assumes CACR[IVO] is 0 ++ * CACR[DDPI] is 0 ++ * ++ * Sets CACR[SPA] to 1 for the duration of this routine ++ */ ++static inline void cf_dcache_flush_range(unsigned long vstart, ++ unsigned long vend) ++{ ++ /* align on set boundary */ ++ vstart &= 0xfffffff0; ++ vend = (vend + (CACHE_LINE_SIZE-1)) & 0xfffffff0; ++ ++ asm volatile("nop\n" ++ "move%.l %2,%%d0\n" ++ "or%.l %3,%%d0\n" ++ "movec %%d0,%%cacr\n" ++ "move%.l %0,%%a0\n" ++ "move%.l %1,%%a1\n" ++ "1:\n" ++ "cpushl %%dc,(%%a0)\n" ++ "lea 0x10(%%a0),%%a0\n" ++ "cmpa%.l %%a0,%%a1\n" ++ "bne.b 1b\n" ++ "movec %2,%%cacr\n" ++ : /* no return */ ++ : "a" (__pa(vstart)), "a" (__pa(vend)), ++ "r" (shadow_cacr), ++ "i" (CF_CACR_SPA) ++ : "a0", "a1", "d0"); ++} ++ ++/** ++ * cf_dcache_inv_range - Invalidate data cache in range ++ * @vstart - starting virtual address ++ * @vend: ending virtual address ++ * ++ * Invalidate the virtual range *vstart* -> *vend* using the enhanced ++ * cpushl instruction to search by physical address. ++ * ++ * Assumes CACR[DDPI] is 0 ++ * ++ * Sets CACR[SPA] and CACR[IVO] to 1 for the duration of this routine ++ */ ++static inline void cf_dcache_inv_range(unsigned long vstart, ++ unsigned long vend) ++{ ++ /* align on set boundary */ ++ vstart &= 0xfffffff0; ++ vend = (vend + (CACHE_LINE_SIZE-1)) & 0xfffffff0; ++ ++ asm volatile("nop\n" ++ "move%.l %2,%%d0\n" ++ "or%.l %3,%%d0\n" ++ "movec %%d0,%%cacr\n" ++ "move%.l %0,%%a0\n" ++ "move%.l %1,%%a1\n" ++ "1:\n" ++ "cpushl %%dc,(%%a0)\n" ++ "lea 0x10(%%a0),%%a0\n" ++ "cmpa%.l %%a0,%%a1\n" ++ "bne.b 1b\n" ++ "movec %2,%%cacr\n" ++ : /* no return */ ++ : "a" (__pa(vstart)), "a" (__pa(vend)), ++ "r" (shadow_cacr), ++ "i" (CF_CACR_SPA | CF_CACR_IVO) ++ : "a0", "a1", "d0"); ++} ++ ++/** ++ * cf_dcache_push_range - Push data cache in range ++ * @vstart - starting virtual address ++ * @vend: ending virtual address ++ * ++ * Push the virtual range *vstart* -> *vend* using the enhanced ++ * cpushl instruction to search by physical address. ++ * ++ * Assumes CACR[IVO] is 0 ++ * ++ * Sets CACR[SPA] and CACR[DDPI] to 1 for the duration of this routine ++ */ ++static inline void cf_dcache_push_range(unsigned long vstart, ++ unsigned long vend) ++{ ++ /* align on set boundary */ ++ vstart &= 0xfffffff0; ++ vend = (vend + (CACHE_LINE_SIZE-1)) & 0xfffffff0; ++ ++ asm volatile("nop\n" ++ "move%.l %2,%%d0\n" ++ "or%.l %3,%%d0\n" ++ "movec %%d0,%%cacr\n" ++ "move%.l %0,%%a0\n" ++ "move%.l %1,%%a1\n" ++ "1:\n" ++ "cpushl %%dc,(%%a0)\n" ++ "lea 0x10(%%a0),%%a0\n" ++ "cmpa%.l %%a0,%%a1\n" ++ "bne.b 1b\n" ++ "movec %2,%%cacr\n" ++ : /* no return */ ++ : "a" (__pa(vstart)), "a" (__pa(vend)), ++ "r" (shadow_cacr), ++ "i" (CF_CACR_SPA | CF_CACR_DPI) ++ : "a0", "a1", "d0"); ++} ++ ++/** ++ * cf_icache_flush_range - Push dirty inst cache in range out and invalidate ++ * @vstart - starting virtual address ++ * @vend: ending virtual address ++ * ++ * Push the any dirty instr lines starting at paddr for len bytes and ++ * invalidate those lines. This should just be an invalidate since you ++ * shouldn't be able to have dirty instruction cache. ++ */ ++static inline void cf_icache_flush_range(unsigned long vstart, ++ unsigned long vend) ++{ ++ /* align on set boundary */ ++ vstart &= 0xfffffff0; ++ vend = (vend + (CACHE_LINE_SIZE-1)) & 0xfffffff0; ++ ++ asm volatile("nop\n" ++ "move%.l %2,%%d0\n" ++ "or%.l %3,%%d0\n" ++ "movec %%d0,%%cacr\n" ++ "move%.l %0,%%a0\n" ++ "move%.l %1,%%a1\n" ++ "1:\n" ++ "cpushl %%ic,(%%a0)\n" ++ "lea 0x10(%%a0),%%a0\n" ++ "cmpa%.l %%a0,%%a1\n" ++ "bne.b 1b\n" ++ "movec %2,%%cacr\n" ++ : /* no return */ ++ : "a" (__pa(vstart)), "a" (__pa(vend)), ++ "r" (shadow_cacr), ++ "i" (CF_CACR_SPA) ++ : "a0", "a1", "d0"); ++} ++ ++/** ++ * flush_cache_mm - Flush an mm_struct ++ * @mm: mm_struct to flush ++ */ ++static inline void flush_cache_mm(struct mm_struct *mm) ++{ ++ if (mm == current->mm) ++ flush_bcache(); ++} ++ ++#define flush_cache_dup_mm(mm) flush_cache_mm(mm) ++ ++/** ++ * flush_cache_range - Flush a cache range ++ * @vma: vma struct ++ * @start: Starting address ++ * @end: Ending address ++ * ++ * flush_cache_range must be a macro to avoid a dependency on ++ * linux/mm.h which includes this file. ++ */ ++static inline void flush_cache_range(struct vm_area_struct *vma, ++ unsigned long start, unsigned long end) ++{ ++ if (vma->vm_mm == current->mm) ++ cf_cache_flush_range(start, end); ++} ++ ++/** ++ * flush_cache_page - Flush a page of the cache ++ * @vma: vma struct ++ * @vmaddr: ++ * @pfn: page numer ++ * ++ * flush_cache_page must be a macro to avoid a dependency on ++ * linux/mm.h which includes this file. ++ */ ++static inline void flush_cache_page(struct vm_area_struct *vma, ++ unsigned long vmaddr, unsigned long pfn) ++{ ++ if (vma->vm_mm == current->mm) ++ cf_cache_flush_range(vmaddr, vmaddr+PAGE_SIZE); ++} ++ ++/** ++ * __flush_page_to_ram - Push a page out of the cache ++ * @vaddr: Virtual address at start of page ++ * ++ * Push the page at kernel virtual address *vaddr* and clear ++ * the icache. ++ */ ++static inline void __flush_page_to_ram(void *vaddr) ++{ ++ asm volatile("nop\n" ++ "move%.l %2,%%d0\n" ++ "or%.l %3,%%d0\n" ++ "movec %%d0,%%cacr\n" ++ "move%.l %0,%%d0\n" ++ "and%.l #0xfffffff0,%%d0\n" ++ "move%.l %%d0,%%a0\n" ++ "move%.l %1,%%d0\n" ++ "1:\n" ++ "cpushl %%bc,(%%a0)\n" ++ "lea 0x10(%%a0),%%a0\n" ++ "subq%.l #1,%%d0\n" ++ "bne.b 1b\n" ++ "movec %2,%%cacr\n" ++ : : "a" (__pa(vaddr)), "i" (PAGE_SIZE / CACHE_LINE_SIZE), ++ "r" (shadow_cacr), "i" (CF_CACR_SPA) ++ : "a0", "d0"); ++} ++ ++/* ++ * Various defines for the kernel. ++ */ ++ ++extern void cache_clear(unsigned long paddr, int len); ++extern void cache_push(unsigned long paddr, int len); ++extern void flush_icache_range(unsigned long address, unsigned long endaddr); ++ ++#define flush_cache_all() flush_bcache() ++#define flush_cache_vmap(start, end) flush_bcache() ++#define flush_cache_vunmap(start, end) flush_bcache() ++ ++#define flush_dcache_range(vstart, vend) \ ++ cf_dcache_flush_range(vstart, vend) ++#define flush_dcache_page(page) \ ++ __flush_page_to_ram(page_address(page)) ++#define flush_dcache_mmap_lock(mapping) do { } while (0) ++#define flush_dcache_mmap_unlock(mapping) do { } while (0) ++ ++#define flush_icache_page(vma, page) \ ++ __flush_page_to_ram(page_address(page)) ++ ++/** ++ * copy_to_user_page - Copy memory to user page ++ */ ++static inline void copy_to_user_page(struct vm_area_struct *vma, ++ struct page *page, unsigned long vaddr, ++ void *dst, void *src, int len) ++{ ++ memcpy(dst, src, len); ++ cf_cache_flush(page_to_phys(page), PAGE_SIZE); ++} ++ ++/** ++ * copy_from_user_page - Copy memory from user page ++ */ ++static inline void copy_from_user_page(struct vm_area_struct *vma, ++ struct page *page, unsigned long vaddr, ++ void *dst, void *src, int len) ++{ ++ cf_cache_flush(page_to_phys(page), PAGE_SIZE); ++ memcpy(dst, src, len); ++} ++ ++#endif /* M68K_CF_5445x_CACHEFLUSH_H */ +--- /dev/null ++++ b/arch/m68k/include/asm/mcf5445x_ccm.h +@@ -0,0 +1,206 @@ ++/* ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * Matt Waddel Matt.Waddel@freescale.com ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#ifndef __MCF5445X_CCM_H__ ++#define __MCF5445X_CCM_H__ ++ ++/********************************************************************* ++* ++* Chip Configuration Module (CCM) ++* ++*********************************************************************/ ++ ++/* Register read/write macros */ ++/* Chip Configuration Register (Read-only) (256 or 360 TEPBGA) */ ++#define MCF_CCM_CCR MCF_REG16(0xFC0A0004) ++/* Reset Configuration (Read-only) (256 or 360 TEPBGA) */ ++#define MCF_CCM_RCON MCF_REG16(0xFC0A0008) ++/* Chip Identification Register (Read-only) */ ++#define MCF_CCM_CIR MCF_REG16(0xFC0A000A) ++/* Miscellaneous Control Register */ ++#define MCF_CCM_MISCCR MCF_REG16(0xFC0A0010) ++#define MCF_CCM_CDR MCF_REG16(0xFC0A0012) /* Clock Divider Register */ ++/* USB On-the-Go Controller Status Register */ ++#define MCF_CCM_UOCSR MCF_REG16(0xFC0A0014) ++/* Serial Boot Facility Status Register (Read Only) */ ++#define MCF_CCM_SBFSR MCF_REG16(0xFC0A0018) ++/* Serial Boot Facility Control Register */ ++#define MCF_CCM_SBFCR MCF_REG16(0xFC0A0020) ++ ++/* Bit definitions and macros for CCR_360 */ ++/* 2-Bit PLL clock mode */ ++#define MCF_CCM_CCR_360_PLLMULT2(x) (((x) & 0x0003)) ++/* PCI pad slew rate mode */ ++#define MCF_CCM_CCR_360_PCISLEW (0x0004) ++#define MCF_CCM_CCR_360_PCIMODE (0x0008) /* PCI host/agent mode */ ++#define MCF_CCM_CCR_360_PLLMODE (0x0010) /* PLL Mode */ ++/* Flexbus/PCI port size configuration */ ++#define MCF_CCM_CCR_360_FBCONFIG(x) (((x) & 0x0007) << 5) ++/* 3-Bit PLL Clock Mode */ ++#define MCF_CCM_CCR_360_PLLMULT3(x) (((x) & 0x0007)) ++#define MCF_CCM_CCR_360_OSCMODE (0x0008) /* Oscillator Clock Mode */ ++#define MCF_CCM_CCR_360_FBCONFIG_MASK (0x00E0) ++#define MCF_CCM_CCR_360_PLLMULT2_MASK (0x0003) ++#define MCF_CCM_CCR_360_PLLMULT3_MASK (0x0007) ++#define MCF_CCM_CCR_360_FBCONFIG_NM_NP_32 (0x0000) ++#define MCF_CCM_CCR_360_FBCONFIG_NM_NP_8 (0x0020) ++#define MCF_CCM_CCR_360_FBCONFIG_NM_NP_16 (0x0040) ++#define MCF_CCM_CCR_360_FBCONFIG_M_P_16 (0x0060) ++#define MCF_CCM_CCR_360_FBCONFIG_M_NP_32 (0x0080) ++#define MCF_CCM_CCR_360_FBCONFIG_M_NP_8 (0x00A0) ++#define MCF_CCM_CCR_360_FBCONFIG_M_NP_16 (0x00C0) ++#define MCF_CCM_CCR_360_FBCONFIG_M_P_8 (0x00E0) ++#define MCF_CCM_CCR_360_PLLMULT2_12X (0x0000) ++#define MCF_CCM_CCR_360_PLLMULT2_6X (0x0001) ++#define MCF_CCM_CCR_360_PLLMULT2_16X (0x0002) ++#define MCF_CCM_CCR_360_PLLMULT2_8X (0x0003) ++#define MCF_CCM_CCR_360_PLLMULT3_20X (0x0000) ++#define MCF_CCM_CCR_360_PLLMULT3_10X (0x0001) ++#define MCF_CCM_CCR_360_PLLMULT3_24X (0x0002) ++#define MCF_CCM_CCR_360_PLLMULT3_18X (0x0003) ++#define MCF_CCM_CCR_360_PLLMULT3_12X (0x0004) ++#define MCF_CCM_CCR_360_PLLMULT3_6X (0x0005) ++#define MCF_CCM_CCR_360_PLLMULT3_16X (0x0006) ++#define MCF_CCM_CCR_360_PLLMULT3_8X (0x0007) ++ ++/* Bit definitions and macros for CCR_256 */ ++/* 3-Bit PLL clock mode */ ++#define MCF_CCM_CCR_256_PLLMULT3(x) (((x) & 0x0007)) ++/* Oscillator clock mode */ ++#define MCF_CCM_CCR_256_OSCMODE (0x0008) ++#define MCF_CCM_CCR_256_PLLMODE (0x0010) /* PLL Mode */ ++/* Flexbus/PCI port size configuration */ ++#define MCF_CCM_CCR_256_FBCONFIG(x) (((x) & 0x0007) << 5) ++#define MCF_CCM_CCR_256_FBCONFIG_MASK (0x00E0) ++#define MCF_CCM_CCR_256_FBCONFIG_NM_32 (0x0000) ++#define MCF_CCM_CCR_256_FBCONFIG_NM_8 (0x0020) ++#define MCF_CCM_CCR_256_FBCONFIG_NM_16 (0x0040) ++#define MCF_CCM_CCR_256_FBCONFIG_M_32 (0x0080) ++#define MCF_CCM_CCR_256_FBCONFIG_M_8 (0x00A0) ++#define MCF_CCM_CCR_256_FBCONFIG_M_16 (0x00C0) ++#define MCF_CCM_CCR_256_PLLMULT3_MASK (0x0007) ++#define MCF_CCM_CCR_256_PLLMULT3_20X (0x0000) ++#define MCF_CCM_CCR_256_PLLMULT3_10X (0x0001) ++#define MCF_CCM_CCR_256_PLLMULT3_24X (0x0002) ++#define MCF_CCM_CCR_256_PLLMULT3_18X (0x0003) ++#define MCF_CCM_CCR_256_PLLMULT3_12X (0x0004) ++#define MCF_CCM_CCR_256_PLLMULT3_6X (0x0005) ++#define MCF_CCM_CCR_256_PLLMULT3_16X (0x0006) ++#define MCF_CCM_CCR_256_PLLMULT3_8X (0x0007) ++ ++/* Bit definitions and macros for RCON_360 */ ++#define MCF_CCM_RCON_360_PLLMULT(x) (((x)&0x0003)) /* PLL clock mode */ ++#define MCF_CCM_RCON_360_PCISLEW (0x0004) /* PCI pad slew rate mode */ ++#define MCF_CCM_RCON_360_PCIMODE (0x0008) /* PCI host/agent mode */ ++#define MCF_CCM_RCON_360_PLLMODE (0x0010) /* PLL Mode */ ++/* Flexbus/PCI port size configuration */ ++#define MCF_CCM_RCON_360_FBCONFIG(x) (((x) & 0x0007) << 5) ++ ++/* Bit definitions and macros for RCON_256 */ ++#define MCF_CCM_RCON_256_PLLMULT(x) (((x) & 0x0007)) /* PLL clock mode */ ++#define MCF_CCM_RCON_256_OSCMODE (0x0008) /* Oscillator clock mode */ ++#define MCF_CCM_RCON_256_PLLMODE (0x0010) /* PLL Mode */ ++/* Flexbus/PCI port size configuration */ ++#define MCF_CCM_RCON_256_FBCONFIG(x) (((x) & 0x0007) << 5) ++ ++/* Bit definitions and macros for CIR */ ++/* Part revision number */ ++#define MCF_CCM_CIR_PRN(x) (((x) & 0x003F)) ++/* Part identification number */ ++#define MCF_CCM_CIR_PIN(x) (((x) & 0x03FF) << 6) ++#define MCF_CCM_CIR_PIN_MASK (0xFFC0) ++#define MCF_CCM_CIR_PRN_MASK (0x003F) ++#define MCF_CCM_CIR_PIN_MCF54450 (0x4F << 6) ++#define MCF_CCM_CIR_PIN_MCF54451 (0x4D << 6) ++#define MCF_CCM_CIR_PIN_MCF54452 (0x4B << 6) ++#define MCF_CCM_CIR_PIN_MCF54453 (0x49 << 6) ++#define MCF_CCM_CIR_PIN_MCF54454 (0x4A << 6) ++#define MCF_CCM_CIR_PIN_MCF54455 (0x48 << 6) ++ ++/* Bit definitions and macros for MISCCR */ ++/* USB clock source */ ++#define MCF_CCM_MISCCR_USBSRC (0x0001) ++/* USB VBUS over-current sense polarity */ ++#define MCF_CCM_MISCCR_USBOC (0x0002) ++/* USB transceiver pull-up enable */ ++#define MCF_CCM_MISCCR_USBPUE (0x0004) ++/* SSI clock source */ ++#define MCF_CCM_MISCCR_SSI_SRC (0x0010) ++/* Timer DMA mux selection */ ++#define MCF_CCM_MISCCR_TIM_DMA (0x0020) ++/* SSI RXD/TXD pull select */ ++#define MCF_CCM_MISCCR_SSI_PUS (0x0040) ++/* SSI RXD/TXD pull enable */ ++#define MCF_CCM_MISCCR_SSI_PUE (0x0080) ++/* Bus monitor timing field */ ++#define MCF_CCM_MISCCR_BMT(x) (((x) & 0x0007) << 8) ++/* Bus monitor external enable bit */ ++#define MCF_CCM_MISCCR_BME (0x0800) ++/* Limp mode enable */ ++#define MCF_CCM_MISCCR_LIMP (0x1000) ++#define MCF_CCM_MISCCR_BMT_65536 (0 << 8) ++#define MCF_CCM_MISCCR_BMT_32768 (1 << 8) ++#define MCF_CCM_MISCCR_BMT_16384 (2 << 8) ++#define MCF_CCM_MISCCR_BMT_8192 (3 << 8) ++#define MCF_CCM_MISCCR_BMT_4096 (4 << 8) ++#define MCF_CCM_MISCCR_BMT_2048 (5 << 8) ++#define MCF_CCM_MISCCR_BMT_1024 (6 << 8) ++#define MCF_CCM_MISCCR_BMT_512 (7 << 8) ++#define MCF_CCM_MISCCR_SSIPUE_UP (1 << 7) ++#define MCF_CCM_MISCCR_SSIPUE_DOWN (0 << 7) ++#define MCF_CCM_MISCCR_SSIPUS_UP (1 << 6) ++#define MCF_CCM_MISCCR_SSIPUS_DOWN (0 << 6) ++#define MCF_CCM_MISCCR_TIMDMA_TIM (1 << 5) ++#define MCF_CCM_MISCCR_TIMDMA_SSI (0 << 5) ++#define MCF_CCM_MISCCR_SSISRC_CLKIN (0 << 4) ++#define MCF_CCM_MISCCR_SSISRC_PLL (1 << 4) ++#define MCF_CCM_MISCCR_USBOC_ACTHI (0 << 1) ++#define MCF_CCM_MISCCR_USBOC_ACTLO (1 << 1) ++#define MCF_CCM_MISCCR_USBSRC_CLKIN (0) ++#define MCF_CCM_MISCCR_USBSRC_PLL (1) ++ ++/* Bit definitions and macros for CDR */ ++/* SSI oversampling clock divider */ ++#define MCF_CCM_CDR_SSIDIV(x) (((x) & 0x00FF)) ++/* Low power clock divider */ ++#define MCF_CCM_CDR_LPDIV(x) (((x) & 0x000F) << 8) ++ ++/* Bit definitions and macros for UOCSR */ ++/* On-chip transceiver pull-down enable */ ++#define MCF_CCM_UOCSR_XPDE (0x0001) ++/* USB OTG misc interrupt enable */ ++#define MCF_CCM_UOCSR_UOMIE (0x0002) ++/* USB OTG controller wake-up event */ ++#define MCF_CCM_UOCSR_WKUP (0x0004) ++/* VBUS power fault */ ++#define MCF_CCM_UOCSR_PWRFLT (0x0008) ++/* Session end */ ++#define MCF_CCM_UOCSR_SEND (0x0010) ++/* VBUS valid indicator */ ++#define MCF_CCM_UOCSR_VVLD (0x0020) ++/* B-peripheral valid indicator */ ++#define MCF_CCM_UOCSR_BVLD (0x0040) ++/* A-peripheral valid indicator */ ++#define MCF_CCM_UOCSR_AVLD (0x0080) ++/* D+ pull-up for FS enabled (read-only) */ ++#define MCF_CCM_UOCSR_DPPU (0x0100) ++/* VBUS discharge resistor enabled (read-only) */ ++#define MCF_CCM_UOCSR_DCR_VBUS (0x0200) ++/* VBUS charge resistor enabled (read-only) */ ++#define MCF_CCM_UOCSR_CRG_VBUS (0x0400) ++/* D- 15Kohm pull-down (read-only) */ ++#define MCF_CCM_UOCSR_DMPD (0x1000) ++/* D+ 15Kohm pull-down (read-only) */ ++#define MCF_CCM_UOCSR_DPPD (0x2000) ++ ++/********************************************************************/ ++ ++#endif /* __MCF5445X_CCM_H__ */ +--- /dev/null ++++ b/arch/m68k/include/asm/mcf5445x_dspi.h +@@ -0,0 +1,665 @@ ++/* ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * Yaroslav Vinogradov yaroslav.vinogradov@freescale.com ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#ifndef __MCF5445X_DSPI_H__ ++#define __MCF5445X_DSPI_H__ ++ ++/********************************************************************* ++* ++* DMA Serial Peripheral Interface (DSPI) ++* ++*********************************************************************/ ++ ++/* Register read/write macros */ ++/* DSPI Module Configuration Register */ ++#define MCF_DSPI_DMCR MCF_REG32(0xFC05C000) ++/* DSPI Transfer Count Register */ ++#define MCF_DSPI_DTCR MCF_REG32(0xFC05C008) ++/* DSPI Clock and Transfer Attributes Register */ ++#define MCF_DSPI_DCTAR0 MCF_REG32(0xFC05C00C) ++/* DSPI Clock and Transfer Attributes Register */ ++#define MCF_DSPI_DCTAR1 MCF_REG32(0xFC05C010) ++/* DSPI Clock and Transfer Attributes Register */ ++#define MCF_DSPI_DCTAR2 MCF_REG32(0xFC05C014) ++/* DSPI Clock and Transfer Attributes Register */ ++#define MCF_DSPI_DCTAR3 MCF_REG32(0xFC05C018) ++/* DSPI Clock and Transfer Attributes Register */ ++#define MCF_DSPI_DCTAR4 MCF_REG32(0xFC05C01C) ++/* DSPI Clock and Transfer Attributes Register */ ++#define MCF_DSPI_DCTAR5 MCF_REG32(0xFC05C020) ++/* DSPI Clock and Transfer Attributes Register */ ++#define MCF_DSPI_DCTAR6 MCF_REG32(0xFC05C024) ++/* DSPI Clock and Transfer Attributes Register */ ++#define MCF_DSPI_DCTAR7 MCF_REG32(0xFC05C028 ++/* DSPI Status Register */ ++#define MCF_DSPI_DSR MCF_REG32(0xFC05C02C) ++/* DSPI DMA/Interrupt Request Select and Enable Register */ ++#define MCF_DSPI_DRSER MCF_REG32(0xFC05C030) ++/* DSPI Transmit FIFO Register */ ++#define MCF_DSPI_DTFR MCF_REG32(0xFC05C034) ++/* DSPI Receive FIFO Register */ ++#define MCF_DSPI_DRFR MCF_REG32(0xFC05C038) ++/* DSPI Transmit FIFO Debugging Registers */ ++#define MCF_DSPI_DTFDR0 MCF_REG32(0xFC05C03C) ++/* DSPI Transmit FIFO Debugging Registers */ ++#define MCF_DSPI_DTFDR1 MCF_REG32(0xFC05C040) ++/* DSPI Transmit FIFO Debugging Registers */ ++#define MCF_DSPI_DTFDR2 MCF_REG32(0xFC05C044) ++/* DSPI Transmit FIFO Debugging Registers */ ++#define MCF_DSPI_DTFDR3 MCF_REG32(0xFC05C048) ++/* DSPI Receive FIFO Debugging Registers */ ++#define MCF_DSPI_DRFDR0 MCF_REG32(0xFC05C07C) ++/* DSPI Receive FIFO Debugging Registers */ ++#define MCF_DSPI_DRFDR1 MCF_REG32(0xFC05C080) ++/* DSPI Receive FIFO Debugging Registers */ ++#define MCF_DSPI_DRFDR2 MCF_REG32(0xFC05C084) ++/* DSPI Receive FIFO Debugging Registers */ ++#define MCF_DSPI_DRFDR3 MCF_REG32(0xFC05C088) ++ ++ ++/* Parameterized register read/write macros for multiple registers */ ++/* DSPI Clock and Transfer Attributes Register */ ++#define MCF_DSPI_DCTAR(x) MCF_REG32(0xFC05C00C+((x)*0x004)) ++/* DSPI Transmit FIFO Debugging Registers */ ++#define MCF_DSPI_DTFDR(x) MCF_REG32(0xFC05C03C+((x)*0x004)) ++/* DSPI Receive FIFO Debugging Registers */ ++#define MCF_DSPI_DRFDR(x) MCF_REG32(0xFC05C07C+((x)*0x004)) ++ ++/* Bit definitions and macros for DMCR */ ++/* Halt -- stops and starts DSPI transfers */ ++#define MCF_DSPI_DMCR_HALT (0x00000001) ++/* Sample point selection */ ++#define MCF_DSPI_DMCR_SMPLPT(x) (((x)&0x00000003)<<8) ++/* Clear receive FIFO */ ++#define MCF_DSPI_DMCR_CLRRXF (0x00000400) ++/* Clear transmit FIFO */ ++#define MCF_DSPI_DMCR_CLRTXF (0x00000800) ++/* Disable receive FIFO */ ++#define MCF_DSPI_DMCR_DISRXF (0x00001000) ++/* Disable transmit FIFO */ ++#define MCF_DSPI_DMCR_DISTXF (0x00002000) ++/* Module Disable */ ++#define MCF_DSPI_DMCR_MDIS (0x00004000) ++/* Peripheral chip-select 0 inactive state */ ++#define MCF_DSPI_DMCR_PCSIS0 (0x00010000) ++/* Peripheral chip-select 1 inactive state */ ++#define MCF_DSPI_DMCR_PCSIS1 (0x00020000) ++/* Peripheral chip-select 2 inactive state */ ++#define MCF_DSPI_DMCR_PCSIS2 (0x00040000) ++/* Peripheral chip-select 3 inactive state */ ++#define MCF_DSPI_DMCR_PCSIS3 (0x00080000) ++/* Peripheral chip-select 4 inactive state */ ++#define MCF_DSPI_DMCR_PCSIS4 (0x00100000) ++/* Peripheral chip-select 5 inactive state */ ++#define MCF_DSPI_DMCR_PCSIS5 (0x00200000) ++/* Peripheral chip-select 6 inactive state */ ++#define MCF_DSPI_DMCR_PCSIS6 (0x00400000) ++/* Peripheral chip-select 7 inactive state */ ++#define MCF_DSPI_DMCR_PCSIS7 (0x00800000) ++/* Receive FIFO overflow overwrite enable */ ++#define MCF_DSPI_DMCR_ROOE (0x01000000) ++/* Peripheral chip select strobe enable */ ++#define MCF_DSPI_DMCR_PCSSE (0x02000000) ++/* Modified timing format enable */ ++#define MCF_DSPI_DMCR_MTFE (0x04000000) ++/* Freeze */ ++#define MCF_DSPI_DMCR_FRZ (0x08000000) ++/* DSPI configuration */ ++#define MCF_DSPI_DMCR_DCONF(x) (((x)&0x00000003)<<28) ++/* Continuous SCK enable */ ++#define MCF_DSPI_DMCR_CONT_SCKE (0x40000000) ++/* Master/Slave mode select */ ++#define MCF_DSPI_DMCR_MSTR (0x80000000) ++#define MCF_DSPI_DMCR_DCONF_SPI (0x00000000) ++#define MCF_DSPI_DMCR_PCSIS7_LOW (0x00000000) ++#define MCF_DSPI_DMCR_PCSIS7_HIGH (0x00800000) ++#define MCF_DSPI_DMCR_PCSIS6_LOW (0x00000000) ++#define MCF_DSPI_DMCR_PCSIS6_HIGH (0x00400000) ++#define MCF_DSPI_DMCR_PCSIS5_LOW (0x00000000) ++#define MCF_DSPI_DMCR_PCSIS5_HIGH (0x00200000) ++#define MCF_DSPI_DMCR_PCSIS4_LOW (0x00000000) ++#define MCF_DSPI_DMCR_PCSIS4_HIGH (0x00100000) ++#define MCF_DSPI_DMCR_PCSIS3_LOW (0x00000000) ++#define MCF_DSPI_DMCR_PCSIS3_HIGH (0x00080000) ++#define MCF_DSPI_DMCR_PCSIS2_LOW (0x00000000) ++#define MCF_DSPI_DMCR_PCSIS2_HIGH (0x00040000) ++#define MCF_DSPI_DMCR_PCSIS1_LOW (0x00000000) ++#define MCF_DSPI_DMCR_PCSIS1_HIGH (0x00020000) ++#define MCF_DSPI_DMCR_PCSIS0_LOW (0x00000000) ++#define MCF_DSPI_DMCR_PCSIS0_HIGH (0x00010000) ++ ++/* Bit definitions and macros for DTCR */ ++/* SPI transfer count */ ++#define MCF_DSPI_DTCR_SPI_TCNT(x) (((x)&0x0000FFFF)<<16) ++ ++/* Bit definitions and macros for DCTAR group */ ++/* Baud rate scaler */ ++#define MCF_DSPI_DCTAR_BR(x) (((x)&0x0000000F)) ++/* Delay after transfer scaler */ ++#define MCF_DSPI_DCTAR_DT(x) (((x)&0x0000000F)<<4) ++/* After SCK delay scaler */ ++#define MCF_DSPI_DCTAR_ASC(x) (((x)&0x0000000F)<<8) ++/* PCS to SCK delay scaler */ ++#define MCF_DSPI_DCTAR_CSSCK(x) (((x)&0x0000000F)<<12) ++/* Baud rate prescaler */ ++#define MCF_DSPI_DCTAR_PBR(x) (((x)&0x00000003)<<16) ++/* Delay after transfer prescaler */ ++#define MCF_DSPI_DCTAR_PDT(x) (((x)&0x00000003)<<18) ++/* After SCK delay prescaler */ ++#define MCF_DSPI_DCTAR_PASC(x) (((x)&0x00000003)<<20) ++/* PCS to SCK delay prescaler */ ++#define MCF_DSPI_DCTAR_PCSSCK(x) (((x)&0x00000003)<<22) ++/* LSB first enable */ ++#define MCF_DSPI_DCTAR_LSBFE (0x01000000) ++/* Clock phase */ ++#define MCF_DSPI_DCTAR_CPHA (0x02000000) ++/* Clock polarity */ ++#define MCF_DSPI_DCTAR_CPOL (0x04000000) ++/* Frame size */ ++#define MCF_DSPI_DCTAR_FMSZ(x) (((x)&0x0000000F)<<27) ++/* Double baud rate */ ++#define MCF_DSPI_DCTAR_DBR (0x80000000) ++#define MCF_DSPI_DCTAR_CPOL_LOW (0x00000000) ++#define MCF_DSPI_DCTAR_CPOL_HIGH (0x04000000) ++#define MCF_DSPI_DCTAR_CPHA_LATCH_RISING (0x00000000) ++#define MCF_DSPI_DCTAR_CPHA_LATCH_FALLING (0x02000000) ++#define MCF_DSPI_DCTAR_PCSSCK_1CLK (0x00000000) ++#define MCF_DSPI_DCTAR_PCSSCK_3CLK (0x00400000) ++#define MCF_DSPI_DCTAR_PCSSCK_5CLK (0x00800000) ++#define MCF_DSPI_DCTAR_PCSSCK_7CLK (0x00C00000) ++#define MCF_DSPI_DCTAR_PASC_1CLK (0x00000000) ++#define MCF_DSPI_DCTAR_PASC_3CLK (0x00100000) ++#define MCF_DSPI_DCTAR_PASC_5CLK (0x00200000) ++#define MCF_DSPI_DCTAR_PASC_7CLK (0x00300000) ++#define MCF_DSPI_DCTAR_PDT_1CLK (0x00000000) ++#define MCF_DSPI_DCTAR_PDT_3CLK (0x00040000) ++#define MCF_DSPI_DCTAR_PDT_5CLK (0x00080000) ++#define MCF_DSPI_DCTAR_PDT_7CLK (0x000C0000) ++#define MCF_DSPI_DCTAR_PBR_2CLK (0x00000000) ++#define MCF_DSPI_DCTAR_PBR_3CLK (0x00010000) ++#define MCF_DSPI_DCTAR_PBR_5CLK (0x00020000) ++#define MCF_DSPI_DCTAR_PBR_7CLK (0x00030000) ++ ++/* Bit definitions and macros for DCTAR0 */ ++/* Baud rate scaler */ ++#define MCF_DSPI_DCTAR0_BR(x) (((x)&0x0000000F)) ++/* Delay after transfer scaler */ ++#define MCF_DSPI_DCTAR0_DT(x) (((x)&0x0000000F)<<4) ++/* After SCK delay scaler */ ++#define MCF_DSPI_DCTAR0_ASC(x) (((x)&0x0000000F)<<8) ++/* PCS to SCK delay scaler */ ++#define MCF_DSPI_DCTAR0_CSSCK(x) (((x)&0x0000000F)<<12) ++/* Baud rate prescaler */ ++#define MCF_DSPI_DCTAR0_PBR(x) (((x)&0x00000003)<<16) ++/* Delay after transfer prescaler */ ++#define MCF_DSPI_DCTAR0_PDT(x) (((x)&0x00000003)<<18) ++/* After SCK delay prescaler */ ++#define MCF_DSPI_DCTAR0_PASC(x) (((x)&0x00000003)<<20) ++/* PCS to SCK delay prescaler */ ++#define MCF_DSPI_DCTAR0_PCSSCK(x) (((x)&0x00000003)<<22) ++/* LSB first enable */ ++#define MCF_DSPI_DCTAR0_LSBFE (0x01000000) ++/* Clock phase */ ++#define MCF_DSPI_DCTAR0_CPHA (0x02000000) ++/* Clock polarity */ ++#define MCF_DSPI_DCTAR0_CPOL (0x04000000) ++/* Frame size */ ++#define MCF_DSPI_DCTAR0_FMSZ(x) (((x)&0x0000000F)<<27) ++/* Double baud rate */ ++#define MCF_DSPI_DCTAR0_DBR (0x80000000) ++#define MCF_DSPI_DCTAR0_CPOL_LOW (0x00000000) ++#define MCF_DSPI_DCTAR0_CPOL_HIGH (0x04000000) ++#define MCF_DSPI_DCTAR0_CPHA_LATCH_RISING (0x00000000) ++#define MCF_DSPI_DCTAR0_CPHA_LATCH_FALLING (0x02000000) ++#define MCF_DSPI_DCTAR0_PCSSCK_1CLK (0x00000000) ++#define MCF_DSPI_DCTAR0_PCSSCK_3CLK (0x00400000) ++#define MCF_DSPI_DCTAR0_PCSSCK_5CLK (0x00800000) ++#define MCF_DSPI_DCTAR0_PCSSCK_7CLK (0x00C00000) ++#define MCF_DSPI_DCTAR0_PASC_1CLK (0x00000000) ++#define MCF_DSPI_DCTAR0_PASC_3CLK (0x00100000) ++#define MCF_DSPI_DCTAR0_PASC_5CLK (0x00200000) ++#define MCF_DSPI_DCTAR0_PASC_7CLK (0x00300000) ++#define MCF_DSPI_DCTAR0_PDT_1CLK (0x00000000) ++#define MCF_DSPI_DCTAR0_PDT_3CLK (0x00040000) ++#define MCF_DSPI_DCTAR0_PDT_5CLK (0x00080000) ++#define MCF_DSPI_DCTAR0_PDT_7CLK (0x000C0000) ++#define MCF_DSPI_DCTAR0_PBR_2CLK (0x00000000) ++#define MCF_DSPI_DCTAR0_PBR_3CLK (0x00010000) ++#define MCF_DSPI_DCTAR0_PBR_5CLK (0x00020000) ++#define MCF_DSPI_DCTAR0_PBR_7CLK (0x00030000) ++ ++/* Bit definitions and macros for DCTAR1 */ ++/* Baud rate scaler */ ++#define MCF_DSPI_DCTAR1_BR(x) (((x)&0x0000000F)) ++/* Delay after transfer scaler */ ++#define MCF_DSPI_DCTAR1_DT(x) (((x)&0x0000000F)<<4) ++/* After SCK delay scaler */ ++#define MCF_DSPI_DCTAR1_ASC(x) (((x)&0x0000000F)<<8) ++/* PCS to SCK delay scaler */ ++#define MCF_DSPI_DCTAR1_CSSCK(x) (((x)&0x0000000F)<<12) ++/* Baud rate prescaler */ ++#define MCF_DSPI_DCTAR1_PBR(x) (((x)&0x00000003)<<16) ++/* Delay after transfer prescaler */ ++#define MCF_DSPI_DCTAR1_PDT(x) (((x)&0x00000003)<<18) ++/* After SCK delay prescaler */ ++#define MCF_DSPI_DCTAR1_PASC(x) (((x)&0x00000003)<<20) ++/* PCS to SCK delay prescaler */ ++#define MCF_DSPI_DCTAR1_PCSSCK(x) (((x)&0x00000003)<<22) ++/* LSB first enable */ ++#define MCF_DSPI_DCTAR1_LSBFE (0x01000000) ++/* Clock phase */ ++#define MCF_DSPI_DCTAR1_CPHA (0x02000000) ++/* Clock polarity */ ++#define MCF_DSPI_DCTAR1_CPOL (0x04000000) ++/* Frame size */ ++#define MCF_DSPI_DCTAR1_FMSZ(x) (((x)&0x0000000F)<<27) ++/* Double baud rate */ ++#define MCF_DSPI_DCTAR1_DBR (0x80000000) ++ ++ ++/* Bit definitions and macros for DCTAR2 */ ++/* Baud rate scaler */ ++#define MCF_DSPI_DCTAR2_BR(x) (((x)&0x0000000F)) ++/* Delay after transfer scaler */ ++#define MCF_DSPI_DCTAR2_DT(x) (((x)&0x0000000F)<<4) ++/* After SCK delay scaler */ ++#define MCF_DSPI_DCTAR2_ASC(x) (((x)&0x0000000F)<<8) ++/* PCS to SCK delay scaler */ ++#define MCF_DSPI_DCTAR2_CSSCK(x) (((x)&0x0000000F)<<12) ++/* Baud rate prescaler */ ++#define MCF_DSPI_DCTAR2_PBR(x) (((x)&0x00000003)<<16) ++/* Delay after transfer prescaler */ ++#define MCF_DSPI_DCTAR2_PDT(x) (((x)&0x00000003)<<18) ++/* After SCK delay prescaler */ ++#define MCF_DSPI_DCTAR2_PASC(x) (((x)&0x00000003)<<20) ++/* PCS to SCK delay prescaler */ ++#define MCF_DSPI_DCTAR2_PCSSCK(x) (((x)&0x00000003)<<22) ++/* LSB first enable */ ++#define MCF_DSPI_DCTAR2_LSBFE (0x01000000) ++/* Clock phase */ ++#define MCF_DSPI_DCTAR2_CPHA (0x02000000) ++/* Clock polarity */ ++#define MCF_DSPI_DCTAR2_CPOL (0x04000000) ++/* Frame size */ ++#define MCF_DSPI_DCTAR2_FMSZ(x) (((x)&0x0000000F)<<27) ++/* Double baud rate */ ++#define MCF_DSPI_DCTAR2_DBR (0x80000000) ++ ++/* Bit definitions and macros for DCTAR3 */ ++/* Baud rate scaler */ ++#define MCF_DSPI_DCTAR3_BR(x) (((x)&0x0000000F)) ++/* Delay after transfer scaler */ ++#define MCF_DSPI_DCTAR3_DT(x) (((x)&0x0000000F)<<4) ++/* After SCK delay scaler */ ++#define MCF_DSPI_DCTAR3_ASC(x) (((x)&0x0000000F)<<8) ++/* PCS to SCK delay scaler */ ++#define MCF_DSPI_DCTAR3_CSSCK(x) (((x)&0x0000000F)<<12) ++/* Baud rate prescaler */ ++#define MCF_DSPI_DCTAR3_PBR(x) (((x)&0x00000003)<<16) ++/* Delay after transfer prescaler */ ++#define MCF_DSPI_DCTAR3_PDT(x) (((x)&0x00000003)<<18) ++/* After SCK delay prescaler */ ++#define MCF_DSPI_DCTAR3_PASC(x) (((x)&0x00000003)<<20) ++/* PCS to SCK delay prescaler */ ++#define MCF_DSPI_DCTAR3_PCSSCK(x) (((x)&0x00000003)<<22) ++/* LSB first enable */ ++#define MCF_DSPI_DCTAR3_LSBFE (0x01000000) ++/* Clock phase */ ++#define MCF_DSPI_DCTAR3_CPHA (0x02000000) ++/* Clock polarity */ ++#define MCF_DSPI_DCTAR3_CPOL (0x04000000) ++/* Frame size */ ++#define MCF_DSPI_DCTAR3_FMSZ(x) (((x)&0x0000000F)<<27) ++/* Double baud rate */ ++#define MCF_DSPI_DCTAR3_DBR (0x80000000) ++ ++/* Bit definitions and macros for DCTAR4 */ ++/* Baud rate scaler */ ++#define MCF_DSPI_DCTAR4_BR(x) (((x)&0x0000000F)) ++/* Delay after transfer scaler */ ++#define MCF_DSPI_DCTAR4_DT(x) (((x)&0x0000000F)<<4) ++/* After SCK delay scaler */ ++#define MCF_DSPI_DCTAR4_ASC(x) (((x)&0x0000000F)<<8) ++/* PCS to SCK delay scaler */ ++#define MCF_DSPI_DCTAR4_CSSCK(x) (((x)&0x0000000F)<<12) ++/* Baud rate prescaler */ ++#define MCF_DSPI_DCTAR4_PBR(x) (((x)&0x00000003)<<16) ++/* Delay after transfer prescaler */ ++#define MCF_DSPI_DCTAR4_PDT(x) (((x)&0x00000003)<<18) ++/* After SCK delay prescaler */ ++#define MCF_DSPI_DCTAR4_PASC(x) (((x)&0x00000003)<<20) ++/* PCS to SCK delay prescaler */ ++#define MCF_DSPI_DCTAR4_PCSSCK(x) (((x)&0x00000003)<<22) ++/* LSB first enable */ ++#define MCF_DSPI_DCTAR4_LSBFE (0x01000000) ++/* Clock phase */ ++#define MCF_DSPI_DCTAR4_CPHA (0x02000000) ++/* Clock polarity */ ++#define MCF_DSPI_DCTAR4_CPOL (0x04000000) ++/* Frame size */ ++#define MCF_DSPI_DCTAR4_FMSZ(x) (((x)&0x0000000F)<<27) ++/* Double baud rate */ ++#define MCF_DSPI_DCTAR4_DBR (0x80000000) ++ ++/* Bit definitions and macros for DCTAR5 */ ++/* Baud rate scaler */ ++#define MCF_DSPI_DCTAR5_BR(x) (((x)&0x0000000F)) ++/* Delay after transfer scaler */ ++#define MCF_DSPI_DCTAR5_DT(x) (((x)&0x0000000F)<<4) ++/* After SCK delay scaler */ ++#define MCF_DSPI_DCTAR5_ASC(x) (((x)&0x0000000F)<<8) ++/* PCS to SCK delay scaler */ ++#define MCF_DSPI_DCTAR5_CSSCK(x) (((x)&0x0000000F)<<12) ++/* Baud rate prescaler */ ++#define MCF_DSPI_DCTAR5_PBR(x) (((x)&0x00000003)<<16) ++/* Delay after transfer prescaler */ ++#define MCF_DSPI_DCTAR5_PDT(x) (((x)&0x00000003)<<18) ++/* After SCK delay prescaler */ ++#define MCF_DSPI_DCTAR5_PASC(x) (((x)&0x00000003)<<20) ++/* PCS to SCK delay prescaler */ ++#define MCF_DSPI_DCTAR5_PCSSCK(x) (((x)&0x00000003)<<22) ++/* LSB first enable */ ++#define MCF_DSPI_DCTAR5_LSBFE (0x01000000) ++/* Clock phase */ ++#define MCF_DSPI_DCTAR5_CPHA (0x02000000) ++/* Clock polarity */ ++#define MCF_DSPI_DCTAR5_CPOL (0x04000000) ++/* Frame size */ ++#define MCF_DSPI_DCTAR5_FMSZ(x) (((x)&0x0000000F)<<27) ++/* Double baud rate */ ++#define MCF_DSPI_DCTAR5_DBR (0x80000000) ++ ++/* Bit definitions and macros for DCTAR6 */ ++/* Baud rate scaler */ ++#define MCF_DSPI_DCTAR6_BR(x) (((x)&0x0000000F)) ++/* Delay after transfer scaler */ ++#define MCF_DSPI_DCTAR6_DT(x) (((x)&0x0000000F)<<4) ++/* After SCK delay scaler */ ++#define MCF_DSPI_DCTAR6_ASC(x) (((x)&0x0000000F)<<8) ++/* PCS to SCK delay scaler */ ++#define MCF_DSPI_DCTAR6_CSSCK(x) (((x)&0x0000000F)<<12) ++/* Baud rate prescaler */ ++#define MCF_DSPI_DCTAR6_PBR(x) (((x)&0x00000003)<<16) ++/* Delay after transfer prescaler */ ++#define MCF_DSPI_DCTAR6_PDT(x) (((x)&0x00000003)<<18) ++/* After SCK delay prescaler */ ++#define MCF_DSPI_DCTAR6_PASC(x) (((x)&0x00000003)<<20) ++/* PCS to SCK delay prescaler */ ++#define MCF_DSPI_DCTAR6_PCSSCK(x) (((x)&0x00000003)<<22) ++/* LSB first enable */ ++#define MCF_DSPI_DCTAR6_LSBFE (0x01000000) ++/* Clock phase */ ++#define MCF_DSPI_DCTAR6_CPHA (0x02000000) ++/* Clock polarity */ ++#define MCF_DSPI_DCTAR6_CPOL (0x04000000) ++/* Frame size */ ++#define MCF_DSPI_DCTAR6_FMSZ(x) (((x)&0x0000000F)<<27) ++/* Double baud rate */ ++#define MCF_DSPI_DCTAR6_DBR (0x80000000) ++ ++/* Bit definitions and macros for DCTAR7 */ ++/* Baud rate scaler */ ++#define MCF_DSPI_DCTAR7_BR(x) (((x)&0x0000000F)) ++/* Delay after transfer scaler */ ++#define MCF_DSPI_DCTAR7_DT(x) (((x)&0x0000000F)<<4) ++/* After SCK delay scaler */ ++#define MCF_DSPI_DCTAR7_ASC(x) (((x)&0x0000000F)<<8) ++/* PCS to SCK delay scaler */ ++#define MCF_DSPI_DCTAR7_CSSCK(x) (((x)&0x0000000F)<<12) ++/* Baud rate prescaler */ ++#define MCF_DSPI_DCTAR7_PBR(x) (((x)&0x00000003)<<16) ++/* Delay after transfer prescaler */ ++#define MCF_DSPI_DCTAR7_PDT(x) (((x)&0x00000003)<<18) ++/* After SCK delay prescaler */ ++#define MCF_DSPI_DCTAR7_PASC(x) (((x)&0x00000003)<<20) ++/* PCS to SCK delay prescaler */ ++#define MCF_DSPI_DCTAR7_PCSSCK(x) (((x)&0x00000003)<<22) ++/* LSB first enable */ ++#define MCF_DSPI_DCTAR7_LSBFE (0x01000000) ++/* Clock phase */ ++#define MCF_DSPI_DCTAR7_CPHA (0x02000000) ++/* Clock polarity */ ++#define MCF_DSPI_DCTAR7_CPOL (0x04000000) ++/* Frame size */ ++#define MCF_DSPI_DCTAR7_FMSZ(x) (((x)&0x0000000F)<<27) ++/* Double baud rate */ ++#define MCF_DSPI_DCTAR7_DBR (0x80000000) ++ ++/* Bit definitions and macros for DSR */ ++/* Receive next pointer */ ++#define MCF_DSPI_DSR_RXPTR(x) (((x)&0x0000000F)) ++/* Receive FIFO counter */ ++#define MCF_DSPI_DSR_RXCTR(x) (((x)&0x0000000F)<<4) ++/* Transmit next pointer */ ++#define MCF_DSPI_DSR_TXPTR(x) (((x)&0x0000000F)<<8) ++/* Transmit FIFO counter */ ++#define MCF_DSPI_DSR_TXCTR(x) (((x)&0x0000000F)<<12) ++/* Receive FIFO drain flag */ ++#define MCF_DSPI_DSR_RFDF (0x00020000) ++/* Receive FIFO overflow flag */ ++#define MCF_DSPI_DSR_RFOF (0x00080000) ++/* Transmit FIFO fill flag */ ++#define MCF_DSPI_DSR_TFFF (0x02000000) ++/* Transmit FIFO underflow flag */ ++#define MCF_DSPI_DSR_TFUF (0x08000000) ++/* End of queue flag */ ++#define MCF_DSPI_DSR_EOQF (0x10000000) ++/* Tx and Rx status (enabled | disabled) */ ++#define MCF_DSPI_DSR_TXRXS (0x40000000) ++/* Transfer complete flag */ ++#define MCF_DSPI_DSR_TCF (0x80000000) ++ ++/* Bit definitions and macros for DRSER */ ++/* Receive FIFO drain DMA or interrupt select */ ++#define MCF_DSPI_DRSER_RFDFS (0x00010000) ++/* Receive FIFO drain request enable */ ++#define MCF_DSPI_DRSER_RFDFE (0x00020000) ++/* Receive FIFO overflow request enable */ ++#define MCF_DSPI_DRSER_RFOFE (0x00080000) ++/* Transmit FIFO fill DMA or interrupt select */ ++#define MCF_DSPI_DRSER_TFFFS (0x01000000) ++/* Transmit FIFO fill request enable */ ++#define MCF_DSPI_DRSER_TFFFE (0x02000000) ++/* Transmit FIFO underflow request enable */ ++#define MCF_DSPI_DRSER_TFUFE (0x08000000) ++/* DSPI finished request enable */ ++#define MCF_DSPI_DRSER_EOQFE (0x10000000) ++/* Transmission complete request enable */ ++#define MCF_DSPI_DRSER_TCFE (0x80000000) ++ ++/* Bit definitions and macros for DTFR */ ++/* Transmit data */ ++#define MCF_DSPI_DTFR_TXDATA(x) (((x)&0x0000FFFF)) ++/* Peripheral chip select 0 */ ++#define MCF_DSPI_DTFR_PCS0 (0x00010000) ++/* Peripheral chip select 1 */ ++#define MCF_DSPI_DTFR_PCS1 (0x00020000) ++/* Peripheral chip select 2 */ ++#define MCF_DSPI_DTFR_PCS2 (0x00040000) ++/* Peripheral chip select 3 */ ++#define MCF_DSPI_DTFR_PCS3 (0x00080000) ++/* Peripheral chip select 4 */ ++#define MCF_DSPI_DTFR_PCS4 (0x00100000) ++/* Peripheral chip select 5 */ ++#define MCF_DSPI_DTFR_PCS5 (0x00200000) ++/* Peripheral chip select 6 */ ++#define MCF_DSPI_DTFR_PCS6 (0x00400000) ++/* Peripheral chip select 7 */ ++#define MCF_DSPI_DTFR_PCS7 (0x00800000) ++/* Clear SPI transfer counter */ ++#define MCF_DSPI_DTFR_CTCNT (0x04000000) ++/* End of queue */ ++#define MCF_DSPI_DTFR_EOQ (0x08000000) ++/* Clock and transfer attributes select */ ++#define MCF_DSPI_DTFR_CTAS(x) (((x)&0x00000007)<<28) ++/* Continuous peripheral chip-select enable */ ++#define MCF_DSPI_DTFR_CONT (0x80000000) ++ ++/* Bit definitions and macros for DRFR */ ++/* Receive data */ ++#define MCF_DSPI_DRFR_RXDATA(x) (((x)&0x0000FFFF)) ++ ++/* Bit definitions and macros for DTFDR group */ ++/* Transmit data */ ++#define MCF_DSPI_DTFDR_TXDATA(x) (((x)&0x0000FFFF)) ++/* Peripheral chip select 0 */ ++#define MCF_DSPI_DTFDR_PCS0 (0x00010000) ++/* Peripheral chip select 0 */ ++#define MCF_DSPI_DTFDR_PCS1 (0x00020000) ++/* Peripheral chip select 0 */ ++#define MCF_DSPI_DTFDR_PCS2 (0x00040000) ++/* Peripheral chip select 0 */ ++#define MCF_DSPI_DTFDR_PCS3 (0x00080000) ++/* Peripheral chip select 0 */ ++#define MCF_DSPI_DTFDR_PCS4 (0x00100000) ++/* Peripheral chip select 0 */ ++#define MCF_DSPI_DTFDR_PCS5 (0x00200000) ++/* Peripheral chip select 0 */ ++#define MCF_DSPI_DTFDR_PCS6 (0x00400000) ++/* Peripheral chip select 0 */ ++#define MCF_DSPI_DTFDR_PCS7 (0x00800000) ++/* Clear SPI transfer counter */ ++#define MCF_DSPI_DTFDR_CTCNT (0x04000000) ++/* End of queue */ ++#define MCF_DSPI_DTFDR_EOQ (0x08000000) ++/* Clock and transfer attributes select */ ++#define MCF_DSPI_DTFDR_CTAS(x) (((x)&0x00000007)<<28) ++/* Continuous peripheral chip-select enable */ ++#define MCF_DSPI_DTFDR_CONT (0x80000000) ++ ++/* Bit definitions and macros for DTFDR0 */ ++/* Transmit data */ ++#define MCF_DSPI_DTFDR0_TXDATA(x) (((x)&0x0000FFFF)) ++/* Peripheral chip select 0 */ ++#define MCF_DSPI_DTFDR0_PCS0 (0x00010000) ++/* Peripheral chip select 0 */ ++#define MCF_DSPI_DTFDR0_PCS1 (0x00020000) ++/* Peripheral chip select 0 */ ++#define MCF_DSPI_DTFDR0_PCS2 (0x00040000) ++/* Peripheral chip select 0 */ ++#define MCF_DSPI_DTFDR0_PCS3 (0x00080000) ++/* Peripheral chip select 0 */ ++#define MCF_DSPI_DTFDR0_PCS4 (0x00100000) ++/* Peripheral chip select 0 */ ++#define MCF_DSPI_DTFDR0_PCS5 (0x00200000) ++/* Peripheral chip select 0 */ ++#define MCF_DSPI_DTFDR0_PCS6 (0x00400000) ++/* Peripheral chip select 0 */ ++#define MCF_DSPI_DTFDR0_PCS7 (0x00800000) ++/* Clear SPI transfer counter */ ++#define MCF_DSPI_DTFDR0_CTCNT (0x04000000) ++/* End of queue */ ++#define MCF_DSPI_DTFDR0_EOQ (0x08000000) ++/* Clock and transfer attributes select */ ++#define MCF_DSPI_DTFDR0_CTAS(x) (((x)&0x00000007)<<28) ++/* Continuous peripheral chip-select enable */ ++#define MCF_DSPI_DTFDR0_CONT (0x80000000) ++/* Bit definitions and macros for DTFDR1 */ ++/* Transmit data */ ++#define MCF_DSPI_DTFDR1_TXDATA(x) (((x)&0x0000FFFF)) ++/* Peripheral chip select 0 */ ++#define MCF_DSPI_DTFDR1_PCS0 (0x00010000) ++/* Peripheral chip select 1 */ ++#define MCF_DSPI_DTFDR1_PCS1 (0x00020000) ++/* Peripheral chip select 2 */ ++#define MCF_DSPI_DTFDR1_PCS2 (0x00040000) ++/* Peripheral chip select 3 */ ++#define MCF_DSPI_DTFDR1_PCS3 (0x00080000) ++/* Peripheral chip select 4 */ ++#define MCF_DSPI_DTFDR1_PCS4 (0x00100000) ++/* Peripheral chip select 5 */ ++#define MCF_DSPI_DTFDR1_PCS5 (0x00200000) ++/* Peripheral chip select 6 */ ++#define MCF_DSPI_DTFDR1_PCS6 (0x00400000) ++/* Peripheral chip select 7 */ ++#define MCF_DSPI_DTFDR1_PCS7 (0x00800000) ++/* Clear SPI transfer counter */ ++#define MCF_DSPI_DTFDR1_CTCNT (0x04000000) ++/* End of queue */ ++#define MCF_DSPI_DTFDR1_EOQ (0x08000000) ++/* Clock and transfer attributes select */ ++#define MCF_DSPI_DTFDR1_CTAS(x) (((x)&0x00000007)<<28) ++/* Continuous peripheral chip-select enable */ ++#define MCF_DSPI_DTFDR1_CONT (0x80000000) ++ ++/* Bit definitions and macros for DTFDR2 */ ++#define MCF_DSPI_DTFDR2_TXDATA(x) (((x)&0x0000FFFF)) ++/* Peripheral chip select 0 */ ++#define MCF_DSPI_DTFDR2_PCS0 (0x00010000) ++/* Peripheral chip select 1 */ ++#define MCF_DSPI_DTFDR2_PCS1 (0x00020000) ++/* Peripheral chip select 2 */ ++#define MCF_DSPI_DTFDR2_PCS2 (0x00040000) ++/* Peripheral chip select 3 */ ++#define MCF_DSPI_DTFDR2_PCS3 (0x00080000) ++/* Peripheral chip select 4 */ ++#define MCF_DSPI_DTFDR2_PCS4 (0x00100000) ++/* Peripheral chip select 5 */ ++#define MCF_DSPI_DTFDR2_PCS5 (0x00200000) ++/* Peripheral chip select 6 */ ++#define MCF_DSPI_DTFDR2_PCS6 (0x00400000) ++/* Peripheral chip select 7 */ ++#define MCF_DSPI_DTFDR2_PCS7 (0x00800000) ++/* Clear SPI transfer counter */ ++#define MCF_DSPI_DTFDR2_CTCNT (0x04000000) ++/* End of queue */ ++#define MCF_DSPI_DTFDR2_EOQ (0x08000000) ++/* Clock and transfer attributes select */ ++#define MCF_DSPI_DTFDR2_CTAS(x) (((x)&0x00000007)<<28) ++/* Continuous peripheral chip-select enable */ ++#define MCF_DSPI_DTFDR2_CONT (0x80000000) ++ ++/* Bit definitions and macros for DTFDR3 */ ++/* Transmit data */ ++#define MCF_DSPI_DTFDR3_TXDATA(x) (((x)&0x0000FFFF)) ++/* Peripheral chip select 0 */ ++#define MCF_DSPI_DTFDR3_PCS0 (0x00010000) ++/* Peripheral chip select 1 */ ++#define MCF_DSPI_DTFDR3_PCS1 (0x00020000) ++/* Peripheral chip select 2 */ ++#define MCF_DSPI_DTFDR3_PCS2 (0x00040000) ++/* Peripheral chip select 3 */ ++#define MCF_DSPI_DTFDR3_PCS3 (0x00080000) ++/* Peripheral chip select 4 */ ++#define MCF_DSPI_DTFDR3_PCS4 (0x00100000) ++/* Peripheral chip select 5 */ ++#define MCF_DSPI_DTFDR3_PCS5 (0x00200000) ++/* Peripheral chip select 6 */ ++#define MCF_DSPI_DTFDR3_PCS6 (0x00400000) ++/* Peripheral chip select 7 */ ++#define MCF_DSPI_DTFDR3_PCS7 (0x00800000) ++/* Clear SPI transfer counter */ ++#define MCF_DSPI_DTFDR3_CTCNT (0x04000000) ++/* End of queue */ ++#define MCF_DSPI_DTFDR3_EOQ (0x08000000) ++/* Clock and transfer attributes select */ ++#define MCF_DSPI_DTFDR3_CTAS(x) (((x)&0x00000007)<<28) ++/* Continuous peripheral chip-select enable */ ++#define MCF_DSPI_DTFDR3_CONT (0x80000000) ++ ++/* Bit definitions and macros for DRFDR group */ ++#define MCF_DSPI_DRFDR_RXDATA(x) (((x)&0x0000FFFF)) ++ ++/* Bit definitions and macros for DRFDR0 */ ++#define MCF_DSPI_DRFDR0_RXDATA(x) (((x)&0x0000FFFF)) ++ ++/* Bit definitions and macros for DRFDR1 */ ++#define MCF_DSPI_DRFDR1_RXDATA(x) (((x)&0x0000FFFF)) ++ ++/* Bit definitions and macros for DRFDR2 */ ++#define MCF_DSPI_DRFDR2_RXDATA(x) (((x)&0x0000FFFF)) ++ ++/* Bit definitions and macros for DRFDR3 */ ++#define MCF_DSPI_DRFDR3_RXDATA(x) (((x)&0x0000FFFF)) ++ ++/********************************************************************/ ++ ++#endif /* __MCF5445X_DSPI_H__ */ +--- /dev/null ++++ b/arch/m68k/include/asm/mcf5445x_dtim.h +@@ -0,0 +1,96 @@ ++/* ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * Matt Waddel Matt.Waddel@freescale.com ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#ifndef __MCF5445X_DTIM_H__ ++#define __MCF5445X_DTIM_H__ ++ ++/********************************************************************* ++* ++* DMA Timers (DTIM) ++* ++*********************************************************************/ ++/* Register read/write macros */ ++#define MCF_DTIM0_DTMR 0xFC070000 /* DMA Timer Mode Register */ ++#define MCF_DTIM0_DTXMR 0xFC070002 /* DMA Timer Extended Mode Register */ ++#define MCF_DTIM0_DTER 0xFC070003 /* DMA Timer Event Register */ ++#define MCF_DTIM0_DTRR 0xFC070004 /* DMA Timer Reference Register */ ++#define MCF_DTIM0_DTCR 0xFC070008 /* DMA Timer Capture Register */ ++#define MCF_DTIM0_DTCN 0xFC07000C /* DMA Timer Counter Register */ ++#define MCF_DTIM1_DTMR 0xFC074000 /* DMA Timer Mode Register */ ++#define MCF_DTIM1_DTXMR 0xFC074002 /* DMA Timer Extended Mode Register */ ++#define MCF_DTIM1_DTER 0xFC074003 /* DMA Timer Event Register */ ++#define MCF_DTIM1_DTRR 0xFC074004 /* DMA Timer Reference Register */ ++#define MCF_DTIM1_DTCR 0xFC074008 /* DMA Timer Capture Register */ ++#define MCF_DTIM1_DTCN 0xFC07400C /* DMA Timer Counter Register */ ++#define MCF_DTIM2_DTMR 0xFC078000 /* DMA Timer Mode Register */ ++#define MCF_DTIM2_DTXMR 0xFC078002 /* DMA Timer Extended Mode Register */ ++#define MCF_DTIM2_DTER 0xFC078003 /* DMA Timer Event Register */ ++#define MCF_DTIM2_DTRR 0xFC078004 /* DMA Timer Reference Register */ ++#define MCF_DTIM2_DTCR 0xFC078008 /* DMA Timer Capture Register */ ++#define MCF_DTIM2_DTCN 0xFC07800C /* DMA Timer Counter Register */ ++#define MCF_DTIM3_DTMR 0xFC07C000 /* DMA Timer Mode Register */ ++#define MCF_DTIM3_DTXMR 0xFC07C002 /* DMA Timer Extended Mode Register */ ++#define MCF_DTIM3_DTER 0xFC07C003 /* DMA Timer Event Register */ ++#define MCF_DTIM3_DTRR 0xFC07C004 /* DMA Timer Reference Register */ ++#define MCF_DTIM3_DTCR 0xFC07C008 /* DMA Timer Capture Register */ ++#define MCF_DTIM3_DTCN 0xFC07C00C /* DMA Timer Counter Register */ ++ ++/* Parameterized register read/write macros for multiple modules */ ++/* DMA Timer Mode Register */ ++#define MCF_DTIM_DTMR(x) (0xFC070000+((x)*0x4000)) ++/* DMA Timer Extended Mode Register */ ++#define MCF_DTIM_DTXMR(x) (0xFC070002+((x)*0x4000)) ++/* DMA Timer Event Register */ ++#define MCF_DTIM_DTER(x) (0xFC070003+((x)*0x4000)) ++/* DMA Timer Reference Register */ ++#define MCF_DTIM_DTRR(x) (0xFC070004+((x)*0x4000)) ++/* DMA Timer Capture Register */ ++#define MCF_DTIM_DTCR(x) (0xFC070008+((x)*0x4000)) ++/* DMA Timer Counter Register */ ++#define MCF_DTIM_DTCN(x) (0xFC07000C+((x)*0x4000)) ++ ++/* Bit definitions and macros for DTMR */ ++#define MCF_DTIM_DTMR_RST (0x0001) /* Reset */ ++#define MCF_DTIM_DTMR_CLK(x) (((x)&0x0003)<<1) /* Input clock source */ ++#define MCF_DTIM_DTMR_FRR (0x0008) /* Free run/restart */ ++/* Output reference request/interrupt enable */ ++#define MCF_DTIM_DTMR_ORRI (0x0010) ++#define MCF_DTIM_DTMR_OM (0x0020) /* Output Mode */ ++#define MCF_DTIM_DTMR_CE(x) (((x)&0x0003)<<6) /* Capture Edge */ ++#define MCF_DTIM_DTMR_PS(x) (((x)&0x00FF)<<8) /* Prescaler value */ ++#define MCF_DTIM_DTMR_RST_EN (0x0001) ++#define MCF_DTIM_DTMR_RST_RST (0x0000) ++#define MCF_DTIM_DTMR_CE_ANY (0x00C0) ++#define MCF_DTIM_DTMR_CE_FALL (0x0080) ++#define MCF_DTIM_DTMR_CE_RISE (0x0040) ++#define MCF_DTIM_DTMR_CE_NONE (0x0000) ++#define MCF_DTIM_DTMR_CLK_DTIN (0x0006) ++#define MCF_DTIM_DTMR_CLK_DIV16 (0x0004) ++#define MCF_DTIM_DTMR_CLK_DIV1 (0x0002) ++#define MCF_DTIM_DTMR_CLK_STOP (0x0000) ++ ++/* Bit definitions and macros for DTXMR */ ++#define MCF_DTIM_DTXMR_MODE16 (0x01) /* Increment Mode */ ++#define MCF_DTIM_DTXMR_DMAEN (0x80) /* DMA request */ ++ ++/* Bit definitions and macros for DTER */ ++#define MCF_DTIM_DTER_CAP (0x01) /* Capture event */ ++#define MCF_DTIM_DTER_REF (0x02) /* Output reference event */ ++ ++/* Interrupts used for system timers */ ++#define MCFSIM_ICR_TIMER0 (0xFC048040+32) ++#define MCFSIM_ICR_TIMER1 (0xFC048040+33) ++#define MCFSIM_ICR_TIMER2 (0xFC048040+34) ++#define MCFSIM_ICR_TIMER3 (0xFC048040+35) ++ ++/********************************************************************/ ++ ++#endif /* __MCF5445X_DTIM_H__ */ +--- /dev/null ++++ b/arch/m68k/include/asm/mcf5445x_edma.h +@@ -0,0 +1,1472 @@ ++/* ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * Yaroslav Vinogradov yaroslav.vinogradov@freescale.com ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++#ifndef __MCF5445X_EDMA_H__ ++#define __MCF5445X_EDMA_H__ ++ ++/* ++ * Enhanced DMA (EDMA) ++ */ ++ ++/* Channels */ ++#define MCF_EDMA_CHAN_DREQ0 0 /* External DMA request 0 */ ++#define MCF_EDMA_CHAN_DREQ1 1 /* External DMA request 1 */ ++#define MCF_EDMA_CHAN_UART0_RX 2 /* UART0 Receive */ ++#define MCF_EDMA_CHAN_UART0_TX 3 /* UART0 Transmit */ ++#define MCF_EDMA_CHAN_UART1_RX 4 /* UART1 Receive */ ++#define MCF_EDMA_CHAN_UART1_TX 5 /* UART1 Transmit */ ++#define MCF_EDMA_CHAN_UART2_RX 6 /* UART2 Receive */ ++#define MCF_EDMA_CHAN_UART2_TX 7 /* UART2 Transmit */ ++#define MCF_EDMA_CHAN_TIMER0 8 /* Timer 0 / SSI0 Rx */ ++#define MCF_EDMA_CHAN_TIMER1 9 /* Timer 1 / SSI1 Rx */ ++#define MCF_EDMA_CHAN_TIMER2 10 /* Timer 2 / SSI0 Tx */ ++#define MCF_EDMA_CHAN_TIMER3 11 /* Timer 3 / SSI1 Tx */ ++#define MCF_EDMA_CHAN_DSPI_RX 12 /* DSPI Receive */ ++#define MCF_EDMA_CHAN_DSPI_TX 13 /* DSPI Transmit */ ++#define MCF_EDMA_CHAN_ATA_RX 14 /* ATA Receive */ ++#define MCF_EDMA_CHAN_ATA_TX 15 /* ATA Transmit */ ++ ++/* Register read/write macros */ ++#define MCF_EDMA_CR MCF_REG32(0xFC044000) ++#define MCF_EDMA_ES MCF_REG32(0xFC044004) ++#define MCF_EDMA_ERQ MCF_REG16(0xFC04400E) ++#define MCF_EDMA_EEI MCF_REG16(0xFC044016) ++#define MCF_EDMA_SERQ MCF_REG08(0xFC044018) ++#define MCF_EDMA_CERQ MCF_REG08(0xFC044019) ++#define MCF_EDMA_SEEI MCF_REG08(0xFC04401A) ++#define MCF_EDMA_CEEI MCF_REG08(0xFC04401B) ++#define MCF_EDMA_CINT MCF_REG08(0xFC04401C) ++#define MCF_EDMA_CERR MCF_REG08(0xFC04401D) ++#define MCF_EDMA_SSRT MCF_REG08(0xFC04401E) ++#define MCF_EDMA_CDNE MCF_REG08(0xFC04401F) ++#define MCF_EDMA_INTR MCF_REG16(0xFC044026) ++#define MCF_EDMA_ERR MCF_REG16(0xFC04402E) ++#define MCF_EDMA_DCHPRI0 MCF_REG08(0xFC044100) ++#define MCF_EDMA_DCHPRI1 MCF_REG08(0xFC044101) ++#define MCF_EDMA_DCHPRI2 MCF_REG08(0xFC044102) ++#define MCF_EDMA_DCHPRI3 MCF_REG08(0xFC044103) ++#define MCF_EDMA_DCHPRI4 MCF_REG08(0xFC044104) ++#define MCF_EDMA_DCHPRI5 MCF_REG08(0xFC044105) ++#define MCF_EDMA_DCHPRI6 MCF_REG08(0xFC044106) ++#define MCF_EDMA_DCHPRI7 MCF_REG08(0xFC044107) ++#define MCF_EDMA_DCHPRI8 MCF_REG08(0xFC044108) ++#define MCF_EDMA_DCHPRI9 MCF_REG08(0xFC044109) ++#define MCF_EDMA_DCHPRI10 MCF_REG08(0xFC04410A) ++#define MCF_EDMA_DCHPRI11 MCF_REG08(0xFC04410B) ++#define MCF_EDMA_DCHPRI12 MCF_REG08(0xFC04410C) ++#define MCF_EDMA_DCHPRI13 MCF_REG08(0xFC04410D) ++#define MCF_EDMA_DCHPRI14 MCF_REG08(0xFC04410E) ++#define MCF_EDMA_DCHPRI15 MCF_REG08(0xFC04410F) ++#define MCF_EDMA_TCD0_SADDR MCF_REG32(0xFC045000) ++#define MCF_EDMA_TCD0_ATTR MCF_REG16(0xFC045004) ++#define MCF_EDMA_TCD0_SOFF MCF_REG16(0xFC045006) ++#define MCF_EDMA_TCD0_NBYTES MCF_REG32(0xFC045008) ++#define MCF_EDMA_TCD0_SLAST MCF_REG32(0xFC04500C) ++#define MCF_EDMA_TCD0_DADDR MCF_REG32(0xFC045010) ++#define MCF_EDMA_TCD0_CITER_ELINK MCF_REG16(0xFC045014) ++#define MCF_EDMA_TCD0_CITER MCF_REG16(0xFC045014) ++#define MCF_EDMA_TCD0_DOFF MCF_REG16(0xFC045016) ++#define MCF_EDMA_TCD0_DLAST_SGA MCF_REG32(0xFC045018) ++#define MCF_EDMA_TCD0_BITER_ELINK MCF_REG16(0xFC04501C) ++#define MCF_EDMA_TCD0_BITER MCF_REG16(0xFC04501C) ++#define MCF_EDMA_TCD0_CSR MCF_REG16(0xFC04501E) ++#define MCF_EDMA_TCD1_SADDR MCF_REG32(0xFC045020) ++#define MCF_EDMA_TCD1_ATTR MCF_REG16(0xFC045024) ++#define MCF_EDMA_TCD1_SOFF MCF_REG16(0xFC045026) ++#define MCF_EDMA_TCD1_NBYTES MCF_REG32(0xFC045028) ++#define MCF_EDMA_TCD1_SLAST MCF_REG32(0xFC04502C) ++#define MCF_EDMA_TCD1_DADDR MCF_REG32(0xFC045030) ++#define MCF_EDMA_TCD1_CITER_ELINK MCF_REG16(0xFC045034) ++#define MCF_EDMA_TCD1_CITER MCF_REG16(0xFC045034) ++#define MCF_EDMA_TCD1_DOFF MCF_REG16(0xFC045036) ++#define MCF_EDMA_TCD1_DLAST_SGA MCF_REG32(0xFC045038) ++#define MCF_EDMA_TCD1_BITER MCF_REG16(0xFC04503C) ++#define MCF_EDMA_TCD1_BITER_ELINK MCF_REG16(0xFC04503C) ++#define MCF_EDMA_TCD1_CSR MCF_REG16(0xFC04503E) ++#define MCF_EDMA_TCD2_SADDR MCF_REG32(0xFC045040) ++#define MCF_EDMA_TCD2_ATTR MCF_REG16(0xFC045044) ++#define MCF_EDMA_TCD2_SOFF MCF_REG16(0xFC045046) ++#define MCF_EDMA_TCD2_NBYTES MCF_REG32(0xFC045048) ++#define MCF_EDMA_TCD2_SLAST MCF_REG32(0xFC04504C) ++#define MCF_EDMA_TCD2_DADDR MCF_REG32(0xFC045050) ++#define MCF_EDMA_TCD2_CITER MCF_REG16(0xFC045054) ++#define MCF_EDMA_TCD2_CITER_ELINK MCF_REG16(0xFC045054) ++#define MCF_EDMA_TCD2_DOFF MCF_REG16(0xFC045056) ++#define MCF_EDMA_TCD2_DLAST_SGA MCF_REG32(0xFC045058) ++#define MCF_EDMA_TCD2_BITER_ELINK MCF_REG16(0xFC04505C) ++#define MCF_EDMA_TCD2_BITER MCF_REG16(0xFC04505C) ++#define MCF_EDMA_TCD2_CSR MCF_REG16(0xFC04505E) ++#define MCF_EDMA_TCD3_SADDR MCF_REG32(0xFC045060) ++#define MCF_EDMA_TCD3_ATTR MCF_REG16(0xFC045064) ++#define MCF_EDMA_TCD3_SOFF MCF_REG16(0xFC045066) ++#define MCF_EDMA_TCD3_NBYTES MCF_REG32(0xFC045068) ++#define MCF_EDMA_TCD3_SLAST MCF_REG32(0xFC04506C) ++#define MCF_EDMA_TCD3_DADDR MCF_REG32(0xFC045070) ++#define MCF_EDMA_TCD3_CITER MCF_REG16(0xFC045074) ++#define MCF_EDMA_TCD3_CITER_ELINK MCF_REG16(0xFC045074) ++#define MCF_EDMA_TCD3_DOFF MCF_REG16(0xFC045076) ++#define MCF_EDMA_TCD3_DLAST_SGA MCF_REG32(0xFC045078) ++#define MCF_EDMA_TCD3_BITER_ELINK MCF_REG16(0xFC04507C) ++#define MCF_EDMA_TCD3_BITER MCF_REG16(0xFC04507C) ++#define MCF_EDMA_TCD3_CSR MCF_REG16(0xFC04507E) ++#define MCF_EDMA_TCD4_SADDR MCF_REG32(0xFC045080) ++#define MCF_EDMA_TCD4_ATTR MCF_REG16(0xFC045084) ++#define MCF_EDMA_TCD4_SOFF MCF_REG16(0xFC045086) ++#define MCF_EDMA_TCD4_NBYTES MCF_REG32(0xFC045088) ++#define MCF_EDMA_TCD4_SLAST MCF_REG32(0xFC04508C) ++#define MCF_EDMA_TCD4_DADDR MCF_REG32(0xFC045090) ++#define MCF_EDMA_TCD4_CITER MCF_REG16(0xFC045094) ++#define MCF_EDMA_TCD4_CITER_ELINK MCF_REG16(0xFC045094) ++#define MCF_EDMA_TCD4_DOFF MCF_REG16(0xFC045096) ++#define MCF_EDMA_TCD4_DLAST_SGA MCF_REG32(0xFC045098) ++#define MCF_EDMA_TCD4_BITER MCF_REG16(0xFC04509C) ++#define MCF_EDMA_TCD4_BITER_ELINK MCF_REG16(0xFC04509C) ++#define MCF_EDMA_TCD4_CSR MCF_REG16(0xFC04509E) ++#define MCF_EDMA_TCD5_SADDR MCF_REG32(0xFC0450A0) ++#define MCF_EDMA_TCD5_ATTR MCF_REG16(0xFC0450A4) ++#define MCF_EDMA_TCD5_SOFF MCF_REG16(0xFC0450A6) ++#define MCF_EDMA_TCD5_NBYTES MCF_REG32(0xFC0450A8) ++#define MCF_EDMA_TCD5_SLAST MCF_REG32(0xFC0450AC) ++#define MCF_EDMA_TCD5_DADDR MCF_REG32(0xFC0450B0) ++#define MCF_EDMA_TCD5_CITER MCF_REG16(0xFC0450B4) ++#define MCF_EDMA_TCD5_CITER_ELINK MCF_REG16(0xFC0450B4) ++#define MCF_EDMA_TCD5_DOFF MCF_REG16(0xFC0450B6) ++#define MCF_EDMA_TCD5_DLAST_SGA MCF_REG32(0xFC0450B8) ++#define MCF_EDMA_TCD5_BITER_ELINK MCF_REG16(0xFC0450BC) ++#define MCF_EDMA_TCD5_BITER MCF_REG16(0xFC0450BC) ++#define MCF_EDMA_TCD5_CSR MCF_REG16(0xFC0450BE) ++#define MCF_EDMA_TCD6_SADDR MCF_REG32(0xFC0450C0) ++#define MCF_EDMA_TCD6_ATTR MCF_REG16(0xFC0450C4) ++#define MCF_EDMA_TCD6_SOFF MCF_REG16(0xFC0450C6) ++#define MCF_EDMA_TCD6_NBYTES MCF_REG32(0xFC0450C8) ++#define MCF_EDMA_TCD6_SLAST MCF_REG32(0xFC0450CC) ++#define MCF_EDMA_TCD6_DADDR MCF_REG32(0xFC0450D0) ++#define MCF_EDMA_TCD6_CITER MCF_REG16(0xFC0450D4) ++#define MCF_EDMA_TCD6_CITER_ELINK MCF_REG16(0xFC0450D4) ++#define MCF_EDMA_TCD6_DOFF MCF_REG16(0xFC0450D6) ++#define MCF_EDMA_TCD6_DLAST_SGA MCF_REG32(0xFC0450D8) ++#define MCF_EDMA_TCD6_BITER_ELINK MCF_REG16(0xFC0450DC) ++#define MCF_EDMA_TCD6_BITER MCF_REG16(0xFC0450DC) ++#define MCF_EDMA_TCD6_CSR MCF_REG16(0xFC0450DE) ++#define MCF_EDMA_TCD7_SADDR MCF_REG32(0xFC0450E0) ++#define MCF_EDMA_TCD7_ATTR MCF_REG16(0xFC0450E4) ++#define MCF_EDMA_TCD7_SOFF MCF_REG16(0xFC0450E6) ++#define MCF_EDMA_TCD7_NBYTES MCF_REG32(0xFC0450E8) ++#define MCF_EDMA_TCD7_SLAST MCF_REG32(0xFC0450EC) ++#define MCF_EDMA_TCD7_DADDR MCF_REG32(0xFC0450F0) ++#define MCF_EDMA_TCD7_CITER MCF_REG16(0xFC0450F4) ++#define MCF_EDMA_TCD7_CITER_ELINK MCF_REG16(0xFC0450F4) ++#define MCF_EDMA_TCD7_DOFF MCF_REG16(0xFC0450F6) ++#define MCF_EDMA_TCD7_DLAST_SGA MCF_REG32(0xFC0450F8) ++#define MCF_EDMA_TCD7_BITER_ELINK MCF_REG16(0xFC0450FC) ++#define MCF_EDMA_TCD7_BITER MCF_REG16(0xFC0450FC) ++#define MCF_EDMA_TCD7_CSR MCF_REG16(0xFC0450FE) ++#define MCF_EDMA_TCD8_SADDR MCF_REG32(0xFC045100) ++#define MCF_EDMA_TCD8_ATTR MCF_REG16(0xFC045104) ++#define MCF_EDMA_TCD8_SOFF MCF_REG16(0xFC045106) ++#define MCF_EDMA_TCD8_NBYTES MCF_REG32(0xFC045108) ++#define MCF_EDMA_TCD8_SLAST MCF_REG32(0xFC04510C) ++#define MCF_EDMA_TCD8_DADDR MCF_REG32(0xFC045110) ++#define MCF_EDMA_TCD8_CITER MCF_REG16(0xFC045114) ++#define MCF_EDMA_TCD8_CITER_ELINK MCF_REG16(0xFC045114) ++#define MCF_EDMA_TCD8_DOFF MCF_REG16(0xFC045116) ++#define MCF_EDMA_TCD8_DLAST_SGA MCF_REG32(0xFC045118) ++#define MCF_EDMA_TCD8_BITER_ELINK MCF_REG16(0xFC04511C) ++#define MCF_EDMA_TCD8_BITER MCF_REG16(0xFC04511C) ++#define MCF_EDMA_TCD8_CSR MCF_REG16(0xFC04511E) ++#define MCF_EDMA_TCD9_SADDR MCF_REG32(0xFC045120) ++#define MCF_EDMA_TCD9_ATTR MCF_REG16(0xFC045124) ++#define MCF_EDMA_TCD9_SOFF MCF_REG16(0xFC045126) ++#define MCF_EDMA_TCD9_NBYTES MCF_REG32(0xFC045128) ++#define MCF_EDMA_TCD9_SLAST MCF_REG32(0xFC04512C) ++#define MCF_EDMA_TCD9_DADDR MCF_REG32(0xFC045130) ++#define MCF_EDMA_TCD9_CITER_ELINK MCF_REG16(0xFC045134) ++#define MCF_EDMA_TCD9_CITER MCF_REG16(0xFC045134) ++#define MCF_EDMA_TCD9_DOFF MCF_REG16(0xFC045136) ++#define MCF_EDMA_TCD9_DLAST_SGA MCF_REG32(0xFC045138) ++#define MCF_EDMA_TCD9_BITER_ELINK MCF_REG16(0xFC04513C) ++#define MCF_EDMA_TCD9_BITER MCF_REG16(0xFC04513C) ++#define MCF_EDMA_TCD9_CSR MCF_REG16(0xFC04513E) ++#define MCF_EDMA_TCD10_SADDR MCF_REG32(0xFC045140) ++#define MCF_EDMA_TCD10_ATTR MCF_REG16(0xFC045144) ++#define MCF_EDMA_TCD10_SOFF MCF_REG16(0xFC045146) ++#define MCF_EDMA_TCD10_NBYTES MCF_REG32(0xFC045148) ++#define MCF_EDMA_TCD10_SLAST MCF_REG32(0xFC04514C) ++#define MCF_EDMA_TCD10_DADDR MCF_REG32(0xFC045150) ++#define MCF_EDMA_TCD10_CITER_ELINK MCF_REG16(0xFC045154) ++#define MCF_EDMA_TCD10_CITER MCF_REG16(0xFC045154) ++#define MCF_EDMA_TCD10_DOFF MCF_REG16(0xFC045156) ++#define MCF_EDMA_TCD10_DLAST_SGA MCF_REG32(0xFC045158) ++#define MCF_EDMA_TCD10_BITER MCF_REG16(0xFC04515C) ++#define MCF_EDMA_TCD10_BITER_ELINK MCF_REG16(0xFC04515C) ++#define MCF_EDMA_TCD10_CSR MCF_REG16(0xFC04515E) ++#define MCF_EDMA_TCD11_SADDR MCF_REG32(0xFC045160) ++#define MCF_EDMA_TCD11_ATTR MCF_REG16(0xFC045164) ++#define MCF_EDMA_TCD11_SOFF MCF_REG16(0xFC045166) ++#define MCF_EDMA_TCD11_NBYTES MCF_REG32(0xFC045168) ++#define MCF_EDMA_TCD11_SLAST MCF_REG32(0xFC04516C) ++#define MCF_EDMA_TCD11_DADDR MCF_REG32(0xFC045170) ++#define MCF_EDMA_TCD11_CITER MCF_REG16(0xFC045174) ++#define MCF_EDMA_TCD11_CITER_ELINK MCF_REG16(0xFC045174) ++#define MCF_EDMA_TCD11_DOFF MCF_REG16(0xFC045176) ++#define MCF_EDMA_TCD11_DLAST_SGA MCF_REG32(0xFC045178) ++#define MCF_EDMA_TCD11_BITER MCF_REG16(0xFC04517C) ++#define MCF_EDMA_TCD11_BITER_ELINK MCF_REG16(0xFC04517C) ++#define MCF_EDMA_TCD11_CSR MCF_REG16(0xFC04517E) ++#define MCF_EDMA_TCD12_SADDR MCF_REG32(0xFC045180) ++#define MCF_EDMA_TCD12_ATTR MCF_REG16(0xFC045184) ++#define MCF_EDMA_TCD12_SOFF MCF_REG16(0xFC045186) ++#define MCF_EDMA_TCD12_NBYTES MCF_REG32(0xFC045188) ++#define MCF_EDMA_TCD12_SLAST MCF_REG32(0xFC04518C) ++#define MCF_EDMA_TCD12_DADDR MCF_REG32(0xFC045190) ++#define MCF_EDMA_TCD12_CITER MCF_REG16(0xFC045194) ++#define MCF_EDMA_TCD12_CITER_ELINK MCF_REG16(0xFC045194) ++#define MCF_EDMA_TCD12_DOFF MCF_REG16(0xFC045196) ++#define MCF_EDMA_TCD12_DLAST_SGA MCF_REG32(0xFC045198) ++#define MCF_EDMA_TCD12_BITER MCF_REG16(0xFC04519C) ++#define MCF_EDMA_TCD12_BITER_ELINK MCF_REG16(0xFC04519C) ++#define MCF_EDMA_TCD12_CSR MCF_REG16(0xFC04519E) ++#define MCF_EDMA_TCD13_SADDR MCF_REG32(0xFC0451A0) ++#define MCF_EDMA_TCD13_ATTR MCF_REG16(0xFC0451A4) ++#define MCF_EDMA_TCD13_SOFF MCF_REG16(0xFC0451A6) ++#define MCF_EDMA_TCD13_NBYTES MCF_REG32(0xFC0451A8) ++#define MCF_EDMA_TCD13_SLAST MCF_REG32(0xFC0451AC) ++#define MCF_EDMA_TCD13_DADDR MCF_REG32(0xFC0451B0) ++#define MCF_EDMA_TCD13_CITER_ELINK MCF_REG16(0xFC0451B4) ++#define MCF_EDMA_TCD13_CITER MCF_REG16(0xFC0451B4) ++#define MCF_EDMA_TCD13_DOFF MCF_REG16(0xFC0451B6) ++#define MCF_EDMA_TCD13_DLAST_SGA MCF_REG32(0xFC0451B8) ++#define MCF_EDMA_TCD13_BITER_ELINK MCF_REG16(0xFC0451BC) ++#define MCF_EDMA_TCD13_BITER MCF_REG16(0xFC0451BC) ++#define MCF_EDMA_TCD13_CSR MCF_REG16(0xFC0451BE) ++#define MCF_EDMA_TCD14_SADDR MCF_REG32(0xFC0451C0) ++#define MCF_EDMA_TCD14_ATTR MCF_REG16(0xFC0451C4) ++#define MCF_EDMA_TCD14_SOFF MCF_REG16(0xFC0451C6) ++#define MCF_EDMA_TCD14_NBYTES MCF_REG32(0xFC0451C8) ++#define MCF_EDMA_TCD14_SLAST MCF_REG32(0xFC0451CC) ++#define MCF_EDMA_TCD14_DADDR MCF_REG32(0xFC0451D0) ++#define MCF_EDMA_TCD14_CITER MCF_REG16(0xFC0451D4) ++#define MCF_EDMA_TCD14_CITER_ELINK MCF_REG16(0xFC0451D4) ++#define MCF_EDMA_TCD14_DOFF MCF_REG16(0xFC0451D6) ++#define MCF_EDMA_TCD14_DLAST_SGA MCF_REG32(0xFC0451D8) ++#define MCF_EDMA_TCD14_BITER_ELINK MCF_REG16(0xFC0451DC) ++#define MCF_EDMA_TCD14_BITER MCF_REG16(0xFC0451DC) ++#define MCF_EDMA_TCD14_CSR MCF_REG16(0xFC0451DE) ++#define MCF_EDMA_TCD15_SADDR MCF_REG32(0xFC0451E0) ++#define MCF_EDMA_TCD15_ATTR MCF_REG16(0xFC0451E4) ++#define MCF_EDMA_TCD15_SOFF MCF_REG16(0xFC0451E6) ++#define MCF_EDMA_TCD15_NBYTES MCF_REG32(0xFC0451E8) ++#define MCF_EDMA_TCD15_SLAST MCF_REG32(0xFC0451EC) ++#define MCF_EDMA_TCD15_DADDR MCF_REG32(0xFC0451F0) ++#define MCF_EDMA_TCD15_CITER_ELINK MCF_REG16(0xFC0451F4) ++#define MCF_EDMA_TCD15_CITER MCF_REG16(0xFC0451F4) ++#define MCF_EDMA_TCD15_DOFF MCF_REG16(0xFC0451F6) ++#define MCF_EDMA_TCD15_DLAST_SGA MCF_REG32(0xFC0451F8) ++#define MCF_EDMA_TCD15_BITER MCF_REG16(0xFC0451FC) ++#define MCF_EDMA_TCD15_BITER_ELINK MCF_REG16(0xFC0451FC) ++#define MCF_EDMA_TCD15_CSR MCF_REG16(0xFC0451FE) ++ ++/* Parameterized register read/write macros for multiple registers */ ++#define MCF_EDMA_DCHPRI(x) MCF_REG08(0xFC044100+((x)*0x001)) ++#define MCF_EDMA_TCD_SADDR(x) MCF_REG32(0xFC045000+((x)*0x020)) ++#define MCF_EDMA_TCD_ATTR(x) MCF_REG16(0xFC045004+((x)*0x020)) ++#define MCF_EDMA_TCD_SOFF(x) MCF_REG16(0xFC045006+((x)*0x020)) ++#define MCF_EDMA_TCD_NBYTES(x) MCF_REG32(0xFC045008+((x)*0x020)) ++#define MCF_EDMA_TCD_SLAST(x) MCF_REG32(0xFC04500C+((x)*0x020)) ++#define MCF_EDMA_TCD_DADDR(x) MCF_REG32(0xFC045010+((x)*0x020)) ++#define MCF_EDMA_TCD_CITER_ELINK(x) MCF_REG16(0xFC045014+((x)*0x020)) ++#define MCF_EDMA_TCD_CITER(x) MCF_REG16(0xFC045014+((x)*0x020)) ++#define MCF_EDMA_TCD_DOFF(x) MCF_REG16(0xFC045016+((x)*0x020)) ++#define MCF_EDMA_TCD_DLAST_SGA(x) MCF_REG32(0xFC045018+((x)*0x020)) ++#define MCF_EDMA_TCD_BITER_ELINK(x) MCF_REG16(0xFC04501C+((x)*0x020)) ++#define MCF_EDMA_TCD_BITER(x) MCF_REG16(0xFC04501C+((x)*0x020)) ++#define MCF_EDMA_TCD_CSR(x) MCF_REG16((0xFC04501e)+((x)*0x020)) ++ ++/* Bit definitions and macros for CR */ ++#define MCF_EDMA_CR_EDBG (0x00000002) ++#define MCF_EDMA_CR_ERCA (0x00000004) ++ ++/* Bit definitions and macros for ES */ ++#define MCF_EDMA_ES_DBE (0x00000001) ++#define MCF_EDMA_ES_SBE (0x00000002) ++#define MCF_EDMA_ES_SGE (0x00000004) ++#define MCF_EDMA_ES_NCE (0x00000008) ++#define MCF_EDMA_ES_DOE (0x00000010) ++#define MCF_EDMA_ES_DAE (0x00000020) ++#define MCF_EDMA_ES_SOE (0x00000040) ++#define MCF_EDMA_ES_SAE (0x00000080) ++#define MCF_EDMA_ES_ERRCHN(x) (((x)&0x0000000F)<<8) ++#define MCF_EDMA_ES_CPE (0x00004000) ++#define MCF_EDMA_ES_VLD (0x80000000) ++ ++/* Bit definitions and macros for ERQ */ ++#define MCF_EDMA_ERQ_ERQ0 (0x0001) ++#define MCF_EDMA_ERQ_ERQ1 (0x0002) ++#define MCF_EDMA_ERQ_ERQ2 (0x0004) ++#define MCF_EDMA_ERQ_ERQ3 (0x0008) ++#define MCF_EDMA_ERQ_ERQ4 (0x0010) ++#define MCF_EDMA_ERQ_ERQ5 (0x0020) ++#define MCF_EDMA_ERQ_ERQ6 (0x0040) ++#define MCF_EDMA_ERQ_ERQ7 (0x0080) ++#define MCF_EDMA_ERQ_ERQ8 (0x0100) ++#define MCF_EDMA_ERQ_ERQ9 (0x0200) ++#define MCF_EDMA_ERQ_ERQ10 (0x0400) ++#define MCF_EDMA_ERQ_ERQ11 (0x0800) ++#define MCF_EDMA_ERQ_ERQ12 (0x1000) ++#define MCF_EDMA_ERQ_ERQ13 (0x2000) ++#define MCF_EDMA_ERQ_ERQ14 (0x4000) ++#define MCF_EDMA_ERQ_ERQ15 (0x8000) ++ ++/* Bit definitions and macros for EEI */ ++#define MCF_EDMA_EEI_EEI0 (0x0001) ++#define MCF_EDMA_EEI_EEI1 (0x0002) ++#define MCF_EDMA_EEI_EEI2 (0x0004) ++#define MCF_EDMA_EEI_EEI3 (0x0008) ++#define MCF_EDMA_EEI_EEI4 (0x0010) ++#define MCF_EDMA_EEI_EEI5 (0x0020) ++#define MCF_EDMA_EEI_EEI6 (0x0040) ++#define MCF_EDMA_EEI_EEI7 (0x0080) ++#define MCF_EDMA_EEI_EEI8 (0x0100) ++#define MCF_EDMA_EEI_EEI9 (0x0200) ++#define MCF_EDMA_EEI_EEI10 (0x0400) ++#define MCF_EDMA_EEI_EEI11 (0x0800) ++#define MCF_EDMA_EEI_EEI12 (0x1000) ++#define MCF_EDMA_EEI_EEI13 (0x2000) ++#define MCF_EDMA_EEI_EEI14 (0x4000) ++#define MCF_EDMA_EEI_EEI15 (0x8000) ++ ++/* Bit definitions and macros for SERQ */ ++#define MCF_EDMA_SERQ_SERQ(x) (((x)&0x0F)) ++#define MCF_EDMA_SERQ_SAER (0x40) ++ ++/* Bit definitions and macros for CERQ */ ++#define MCF_EDMA_CERQ_CERQ(x) (((x)&0x0F)) ++#define MCF_EDMA_CERQ_CAER (0x40) ++ ++/* Bit definitions and macros for SEEI */ ++#define MCF_EDMA_SEEI_SEEI(x) (((x)&0x0F)) ++#define MCF_EDMA_SEEI_SAEE (0x40) ++ ++/* Bit definitions and macros for CEEI */ ++#define MCF_EDMA_CEEI_CEEI(x) (((x)&0x0F)) ++#define MCF_EDMA_CEEI_CAEE (0x40) ++ ++/* Bit definitions and macros for CINT */ ++#define MCF_EDMA_CINT_CINT(x) (((x)&0x0F)) ++#define MCF_EDMA_CINT_CAIR (0x40) ++ ++/* Bit definitions and macros for CERR */ ++#define MCF_EDMA_CERR_CERR(x) (((x)&0x0F)) ++#define MCF_EDMA_CERR_CAER (0x40) ++ ++/* Bit definitions and macros for SSRT */ ++#define MCF_EDMA_SSRT_SSRT(x) (((x)&0x0F)) ++#define MCF_EDMA_SSRT_SAST (0x40) ++ ++/* Bit definitions and macros for CDNE */ ++#define MCF_EDMA_CDNE_CDNE(x) (((x)&0x0F)) ++#define MCF_EDMA_CDNE_CADN (0x40) ++ ++/* Bit definitions and macros for INTR */ ++#define MCF_EDMA_INTR_INT0 (0x0001) ++#define MCF_EDMA_INTR_INT1 (0x0002) ++#define MCF_EDMA_INTR_INT2 (0x0004) ++#define MCF_EDMA_INTR_INT3 (0x0008) ++#define MCF_EDMA_INTR_INT4 (0x0010) ++#define MCF_EDMA_INTR_INT5 (0x0020) ++#define MCF_EDMA_INTR_INT6 (0x0040) ++#define MCF_EDMA_INTR_INT7 (0x0080) ++#define MCF_EDMA_INTR_INT8 (0x0100) ++#define MCF_EDMA_INTR_INT9 (0x0200) ++#define MCF_EDMA_INTR_INT10 (0x0400) ++#define MCF_EDMA_INTR_INT11 (0x0800) ++#define MCF_EDMA_INTR_INT12 (0x1000) ++#define MCF_EDMA_INTR_INT13 (0x2000) ++#define MCF_EDMA_INTR_INT14 (0x4000) ++#define MCF_EDMA_INTR_INT15 (0x8000) ++ ++/* Bit definitions and macros for ERR */ ++#define MCF_EDMA_ERR_ERR0 (0x0001) ++#define MCF_EDMA_ERR_ERR1 (0x0002) ++#define MCF_EDMA_ERR_ERR2 (0x0004) ++#define MCF_EDMA_ERR_ERR3 (0x0008) ++#define MCF_EDMA_ERR_ERR4 (0x0010) ++#define MCF_EDMA_ERR_ERR5 (0x0020) ++#define MCF_EDMA_ERR_ERR6 (0x0040) ++#define MCF_EDMA_ERR_ERR7 (0x0080) ++#define MCF_EDMA_ERR_ERR8 (0x0100) ++#define MCF_EDMA_ERR_ERR9 (0x0200) ++#define MCF_EDMA_ERR_ERR10 (0x0400) ++#define MCF_EDMA_ERR_ERR11 (0x0800) ++#define MCF_EDMA_ERR_ERR12 (0x1000) ++#define MCF_EDMA_ERR_ERR13 (0x2000) ++#define MCF_EDMA_ERR_ERR14 (0x4000) ++#define MCF_EDMA_ERR_ERR15 (0x8000) ++ ++/* Bit definitions and macros for DCHPRI group */ ++#define MCF_EDMA_DCHPRI_CHPRI(x) (((x)&0x0F)) ++#define MCF_EDMA_DCHPRI_ECP (0x80) ++ ++/* Bit definitions and macros for DCHPRI0 */ ++#define MCF_EDMA_DCHPRI0_CHPRI(x) (((x)&0x0F)) ++#define MCF_EDMA_DCHPRI0_ECP (0x80) ++ ++/* Bit definitions and macros for DCHPRI1 */ ++#define MCF_EDMA_DCHPRI1_CHPRI(x) (((x)&0x0F)) ++#define MCF_EDMA_DCHPRI1_ECP (0x80) ++ ++/* Bit definitions and macros for DCHPRI2 */ ++#define MCF_EDMA_DCHPRI2_CHPRI(x) (((x)&0x0F)) ++#define MCF_EDMA_DCHPRI2_ECP (0x80) ++ ++/* Bit definitions and macros for DCHPRI3 */ ++#define MCF_EDMA_DCHPRI3_CHPRI(x) (((x)&0x0F)) ++#define MCF_EDMA_DCHPRI3_ECP (0x80) ++ ++/* Bit definitions and macros for DCHPRI4 */ ++#define MCF_EDMA_DCHPRI4_CHPRI(x) (((x)&0x0F)) ++#define MCF_EDMA_DCHPRI4_ECP (0x80) ++ ++/* Bit definitions and macros for DCHPRI5 */ ++#define MCF_EDMA_DCHPRI5_CHPRI(x) (((x)&0x0F)) ++#define MCF_EDMA_DCHPRI5_ECP (0x80) ++ ++/* Bit definitions and macros for DCHPRI6 */ ++#define MCF_EDMA_DCHPRI6_CHPRI(x) (((x)&0x0F)) ++#define MCF_EDMA_DCHPRI6_ECP (0x80) ++ ++/* Bit definitions and macros for DCHPRI7 */ ++#define MCF_EDMA_DCHPRI7_CHPRI(x) (((x)&0x0F)) ++#define MCF_EDMA_DCHPRI7_ECP (0x80) ++ ++/* Bit definitions and macros for DCHPRI8 */ ++#define MCF_EDMA_DCHPRI8_CHPRI(x) (((x)&0x0F)) ++#define MCF_EDMA_DCHPRI8_ECP (0x80) ++ ++/* Bit definitions and macros for DCHPRI9 */ ++#define MCF_EDMA_DCHPRI9_CHPRI(x) (((x)&0x0F)) ++#define MCF_EDMA_DCHPRI9_ECP (0x80) ++ ++/* Bit definitions and macros for DCHPRI10 */ ++#define MCF_EDMA_DCHPRI10_CHPRI(x) (((x)&0x0F)) ++#define MCF_EDMA_DCHPRI10_ECP (0x80) ++ ++/* Bit definitions and macros for DCHPRI11 */ ++#define MCF_EDMA_DCHPRI11_CHPRI(x) (((x)&0x0F)) ++#define MCF_EDMA_DCHPRI11_ECP (0x80) ++ ++/* Bit definitions and macros for DCHPRI12 */ ++#define MCF_EDMA_DCHPRI12_CHPRI(x) (((x)&0x0F)) ++#define MCF_EDMA_DCHPRI12_ECP (0x80) ++ ++/* Bit definitions and macros for DCHPRI13 */ ++#define MCF_EDMA_DCHPRI13_CHPRI(x) (((x)&0x0F)) ++#define MCF_EDMA_DCHPRI13_ECP (0x80) ++ ++/* Bit definitions and macros for DCHPRI14 */ ++#define MCF_EDMA_DCHPRI14_CHPRI(x) (((x)&0x0F)) ++#define MCF_EDMA_DCHPRI14_ECP (0x80) ++ ++/* Bit definitions and macros for DCHPRI15 */ ++#define MCF_EDMA_DCHPRI15_CHPRI(x) (((x)&0x0F)) ++#define MCF_EDMA_DCHPRI15_ECP (0x80) ++ ++/* Bit definitions and macros for TCD_SADDR group */ ++#define MCF_EDMA_TCD_SADDR_SADDR(x) (x) ++ ++/* Bit definitions and macros for TCD0_SADDR */ ++#define MCF_EDMA_TCD0_SADDR_SADDR(x) (x) ++ ++/* Bit definitions and macros for TCD_ATTR group */ ++#define MCF_EDMA_TCD_ATTR_DSIZE(x) (((x)&0x0007)) ++#define MCF_EDMA_TCD_ATTR_DMOD(x) (((x)&0x001F)<<3) ++#define MCF_EDMA_TCD_ATTR_SSIZE(x) (((x)&0x0007)<<8) ++#define MCF_EDMA_TCD_ATTR_SMOD(x) (((x)&0x001F)<<11) ++#define MCF_EDMA_TCD_ATTR_SSIZE_8BIT (0x0000) ++#define MCF_EDMA_TCD_ATTR_SSIZE_16BIT (0x0100) ++#define MCF_EDMA_TCD_ATTR_SSIZE_32BIT (0x0200) ++#define MCF_EDMA_TCD_ATTR_SSIZE_16BYTE (0x0400) ++#define MCF_EDMA_TCD_ATTR_DSIZE_8BIT (0x0000) ++#define MCF_EDMA_TCD_ATTR_DSIZE_16BIT (0x0001) ++#define MCF_EDMA_TCD_ATTR_DSIZE_32BIT (0x0002) ++#define MCF_EDMA_TCD_ATTR_DSIZE_16BYTE (0x0004) ++ ++/* Bit definitions and macros for TCD0_ATTR */ ++#define MCF_EDMA_TCD0_ATTR_DSIZE(x) (((x)&0x0007)) ++#define MCF_EDMA_TCD0_ATTR_DMOD(x) (((x)&0x001F)<<3) ++#define MCF_EDMA_TCD0_ATTR_SSIZE(x) (((x)&0x0007)<<8) ++#define MCF_EDMA_TCD0_ATTR_SMOD(x) (((x)&0x001F)<<11) ++#define MCF_EDMA_TCD0_ATTR_SSIZE_8BIT (0x0000) ++#define MCF_EDMA_TCD0_ATTR_SSIZE_16BIT (0x0100) ++#define MCF_EDMA_TCD0_ATTR_SSIZE_32BIT (0x0200) ++#define MCF_EDMA_TCD0_ATTR_SSIZE_16BYTE (0x0400) ++#define MCF_EDMA_TCD0_ATTR_DSIZE_8BIT (0x0000) ++#define MCF_EDMA_TCD0_ATTR_DSIZE_16BIT (0x0001) ++#define MCF_EDMA_TCD0_ATTR_DSIZE_32BIT (0x0002) ++#define MCF_EDMA_TCD0_ATTR_DSIZE_16BYTE (0x0004) ++ ++/* Bit definitions and macros for TCD_SOFF group */ ++#define MCF_EDMA_TCD_SOFF_SOFF(x) (x) ++ ++/* Bit definitions and macros for TCD0_SOFF */ ++#define MCF_EDMA_TCD0_SOFF_SOFF(x) (x) ++ ++/* Bit definitions and macros for TCD_NBYTES group */ ++#define MCF_EDMA_TCD_NBYTES_NBYTES(x) (x) ++ ++/* Bit definitions and macros for TCD0_NBYTES */ ++#define MCF_EDMA_TCD0_NBYTES_NBYTES(x) (x) ++ ++/* Bit definitions and macros for TCD_SLAST group */ ++#define MCF_EDMA_TCD_SLAST_SLAST(x) (x) ++ ++/* Bit definitions and macros for TCD0_SLAST */ ++#define MCF_EDMA_TCD0_SLAST_SLAST(x) (x) ++ ++/* Bit definitions and macros for TCD_DADDR group */ ++#define MCF_EDMA_TCD_DADDR_DADDR(x) (x) ++ ++/* Bit definitions and macros for TCD0_DADDR */ ++#define MCF_EDMA_TCD0_DADDR_DADDR(x) (x) ++ ++/* Bit definitions and macros for TCD_CITER_ELINK group */ ++#define MCF_EDMA_TCD_CITER_ELINK_CITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD_CITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD0_CITER_ELINK */ ++#define MCF_EDMA_TCD0_CITER_ELINK_CITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD0_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD0_CITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD_CITER group */ ++#define MCF_EDMA_TCD_CITER_CITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD_CITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD0_CITER */ ++#define MCF_EDMA_TCD0_CITER_CITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD0_CITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD_DOFF group */ ++#define MCF_EDMA_TCD_DOFF_DOFF(x) (x) ++ ++/* Bit definitions and macros for TCD0_DOFF */ ++#define MCF_EDMA_TCD0_DOFF_DOFF(x) (x) ++ ++/* Bit definitions and macros for TCD_DLAST_SGA group */ ++#define MCF_EDMA_TCD_DLAST_SGA_DLAST_SGA(x) (x) ++ ++/* Bit definitions and macros for TCD0_DLAST_SGA */ ++#define MCF_EDMA_TCD0_DLAST_SGA_DLAST_SGA(x) (x) ++ ++/* Bit definitions and macros for TCD_BITER_ELINK group */ ++#define MCF_EDMA_TCD_BITER_ELINK_BITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD_BITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD0_BITER_ELINK */ ++#define MCF_EDMA_TCD0_BITER_ELINK_BITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD0_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD0_BITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD_BITER group */ ++#define MCF_EDMA_TCD_BITER_BITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD_BITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD0_BITER */ ++#define MCF_EDMA_TCD0_BITER_BITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD0_BITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD_CSR group */ ++#define MCF_EDMA_TCD_CSR_START (0x0001) ++#define MCF_EDMA_TCD_CSR_INT_MAJOR (0x0002) ++#define MCF_EDMA_TCD_CSR_INT_HALF (0x0004) ++#define MCF_EDMA_TCD_CSR_D_REQ (0x0008) ++#define MCF_EDMA_TCD_CSR_E_SG (0x0010) ++#define MCF_EDMA_TCD_CSR_E_LINK (0x0020) ++#define MCF_EDMA_TCD_CSR_ACTIVE (0x0040) ++#define MCF_EDMA_TCD_CSR_DONE (0x0080) ++#define MCF_EDMA_TCD_CSR_LINKCH(x) (((x)&0x003F)<<8) ++#define MCF_EDMA_TCD_CSR_BWC(x) (((x)&0x0003)<<14) ++#define MCF_EDMA_TCD_CSR_BWC_NO_STALL (0x0000) ++#define MCF_EDMA_TCD_CSR_BWC_4CYC_STALL (0x8000) ++#define MCF_EDMA_TCD_CSR_BWC_8CYC_STALL (0xC000) ++ ++/* Bit definitions and macros for TCD0_CSR */ ++#define MCF_EDMA_TCD0_CSR_START (0x0001) ++#define MCF_EDMA_TCD0_CSR_INT_MAJOR (0x0002) ++#define MCF_EDMA_TCD0_CSR_INT_HALF (0x0004) ++#define MCF_EDMA_TCD0_CSR_D_REQ (0x0008) ++#define MCF_EDMA_TCD0_CSR_E_SG (0x0010) ++#define MCF_EDMA_TCD0_CSR_E_LINK (0x0020) ++#define MCF_EDMA_TCD0_CSR_ACTIVE (0x0040) ++#define MCF_EDMA_TCD0_CSR_DONE (0x0080) ++#define MCF_EDMA_TCD0_CSR_LINKCH(x) (((x)&0x003F)<<8) ++#define MCF_EDMA_TCD0_CSR_BWC(x) (((x)&0x0003)<<14) ++#define MCF_EDMA_TCD0_CSR_BWC_NO_STALL (0x0000) ++#define MCF_EDMA_TCD0_CSR_BWC_4CYC_STALL (0x8000) ++#define MCF_EDMA_TCD0_CSR_BWC_8CYC_STALL (0xC000) ++ ++/* Bit definitions and macros for TCD1_SADDR */ ++#define MCF_EDMA_TCD1_SADDR_SADDR(x) (x) ++ ++/* Bit definitions and macros for TCD1_ATTR */ ++#define MCF_EDMA_TCD1_ATTR_DSIZE(x) (((x)&0x0007)) ++#define MCF_EDMA_TCD1_ATTR_DMOD(x) (((x)&0x001F)<<3) ++#define MCF_EDMA_TCD1_ATTR_SSIZE(x) (((x)&0x0007)<<8) ++#define MCF_EDMA_TCD1_ATTR_SMOD(x) (((x)&0x001F)<<11) ++ ++/* Bit definitions and macros for TCD1_SOFF */ ++#define MCF_EDMA_TCD1_SOFF_SOFF(x) (x) ++ ++/* Bit definitions and macros for TCD1_NBYTES */ ++#define MCF_EDMA_TCD1_NBYTES_NBYTES(x) (x) ++ ++/* Bit definitions and macros for TCD1_SLAST */ ++#define MCF_EDMA_TCD1_SLAST_SLAST(x) (x) ++ ++/* Bit definitions and macros for TCD1_DADDR */ ++#define MCF_EDMA_TCD1_DADDR_DADDR(x) (x) ++ ++/* Bit definitions and macros for TCD1_CITER_ELINK */ ++#define MCF_EDMA_TCD1_CITER_ELINK_CITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD1_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD1_CITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD1_CITER */ ++#define MCF_EDMA_TCD1_CITER_CITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD1_CITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD1_DOFF */ ++#define MCF_EDMA_TCD1_DOFF_DOFF(x) (x) ++ ++/* Bit definitions and macros for TCD1_DLAST_SGA */ ++#define MCF_EDMA_TCD1_DLAST_SGA_DLAST_SGA(x) (x) ++ ++/* Bit definitions and macros for TCD1_BITER */ ++#define MCF_EDMA_TCD1_BITER_BITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD1_BITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD1_BITER_ELINK */ ++#define MCF_EDMA_TCD1_BITER_ELINK_BITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD1_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD1_BITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD1_CSR */ ++#define MCF_EDMA_TCD1_CSR_START (0x0001) ++#define MCF_EDMA_TCD1_CSR_INT_MAJOR (0x0002) ++#define MCF_EDMA_TCD1_CSR_INT_HALF (0x0004) ++#define MCF_EDMA_TCD1_CSR_D_REQ (0x0008) ++#define MCF_EDMA_TCD1_CSR_E_SG (0x0010) ++#define MCF_EDMA_TCD1_CSR_E_LINK (0x0020) ++#define MCF_EDMA_TCD1_CSR_ACTIVE (0x0040) ++#define MCF_EDMA_TCD1_CSR_DONE (0x0080) ++#define MCF_EDMA_TCD1_CSR_LINKCH(x) (((x)&0x003F)<<8) ++#define MCF_EDMA_TCD1_CSR_BWC(x) (((x)&0x0003)<<14) ++ ++/* Bit definitions and macros for TCD2_SADDR */ ++#define MCF_EDMA_TCD2_SADDR_SADDR(x) (x) ++ ++/* Bit definitions and macros for TCD2_ATTR */ ++#define MCF_EDMA_TCD2_ATTR_DSIZE(x) (((x)&0x0007)) ++#define MCF_EDMA_TCD2_ATTR_DMOD(x) (((x)&0x001F)<<3) ++#define MCF_EDMA_TCD2_ATTR_SSIZE(x) (((x)&0x0007)<<8) ++#define MCF_EDMA_TCD2_ATTR_SMOD(x) (((x)&0x001F)<<11) ++ ++/* Bit definitions and macros for TCD2_SOFF */ ++#define MCF_EDMA_TCD2_SOFF_SOFF(x) (x) ++ ++/* Bit definitions and macros for TCD2_NBYTES */ ++#define MCF_EDMA_TCD2_NBYTES_NBYTES(x) (x) ++ ++/* Bit definitions and macros for TCD2_SLAST */ ++#define MCF_EDMA_TCD2_SLAST_SLAST(x) (x) ++ ++/* Bit definitions and macros for TCD2_DADDR */ ++#define MCF_EDMA_TCD2_DADDR_DADDR(x) (x) ++ ++/* Bit definitions and macros for TCD2_CITER */ ++#define MCF_EDMA_TCD2_CITER_CITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD2_CITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD2_CITER_ELINK */ ++#define MCF_EDMA_TCD2_CITER_ELINK_CITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD2_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD2_CITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD2_DOFF */ ++#define MCF_EDMA_TCD2_DOFF_DOFF(x) (x) ++ ++/* Bit definitions and macros for TCD2_DLAST_SGA */ ++#define MCF_EDMA_TCD2_DLAST_SGA_DLAST_SGA(x) (x) ++ ++/* Bit definitions and macros for TCD2_BITER_ELINK */ ++#define MCF_EDMA_TCD2_BITER_ELINK_BITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD2_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD2_BITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD2_BITER */ ++#define MCF_EDMA_TCD2_BITER_BITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD2_BITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD2_CSR */ ++#define MCF_EDMA_TCD2_CSR_START (0x0001) ++#define MCF_EDMA_TCD2_CSR_INT_MAJOR (0x0002) ++#define MCF_EDMA_TCD2_CSR_INT_HALF (0x0004) ++#define MCF_EDMA_TCD2_CSR_D_REQ (0x0008) ++#define MCF_EDMA_TCD2_CSR_E_SG (0x0010) ++#define MCF_EDMA_TCD2_CSR_E_LINK (0x0020) ++#define MCF_EDMA_TCD2_CSR_ACTIVE (0x0040) ++#define MCF_EDMA_TCD2_CSR_DONE (0x0080) ++#define MCF_EDMA_TCD2_CSR_LINKCH(x) (((x)&0x003F)<<8) ++#define MCF_EDMA_TCD2_CSR_BWC(x) (((x)&0x0003)<<14) ++ ++/* Bit definitions and macros for TCD3_SADDR */ ++#define MCF_EDMA_TCD3_SADDR_SADDR(x) (x) ++ ++/* Bit definitions and macros for TCD3_ATTR */ ++#define MCF_EDMA_TCD3_ATTR_DSIZE(x) (((x)&0x0007)) ++#define MCF_EDMA_TCD3_ATTR_DMOD(x) (((x)&0x001F)<<3) ++#define MCF_EDMA_TCD3_ATTR_SSIZE(x) (((x)&0x0007)<<8) ++#define MCF_EDMA_TCD3_ATTR_SMOD(x) (((x)&0x001F)<<11) ++ ++/* Bit definitions and macros for TCD3_SOFF */ ++#define MCF_EDMA_TCD3_SOFF_SOFF(x) (x) ++ ++/* Bit definitions and macros for TCD3_NBYTES */ ++#define MCF_EDMA_TCD3_NBYTES_NBYTES(x) (x) ++ ++/* Bit definitions and macros for TCD3_SLAST */ ++#define MCF_EDMA_TCD3_SLAST_SLAST(x) (x) ++ ++/* Bit definitions and macros for TCD3_DADDR */ ++#define MCF_EDMA_TCD3_DADDR_DADDR(x) (x) ++ ++/* Bit definitions and macros for TCD3_CITER */ ++#define MCF_EDMA_TCD3_CITER_CITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD3_CITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD3_CITER_ELINK */ ++#define MCF_EDMA_TCD3_CITER_ELINK_CITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD3_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD3_CITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD3_DOFF */ ++#define MCF_EDMA_TCD3_DOFF_DOFF(x) (x) ++ ++/* Bit definitions and macros for TCD3_DLAST_SGA */ ++#define MCF_EDMA_TCD3_DLAST_SGA_DLAST_SGA(x) (x) ++ ++/* Bit definitions and macros for TCD3_BITER_ELINK */ ++#define MCF_EDMA_TCD3_BITER_ELINK_BITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD3_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD3_BITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD3_BITER */ ++#define MCF_EDMA_TCD3_BITER_BITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD3_BITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD3_CSR */ ++#define MCF_EDMA_TCD3_CSR_START (0x0001) ++#define MCF_EDMA_TCD3_CSR_INT_MAJOR (0x0002) ++#define MCF_EDMA_TCD3_CSR_INT_HALF (0x0004) ++#define MCF_EDMA_TCD3_CSR_D_REQ (0x0008) ++#define MCF_EDMA_TCD3_CSR_E_SG (0x0010) ++#define MCF_EDMA_TCD3_CSR_E_LINK (0x0020) ++#define MCF_EDMA_TCD3_CSR_ACTIVE (0x0040) ++#define MCF_EDMA_TCD3_CSR_DONE (0x0080) ++#define MCF_EDMA_TCD3_CSR_LINKCH(x) (((x)&0x003F)<<8) ++#define MCF_EDMA_TCD3_CSR_BWC(x) (((x)&0x0003)<<14) ++ ++/* Bit definitions and macros for TCD4_SADDR */ ++#define MCF_EDMA_TCD4_SADDR_SADDR(x) (x) ++ ++/* Bit definitions and macros for TCD4_ATTR */ ++#define MCF_EDMA_TCD4_ATTR_DSIZE(x) (((x)&0x0007)) ++#define MCF_EDMA_TCD4_ATTR_DMOD(x) (((x)&0x001F)<<3) ++#define MCF_EDMA_TCD4_ATTR_SSIZE(x) (((x)&0x0007)<<8) ++#define MCF_EDMA_TCD4_ATTR_SMOD(x) (((x)&0x001F)<<11) ++ ++/* Bit definitions and macros for TCD4_SOFF */ ++#define MCF_EDMA_TCD4_SOFF_SOFF(x) (x) ++ ++/* Bit definitions and macros for TCD4_NBYTES */ ++#define MCF_EDMA_TCD4_NBYTES_NBYTES(x) (x) ++ ++/* Bit definitions and macros for TCD4_SLAST */ ++#define MCF_EDMA_TCD4_SLAST_SLAST(x) (x) ++ ++/* Bit definitions and macros for TCD4_DADDR */ ++#define MCF_EDMA_TCD4_DADDR_DADDR(x) (x) ++ ++/* Bit definitions and macros for TCD4_CITER */ ++#define MCF_EDMA_TCD4_CITER_CITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD4_CITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD4_CITER_ELINK */ ++#define MCF_EDMA_TCD4_CITER_ELINK_CITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD4_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD4_CITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD4_DOFF */ ++#define MCF_EDMA_TCD4_DOFF_DOFF(x) (x) ++ ++/* Bit definitions and macros for TCD4_DLAST_SGA */ ++#define MCF_EDMA_TCD4_DLAST_SGA_DLAST_SGA(x) (x) ++ ++/* Bit definitions and macros for TCD4_BITER */ ++#define MCF_EDMA_TCD4_BITER_BITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD4_BITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD4_BITER_ELINK */ ++#define MCF_EDMA_TCD4_BITER_ELINK_BITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD4_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD4_BITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD4_CSR */ ++#define MCF_EDMA_TCD4_CSR_START (0x0001) ++#define MCF_EDMA_TCD4_CSR_INT_MAJOR (0x0002) ++#define MCF_EDMA_TCD4_CSR_INT_HALF (0x0004) ++#define MCF_EDMA_TCD4_CSR_D_REQ (0x0008) ++#define MCF_EDMA_TCD4_CSR_E_SG (0x0010) ++#define MCF_EDMA_TCD4_CSR_E_LINK (0x0020) ++#define MCF_EDMA_TCD4_CSR_ACTIVE (0x0040) ++#define MCF_EDMA_TCD4_CSR_DONE (0x0080) ++#define MCF_EDMA_TCD4_CSR_LINKCH(x) (((x)&0x003F)<<8) ++#define MCF_EDMA_TCD4_CSR_BWC(x) (((x)&0x0003)<<14) ++ ++/* Bit definitions and macros for TCD5_SADDR */ ++#define MCF_EDMA_TCD5_SADDR_SADDR(x) (x) ++ ++/* Bit definitions and macros for TCD5_ATTR */ ++#define MCF_EDMA_TCD5_ATTR_DSIZE(x) (((x)&0x0007)) ++#define MCF_EDMA_TCD5_ATTR_DMOD(x) (((x)&0x001F)<<3) ++#define MCF_EDMA_TCD5_ATTR_SSIZE(x) (((x)&0x0007)<<8) ++#define MCF_EDMA_TCD5_ATTR_SMOD(x) (((x)&0x001F)<<11) ++ ++/* Bit definitions and macros for TCD5_SOFF */ ++#define MCF_EDMA_TCD5_SOFF_SOFF(x) (x) ++ ++/* Bit definitions and macros for TCD5_NBYTES */ ++#define MCF_EDMA_TCD5_NBYTES_NBYTES(x) (x) ++ ++/* Bit definitions and macros for TCD5_SLAST */ ++#define MCF_EDMA_TCD5_SLAST_SLAST(x) (x) ++ ++/* Bit definitions and macros for TCD5_DADDR */ ++#define MCF_EDMA_TCD5_DADDR_DADDR(x) (x) ++ ++/* Bit definitions and macros for TCD5_CITER */ ++#define MCF_EDMA_TCD5_CITER_CITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD5_CITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD5_CITER_ELINK */ ++#define MCF_EDMA_TCD5_CITER_ELINK_CITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD5_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD5_CITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD5_DOFF */ ++#define MCF_EDMA_TCD5_DOFF_DOFF(x) (x) ++ ++/* Bit definitions and macros for TCD5_DLAST_SGA */ ++#define MCF_EDMA_TCD5_DLAST_SGA_DLAST_SGA(x) (x) ++ ++/* Bit definitions and macros for TCD5_BITER_ELINK */ ++#define MCF_EDMA_TCD5_BITER_ELINK_BITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD5_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD5_BITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD5_BITER */ ++#define MCF_EDMA_TCD5_BITER_BITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD5_BITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD5_CSR */ ++#define MCF_EDMA_TCD5_CSR_START (0x0001) ++#define MCF_EDMA_TCD5_CSR_INT_MAJOR (0x0002) ++#define MCF_EDMA_TCD5_CSR_INT_HALF (0x0004) ++#define MCF_EDMA_TCD5_CSR_D_REQ (0x0008) ++#define MCF_EDMA_TCD5_CSR_E_SG (0x0010) ++#define MCF_EDMA_TCD5_CSR_E_LINK (0x0020) ++#define MCF_EDMA_TCD5_CSR_ACTIVE (0x0040) ++#define MCF_EDMA_TCD5_CSR_DONE (0x0080) ++#define MCF_EDMA_TCD5_CSR_LINKCH(x) (((x)&0x003F)<<8) ++#define MCF_EDMA_TCD5_CSR_BWC(x) (((x)&0x0003)<<14) ++ ++/* Bit definitions and macros for TCD6_SADDR */ ++#define MCF_EDMA_TCD6_SADDR_SADDR(x) (x) ++ ++/* Bit definitions and macros for TCD6_ATTR */ ++#define MCF_EDMA_TCD6_ATTR_DSIZE(x) (((x)&0x0007)) ++#define MCF_EDMA_TCD6_ATTR_DMOD(x) (((x)&0x001F)<<3) ++#define MCF_EDMA_TCD6_ATTR_SSIZE(x) (((x)&0x0007)<<8) ++#define MCF_EDMA_TCD6_ATTR_SMOD(x) (((x)&0x001F)<<11) ++ ++/* Bit definitions and macros for TCD6_SOFF */ ++#define MCF_EDMA_TCD6_SOFF_SOFF(x) (x) ++ ++/* Bit definitions and macros for TCD6_NBYTES */ ++#define MCF_EDMA_TCD6_NBYTES_NBYTES(x) (x) ++ ++/* Bit definitions and macros for TCD6_SLAST */ ++#define MCF_EDMA_TCD6_SLAST_SLAST(x) (x) ++ ++/* Bit definitions and macros for TCD6_DADDR */ ++#define MCF_EDMA_TCD6_DADDR_DADDR(x) (x) ++ ++/* Bit definitions and macros for TCD6_CITER */ ++#define MCF_EDMA_TCD6_CITER_CITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD6_CITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD6_CITER_ELINK */ ++#define MCF_EDMA_TCD6_CITER_ELINK_CITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD6_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD6_CITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD6_DOFF */ ++#define MCF_EDMA_TCD6_DOFF_DOFF(x) (x) ++ ++/* Bit definitions and macros for TCD6_DLAST_SGA */ ++#define MCF_EDMA_TCD6_DLAST_SGA_DLAST_SGA(x) (x) ++ ++/* Bit definitions and macros for TCD6_BITER_ELINK */ ++#define MCF_EDMA_TCD6_BITER_ELINK_BITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD6_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD6_BITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD6_BITER */ ++#define MCF_EDMA_TCD6_BITER_BITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD6_BITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD6_CSR */ ++#define MCF_EDMA_TCD6_CSR_START (0x0001) ++#define MCF_EDMA_TCD6_CSR_INT_MAJOR (0x0002) ++#define MCF_EDMA_TCD6_CSR_INT_HALF (0x0004) ++#define MCF_EDMA_TCD6_CSR_D_REQ (0x0008) ++#define MCF_EDMA_TCD6_CSR_E_SG (0x0010) ++#define MCF_EDMA_TCD6_CSR_E_LINK (0x0020) ++#define MCF_EDMA_TCD6_CSR_ACTIVE (0x0040) ++#define MCF_EDMA_TCD6_CSR_DONE (0x0080) ++#define MCF_EDMA_TCD6_CSR_LINKCH(x) (((x)&0x003F)<<8) ++#define MCF_EDMA_TCD6_CSR_BWC(x) (((x)&0x0003)<<14) ++ ++/* Bit definitions and macros for TCD7_SADDR */ ++#define MCF_EDMA_TCD7_SADDR_SADDR(x) (x) ++ ++/* Bit definitions and macros for TCD7_ATTR */ ++#define MCF_EDMA_TCD7_ATTR_DSIZE(x) (((x)&0x0007)) ++#define MCF_EDMA_TCD7_ATTR_DMOD(x) (((x)&0x001F)<<3) ++#define MCF_EDMA_TCD7_ATTR_SSIZE(x) (((x)&0x0007)<<8) ++#define MCF_EDMA_TCD7_ATTR_SMOD(x) (((x)&0x001F)<<11) ++ ++/* Bit definitions and macros for TCD7_SOFF */ ++#define MCF_EDMA_TCD7_SOFF_SOFF(x) (x) ++ ++/* Bit definitions and macros for TCD7_NBYTES */ ++#define MCF_EDMA_TCD7_NBYTES_NBYTES(x) (x) ++ ++/* Bit definitions and macros for TCD7_SLAST */ ++#define MCF_EDMA_TCD7_SLAST_SLAST(x) (x) ++ ++/* Bit definitions and macros for TCD7_DADDR */ ++#define MCF_EDMA_TCD7_DADDR_DADDR(x) (x) ++ ++/* Bit definitions and macros for TCD7_CITER */ ++#define MCF_EDMA_TCD7_CITER_CITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD7_CITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD7_CITER_ELINK */ ++#define MCF_EDMA_TCD7_CITER_ELINK_CITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD7_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD7_CITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD7_DOFF */ ++#define MCF_EDMA_TCD7_DOFF_DOFF(x) (x) ++ ++/* Bit definitions and macros for TCD7_DLAST_SGA */ ++#define MCF_EDMA_TCD7_DLAST_SGA_DLAST_SGA(x) (x) ++ ++/* Bit definitions and macros for TCD7_BITER_ELINK */ ++#define MCF_EDMA_TCD7_BITER_ELINK_BITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD7_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD7_BITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD7_BITER */ ++#define MCF_EDMA_TCD7_BITER_BITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD7_BITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD7_CSR */ ++#define MCF_EDMA_TCD7_CSR_START (0x0001) ++#define MCF_EDMA_TCD7_CSR_INT_MAJOR (0x0002) ++#define MCF_EDMA_TCD7_CSR_INT_HALF (0x0004) ++#define MCF_EDMA_TCD7_CSR_D_REQ (0x0008) ++#define MCF_EDMA_TCD7_CSR_E_SG (0x0010) ++#define MCF_EDMA_TCD7_CSR_E_LINK (0x0020) ++#define MCF_EDMA_TCD7_CSR_ACTIVE (0x0040) ++#define MCF_EDMA_TCD7_CSR_DONE (0x0080) ++#define MCF_EDMA_TCD7_CSR_LINKCH(x) (((x)&0x003F)<<8) ++#define MCF_EDMA_TCD7_CSR_BWC(x) (((x)&0x0003)<<14) ++ ++/* Bit definitions and macros for TCD8_SADDR */ ++#define MCF_EDMA_TCD8_SADDR_SADDR(x) (x) ++ ++/* Bit definitions and macros for TCD8_ATTR */ ++#define MCF_EDMA_TCD8_ATTR_DSIZE(x) (((x)&0x0007)) ++#define MCF_EDMA_TCD8_ATTR_DMOD(x) (((x)&0x001F)<<3) ++#define MCF_EDMA_TCD8_ATTR_SSIZE(x) (((x)&0x0007)<<8) ++#define MCF_EDMA_TCD8_ATTR_SMOD(x) (((x)&0x001F)<<11) ++ ++/* Bit definitions and macros for TCD8_SOFF */ ++#define MCF_EDMA_TCD8_SOFF_SOFF(x) (x) ++ ++/* Bit definitions and macros for TCD8_NBYTES */ ++#define MCF_EDMA_TCD8_NBYTES_NBYTES(x) (x) ++ ++/* Bit definitions and macros for TCD8_SLAST */ ++#define MCF_EDMA_TCD8_SLAST_SLAST(x) (x) ++ ++/* Bit definitions and macros for TCD8_DADDR */ ++#define MCF_EDMA_TCD8_DADDR_DADDR(x) (x) ++ ++/* Bit definitions and macros for TCD8_CITER */ ++#define MCF_EDMA_TCD8_CITER_CITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD8_CITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD8_CITER_ELINK */ ++#define MCF_EDMA_TCD8_CITER_ELINK_CITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD8_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD8_CITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD8_DOFF */ ++#define MCF_EDMA_TCD8_DOFF_DOFF(x) (x) ++ ++/* Bit definitions and macros for TCD8_DLAST_SGA */ ++#define MCF_EDMA_TCD8_DLAST_SGA_DLAST_SGA(x) (x) ++ ++/* Bit definitions and macros for TCD8_BITER_ELINK */ ++#define MCF_EDMA_TCD8_BITER_ELINK_BITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD8_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD8_BITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD8_BITER */ ++#define MCF_EDMA_TCD8_BITER_BITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD8_BITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD8_CSR */ ++#define MCF_EDMA_TCD8_CSR_START (0x0001) ++#define MCF_EDMA_TCD8_CSR_INT_MAJOR (0x0002) ++#define MCF_EDMA_TCD8_CSR_INT_HALF (0x0004) ++#define MCF_EDMA_TCD8_CSR_D_REQ (0x0008) ++#define MCF_EDMA_TCD8_CSR_E_SG (0x0010) ++#define MCF_EDMA_TCD8_CSR_E_LINK (0x0020) ++#define MCF_EDMA_TCD8_CSR_ACTIVE (0x0040) ++#define MCF_EDMA_TCD8_CSR_DONE (0x0080) ++#define MCF_EDMA_TCD8_CSR_LINKCH(x) (((x)&0x003F)<<8) ++#define MCF_EDMA_TCD8_CSR_BWC(x) (((x)&0x0003)<<14) ++ ++/* Bit definitions and macros for TCD9_SADDR */ ++#define MCF_EDMA_TCD9_SADDR_SADDR(x) (x) ++ ++/* Bit definitions and macros for TCD9_ATTR */ ++#define MCF_EDMA_TCD9_ATTR_DSIZE(x) (((x)&0x0007)) ++#define MCF_EDMA_TCD9_ATTR_DMOD(x) (((x)&0x001F)<<3) ++#define MCF_EDMA_TCD9_ATTR_SSIZE(x) (((x)&0x0007)<<8) ++#define MCF_EDMA_TCD9_ATTR_SMOD(x) (((x)&0x001F)<<11) ++ ++/* Bit definitions and macros for TCD9_SOFF */ ++#define MCF_EDMA_TCD9_SOFF_SOFF(x) (x) ++ ++/* Bit definitions and macros for TCD9_NBYTES */ ++#define MCF_EDMA_TCD9_NBYTES_NBYTES(x) (x) ++ ++/* Bit definitions and macros for TCD9_SLAST */ ++#define MCF_EDMA_TCD9_SLAST_SLAST(x) (x) ++ ++/* Bit definitions and macros for TCD9_DADDR */ ++#define MCF_EDMA_TCD9_DADDR_DADDR(x) (x) ++ ++/* Bit definitions and macros for TCD9_CITER_ELINK */ ++#define MCF_EDMA_TCD9_CITER_ELINK_CITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD9_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD9_CITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD9_CITER */ ++#define MCF_EDMA_TCD9_CITER_CITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD9_CITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD9_DOFF */ ++#define MCF_EDMA_TCD9_DOFF_DOFF(x) (x) ++ ++/* Bit definitions and macros for TCD9_DLAST_SGA */ ++#define MCF_EDMA_TCD9_DLAST_SGA_DLAST_SGA(x) (x) ++ ++/* Bit definitions and macros for TCD9_BITER_ELINK */ ++#define MCF_EDMA_TCD9_BITER_ELINK_BITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD9_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD9_BITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD9_BITER */ ++#define MCF_EDMA_TCD9_BITER_BITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD9_BITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD9_CSR */ ++#define MCF_EDMA_TCD9_CSR_START (0x0001) ++#define MCF_EDMA_TCD9_CSR_INT_MAJOR (0x0002) ++#define MCF_EDMA_TCD9_CSR_INT_HALF (0x0004) ++#define MCF_EDMA_TCD9_CSR_D_REQ (0x0008) ++#define MCF_EDMA_TCD9_CSR_E_SG (0x0010) ++#define MCF_EDMA_TCD9_CSR_E_LINK (0x0020) ++#define MCF_EDMA_TCD9_CSR_ACTIVE (0x0040) ++#define MCF_EDMA_TCD9_CSR_DONE (0x0080) ++#define MCF_EDMA_TCD9_CSR_LINKCH(x) (((x)&0x003F)<<8) ++#define MCF_EDMA_TCD9_CSR_BWC(x) (((x)&0x0003)<<14) ++ ++/* Bit definitions and macros for TCD10_SADDR */ ++#define MCF_EDMA_TCD10_SADDR_SADDR(x) (x) ++ ++/* Bit definitions and macros for TCD10_ATTR */ ++#define MCF_EDMA_TCD10_ATTR_DSIZE(x) (((x)&0x0007)) ++#define MCF_EDMA_TCD10_ATTR_DMOD(x) (((x)&0x001F)<<3) ++#define MCF_EDMA_TCD10_ATTR_SSIZE(x) (((x)&0x0007)<<8) ++#define MCF_EDMA_TCD10_ATTR_SMOD(x) (((x)&0x001F)<<11) ++ ++/* Bit definitions and macros for TCD10_SOFF */ ++#define MCF_EDMA_TCD10_SOFF_SOFF(x) (x) ++ ++/* Bit definitions and macros for TCD10_NBYTES */ ++#define MCF_EDMA_TCD10_NBYTES_NBYTES(x) (x) ++ ++/* Bit definitions and macros for TCD10_SLAST */ ++#define MCF_EDMA_TCD10_SLAST_SLAST(x) (x) ++ ++/* Bit definitions and macros for TCD10_DADDR */ ++#define MCF_EDMA_TCD10_DADDR_DADDR(x) (x) ++ ++/* Bit definitions and macros for TCD10_CITER_ELINK */ ++#define MCF_EDMA_TCD10_CITER_ELINK_CITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD10_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD10_CITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD10_CITER */ ++#define MCF_EDMA_TCD10_CITER_CITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD10_CITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD10_DOFF */ ++#define MCF_EDMA_TCD10_DOFF_DOFF(x) (x) ++ ++/* Bit definitions and macros for TCD10_DLAST_SGA */ ++#define MCF_EDMA_TCD10_DLAST_SGA_DLAST_SGA(x) (x) ++ ++/* Bit definitions and macros for TCD10_BITER */ ++#define MCF_EDMA_TCD10_BITER_BITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD10_BITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD10_BITER_ELINK */ ++#define MCF_EDMA_TCD10_BITER_ELINK_BITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD10_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD10_BITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD10_CSR */ ++#define MCF_EDMA_TCD10_CSR_START (0x0001) ++#define MCF_EDMA_TCD10_CSR_INT_MAJOR (0x0002) ++#define MCF_EDMA_TCD10_CSR_INT_HALF (0x0004) ++#define MCF_EDMA_TCD10_CSR_D_REQ (0x0008) ++#define MCF_EDMA_TCD10_CSR_E_SG (0x0010) ++#define MCF_EDMA_TCD10_CSR_E_LINK (0x0020) ++#define MCF_EDMA_TCD10_CSR_ACTIVE (0x0040) ++#define MCF_EDMA_TCD10_CSR_DONE (0x0080) ++#define MCF_EDMA_TCD10_CSR_LINKCH(x) (((x)&0x003F)<<8) ++#define MCF_EDMA_TCD10_CSR_BWC(x) (((x)&0x0003)<<14) ++ ++/* Bit definitions and macros for TCD11_SADDR */ ++#define MCF_EDMA_TCD11_SADDR_SADDR(x) (x) ++ ++/* Bit definitions and macros for TCD11_ATTR */ ++#define MCF_EDMA_TCD11_ATTR_DSIZE(x) (((x)&0x0007)) ++#define MCF_EDMA_TCD11_ATTR_DMOD(x) (((x)&0x001F)<<3) ++#define MCF_EDMA_TCD11_ATTR_SSIZE(x) (((x)&0x0007)<<8) ++#define MCF_EDMA_TCD11_ATTR_SMOD(x) (((x)&0x001F)<<11) ++ ++/* Bit definitions and macros for TCD11_SOFF */ ++#define MCF_EDMA_TCD11_SOFF_SOFF(x) (x) ++ ++/* Bit definitions and macros for TCD11_NBYTES */ ++#define MCF_EDMA_TCD11_NBYTES_NBYTES(x) (x) ++ ++/* Bit definitions and macros for TCD11_SLAST */ ++#define MCF_EDMA_TCD11_SLAST_SLAST(x) (x) ++ ++/* Bit definitions and macros for TCD11_DADDR */ ++#define MCF_EDMA_TCD11_DADDR_DADDR(x) (x) ++ ++/* Bit definitions and macros for TCD11_CITER */ ++#define MCF_EDMA_TCD11_CITER_CITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD11_CITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD11_CITER_ELINK */ ++#define MCF_EDMA_TCD11_CITER_ELINK_CITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD11_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD11_CITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD11_DOFF */ ++#define MCF_EDMA_TCD11_DOFF_DOFF(x) (x) ++ ++/* Bit definitions and macros for TCD11_DLAST_SGA */ ++#define MCF_EDMA_TCD11_DLAST_SGA_DLAST_SGA(x) (x) ++ ++/* Bit definitions and macros for TCD11_BITER */ ++#define MCF_EDMA_TCD11_BITER_BITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD11_BITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD11_BITER_ELINK */ ++#define MCF_EDMA_TCD11_BITER_ELINK_BITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD11_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD11_BITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD11_CSR */ ++#define MCF_EDMA_TCD11_CSR_START (0x0001) ++#define MCF_EDMA_TCD11_CSR_INT_MAJOR (0x0002) ++#define MCF_EDMA_TCD11_CSR_INT_HALF (0x0004) ++#define MCF_EDMA_TCD11_CSR_D_REQ (0x0008) ++#define MCF_EDMA_TCD11_CSR_E_SG (0x0010) ++#define MCF_EDMA_TCD11_CSR_E_LINK (0x0020) ++#define MCF_EDMA_TCD11_CSR_ACTIVE (0x0040) ++#define MCF_EDMA_TCD11_CSR_DONE (0x0080) ++#define MCF_EDMA_TCD11_CSR_LINKCH(x) (((x)&0x003F)<<8) ++#define MCF_EDMA_TCD11_CSR_BWC(x) (((x)&0x0003)<<14) ++ ++/* Bit definitions and macros for TCD12_SADDR */ ++#define MCF_EDMA_TCD12_SADDR_SADDR(x) (x) ++ ++/* Bit definitions and macros for TCD12_ATTR */ ++#define MCF_EDMA_TCD12_ATTR_DSIZE(x) (((x)&0x0007)) ++#define MCF_EDMA_TCD12_ATTR_DMOD(x) (((x)&0x001F)<<3) ++#define MCF_EDMA_TCD12_ATTR_SSIZE(x) (((x)&0x0007)<<8) ++#define MCF_EDMA_TCD12_ATTR_SMOD(x) (((x)&0x001F)<<11) ++ ++/* Bit definitions and macros for TCD12_SOFF */ ++#define MCF_EDMA_TCD12_SOFF_SOFF(x) (x) ++ ++/* Bit definitions and macros for TCD12_NBYTES */ ++#define MCF_EDMA_TCD12_NBYTES_NBYTES(x) (x) ++ ++/* Bit definitions and macros for TCD12_SLAST */ ++#define MCF_EDMA_TCD12_SLAST_SLAST(x) (x) ++ ++/* Bit definitions and macros for TCD12_DADDR */ ++#define MCF_EDMA_TCD12_DADDR_DADDR(x) (x) ++ ++/* Bit definitions and macros for TCD12_CITER */ ++#define MCF_EDMA_TCD12_CITER_CITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD12_CITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD12_CITER_ELINK */ ++#define MCF_EDMA_TCD12_CITER_ELINK_CITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD12_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD12_CITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD12_DOFF */ ++#define MCF_EDMA_TCD12_DOFF_DOFF(x) (x) ++ ++/* Bit definitions and macros for TCD12_DLAST_SGA */ ++#define MCF_EDMA_TCD12_DLAST_SGA_DLAST_SGA(x) (x) ++ ++/* Bit definitions and macros for TCD12_BITER */ ++#define MCF_EDMA_TCD12_BITER_BITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD12_BITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD12_BITER_ELINK */ ++#define MCF_EDMA_TCD12_BITER_ELINK_BITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD12_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD12_BITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD12_CSR */ ++#define MCF_EDMA_TCD12_CSR_START (0x0001) ++#define MCF_EDMA_TCD12_CSR_INT_MAJOR (0x0002) ++#define MCF_EDMA_TCD12_CSR_INT_HALF (0x0004) ++#define MCF_EDMA_TCD12_CSR_D_REQ (0x0008) ++#define MCF_EDMA_TCD12_CSR_E_SG (0x0010) ++#define MCF_EDMA_TCD12_CSR_E_LINK (0x0020) ++#define MCF_EDMA_TCD12_CSR_ACTIVE (0x0040) ++#define MCF_EDMA_TCD12_CSR_DONE (0x0080) ++#define MCF_EDMA_TCD12_CSR_LINKCH(x) (((x)&0x003F)<<8) ++#define MCF_EDMA_TCD12_CSR_BWC(x) (((x)&0x0003)<<14) ++ ++/* Bit definitions and macros for TCD13_SADDR */ ++#define MCF_EDMA_TCD13_SADDR_SADDR(x) (x) ++ ++/* Bit definitions and macros for TCD13_ATTR */ ++#define MCF_EDMA_TCD13_ATTR_DSIZE(x) (((x)&0x0007)) ++#define MCF_EDMA_TCD13_ATTR_DMOD(x) (((x)&0x001F)<<3) ++#define MCF_EDMA_TCD13_ATTR_SSIZE(x) (((x)&0x0007)<<8) ++#define MCF_EDMA_TCD13_ATTR_SMOD(x) (((x)&0x001F)<<11) ++ ++/* Bit definitions and macros for TCD13_SOFF */ ++#define MCF_EDMA_TCD13_SOFF_SOFF(x) (x) ++ ++/* Bit definitions and macros for TCD13_NBYTES */ ++#define MCF_EDMA_TCD13_NBYTES_NBYTES(x) (x) ++ ++/* Bit definitions and macros for TCD13_SLAST */ ++#define MCF_EDMA_TCD13_SLAST_SLAST(x) (x) ++ ++/* Bit definitions and macros for TCD13_DADDR */ ++#define MCF_EDMA_TCD13_DADDR_DADDR(x) (x) ++ ++/* Bit definitions and macros for TCD13_CITER_ELINK */ ++#define MCF_EDMA_TCD13_CITER_ELINK_CITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD13_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD13_CITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD13_CITER */ ++#define MCF_EDMA_TCD13_CITER_CITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD13_CITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD13_DOFF */ ++#define MCF_EDMA_TCD13_DOFF_DOFF(x) (x) ++ ++/* Bit definitions and macros for TCD13_DLAST_SGA */ ++#define MCF_EDMA_TCD13_DLAST_SGA_DLAST_SGA(x) (x) ++ ++/* Bit definitions and macros for TCD13_BITER_ELINK */ ++#define MCF_EDMA_TCD13_BITER_ELINK_BITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD13_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD13_BITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD13_BITER */ ++#define MCF_EDMA_TCD13_BITER_BITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD13_BITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD13_CSR */ ++#define MCF_EDMA_TCD13_CSR_START (0x0001) ++#define MCF_EDMA_TCD13_CSR_INT_MAJOR (0x0002) ++#define MCF_EDMA_TCD13_CSR_INT_HALF (0x0004) ++#define MCF_EDMA_TCD13_CSR_D_REQ (0x0008) ++#define MCF_EDMA_TCD13_CSR_E_SG (0x0010) ++#define MCF_EDMA_TCD13_CSR_E_LINK (0x0020) ++#define MCF_EDMA_TCD13_CSR_ACTIVE (0x0040) ++#define MCF_EDMA_TCD13_CSR_DONE (0x0080) ++#define MCF_EDMA_TCD13_CSR_LINKCH(x) (((x)&0x003F)<<8) ++#define MCF_EDMA_TCD13_CSR_BWC(x) (((x)&0x0003)<<14) ++ ++/* Bit definitions and macros for TCD14_SADDR */ ++#define MCF_EDMA_TCD14_SADDR_SADDR(x) (x) ++ ++/* Bit definitions and macros for TCD14_ATTR */ ++#define MCF_EDMA_TCD14_ATTR_DSIZE(x) (((x)&0x0007)) ++#define MCF_EDMA_TCD14_ATTR_DMOD(x) (((x)&0x001F)<<3) ++#define MCF_EDMA_TCD14_ATTR_SSIZE(x) (((x)&0x0007)<<8) ++#define MCF_EDMA_TCD14_ATTR_SMOD(x) (((x)&0x001F)<<11) ++ ++/* Bit definitions and macros for TCD14_SOFF */ ++#define MCF_EDMA_TCD14_SOFF_SOFF(x) (x) ++ ++/* Bit definitions and macros for TCD14_NBYTES */ ++#define MCF_EDMA_TCD14_NBYTES_NBYTES(x) (x) ++ ++/* Bit definitions and macros for TCD14_SLAST */ ++#define MCF_EDMA_TCD14_SLAST_SLAST(x) (x) ++ ++/* Bit definitions and macros for TCD14_DADDR */ ++#define MCF_EDMA_TCD14_DADDR_DADDR(x) (x) ++ ++/* Bit definitions and macros for TCD14_CITER */ ++#define MCF_EDMA_TCD14_CITER_CITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD14_CITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD14_CITER_ELINK */ ++#define MCF_EDMA_TCD14_CITER_ELINK_CITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD14_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD14_CITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD14_DOFF */ ++#define MCF_EDMA_TCD14_DOFF_DOFF(x) (x) ++ ++/* Bit definitions and macros for TCD14_DLAST_SGA */ ++#define MCF_EDMA_TCD14_DLAST_SGA_DLAST_SGA(x) (x) ++ ++/* Bit definitions and macros for TCD14_BITER_ELINK */ ++#define MCF_EDMA_TCD14_BITER_ELINK_BITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD14_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD14_BITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD14_BITER */ ++#define MCF_EDMA_TCD14_BITER_BITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD14_BITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD14_CSR */ ++#define MCF_EDMA_TCD14_CSR_START (0x0001) ++#define MCF_EDMA_TCD14_CSR_INT_MAJOR (0x0002) ++#define MCF_EDMA_TCD14_CSR_INT_HALF (0x0004) ++#define MCF_EDMA_TCD14_CSR_D_REQ (0x0008) ++#define MCF_EDMA_TCD14_CSR_E_SG (0x0010) ++#define MCF_EDMA_TCD14_CSR_E_LINK (0x0020) ++#define MCF_EDMA_TCD14_CSR_ACTIVE (0x0040) ++#define MCF_EDMA_TCD14_CSR_DONE (0x0080) ++#define MCF_EDMA_TCD14_CSR_LINKCH(x) (((x)&0x003F)<<8) ++#define MCF_EDMA_TCD14_CSR_BWC(x) (((x)&0x0003)<<14) ++ ++/* Bit definitions and macros for TCD15_SADDR */ ++#define MCF_EDMA_TCD15_SADDR_SADDR(x) (x) ++ ++/* Bit definitions and macros for TCD15_ATTR */ ++#define MCF_EDMA_TCD15_ATTR_DSIZE(x) (((x)&0x0007)) ++#define MCF_EDMA_TCD15_ATTR_DMOD(x) (((x)&0x001F)<<3) ++#define MCF_EDMA_TCD15_ATTR_SSIZE(x) (((x)&0x0007)<<8) ++#define MCF_EDMA_TCD15_ATTR_SMOD(x) (((x)&0x001F)<<11) ++ ++/* Bit definitions and macros for TCD15_SOFF */ ++#define MCF_EDMA_TCD15_SOFF_SOFF(x) (x) ++ ++/* Bit definitions and macros for TCD15_NBYTES */ ++#define MCF_EDMA_TCD15_NBYTES_NBYTES(x) (x) ++ ++/* Bit definitions and macros for TCD15_SLAST */ ++#define MCF_EDMA_TCD15_SLAST_SLAST(x) (x) ++ ++/* Bit definitions and macros for TCD15_DADDR */ ++#define MCF_EDMA_TCD15_DADDR_DADDR(x) (x) ++ ++/* Bit definitions and macros for TCD15_CITER_ELINK */ ++#define MCF_EDMA_TCD15_CITER_ELINK_CITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD15_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD15_CITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD15_CITER */ ++#define MCF_EDMA_TCD15_CITER_CITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD15_CITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD15_DOFF */ ++#define MCF_EDMA_TCD15_DOFF_DOFF(x) (x) ++ ++/* Bit definitions and macros for TCD15_DLAST_SGA */ ++#define MCF_EDMA_TCD15_DLAST_SGA_DLAST_SGA(x) (x) ++ ++/* Bit definitions and macros for TCD15_BITER */ ++#define MCF_EDMA_TCD15_BITER_BITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD15_BITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD15_BITER_ELINK */ ++#define MCF_EDMA_TCD15_BITER_ELINK_BITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD15_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD15_BITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD15_CSR */ ++#define MCF_EDMA_TCD15_CSR_START (0x0001) ++#define MCF_EDMA_TCD15_CSR_INT_MAJOR (0x0002) ++#define MCF_EDMA_TCD15_CSR_INT_HALF (0x0004) ++#define MCF_EDMA_TCD15_CSR_D_REQ (0x0008) ++#define MCF_EDMA_TCD15_CSR_E_SG (0x0010) ++#define MCF_EDMA_TCD15_CSR_E_LINK (0x0020) ++#define MCF_EDMA_TCD15_CSR_ACTIVE (0x0040) ++#define MCF_EDMA_TCD15_CSR_DONE (0x0080) ++#define MCF_EDMA_TCD15_CSR_LINKCH(x) (((x)&0x003F)<<8) ++#define MCF_EDMA_TCD15_CSR_BWC(x) (((x)&0x0003)<<14) ++ ++#endif /* __MCF5445X_EDMA_H__ */ +--- /dev/null ++++ b/arch/m68k/include/asm/mcf5445x_eport.h +@@ -0,0 +1,117 @@ ++/* ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * Kurt Mahan kmahan@freescale.com ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#ifndef __MCF5445X_EPORT_H__ ++#define __MCF5445X_EPORT_H__ ++ ++/********************************************************************* ++* ++* Edge Port Module (EPORT) ++* ++*********************************************************************/ ++ ++/* Register read/write macros */ ++#define MCF_EPORT_EPPAR MCF_REG16(0xFC094000) ++#define MCF_EPORT_EPDDR MCF_REG08(0xFC094002) ++#define MCF_EPORT_EPIER MCF_REG08(0xFC094003) ++#define MCF_EPORT_EPDR MCF_REG08(0xFC094004) ++#define MCF_EPORT_EPPDR MCF_REG08(0xFC094005) ++#define MCF_EPORT_EPFR MCF_REG08(0xFC094006) ++ ++/* Bit definitions and macros for EPPAR */ ++#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2) ++#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4) ++#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6) ++#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8) ++#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10) ++#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12) ++#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14) ++#define MCF_EPORT_EPPAR_LEVEL (0) ++#define MCF_EPORT_EPPAR_RISING (1) ++#define MCF_EPORT_EPPAR_FALLING (2) ++#define MCF_EPORT_EPPAR_BOTH (3) ++#define MCF_EPORT_EPPAR_EPPA7_LEVEL (0x0000) ++#define MCF_EPORT_EPPAR_EPPA7_RISING (0x4000) ++#define MCF_EPORT_EPPAR_EPPA7_FALLING (0x8000) ++#define MCF_EPORT_EPPAR_EPPA7_BOTH (0xC000) ++#define MCF_EPORT_EPPAR_EPPA6_LEVEL (0x0000) ++#define MCF_EPORT_EPPAR_EPPA6_RISING (0x1000) ++#define MCF_EPORT_EPPAR_EPPA6_FALLING (0x2000) ++#define MCF_EPORT_EPPAR_EPPA6_BOTH (0x3000) ++#define MCF_EPORT_EPPAR_EPPA5_LEVEL (0x0000) ++#define MCF_EPORT_EPPAR_EPPA5_RISING (0x0400) ++#define MCF_EPORT_EPPAR_EPPA5_FALLING (0x0800) ++#define MCF_EPORT_EPPAR_EPPA5_BOTH (0x0C00) ++#define MCF_EPORT_EPPAR_EPPA4_LEVEL (0x0000) ++#define MCF_EPORT_EPPAR_EPPA4_RISING (0x0100) ++#define MCF_EPORT_EPPAR_EPPA4_FALLING (0x0200) ++#define MCF_EPORT_EPPAR_EPPA4_BOTH (0x0300) ++#define MCF_EPORT_EPPAR_EPPA3_LEVEL (0x0000) ++#define MCF_EPORT_EPPAR_EPPA3_RISING (0x0040) ++#define MCF_EPORT_EPPAR_EPPA3_FALLING (0x0080) ++#define MCF_EPORT_EPPAR_EPPA3_BOTH (0x00C0) ++#define MCF_EPORT_EPPAR_EPPA2_LEVEL (0x0000) ++#define MCF_EPORT_EPPAR_EPPA2_RISING (0x0010) ++#define MCF_EPORT_EPPAR_EPPA2_FALLING (0x0020) ++#define MCF_EPORT_EPPAR_EPPA2_BOTH (0x0030) ++#define MCF_EPORT_EPPAR_EPPA1_LEVEL (0x0000) ++#define MCF_EPORT_EPPAR_EPPA1_RISING (0x0004) ++#define MCF_EPORT_EPPAR_EPPA1_FALLING (0x0008) ++#define MCF_EPORT_EPPAR_EPPA1_BOTH (0x000C) ++ ++/* Bit definitions and macros for EPDDR */ ++#define MCF_EPORT_EPDDR_EPDD1 (0x02) ++#define MCF_EPORT_EPDDR_EPDD2 (0x04) ++#define MCF_EPORT_EPDDR_EPDD3 (0x08) ++#define MCF_EPORT_EPDDR_EPDD4 (0x10) ++#define MCF_EPORT_EPDDR_EPDD5 (0x20) ++#define MCF_EPORT_EPDDR_EPDD6 (0x40) ++#define MCF_EPORT_EPDDR_EPDD7 (0x80) ++ ++/* Bit definitions and macros for EPIER */ ++#define MCF_EPORT_EPIER_EPIE1 (0x02) ++#define MCF_EPORT_EPIER_EPIE2 (0x04) ++#define MCF_EPORT_EPIER_EPIE3 (0x08) ++#define MCF_EPORT_EPIER_EPIE4 (0x10) ++#define MCF_EPORT_EPIER_EPIE5 (0x20) ++#define MCF_EPORT_EPIER_EPIE6 (0x40) ++#define MCF_EPORT_EPIER_EPIE7 (0x80) ++ ++/* Bit definitions and macros for EPDR */ ++#define MCF_EPORT_EPDR_EPD1 (0x02) ++#define MCF_EPORT_EPDR_EPD2 (0x04) ++#define MCF_EPORT_EPDR_EPD3 (0x08) ++#define MCF_EPORT_EPDR_EPD4 (0x10) ++#define MCF_EPORT_EPDR_EPD5 (0x20) ++#define MCF_EPORT_EPDR_EPD6 (0x40) ++#define MCF_EPORT_EPDR_EPD7 (0x80) ++ ++/* Bit definitions and macros for EPPDR */ ++#define MCF_EPORT_EPPDR_EPPD1 (0x02) ++#define MCF_EPORT_EPPDR_EPPD2 (0x04) ++#define MCF_EPORT_EPPDR_EPPD3 (0x08) ++#define MCF_EPORT_EPPDR_EPPD4 (0x10) ++#define MCF_EPORT_EPPDR_EPPD5 (0x20) ++#define MCF_EPORT_EPPDR_EPPD6 (0x40) ++#define MCF_EPORT_EPPDR_EPPD7 (0x80) ++ ++/* Bit definitions and macros for EPFR */ ++#define MCF_EPORT_EPFR_EPF1 (0x02) ++#define MCF_EPORT_EPFR_EPF2 (0x04) ++#define MCF_EPORT_EPFR_EPF3 (0x08) ++#define MCF_EPORT_EPFR_EPF4 (0x10) ++#define MCF_EPORT_EPFR_EPF5 (0x20) ++#define MCF_EPORT_EPFR_EPF6 (0x40) ++#define MCF_EPORT_EPFR_EPF7 (0x80) ++ ++/********************************************************************/ ++ ++#endif /* __MCF5445X_EPORT_H__ */ +--- /dev/null ++++ b/arch/m68k/include/asm/mcf5445x_fbcs.h +@@ -0,0 +1,200 @@ ++/* ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * Matt Waddel Matt.Waddel@freescale.com ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#ifndef __MCF5445X_FBCS_H__ ++#define __MCF5445X_FBCS_H__ ++ ++/********************************************************************* ++* ++* FlexBus Chip Selects (FBCS) ++* ++*********************************************************************/ ++ ++/* Register read/write macros */ ++#define MCF_FBCS_CSAR0 MCF_REG32(0xFC008000) /* Chip-select Addr Register */ ++#define MCF_FBCS_CSMR0 MCF_REG32(0xFC008004) /* Chip-select Mask Register */ ++#define MCF_FBCS_CSCR0 MCF_REG32(0xFC008008) /* Chip-select Cntl Register */ ++#define MCF_FBCS_CSAR1 MCF_REG32(0xFC00800C) /* Chip-select Addr Register */ ++#define MCF_FBCS_CSMR1 MCF_REG32(0xFC008010) /* Chip-select Mask Register */ ++#define MCF_FBCS_CSCR1 MCF_REG32(0xFC008014) /* Chip-select Cntl Register */ ++#define MCF_FBCS_CSAR2 MCF_REG32(0xFC008018) /* Chip-select Addr Register */ ++#define MCF_FBCS_CSMR2 MCF_REG32(0xFC00801C) /* Chip-select Mask Register */ ++#define MCF_FBCS_CSCR2 MCF_REG32(0xFC008020) /* Chip-select Cntl Register */ ++#define MCF_FBCS_CSAR3 MCF_REG32(0xFC008024) /* Chip-select Addr Register */ ++#define MCF_FBCS_CSMR3 MCF_REG32(0xFC008028) /* Chip-select Mask Register */ ++#define MCF_FBCS_CSCR3 MCF_REG32(0xFC00802C) /* Chip-select Cntl Register */ ++ ++/* Parameterized register read/write macros for multiple registers */ ++/* Chip-select Addr Register */ ++#define MCF_FBCS_CSAR(x) MCF_REG32(0xFC008000+((x)*0x00C)) ++/* Chip-select Mask Register */ ++#define MCF_FBCS_CSMR(x) MCF_REG32(0xFC008004+((x)*0x00C)) ++/* Chip-select Cntl Register */ ++#define MCF_FBCS_CSCR(x) MCF_REG32(0xFC008008+((x)*0x00C)) ++ ++/* Bit definitions and macros for CSAR group */ ++#define MCF_FBCS_CSAR_BA(x) ((x)&0xFFFF0000) ++ ++/* Bit definitions and macros for CSAR0 */ ++#define MCF_FBCS_CSAR0_BA(x) ((x)&0xFFFF0000) ++ ++/* Bit definitions and macros for CSMR group */ ++#define MCF_FBCS_CSMR_V (0x00000001) /* Valid bit */ ++#define MCF_FBCS_CSMR_WP (0x00000100) /* Write protect */ ++#define MCF_FBCS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16) /* Base addr mask */ ++#define MCF_FBCS_CSMR_BAM_4G (0xFFFF0000) ++#define MCF_FBCS_CSMR_BAM_2G (0x7FFF0000) ++#define MCF_FBCS_CSMR_BAM_1G (0x3FFF0000) ++#define MCF_FBCS_CSMR_BAM_1024M (0x3FFF0000) ++#define MCF_FBCS_CSMR_BAM_512M (0x1FFF0000) ++#define MCF_FBCS_CSMR_BAM_256M (0x0FFF0000) ++#define MCF_FBCS_CSMR_BAM_128M (0x07FF0000) ++#define MCF_FBCS_CSMR_BAM_64M (0x03FF0000) ++#define MCF_FBCS_CSMR_BAM_32M (0x01FF0000) ++#define MCF_FBCS_CSMR_BAM_16M (0x00FF0000) ++#define MCF_FBCS_CSMR_BAM_8M (0x007F0000) ++#define MCF_FBCS_CSMR_BAM_4M (0x003F0000) ++#define MCF_FBCS_CSMR_BAM_2M (0x001F0000) ++#define MCF_FBCS_CSMR_BAM_1M (0x000F0000) ++#define MCF_FBCS_CSMR_BAM_1024K (0x000F0000) ++#define MCF_FBCS_CSMR_BAM_512K (0x00070000) ++#define MCF_FBCS_CSMR_BAM_256K (0x00030000) ++#define MCF_FBCS_CSMR_BAM_128K (0x00010000) ++#define MCF_FBCS_CSMR_BAM_64K (0x00000000) ++ ++/* Bit definitions and macros for CSMR0 */ ++#define MCF_FBCS_CSMR0_V (0x00000001) /* Valid bit */ ++#define MCF_FBCS_CSMR0_WP (0x00000100) /* Write protect */ ++#define MCF_FBCS_CSMR0_BAM(x) (((x)&0x0000FFFF)<<16) /* Base addr mask */ ++#define MCF_FBCS_CSMR0_BAM_4G (0xFFFF0000) ++#define MCF_FBCS_CSMR0_BAM_2G (0x7FFF0000) ++#define MCF_FBCS_CSMR0_BAM_1G (0x3FFF0000) ++#define MCF_FBCS_CSMR0_BAM_1024M (0x3FFF0000) ++#define MCF_FBCS_CSMR0_BAM_512M (0x1FFF0000) ++#define MCF_FBCS_CSMR0_BAM_256M (0x0FFF0000) ++#define MCF_FBCS_CSMR0_BAM_128M (0x07FF0000) ++#define MCF_FBCS_CSMR0_BAM_64M (0x03FF0000) ++#define MCF_FBCS_CSMR0_BAM_32M (0x01FF0000) ++#define MCF_FBCS_CSMR0_BAM_16M (0x00FF0000) ++#define MCF_FBCS_CSMR0_BAM_8M (0x007F0000) ++#define MCF_FBCS_CSMR0_BAM_4M (0x003F0000) ++#define MCF_FBCS_CSMR0_BAM_2M (0x001F0000) ++#define MCF_FBCS_CSMR0_BAM_1M (0x000F0000) ++#define MCF_FBCS_CSMR0_BAM_1024K (0x000F0000) ++#define MCF_FBCS_CSMR0_BAM_512K (0x00070000) ++#define MCF_FBCS_CSMR0_BAM_256K (0x00030000) ++#define MCF_FBCS_CSMR0_BAM_128K (0x00010000) ++#define MCF_FBCS_CSMR0_BAM_64K (0x00000000) ++ ++/* Bit definitions and macros for CSCR group */ ++#define MCF_FBCS_CSCR_BSTW (0x00000008) /* Burst-write enable */ ++#define MCF_FBCS_CSCR_BSTR (0x00000010) /* Burst-read enable */ ++#define MCF_FBCS_CSCR_BEM (0x00000020) /* Byte-enable mode */ ++#define MCF_FBCS_CSCR_PS(x) (((x)&0x00000003)<<6) /* Port size */ ++#define MCF_FBCS_CSCR_AA (0x00000100) /* Auto-acknowledge */ ++#define MCF_FBCS_CSCR_WS(x) (((x)&0x0000003F)<<10) /* Wait states */ ++/* Write address hold or deselect */ ++#define MCF_FBCS_CSCR_WRAH(x) (((x)&0x00000003)<<16) ++/* Read address hold or deselect */ ++#define MCF_FBCS_CSCR_RDAH(x) (((x)&0x00000003)<<18) ++#define MCF_FBCS_CSCR_ASET(x) (((x)&0x00000003)<<20) /* Address setup */ ++#define MCF_FBCS_CSCR_SWSEN (0x00800000) /* Secondary wait state enable */ ++/* Secondary wait states */ ++#define MCF_FBCS_CSCR_SWS(x) (((x)&0x0000003F)<<26) ++#define MCF_FBCS_CSCR_PS_8 (0x00000040) ++#define MCF_FBCS_CSCR_PS_16 (0x00000080) ++#define MCF_FBCS_CSCR_PS_32 (0x00000000) ++ ++/* Bit definitions and macros for CSCR0 */ ++#define MCF_FBCS_CSCR0_BSTW (0x00000008) /* Burst-write enable */ ++#define MCF_FBCS_CSCR0_BSTR (0x00000010) /* Burst-read enable */ ++#define MCF_FBCS_CSCR0_BEM (0x00000020) /* Byte-enable mode */ ++#define MCF_FBCS_CSCR0_PS(x) (((x)&0x00000003)<<6) /* Port size */ ++#define MCF_FBCS_CSCR0_AA (0x00000100) /* Auto-acknowledge */ ++#define MCF_FBCS_CSCR0_WS(x) (((x)&0x0000003F)<<10) /* Wait states */ ++/* Write address hold or deselect */ ++#define MCF_FBCS_CSCR0_WRAH(x) (((x)&0x00000003)<<16) ++/* Read address hold or deselect */ ++#define MCF_FBCS_CSCR0_RDAH(x) (((x)&0x00000003)<<18) ++#define MCF_FBCS_CSCR0_ASET(x) (((x)&0x00000003)<<20) /* Address setup */ ++#define MCF_FBCS_CSCR0_SWSEN (0x00800000) /* Secondary wait state enable */ ++/* Secondary wait states */ ++#define MCF_FBCS_CSCR0_SWS(x) (((x)&0x0000003F)<<26) ++#define MCF_FBCS_CSCR0_PS_8 (0x00000040) ++#define MCF_FBCS_CSCR0_PS_16 (0x00000080) ++#define MCF_FBCS_CSCR0_PS_32 (0x00000000) ++ ++/* Bit definitions and macros for CSMR1 */ ++#define MCF_FBCS_CSMR1_V (0x00000001) /* Valid bit */ ++#define MCF_FBCS_CSMR1_WP (0x00000100) /* Write protect */ ++#define MCF_FBCS_CSMR1_BAM(x) (((x)&0x0000FFFF)<<16) /* Base address mask */ ++ ++/* Bit definitions and macros for CSCR1 */ ++#define MCF_FBCS_CSCR1_BSTW (0x00000008) /* Burst-write enable */ ++#define MCF_FBCS_CSCR1_BSTR (0x00000010) /* Burst-read enable */ ++#define MCF_FBCS_CSCR1_BEM (0x00000020) /* Byte-enable mode */ ++#define MCF_FBCS_CSCR1_PS(x) (((x)&0x00000003)<<6) /* Port size */ ++#define MCF_FBCS_CSCR1_AA (0x00000100) /* Auto-acknowledge */ ++#define MCF_FBCS_CSCR1_WS(x) (((x)&0x0000003F)<<10) /* Wait states */ ++/* Write address hold or deselect */ ++#define MCF_FBCS_CSCR1_WRAH(x) (((x)&0x00000003)<<16) ++/* Read address hold or deselect */ ++#define MCF_FBCS_CSCR1_RDAH(x) (((x)&0x00000003)<<18) ++#define MCF_FBCS_CSCR1_ASET(x) (((x)&0x00000003)<<20) /* Address setup */ ++#define MCF_FBCS_CSCR1_SWSEN (0x00800000) /* Secondary wait state enable */ ++/* Secondary wait states */ ++#define MCF_FBCS_CSCR1_SWS(x) (((x)&0x0000003F)<<26) ++ ++/* Bit definitions and macros for CSMR2 */ ++#define MCF_FBCS_CSMR2_V (0x00000001) /* Valid bit */ ++#define MCF_FBCS_CSMR2_WP (0x00000100) /* Write protect */ ++#define MCF_FBCS_CSMR2_BAM(x) (((x)&0x0000FFFF)<<16) /* Base address mask */ ++ ++/* Bit definitions and macros for CSCR2 */ ++#define MCF_FBCS_CSCR2_BSTW (0x00000008) /* Burst-write enable */ ++#define MCF_FBCS_CSCR2_BSTR (0x00000010) /* Burst-read enable */ ++#define MCF_FBCS_CSCR2_BEM (0x00000020) /* Byte-enable mode */ ++#define MCF_FBCS_CSCR2_PS(x) (((x)&0x00000003)<<6) /* Port size */ ++#define MCF_FBCS_CSCR2_AA (0x00000100) /* Auto-acknowledge */ ++#define MCF_FBCS_CSCR2_WS(x) (((x)&0x0000003F)<<10) /* Wait states */ ++/* Write address hold or deselect */ ++#define MCF_FBCS_CSCR2_WRAH(x) (((x)&0x00000003)<<16) ++/* Read address hold or deselect */ ++#define MCF_FBCS_CSCR2_RDAH(x) (((x)&0x00000003)<<18) ++#define MCF_FBCS_CSCR2_ASET(x) (((x)&0x00000003)<<20) /* Address setup */ ++#define MCF_FBCS_CSCR2_SWSEN (0x00800000) /* Secondary wait state enable */ ++/* Secondary wait states */ ++#define MCF_FBCS_CSCR2_SWS(x) (((x)&0x0000003F)<<26) ++ ++/* Bit definitions and macros for CSMR3 */ ++#define MCF_FBCS_CSMR3_V (0x00000001) /* Valid bit */ ++#define MCF_FBCS_CSMR3_WP (0x00000100) /* Write protect */ ++#define MCF_FBCS_CSMR3_BAM(x) (((x)&0x0000FFFF)<<16) /* Base address mask */ ++ ++/* Bit definitions and macros for CSCR3 */ ++#define MCF_FBCS_CSCR3_BSTW (0x00000008) /* Burst-write enable */ ++#define MCF_FBCS_CSCR3_BSTR (0x00000010) /* Burst-read enable */ ++#define MCF_FBCS_CSCR3_BEM (0x00000020) /* Byte-enable mode */ ++#define MCF_FBCS_CSCR3_PS(x) (((x)&0x00000003)<<6) /* Port size */ ++#define MCF_FBCS_CSCR3_AA (0x00000100) /* Auto-acknowledge */ ++#define MCF_FBCS_CSCR3_WS(x) (((x)&0x0000003F)<<10) /* Wait states */ ++/* Write address hold or deselect */ ++#define MCF_FBCS_CSCR3_WRAH(x) (((x)&0x00000003)<<16) ++/* Read address hold or deselect */ ++#define MCF_FBCS_CSCR3_RDAH(x) (((x)&0x00000003)<<18) ++#define MCF_FBCS_CSCR3_ASET(x) (((x)&0x00000003)<<20) /* Address setup */ ++#define MCF_FBCS_CSCR3_SWSEN (0x00800000) /* Secondary wait state enable */ ++/* Secondary wait states */ ++#define MCF_FBCS_CSCR3_SWS(x) (((x)&0x0000003F)<<26) ++ ++/********************************************************************/ ++ ++#endif /* __MCF5445X_FBCS_H__ */ +--- /dev/null ++++ b/arch/m68k/include/asm/mcf5445x_gpio.h +@@ -0,0 +1,1411 @@ ++/* ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * Matt Waddel Matt.Waddel@freescale.com ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#ifndef __MCF5445X_GPIO_H__ ++#define __MCF5445X_GPIO_H__ ++ ++/********************************************************************* ++* ++* General Purpose I/O Module (GPIO) ++* ++*********************************************************************/ ++ ++/* Register read/write macros */ ++#define MCF_GPIO_PODR_FEC0H \ ++ MCF_REG08(0xFC0A4000) /* FEC0 High Port Output Data Register */ ++#define MCF_GPIO_PODR_FEC0L \ ++ MCF_REG08(0xFC0A4001) /* FEC0 Low Port Output Data Register */ ++#define MCF_GPIO_PODR_SSI \ ++ MCF_REG08(0xFC0A4002) /* SSI Port Output Data Register */ ++#define MCF_GPIO_PODR_FBCTL \ ++ MCF_REG08(0xFC0A4003) /* Flexbus Control Port Output Data Register */ ++/* Flexbus Byte Enable Port Output Data Register */ ++#define MCF_GPIO_PODR_BE MCF_REG08(0xFC0A4004) ++/* Flexbus Chip-Select Port Output Data Register */ ++#define MCF_GPIO_PODR_CS MCF_REG08(0xFC0A4005) ++#define MCF_GPIO_PODR_DMA \ ++ MCF_REG08(0xFC0A4006) /* DMA Port Output Data Register */ ++#define MCF_GPIO_PODR_FECI2C \ ++ MCF_REG08(0xFC0A4007) /* FEC1 / I2C Port Output Data Register */ ++#define MCF_GPIO_PODR_UART \ ++ MCF_REG08(0xFC0A4009) /* UART Port Output Data Register */ ++#define MCF_GPIO_PODR_DSPI \ ++ MCF_REG08(0xFC0A400A) /* DSPI Port Output Data Register */ ++#define MCF_GPIO_PODR_TIMER \ ++ MCF_REG08(0xFC0A400B) /* Timer Port Output Data Register */ ++#define MCF_GPIO_PODR_PCI \ ++ MCF_REG08(0xFC0A400C) /* PCI Port Output Data Register */ ++#define MCF_GPIO_PODR_USB \ ++ MCF_REG08(0xFC0A400D) /* USB Port Output Data Register */ ++#define MCF_GPIO_PODR_ATAH \ ++ MCF_REG08(0xFC0A400E) /* ATA High Port Output Data Register */ ++#define MCF_GPIO_PODR_ATAL \ ++ MCF_REG08(0xFC0A400F) /* ATA Low Port Output Data Register */ ++#define MCF_GPIO_PODR_FEC1H \ ++ MCF_REG08(0xFC0A4010) /* FEC1 High Port Output Data Register */ ++#define MCF_GPIO_PODR_FEC1L \ ++ MCF_REG08(0xFC0A4011) /* FEC1 Low Port Output Data Register */ ++#define MCF_GPIO_PODR_FBADH \ ++ MCF_REG08(0xFC0A4014) /* Flexbus AD High Port Output Data Register */ ++/* Flexbus AD Med-High Port Output Data Register */ ++#define MCF_GPIO_PODR_FBADMH MCF_REG08(0xFC0A4015) ++/* Flexbus AD Med-Low Port Output Data Register */ ++#define MCF_GPIO_PODR_FBADML MCF_REG08(0xFC0A4016) ++#define MCF_GPIO_PODR_FBADL \ ++ MCF_REG08(0xFC0A4017) /* Flexbus AD Low Port Output Data Register */ ++#define MCF_GPIO_PDDR_FEC0H \ ++ MCF_REG08(0xFC0A4018) /* FEC0 High Port Data Direction Register */ ++#define MCF_GPIO_PDDR_FEC0L \ ++ MCF_REG08(0xFC0A4019) /* FEC0 Low Port Data Direction Register */ ++#define MCF_GPIO_PDDR_SSI \ ++ MCF_REG08(0xFC0A401A) /* SSI Port Data Direction Register */ ++/* Flexbus Control Port Data Direction Register */ ++#define MCF_GPIO_PDDR_FBCTL MCF_REG08(0xFC0A401B) ++/* Flexbus Byte Enable Port Data Direction Register */ ++#define MCF_GPIO_PDDR_BE MCF_REG08(0xFC0A401C) ++/* Flexbus Chip-Select Port Data Direction Register */ ++#define MCF_GPIO_PDDR_CS MCF_REG08(0xFC0A401D) ++#define MCF_GPIO_PDDR_DMA \ ++ MCF_REG08(0xFC0A401E) /* DMA Port Data Direction Register */ ++#define MCF_GPIO_PDDR_FECI2C \ ++ MCF_REG08(0xFC0A401F) /* FEC1 / I2C Port Data Direction Register */ ++#define MCF_GPIO_PDDR_UART \ ++ MCF_REG08(0xFC0A4021) /* UART Port Data Direction Register */ ++#define MCF_GPIO_PDDR_DSPI \ ++ MCF_REG08(0xFC0A4022) /* DSPI Port Data Direction Register */ ++#define MCF_GPIO_PDDR_TIMER \ ++ MCF_REG08(0xFC0A4023) /* Timer Port Data Direction Register */ ++#define MCF_GPIO_PDDR_PCI \ ++ MCF_REG08(0xFC0A4024) /* PCI Port Data Direction Register */ ++#define MCF_GPIO_PDDR_USB \ ++ MCF_REG08(0xFC0A4025) /* USB Port Data Direction Register */ ++#define MCF_GPIO_PDDR_ATAH \ ++ MCF_REG08(0xFC0A4026) /* ATA High Port Data Direction Register */ ++#define MCF_GPIO_PDDR_ATAL \ ++ MCF_REG08(0xFC0A4027) /* ATA Low Port Data Direction Register */ ++#define MCF_GPIO_PDDR_FEC1H \ ++ MCF_REG08(0xFC0A4028) /* FEC1 High Port Data Direction Register */ ++#define MCF_GPIO_PDDR_FEC1L \ ++ MCF_REG08(0xFC0A4029) /* FEC1 Low Port Data Direction Register */ ++/* Flexbus AD High Port Data Direction Register */ ++#define MCF_GPIO_PDDR_FBADH MCF_REG08(0xFC0A402C) ++/* Flexbus AD Med-High Port Data Direction Register */ ++#define MCF_GPIO_PDDR_FBADMH MCF_REG08(0xFC0A402D) ++/* Flexbus AD Med-Low Port Data Direction Register */ ++#define MCF_GPIO_PDDR_FBADML MCF_REG08(0xFC0A402E) ++/* Flexbus AD Low Port Data Direction Register */ ++#define MCF_GPIO_PDDR_FBADL MCF_REG08(0xFC0A402F) ++#define MCF_GPIO_PPDSDR_FEC0H \ ++ MCF_REG08(0xFC0A4030) /* FEC0 High Port Pin Data/Set Data Register */ ++#define MCF_GPIO_PPDSDR_FEC0L \ ++ MCF_REG08(0xFC0A4031) /* FEC0 Low Port Clear Output Data Register */ ++#define MCF_GPIO_PPDSDR_SSI \ ++ MCF_REG08(0xFC0A4032) /* SSI Port Pin Data/Set Data Register */ ++/* Flexbus Control Port Pin Data/Set Data Register */ ++#define MCF_GPIO_PPDSDR_FBCTL MCF_REG08(0xFC0A4033) ++/* Flexbus Byte Enable Port Pin Data/Set Data Register */ ++#define MCF_GPIO_PPDSDR_BE MCF_REG08(0xFC0A4034) ++/* Flexbus Chip-Select Port Pin Data/Set Data Register */ ++#define MCF_GPIO_PPDSDR_CS MCF_REG08(0xFC0A4035) ++#define MCF_GPIO_PPDSDR_DMA \ ++ MCF_REG08(0xFC0A4036) /* DMA Port Pin Data/Set Data Register */ ++#define MCF_GPIO_PPDSDR_FECI2C \ ++ MCF_REG08(0xFC0A4037) /* FEC1 / I2C Port Pin Data/Set Data Register */ ++#define MCF_GPIO_PPDSDR_UART \ ++ MCF_REG08(0xFC0A4039) /* UART Port Pin Data/Set Data Register */ ++#define MCF_GPIO_PPDSDR_DSPI \ ++ MCF_REG08(0xFC0A403A) /* DSPI Port Pin Data/Set Data Register */ ++#define MCF_GPIO_PPDSDR_TIMER \ ++ MCF_REG08(0xFC0A403B) /* FTimer Port Pin Data/Set Data Register */ ++#define MCF_GPIO_PPDSDR_PCI \ ++ MCF_REG08(0xFC0A403C) /* PCI Port Pin Data/Set Data Register */ ++#define MCF_GPIO_PPDSDR_USB \ ++ MCF_REG08(0xFC0A403D) /* USB Port Pin Data/Set Data Register */ ++#define MCF_GPIO_PPDSDR_ATAH \ ++ MCF_REG08(0xFC0A403E) /* ATA High Port Pin Data/Set Data Register */ ++#define MCF_GPIO_PPDSDR_ATAL \ ++ MCF_REG08(0xFC0A403F) /* ATA Low Port Pin Data/Set Data Register */ ++#define MCF_GPIO_PPDSDR_FEC1H \ ++ MCF_REG08(0xFC0A4040) /* FEC1 High Port Pin Data/Set Data Register */ ++#define MCF_GPIO_PPDSDR_FEC1L \ ++ MCF_REG08(0xFC0A4041) /* FEC1 Low Port Pin Data/Set Data Register */ ++/* Flexbus AD High Port Pin Data/Set Data Register */ ++#define MCF_GPIO_PPDSDR_FBADH MCF_REG08(0xFC0A4044) ++/* Flexbus AD Med-High Port Pin Data/Set Data Register */ ++#define MCF_GPIO_PPDSDR_FBADMH MCF_REG08(0xFC0A4045) ++/* Flexbus AD Med-Low Port Pin Data/Set Data Register */ ++#define MCF_GPIO_PPDSDR_FBADML MCF_REG08(0xFC0A4046) ++/* Flexbus AD Low Port Pin Data/Set Data Register */ ++#define MCF_GPIO_PPDSDR_FBADL MCF_REG08(0xFC0A4047) ++#define MCF_GPIO_PCLRR_FEC0H \ ++ MCF_REG08(0xFC0A4048) /* FEC0 High Port Clear Output Data Register */ ++#define MCF_GPIO_PCLRR_FEC0L \ ++ MCF_REG08(0xFC0A4049) /* FEC0 Low Port Pin Data/Set Data Register */ ++#define MCF_GPIO_PCLRR_SSI \ ++ MCF_REG08(0xFC0A404A) /* SSI Port Clear Output Data Register */ ++/* Flexbus Control Port Clear Output Data Register */ ++#define MCF_GPIO_PCLRR_FBCTL MCF_REG08(0xFC0A404B) ++/* Flexbus Byte Enable Port Clear Output Data Register */ ++#define MCF_GPIO_PCLRR_BE MCF_REG08(0xFC0A404C) ++/* Flexbus Chip-Select Port Clear Output Data Register */ ++#define MCF_GPIO_PCLRR_CS MCF_REG08(0xFC0A404D) ++#define MCF_GPIO_PCLRR_DMA \ ++ MCF_REG08(0xFC0A404E) /* DMA Port Clear Output Data Register */ ++#define MCF_GPIO_PCLRR_FECI2C \ ++ MCF_REG08(0xFC0A404F) /* FEC1 / I2C Port Clear Output Data Register */ ++#define MCF_GPIO_PCLRR_UART \ ++ MCF_REG08(0xFC0A4051) /* UART Port Clear Output Data Register */ ++#define MCF_GPIO_PCLRR_DSPI \ ++ MCF_REG08(0xFC0A4052) /* DSPI Port Clear Output Data Register */ ++#define MCF_GPIO_PCLRR_TIMER \ ++ MCF_REG08(0xFC0A4053) /* Timer Port Clear Output Data Register */ ++#define MCF_GPIO_PCLRR_PCI \ ++ MCF_REG08(0xFC0A4054) /* PCI Port Clear Output Data Register */ ++#define MCF_GPIO_PCLRR_USB \ ++ MCF_REG08(0xFC0A4055) /* USB Port Clear Output Data Register */ ++#define MCF_GPIO_PCLRR_ATAH \ ++ MCF_REG08(0xFC0A4056) /* ATA High Port Clear Output Data Register */ ++#define MCF_GPIO_PCLRR_ATAL \ ++ MCF_REG08(0xFC0A4057) /* ATA Low Port Clear Output Data Register */ ++#define MCF_GPIO_PCLRR_FEC1H \ ++ MCF_REG08(0xFC0A4058) /* FEC1 High Port Clear Output Data Register */ ++#define MCF_GPIO_PCLRR_FEC1L \ ++ MCF_REG08(0xFC0A4059) /* FEC1 Low Port Clear Output Data Register */ ++/* Flexbus AD High Port Clear Output Data Register */ ++#define MCF_GPIO_PCLRR_FBADH MCF_REG08(0xFC0A405C) ++/* Flexbus AD Med-High Port Clear Output Data Register */ ++#define MCF_GPIO_PCLRR_FBADMH MCF_REG08(0xFC0A405D) ++/* Flexbus AD Med-Low Port Clear Output Data Register */ ++#define MCF_GPIO_PCLRR_FBADML MCF_REG08(0xFC0A405E) ++/* Flexbus AD Low Port Clear Output Data Register */ ++#define MCF_GPIO_PCLRR_FBADL MCF_REG08(0xFC0A405F) ++#define MCF_GPIO_PAR_FEC \ ++ MCF_REG08(0xFC0A4060) /* FEC Pin Assignment Register */ ++#define MCF_GPIO_PAR_DMA \ ++ MCF_REG08(0xFC0A4061) /* DMA Pin Assignment Register */ ++#define MCF_GPIO_PAR_FBCTL \ ++ MCF_REG08(0xFC0A4062) /* Flexbus Control Pin Assignment Register */ ++#define MCF_GPIO_PAR_DSPI \ ++ MCF_REG08(0xFC0A4063) /* DSPI Pin Assignment Register */ ++/* Flexbus Byte-Enable Pin Assignment Register */ ++#define MCF_GPIO_PAR_BE MCF_REG08(0xFC0A4064) ++/* Flexbus Chip-Select Pin Assignment Register */ ++#define MCF_GPIO_PAR_CS MCF_REG08(0xFC0A4065) ++#define MCF_GPIO_PAR_TIMER \ ++ MCF_REG08(0xFC0A4066) /* Time Pin Assignment Register */ ++#define MCF_GPIO_PAR_USB \ ++ MCF_REG08(0xFC0A4067) /* USB Pin Assignment Register */ ++#define MCF_GPIO_PAR_UART \ ++ MCF_REG08(0xFC0A4069) /* UART Pin Assignment Register */ ++#define MCF_GPIO_PAR_FECI2C \ ++ MCF_REG16(0xFC0A406A) /* FEC / I2C Pin Assignment Register */ ++#define MCF_GPIO_PAR_SSI \ ++ MCF_REG16(0xFC0A406C) /* SSI Pin Assignment Register */ ++#define MCF_GPIO_PAR_ATA \ ++ MCF_REG16(0xFC0A406E) /* ATA Pin Assignment Register */ ++#define MCF_GPIO_PAR_IRQ \ ++ MCF_REG08(0xFC0A4070) /* IRQ Pin Assignment Register */ ++#define MCF_GPIO_PAR_PCI \ ++ MCF_REG16(0xFC0A4072) /* PCI Pin Assignment Register */ ++#define MCF_GPIO_MSCR_SDRAM \ ++ MCF_REG08(0xFC0A4074) /* SDRAM Mode Select Control Register */ ++#define MCF_GPIO_MSCR_PCI \ ++ MCF_REG08(0xFC0A4075) /* PCI Mode Select Control Register */ ++#define MCF_GPIO_DSCR_I2C \ ++ MCF_REG08(0xFC0A4078) /* I2C Drive Strength Control Register */ ++#define MCF_GPIO_DSCR_FLEXBUS \ ++ MCF_REG08(0xFC0A4079) /* FLEXBUS Drive Strength Control Register */ ++#define MCF_GPIO_DSCR_FEC \ ++ MCF_REG08(0xFC0A407A) /* FEC Drive Strength Control Register */ ++#define MCF_GPIO_DSCR_UART \ ++ MCF_REG08(0xFC0A407B) /* UART Drive Strength Control Register */ ++#define MCF_GPIO_DSCR_DSPI \ ++ MCF_REG08(0xFC0A407C) /* DSPI Drive Strength Control Register */ ++#define MCF_GPIO_DSCR_TIMER \ ++ MCF_REG08(0xFC0A407D) /* TIMER Drive Strength Control Register */ ++#define MCF_GPIO_DSCR_SSI \ ++ MCF_REG08(0xFC0A407E) /* SSI Drive Strength Control Register */ ++#define MCF_GPIO_DSCR_DMA \ ++ MCF_REG08(0xFC0A407F) /* DMA Drive Strength Control Register */ ++#define MCF_GPIO_DSCR_DEBUG \ ++ MCF_REG08(0xFC0A4080) /* DEBUG Drive Strength Control Register */ ++#define MCF_GPIO_DSCR_RESET \ ++ MCF_REG08(0xFC0A4081) /* RESET Drive Strength Control Register */ ++#define MCF_GPIO_DSCR_IRQ \ ++ MCF_REG08(0xFC0A4082) /* IRQ Drive Strength Control Register */ ++#define MCF_GPIO_DSCR_USB \ ++ MCF_REG08(0xFC0A4083) /* USB Drive Strength Control Register */ ++#define MCF_GPIO_DSCR_ATA \ ++ MCF_REG08(0xFC0A4084) /* ATA Drive Strength Control Register */ ++ ++/* Bit definitions and macros for PODR_FEC0H */ ++#define MCF_GPIO_PODR_FEC0H_PODR0 (0x01) /* FEC0_CRS / ULPI_DATA6 */ ++#define MCF_GPIO_PODR_FEC0H_PODR1 (0x02) /* FEC0_RXD0 / FEC0_RMII_RXD0 */ ++#define MCF_GPIO_PODR_FEC0H_PODR2 (0x04) /* FEC0_RXDV/FEC0_RMII_CRS_DV */ ++#define MCF_GPIO_PODR_FEC0H_PODR3 (0x08) /* FEC0_RXCLK / ULPI_DATA1 */ ++#define MCF_GPIO_PODR_FEC0H_PODR4 (0x10) /* FEC0_COL / ULPI_DATA7 */ ++#define MCF_GPIO_PODR_FEC0H_PODR5 (0x20) /* FEC0_TXD0 / FEC0_RMII_TXD0 */ ++#define MCF_GPIO_PODR_FEC0H_PODR6 (0x40) /* FEC0_TXEN / FEC0_RMII_TXEN */ ++#define MCF_GPIO_PODR_FEC0H_PODR7 (0x80) /* FEC0_TXCLK ++ / FEC0_RMII_REF_CLK */ ++ ++/* Bit definitions and macros for PODR_FEC0L */ ++#define MCF_GPIO_PODR_FEC0L_PODR0 (0x01) /* FEC0_RXER / FEC0_RMII_RXER */ ++#define MCF_GPIO_PODR_FEC0L_PODR1 (0x02) /* FEC0_RXD1 / FEC0_RMII_RXD1 */ ++#define MCF_GPIO_PODR_FEC0L_PODR2 (0x04) /* FEC0_RXD2 / ULPI_DATA4 */ ++#define MCF_GPIO_PODR_FEC0L_PODR3 (0x08) /* FEC0_RXD3 / ULPI_DATA5 */ ++#define MCF_GPIO_PODR_FEC0L_PODR4 (0x10) /* FEC0_TXER / ULPI_DATA0 */ ++#define MCF_GPIO_PODR_FEC0L_PODR5 (0x20) /* FEC0_TXD1 / FEC0_RMII_TXD1 */ ++#define MCF_GPIO_PODR_FEC0L_PODR6 (0x40) /* FEC0_TXD2 / ULPI_DATA2 */ ++#define MCF_GPIO_PODR_FEC0L_PODR7 (0x80) /* FEC0_TXD3 / ULPI_DATA3 */ ++ ++/* Bit definitions and macros for PODR_SSI */ ++#define MCF_GPIO_PODR_SSI_PODR0 (0x01) /* SSI_TXD / U1TXD */ ++#define MCF_GPIO_PODR_SSI_PODR1 (0x02) /* SSI_RXD / U1RXD */ ++#define MCF_GPIO_PODR_SSI_PODR2 (0x04) /* SSI_FS / U1RTS */ ++#define MCF_GPIO_PODR_SSI_PODR3 (0x08) /* SSI_BCLK / U1CTS */ ++#define MCF_GPIO_PODR_SSI_PODR4 (0x10) /* SSI_MCLK */ ++ ++/* Bit definitions and macros for PODR_FBCTL */ ++#define MCF_GPIO_PODR_FBCTL_PODR0 (0x01) /* FB_TS / FB_ALE / FB_TBST */ ++#define MCF_GPIO_PODR_FBCTL_PODR1 (0x02) /* FB_RW */ ++#define MCF_GPIO_PODR_FBCTL_PODR2 (0x04) /* FB_TA */ ++#define MCF_GPIO_PODR_FBCTL_PODR3 (0x08) /* FB_OE */ ++ ++/* Bit definitions and macros for PODR_BE */ ++#define MCF_GPIO_PODR_BE_PODR0 (0x01) /* FB_BE/BWE0 / FB_SIZ0 */ ++#define MCF_GPIO_PODR_BE_PODR1 (0x02) /* FB_BE/BWE1 / FB_SIZ1 */ ++#define MCF_GPIO_PODR_BE_PODR2 (0x04) /* FB_BE/BWE2 / FB_SIZ2 */ ++#define MCF_GPIO_PODR_BE_PODR3 (0x08) /* FB_BE/BWE3 / FB_SIZ3 */ ++ ++/* Bit definitions and macros for PODR_CS */ ++#define MCF_GPIO_PODR_CS_PODR1 (0x02) /* FB_CS1 */ ++#define MCF_GPIO_PODR_CS_PODR2 (0x04) /* FB_CS2 */ ++#define MCF_GPIO_PODR_CS_PODR3 (0x08) /* FB_CS3 */ ++ ++/* Bit definitions and macros for PODR_DMA */ ++#define MCF_GPIO_PODR_DMA_PODR0 (0x01) /* DREQ0 */ ++#define MCF_GPIO_PODR_DMA_PODR1 (0x02) /* DACK0 / DSPI_PCS3 */ ++#define MCF_GPIO_PODR_DMA_PODR2 (0x04) /* DREQ1 / USB_CLKIN */ ++#define MCF_GPIO_PODR_DMA_PODR3 (0x08) /* DACK1 / ULPI_DIR */ ++ ++/* Bit definitions and macros for PODR_FECI2C */ ++#define MCF_GPIO_PODR_FECI2C_PODR0 (0x01) /* I2C_SDA / U2RXD */ ++#define MCF_GPIO_PODR_FECI2C_PODR1 (0x02) /* I2C_SCL / U2TXD */ ++#define MCF_GPIO_PODR_FECI2C_PODR2 (0x04) /* FEC0_MDIO */ ++#define MCF_GPIO_PODR_FECI2C_PODR3 (0x08) /* FEC0_MDC */ ++#define MCF_GPIO_PODR_FECI2C_PODR4 (0x10) /* FEC1_MDIO / ATA_DIOW */ ++#define MCF_GPIO_PODR_FECI2C_PODR5 (0x20) /* FEC1_MDC / ATA_DIOR */ ++ ++/* Bit definitions and macros for PODR_UART */ ++#define MCF_GPIO_PODR_UART_PODR0 (0x01) /* U1TXD */ ++#define MCF_GPIO_PODR_UART_PODR1 (0x02) /* U1RXD */ ++#define MCF_GPIO_PODR_UART_PODR2 (0x04) /* U1RTS */ ++#define MCF_GPIO_PODR_UART_PODR3 (0x08) /* U0CTS */ ++#define MCF_GPIO_PODR_UART_PODR4 (0x10) /* U1TXD */ ++#define MCF_GPIO_PODR_UART_PODR5 (0x20) /* U1RXD */ ++#define MCF_GPIO_PODR_UART_PODR6 (0x40) /* U1RTS */ ++#define MCF_GPIO_PODR_UART_PODR7 (0x80) /* U1CTS */ ++ ++/* Bit definitions and macros for PODR_DSPI */ ++#define MCF_GPIO_PODR_DSPI_PODR0 (0x01) /* DSPI_SOUT / SBF_DO */ ++#define MCF_GPIO_PODR_DSPI_PODR1 (0x02) /* DSPI_SIN / SBF_DI */ ++#define MCF_GPIO_PODR_DSPI_PODR2 (0x04) /* DSPI_SCK / SBF_CK */ ++#define MCF_GPIO_PODR_DSPI_PODR3 (0x08) /* DSPI_PCS0/SS */ ++#define MCF_GPIO_PODR_DSPI_PODR4 (0x10) /* DSPI_PCS1 / SBF_CS */ ++#define MCF_GPIO_PODR_DSPI_PODR5 (0x20) /* DSPI_PCS2 */ ++#define MCF_GPIO_PODR_DSPI_PODR6 (0x40) /* DSPI_PCS5/SS */ ++ ++/* Bit definitions and macros for PODR_TIMER */ ++#define MCF_GPIO_PODR_TIMER_PODR0 (0x01) /* T0IN / T0OUT / U2RTS */ ++#define MCF_GPIO_PODR_TIMER_PODR1 (0x02) /* T1IN / T1OUT / U2CTS */ ++#define MCF_GPIO_PODR_TIMER_PODR2 (0x04) /* T2IN / T2OUT / U2TXD */ ++#define MCF_GPIO_PODR_TIMER_PODR3 (0x08) /* T3IN / T3OUT / U2RXD */ ++ ++/* Bit definitions and macros for PODR_PCI */ ++#define MCF_GPIO_PODR_PCI_PODR0 (0x01) /* PCI_REQ0/PCI_EXTGNT */ ++#define MCF_GPIO_PODR_PCI_PODR1 (0x02) /* PCI_REQ1 */ ++#define MCF_GPIO_PODR_PCI_PODR2 (0x04) /* PCI_REQ2 */ ++#define MCF_GPIO_PODR_PCI_PODR3 (0x08) /* PCI_REQ3 / ATA_INTR */ ++#define MCF_GPIO_PODR_PCI_PODR4 (0x10) /* PCI_GNT0/PCI_EXTREQ */ ++#define MCF_GPIO_PODR_PCI_PODR5 (0x20) /* PCI_GNT1 / */ ++#define MCF_GPIO_PODR_PCI_PODR6 (0x40) /* PCI_GNT2 / */ ++#define MCF_GPIO_PODR_PCI_PODR7 (0x80) /* PCI_GNT3 / ATA_DMACK */ ++ ++/* Bit definitions and macros for PODR_USB */ ++#define MCF_GPIO_PODR_USB_PODR0 (0x01) /* USB_VBUS_OC / ULPI_STP */ ++#define MCF_GPIO_PODR_USB_PODR1 (0x02) /* USB_VBUS_EN / USB_PULLUP ++ / ULPI_NXT */ ++ ++/* Bit definitions and macros for PODR_ATAH */ ++#define MCF_GPIO_PODR_ATAH_PODR0 (0x01) /* ATA_DA0 */ ++#define MCF_GPIO_PODR_ATAH_PODR1 (0x02) /* ATA_DA1 */ ++#define MCF_GPIO_PODR_ATAH_PODR2 (0x04) /* ATA_DA2 */ ++#define MCF_GPIO_PODR_ATAH_PODR3 (0x08) /* ATA_CS0 */ ++#define MCF_GPIO_PODR_ATAH_PODR4 (0x10) /* ATA_CS1 */ ++#define MCF_GPIO_PODR_ATAH_PODR5 (0x20) /* ATA_BUFFER_EN */ ++ ++/* Bit definitions and macros for PODR_ATAL */ ++#define MCF_GPIO_PODR_ATAL_PODR0 (0x01) /* ATA_IORDY */ ++#define MCF_GPIO_PODR_ATAL_PODR1 (0x02) /* ATA_DMARQ */ ++#define MCF_GPIO_PODR_ATAL_PODR2 (0x04) /* ATA_RESET */ ++ ++/* Bit definitions and macros for PODR_FEC1H */ ++#define MCF_GPIO_PODR_FEC1H_PODR0 (0x01) /* FEC1_CRS / ATA_DATA6 */ ++/* FEC1_RXD0 / FEC1_RMII_RXD0 / ATA_DATA13 */ ++#define MCF_GPIO_PODR_FEC1H_PODR1 (0x02) ++/* FEC1_RXDV / FEC1_RMII_CRS_DV / ATA_DATA15 */ ++#define MCF_GPIO_PODR_FEC1H_PODR2 (0x04) ++#define MCF_GPIO_PODR_FEC1H_PODR3 (0x08) /* FEC1_RXCLK / ATA_DATA5 */ ++#define MCF_GPIO_PODR_FEC1H_PODR4 (0x10) /* FEC1_COL / ATA_DATA7 */ ++/* FEC1_TXD0 / FEC1_RMII_TXD0 / ATA_DATA9 */ ++#define MCF_GPIO_PODR_FEC1H_PODR5 (0x20) ++/* FEC1_TXEN / FEC1_RMII_TXEN / ATA_DATA8 */ ++#define MCF_GPIO_PODR_FEC1H_PODR6 (0x40) ++/* FEC1_TXCLK / FEC1_RMII_REF_CLK / ATA_DATA11 */ ++#define MCF_GPIO_PODR_FEC1H_PODR7 (0x80) ++ ++/* Bit definitions and macros for PODR_FEC1L */ ++#define MCF_GPIO_PODR_FEC1L_PODR0 (0x01) /* FEC1_RXER / FEC1_RMII_RXER ++ / ATA_DATA12 */ ++#define MCF_GPIO_PODR_FEC1L_PODR1 (0x02) /* FEC1_RXD1 / FEC1_RMII_RXD1 ++ / ATA_DATA14 */ ++#define MCF_GPIO_PODR_FEC1L_PODR2 (0x04) /* FEC1_RXD2 / ATA_DATA3 */ ++#define MCF_GPIO_PODR_FEC1L_PODR3 (0x08) /* FEC1_RXD3 / ATA_DATA4 */ ++#define MCF_GPIO_PODR_FEC1L_PODR4 (0x10) /* FEC1_TXER / ATA_DATA0 */ ++#define MCF_GPIO_PODR_FEC1L_PODR5 (0x20) /* FEC1_TXD1 / FEC1_RMII_TXD1 ++ / ATA_DATA10 */ ++#define MCF_GPIO_PODR_FEC1L_PODR6 (0x40) /* FEC1_TXD2 / ATA_DATA1 */ ++#define MCF_GPIO_PODR_FEC1L_PODR7 (0x80) /* FEC1_TXD3 / ATA_DATA2 */ ++ ++/* Bit definitions and macros for PODR_FBADH */ ++#define MCF_GPIO_PODR_FBADH_PODR0 (0x01) /* FB_AD24 */ ++#define MCF_GPIO_PODR_FBADH_PODR1 (0x02) /* FB_AD25 */ ++#define MCF_GPIO_PODR_FBADH_PODR2 (0x04) /* FB_AD26 */ ++#define MCF_GPIO_PODR_FBADH_PODR3 (0x08) /* FB_AD27 */ ++#define MCF_GPIO_PODR_FBADH_PODR4 (0x10) /* FB_AD28 */ ++#define MCF_GPIO_PODR_FBADH_PODR5 (0x20) /* FB_AD29 */ ++#define MCF_GPIO_PODR_FBADH_PODR6 (0x40) /* FB_AD30 */ ++#define MCF_GPIO_PODR_FBADH_PODR7 (0x80) /* FB_AD31 */ ++ ++/* Bit definitions and macros for PODR_FBADMH */ ++#define MCF_GPIO_PODR_FBADMH_PODR0 (0x01) /* FB_AD16 */ ++#define MCF_GPIO_PODR_FBADMH_PODR1 (0x02) /* FB_AD17 */ ++#define MCF_GPIO_PODR_FBADMH_PODR2 (0x04) /* FB_AD18 */ ++#define MCF_GPIO_PODR_FBADMH_PODR3 (0x08) /* FB_AD19 */ ++#define MCF_GPIO_PODR_FBADMH_PODR4 (0x10) /* FB_AD20 */ ++#define MCF_GPIO_PODR_FBADMH_PODR5 (0x20) /* FB_AD21 */ ++#define MCF_GPIO_PODR_FBADMH_PODR6 (0x40) /* FB_AD22 */ ++#define MCF_GPIO_PODR_FBADMH_PODR7 (0x80) /* FB_AD23 */ ++ ++/* Bit definitions and macros for PODR_FBADML */ ++#define MCF_GPIO_PODR_FBADML_PODR0 (0x01) /* FB_AD8 */ ++#define MCF_GPIO_PODR_FBADML_PODR1 (0x02) /* FB_AD9 */ ++#define MCF_GPIO_PODR_FBADML_PODR2 (0x04) /* FB_AD10 */ ++#define MCF_GPIO_PODR_FBADML_PODR3 (0x08) /* FB_AD11 */ ++#define MCF_GPIO_PODR_FBADML_PODR4 (0x10) /* FB_AD12 */ ++#define MCF_GPIO_PODR_FBADML_PODR5 (0x20) /* FB_AD13 */ ++#define MCF_GPIO_PODR_FBADML_PODR6 (0x40) /* FB_AD14 */ ++#define MCF_GPIO_PODR_FBADML_PODR7 (0x80) /* FB_AD15 */ ++ ++/* Bit definitions and macros for PODR_FBADL */ ++#define MCF_GPIO_PODR_FBADL_PODR0 (0x01) /* FB_AD0 */ ++#define MCF_GPIO_PODR_FBADL_PODR1 (0x02) /* FB_AD1 */ ++#define MCF_GPIO_PODR_FBADL_PODR2 (0x04) /* FB_AD2 */ ++#define MCF_GPIO_PODR_FBADL_PODR3 (0x08) /* FB_AD3 */ ++#define MCF_GPIO_PODR_FBADL_PODR4 (0x10) /* FB_AD4 */ ++#define MCF_GPIO_PODR_FBADL_PODR5 (0x20) /* FB_AD5 */ ++#define MCF_GPIO_PODR_FBADL_PODR6 (0x40) /* FB_AD6 */ ++#define MCF_GPIO_PODR_FBADL_PODR7 (0x80) /* FB_AD7 */ ++ ++/* Bit definitions and macros for PDDR_FEC0H */ ++#define MCF_GPIO_PDDR_FEC0H_PDDR0 (0x01) /* FEC0_CRS / ULPI_DATA6 */ ++#define MCF_GPIO_PDDR_FEC0H_PDDR1 (0x02) /* FEC0_RXD0 / FEC0_RMII_RXD0 */ ++#define MCF_GPIO_PDDR_FEC0H_PDDR2 (0x04) /* FEC0_RXDV/FEC0_RMII_CRS_DV */ ++#define MCF_GPIO_PDDR_FEC0H_PDDR3 (0x08) /* FEC0_RXCLK / ULPI_DATA1 */ ++#define MCF_GPIO_PDDR_FEC0H_PDDR4 (0x10) /* FEC0_COL / ULPI_DATA7 */ ++#define MCF_GPIO_PDDR_FEC0H_PDDR5 (0x20) /* FEC0_TXD0 / FEC0_RMII_TXD0 */ ++#define MCF_GPIO_PDDR_FEC0H_PDDR6 (0x40) /* FEC0_TXEN / FEC0_RMII_TXEN */ ++#define MCF_GPIO_PDDR_FEC0H_PDDR7 (0x80) /* FEC0_TXCLK ++ / FEC0_RMII_REF_CLK */ ++ ++/* Bit definitions and macros for PDDR_FEC0L */ ++#define MCF_GPIO_PDDR_FEC0L_PDDR0 (0x01) /* FEC0_RXER / FEC0_RMII_RXER */ ++#define MCF_GPIO_PDDR_FEC0L_PDDR1 (0x02) /* FEC0_RXD1 / FEC0_RMII_RXD1 */ ++#define MCF_GPIO_PDDR_FEC0L_PDDR2 (0x04) /* FEC0_RXD2 / ULPI_DATA4 */ ++#define MCF_GPIO_PDDR_FEC0L_PDDR3 (0x08) /* FEC0_RXD3 / ULPI_DATA5 */ ++#define MCF_GPIO_PDDR_FEC0L_PDDR4 (0x10) /* FEC0_TXER / ULPI_DATA0 */ ++#define MCF_GPIO_PDDR_FEC0L_PDDR5 (0x20) /* FEC0_TXD1 / FEC0_RMII_TXD1 */ ++#define MCF_GPIO_PDDR_FEC0L_PDDR6 (0x40) /* FEC0_TXD2 / ULPI_DATA2 */ ++#define MCF_GPIO_PDDR_FEC0L_PDDR7 (0x80) /* FEC0_TXD3 / ULPI_DATA3 */ ++ ++/* Bit definitions and macros for PDDR_SSI */ ++#define MCF_GPIO_PDDR_SSI_PDDR0 (0x01) /* SSI_TXD / U1TXD */ ++#define MCF_GPIO_PDDR_SSI_PDDR1 (0x02) /* SSI_RXD / U1RXD */ ++#define MCF_GPIO_PDDR_SSI_PDDR2 (0x04) /* SSI_FS / U1RTS */ ++#define MCF_GPIO_PDDR_SSI_PDDR3 (0x08) /* SSI_BCLK / U1CTS */ ++#define MCF_GPIO_PDDR_SSI_PDDR4 (0x10) /* SSI_MCLK */ ++ ++/* Bit definitions and macros for PDDR_FBCTL */ ++#define MCF_GPIO_PDDR_FBCTL_PDDR0 (0x01) /* FB_TS / FB_ALE / FB_TBST */ ++#define MCF_GPIO_PDDR_FBCTL_PDDR1 (0x02) /* FB_RW */ ++#define MCF_GPIO_PDDR_FBCTL_PDDR2 (0x04) /* FB_TA */ ++#define MCF_GPIO_PDDR_FBCTL_PDDR3 (0x08) /* FB_OE */ ++ ++/* Bit definitions and macros for PDDR_BE */ ++#define MCF_GPIO_PDDR_BE_PDDR0 (0x01) /* FB_BE/BWE0 / FB_SIZ0 */ ++#define MCF_GPIO_PDDR_BE_PDDR1 (0x02) /* FB_BE/BWE1 / FB_SIZ1 */ ++#define MCF_GPIO_PDDR_BE_PDDR2 (0x04) /* FB_BE/BWE2 / FB_SIZ2 */ ++#define MCF_GPIO_PDDR_BE_PDDR3 (0x08) /* FB_BE/BWE3 / FB_SIZ3 */ ++ ++/* Bit definitions and macros for PDDR_CS */ ++#define MCF_GPIO_PDDR_CS_PDDR1 (0x02) /* FB_CS1 */ ++#define MCF_GPIO_PDDR_CS_PDDR2 (0x04) /* FB_CS2 */ ++#define MCF_GPIO_PDDR_CS_PDDR3 (0x08) /* FB_CS3 */ ++ ++/* Bit definitions and macros for PDDR_DMA */ ++#define MCF_GPIO_PDDR_DMA_PDDR0 (0x01) /* DREQ0 */ ++#define MCF_GPIO_PDDR_DMA_PDDR1 (0x02) /* DACK0 / DSPI_PCS3 */ ++#define MCF_GPIO_PDDR_DMA_PDDR2 (0x04) /* DREQ1 / USB_CLKIN */ ++#define MCF_GPIO_PDDR_DMA_PDDR3 (0x08) /* DACK1 / ULPI_DIR */ ++ ++/* Bit definitions and macros for PDDR_FECI2C */ ++#define MCF_GPIO_PDDR_FECI2C_PDDR0 (0x01) /* I2C_SDA / U2RXD */ ++#define MCF_GPIO_PDDR_FECI2C_PDDR1 (0x02) /* I2C_SCL / U2TXD */ ++#define MCF_GPIO_PDDR_FECI2C_PDDR2 (0x04) /* FEC0_MDIO */ ++#define MCF_GPIO_PDDR_FECI2C_PDDR3 (0x08) /* FEC0_MDC */ ++#define MCF_GPIO_PDDR_FECI2C_PDDR4 (0x10) /* FEC1_MDIO / ATA_DIOW */ ++#define MCF_GPIO_PDDR_FECI2C_PDDR5 (0x20) /* FEC1_MDC / ATA_DIOR */ ++ ++/* Bit definitions and macros for PDDR_UART */ ++#define MCF_GPIO_PDDR_UART_PDDR0 (0x01) /* U1TXD */ ++#define MCF_GPIO_PDDR_UART_PDDR1 (0x02) /* U1RXD */ ++#define MCF_GPIO_PDDR_UART_PDDR2 (0x04) /* U1RTS */ ++#define MCF_GPIO_PDDR_UART_PDDR3 (0x08) /* U0CTS */ ++#define MCF_GPIO_PDDR_UART_PDDR4 (0x10) /* U1TXD */ ++#define MCF_GPIO_PDDR_UART_PDDR5 (0x20) /* U1RXD */ ++#define MCF_GPIO_PDDR_UART_PDDR6 (0x40) /* U1RTS */ ++#define MCF_GPIO_PDDR_UART_PDDR7 (0x80) /* U1CTS */ ++ ++/* Bit definitions and macros for PDDR_DSPI */ ++#define MCF_GPIO_PDDR_DSPI_PDDR0 (0x01) /* DSPI_SOUT / SBF_DO */ ++#define MCF_GPIO_PDDR_DSPI_PDDR1 (0x02) /* DSPI_SIN / SBF_DI */ ++#define MCF_GPIO_PDDR_DSPI_PDDR2 (0x04) /* DSPI_SCK / SBF_CK */ ++#define MCF_GPIO_PDDR_DSPI_PDDR3 (0x08) /* DSPI_PCS0/SS */ ++#define MCF_GPIO_PDDR_DSPI_PDDR4 (0x10) /* DSPI_PCS1 / SBF_CS */ ++#define MCF_GPIO_PDDR_DSPI_PDDR5 (0x20) /* DSPI_PCS2 */ ++#define MCF_GPIO_PDDR_DSPI_PDDR6 (0x40) /* DSPI_PCS5/SS */ ++ ++/* Bit definitions and macros for PDDR_TIMER */ ++#define MCF_GPIO_PDDR_TIMER_PDDR0 (0x01) /* T0IN / T0OUT / U2RTS */ ++#define MCF_GPIO_PDDR_TIMER_PDDR1 (0x02) /* T1IN / T1OUT / U2CTS */ ++#define MCF_GPIO_PDDR_TIMER_PDDR2 (0x04) /* T2IN / T2OUT / U2TXD */ ++#define MCF_GPIO_PDDR_TIMER_PDDR3 (0x08) /* T3IN / T3OUT / U2RXD */ ++ ++/* Bit definitions and macros for PDDR_PCI */ ++#define MCF_GPIO_PDDR_PCI_PDDR0 (0x01) /* PCI_REQ0/PCI_EXTGNT */ ++#define MCF_GPIO_PDDR_PCI_PDDR1 (0x02) /* PCI_REQ1 */ ++#define MCF_GPIO_PDDR_PCI_PDDR2 (0x04) /* PCI_REQ2 */ ++#define MCF_GPIO_PDDR_PCI_PDDR3 (0x08) /* PCI_REQ3 / ATA_INTR */ ++#define MCF_GPIO_PDDR_PCI_PDDR4 (0x10) /* PCI_GNT0/PCI_EXTREQ */ ++#define MCF_GPIO_PDDR_PCI_PDDR5 (0x20) /* PCI_GNT1 / */ ++#define MCF_GPIO_PDDR_PCI_PDDR6 (0x40) /* PCI_GNT2 / */ ++#define MCF_GPIO_PDDR_PCI_PDDR7 (0x80) /* PCI_GNT3 / ATA_DMACK */ ++ ++/* Bit definitions and macros for PDDR_USB */ ++#define MCF_GPIO_PDDR_USB_PDDR0 (0x01) /* USB_VBUS_OC / ULPI_STP */ ++#define MCF_GPIO_PDDR_USB_PDDR1 (0x02) /* USB_VBUS_EN / USB_PULLUP ++ / ULPI_NXT */ ++ ++/* Bit definitions and macros for PDDR_ATAH */ ++#define MCF_GPIO_PDDR_ATAH_PDDR0 (0x01) /* ATA_DA0 */ ++#define MCF_GPIO_PDDR_ATAH_PDDR1 (0x02) /* ATA_DA1 */ ++#define MCF_GPIO_PDDR_ATAH_PDDR2 (0x04) /* ATA_DA2 */ ++#define MCF_GPIO_PDDR_ATAH_PDDR3 (0x08) /* ATA_CS0 */ ++#define MCF_GPIO_PDDR_ATAH_PDDR4 (0x10) /* ATA_CS1 */ ++#define MCF_GPIO_PDDR_ATAH_PDDR5 (0x20) /* ATA_BUFFER_EN */ ++ ++/* Bit definitions and macros for PDDR_ATAL */ ++#define MCF_GPIO_PDDR_ATAL_PDDR0 (0x01) /* ATA_IORDY */ ++#define MCF_GPIO_PDDR_ATAL_PDDR1 (0x02) /* ATA_DMARQ */ ++#define MCF_GPIO_PDDR_ATAL_PDDR2 (0x04) /* ATA_RESET */ ++ ++/* Bit definitions and macros for PDDR_FEC1H */ ++#define MCF_GPIO_PDDR_FEC1H_PDDR0 (0x01) /* FEC1_CRS / ATA_DATA6 */ ++#define MCF_GPIO_PDDR_FEC1H_PDDR1 (0x02) /* FEC1_RXD0 / FEC1_RMII_RXD0 ++ / ATA_DATA13 */ ++#define MCF_GPIO_PDDR_FEC1H_PDDR2 (0x04) /* FEC1_RXDV / FEC1_RMII_CRS_DV ++ / ATA_DATA15 */ ++#define MCF_GPIO_PDDR_FEC1H_PDDR3 (0x08) /* FEC1_RXCLK / ATA_DATA5 */ ++#define MCF_GPIO_PDDR_FEC1H_PDDR4 (0x10) /* FEC1_COL / ATA_DATA7 */ ++/* FEC1_TXD0 / FEC1_RMII_TXD0 / ATA_DATA9 */ ++#define MCF_GPIO_PDDR_FEC1H_PDDR5 (0x20) ++/* FEC1_TXEN / FEC1_RMII_TXEN / ATA_DATA8 */ ++#define MCF_GPIO_PDDR_FEC1H_PDDR6 (0x40) ++/* FEC1_TXCLK / FEC1_RMII_REF_CLK / ATA_DATA11 */ ++#define MCF_GPIO_PDDR_FEC1H_PDDR7 (0x80) ++ ++/* Bit definitions and macros for PDDR_FEC1L */ ++#define MCF_GPIO_PDDR_FEC1L_PDDR0 (0x01) /* FEC1_RXER / FEC1_RMII_RXER ++ / ATA_DATA12 */ ++#define MCF_GPIO_PDDR_FEC1L_PDDR1 (0x02) /* FEC1_RXD1 / FEC1_RMII_RXD1 ++ / ATA_DATA14 */ ++#define MCF_GPIO_PDDR_FEC1L_PDDR2 (0x04) /* FEC1_RXD2 / ATA_DATA3 */ ++#define MCF_GPIO_PDDR_FEC1L_PDDR3 (0x08) /* FEC1_RXD3 / ATA_DATA4 */ ++#define MCF_GPIO_PDDR_FEC1L_PDDR4 (0x10) /* FEC1_TXER / ATA_DATA0 */ ++#define MCF_GPIO_PDDR_FEC1L_PDDR5 (0x20) /* FEC1_TXD1 / FEC1_RMII_TXD1 ++ / ATA_DATA10 */ ++#define MCF_GPIO_PDDR_FEC1L_PDDR6 (0x40) /* FEC1_TXD2 / ATA_DATA1 */ ++#define MCF_GPIO_PDDR_FEC1L_PDDR7 (0x80) /* FEC1_TXD3 / ATA_DATA2 */ ++ ++/* Bit definitions and macros for PDDR_FBADH */ ++#define MCF_GPIO_PDDR_FBADH_PDDR0 (0x01) /* FB_AD24 */ ++#define MCF_GPIO_PDDR_FBADH_PDDR1 (0x02) /* FB_AD25 */ ++#define MCF_GPIO_PDDR_FBADH_PDDR2 (0x04) /* FB_AD26 */ ++#define MCF_GPIO_PDDR_FBADH_PDDR3 (0x08) /* FB_AD27 */ ++#define MCF_GPIO_PDDR_FBADH_PDDR4 (0x10) /* FB_AD28 */ ++#define MCF_GPIO_PDDR_FBADH_PDDR5 (0x20) /* FB_AD29 */ ++#define MCF_GPIO_PDDR_FBADH_PDDR6 (0x40) /* FB_AD30 */ ++#define MCF_GPIO_PDDR_FBADH_PDDR7 (0x80) /* FB_AD31 */ ++ ++/* Bit definitions and macros for PDDR_FBADMH */ ++#define MCF_GPIO_PDDR_FBADMH_PDDR0 (0x01) /* FB_AD16 */ ++#define MCF_GPIO_PDDR_FBADMH_PDDR1 (0x02) /* FB_AD17 */ ++#define MCF_GPIO_PDDR_FBADMH_PDDR2 (0x04) /* FB_AD18 */ ++#define MCF_GPIO_PDDR_FBADMH_PDDR3 (0x08) /* FB_AD19 */ ++#define MCF_GPIO_PDDR_FBADMH_PDDR4 (0x10) /* FB_AD20 */ ++#define MCF_GPIO_PDDR_FBADMH_PDDR5 (0x20) /* FB_AD21 */ ++#define MCF_GPIO_PDDR_FBADMH_PDDR6 (0x40) /* FB_AD22 */ ++#define MCF_GPIO_PDDR_FBADMH_PDDR7 (0x80) /* FB_AD23 */ ++ ++/* Bit definitions and macros for PDDR_FBADML */ ++#define MCF_GPIO_PDDR_FBADML_PDDR0 (0x01) /* FB_AD8 */ ++#define MCF_GPIO_PDDR_FBADML_PDDR1 (0x02) /* FB_AD9 */ ++#define MCF_GPIO_PDDR_FBADML_PDDR2 (0x04) /* FB_AD10 */ ++#define MCF_GPIO_PDDR_FBADML_PDDR3 (0x08) /* FB_AD11 */ ++#define MCF_GPIO_PDDR_FBADML_PDDR4 (0x10) /* FB_AD12 */ ++#define MCF_GPIO_PDDR_FBADML_PDDR5 (0x20) /* FB_AD13 */ ++#define MCF_GPIO_PDDR_FBADML_PDDR6 (0x40) /* FB_AD14 */ ++#define MCF_GPIO_PDDR_FBADML_PDDR7 (0x80) /* FB_AD15 */ ++ ++/* Bit definitions and macros for PDDR_FBADL */ ++#define MCF_GPIO_PDDR_FBADL_PDDR0 (0x01) /* FB_AD0 */ ++#define MCF_GPIO_PDDR_FBADL_PDDR1 (0x02) /* FB_AD1 */ ++#define MCF_GPIO_PDDR_FBADL_PDDR2 (0x04) /* FB_AD2 */ ++#define MCF_GPIO_PDDR_FBADL_PDDR3 (0x08) /* FB_AD3 */ ++#define MCF_GPIO_PDDR_FBADL_PDDR4 (0x10) /* FB_AD4 */ ++#define MCF_GPIO_PDDR_FBADL_PDDR5 (0x20) /* FB_AD5 */ ++#define MCF_GPIO_PDDR_FBADL_PDDR6 (0x40) /* FB_AD6 */ ++#define MCF_GPIO_PDDR_FBADL_PDDR7 (0x80) /* FB_AD7 */ ++ ++/* Bit definitions and macros for PPDSDR_FEC0H */ ++#define MCF_GPIO_PPDSDR_FEC0H_PPDR0 (0x01) /* FEC0_CRS / ULPI_DATA6 */ ++#define MCF_GPIO_PPDSDR_FEC0H_PPDR1 (0x02) /* FEC0_RXD0 / FEC0_RMII_RXD0 */ ++#define MCF_GPIO_PPDSDR_FEC0H_PPDR2 (0x04) /* FEC0_RXDV ++ / FEC0_RMII_CRS_DV */ ++#define MCF_GPIO_PPDSDR_FEC0H_PPDR3 (0x08) /* FEC0_RXCLK / ULPI_DATA1 */ ++#define MCF_GPIO_PPDSDR_FEC0H_PPDR4 (0x10) /* FEC0_COL / ULPI_DATA7 */ ++#define MCF_GPIO_PPDSDR_FEC0H_PPDR5 (0x20) /* FEC0_TXD0 / FEC0_RMII_TXD0 */ ++#define MCF_GPIO_PPDSDR_FEC0H_PPDR6 (0x40) /* FEC0_TXEN / FEC0_RMII_TXEN */ ++#define MCF_GPIO_PPDSDR_FEC0H_PPDR7 (0x80) /* FEC0_TXCLK ++ / FEC0_RMII_REF_CLK */ ++ ++/* Bit definitions and macros for PPDSDR_FEC0L */ ++#define MCF_GPIO_PPDSDR_FEC0L_PCLRR0 (0x01) /* FEC0_RXER / FEC0_RMII_RXER */ ++#define MCF_GPIO_PPDSDR_FEC0L_PCLRR1 (0x02) /* FEC0_RXD1 / FEC0_RMII_RXD1 */ ++#define MCF_GPIO_PPDSDR_FEC0L_PCLRR2 (0x04) /* FEC0_RXD2 / ULPI_DATA4 */ ++#define MCF_GPIO_PPDSDR_FEC0L_PCLRR3 (0x08) /* FEC0_RXD3 / ULPI_DATA5 */ ++#define MCF_GPIO_PPDSDR_FEC0L_PCLRR4 (0x10) /* FEC0_TXER / ULPI_DATA0 */ ++#define MCF_GPIO_PPDSDR_FEC0L_PCLRR5 (0x20) /* FEC0_TXD1 / FEC0_RMII_TXD1 */ ++#define MCF_GPIO_PPDSDR_FEC0L_PCLRR6 (0x40) /* FEC0_TXD2 / ULPI_DATA2 */ ++#define MCF_GPIO_PPDSDR_FEC0L_PCLRR7 (0x80) /* FEC0_TXD3 / ULPI_DATA3 */ ++ ++/* Bit definitions and macros for PPDSDR_SSI */ ++#define MCF_GPIO_PPDSDR_SSI_PPDR0 (0x01) /* SSI_TXD / U1TXD */ ++#define MCF_GPIO_PPDSDR_SSI_PPDR1 (0x02) /* SSI_RXD / U1RXD */ ++#define MCF_GPIO_PPDSDR_SSI_PPDR2 (0x04) /* SSI_FS / U1RTS */ ++#define MCF_GPIO_PPDSDR_SSI_PPDR3 (0x08) /* SSI_BCLK / U1CTS */ ++#define MCF_GPIO_PPDSDR_SSI_PPDR4 (0x10) /* SSI_MCLK */ ++ ++/* Bit definitions and macros for PPDSDR_FBCTL */ ++#define MCF_GPIO_PPDSDR_FBCTL_PPDR0 (0x01) /* FB_TS / FB_ALE / FB_TBST */ ++#define MCF_GPIO_PPDSDR_FBCTL_PPDR1 (0x02) /* FB_RW */ ++#define MCF_GPIO_PPDSDR_FBCTL_PPDR2 (0x04) /* FB_TA */ ++#define MCF_GPIO_PPDSDR_FBCTL_PPDR3 (0x08) /* FB_OE */ ++ ++/* Bit definitions and macros for PPDSDR_BE */ ++#define MCF_GPIO_PPDSDR_BE_PPDR0 (0x01) /* FB_BE/BWE0 / FB_SIZ0 */ ++#define MCF_GPIO_PPDSDR_BE_PPDR1 (0x02) /* FB_BE/BWE1 / FB_SIZ1 */ ++#define MCF_GPIO_PPDSDR_BE_PPDR2 (0x04) /* FB_BE/BWE2 / FB_SIZ2 */ ++#define MCF_GPIO_PPDSDR_BE_PPDR3 (0x08) /* FB_BE/BWE3 / FB_SIZ3 */ ++ ++/* Bit definitions and macros for PPDSDR_CS */ ++#define MCF_GPIO_PPDSDR_CS_PPDR1 (0x02) /* FB_CS1 */ ++#define MCF_GPIO_PPDSDR_CS_PPDR2 (0x04) /* FB_CS2 */ ++#define MCF_GPIO_PPDSDR_CS_PPDR3 (0x08) /* FB_CS3 */ ++ ++/* Bit definitions and macros for PPDSDR_DMA */ ++#define MCF_GPIO_PPDSDR_DMA_PPDR0 (0x01) /* DREQ0 */ ++#define MCF_GPIO_PPDSDR_DMA_PPDR1 (0x02) /* DACK0 / DSPI_PCS3 */ ++#define MCF_GPIO_PPDSDR_DMA_PPDR2 (0x04) /* DREQ1 / USB_CLKIN */ ++#define MCF_GPIO_PPDSDR_DMA_PPDR3 (0x08) /* DACK1 / ULPI_DIR */ ++ ++/* Bit definitions and macros for PPDSDR_FECI2C */ ++#define MCF_GPIO_PPDSDR_FECI2C_PPDR0 (0x01) /* I2C_SDA / U2RXD */ ++#define MCF_GPIO_PPDSDR_FECI2C_PPDR1 (0x02) /* I2C_SCL / U2TXD */ ++#define MCF_GPIO_PPDSDR_FECI2C_PPDR2 (0x04) /* FEC0_MDIO */ ++#define MCF_GPIO_PPDSDR_FECI2C_PPDR3 (0x08) /* FEC0_MDC */ ++#define MCF_GPIO_PPDSDR_FECI2C_PPDR4 (0x10) /* FEC1_MDIO / ATA_DIOW */ ++#define MCF_GPIO_PPDSDR_FECI2C_PPDR5 (0x20) /* FEC1_MDC / ATA_DIOR */ ++ ++/* Bit definitions and macros for PPDSDR_UART */ ++#define MCF_GPIO_PPDSDR_UART_PPDR0 (0x01) /* U1TXD */ ++#define MCF_GPIO_PPDSDR_UART_PPDR1 (0x02) /* U1RXD */ ++#define MCF_GPIO_PPDSDR_UART_PPDR2 (0x04) /* U1RTS */ ++#define MCF_GPIO_PPDSDR_UART_PPDR3 (0x08) /* U0CTS */ ++#define MCF_GPIO_PPDSDR_UART_PPDR4 (0x10) /* U1TXD */ ++#define MCF_GPIO_PPDSDR_UART_PPDR5 (0x20) /* U1RXD */ ++#define MCF_GPIO_PPDSDR_UART_PPDR6 (0x40) /* U1RTS */ ++#define MCF_GPIO_PPDSDR_UART_PPDR7 (0x80) /* U1CTS */ ++ ++/* Bit definitions and macros for PPDSDR_DSPI */ ++#define MCF_GPIO_PPDSDR_DSPI_PPDR0 (0x01) /* DSPI_SOUT / SBF_DO */ ++#define MCF_GPIO_PPDSDR_DSPI_PPDR1 (0x02) /* DSPI_SIN / SBF_DI */ ++#define MCF_GPIO_PPDSDR_DSPI_PPDR2 (0x04) /* DSPI_SCK / SBF_CK */ ++#define MCF_GPIO_PPDSDR_DSPI_PPDR3 (0x08) /* DSPI_PCS0/SS */ ++#define MCF_GPIO_PPDSDR_DSPI_PPDR4 (0x10) /* DSPI_PCS1 / SBF_CS */ ++#define MCF_GPIO_PPDSDR_DSPI_PPDR5 (0x20) /* DSPI_PCS2 */ ++#define MCF_GPIO_PPDSDR_DSPI_PPDR6 (0x40) /* DSPI_PCS5/SS */ ++ ++/* Bit definitions and macros for PPDSDR_TIMER */ ++#define MCF_GPIO_PPDSDR_TIMER_PPDR0 (0x01) /* T0IN / T0OUT / U2RTS */ ++#define MCF_GPIO_PPDSDR_TIMER_PPDR1 (0x02) /* T1IN / T1OUT / U2CTS */ ++#define MCF_GPIO_PPDSDR_TIMER_PPDR2 (0x04) /* T2IN / T2OUT / U2TXD */ ++#define MCF_GPIO_PPDSDR_TIMER_PPDR3 (0x08) /* T3IN / T3OUT / U2RXD */ ++ ++/* Bit definitions and macros for PPDSDR_PCI */ ++#define MCF_GPIO_PPDSDR_PCI_PPDR0 (0x01) /* PCI_REQ0/PCI_EXTGNT */ ++#define MCF_GPIO_PPDSDR_PCI_PPDR1 (0x02) /* PCI_REQ1 */ ++#define MCF_GPIO_PPDSDR_PCI_PPDR2 (0x04) /* PCI_REQ2 */ ++#define MCF_GPIO_PPDSDR_PCI_PPDR3 (0x08) /* PCI_REQ3 / ATA_INTR */ ++#define MCF_GPIO_PPDSDR_PCI_PPDR4 (0x10) /* PCI_GNT0/PCI_EXTREQ */ ++#define MCF_GPIO_PPDSDR_PCI_PPDR5 (0x20) /* PCI_GNT1 / */ ++#define MCF_GPIO_PPDSDR_PCI_PPDR6 (0x40) /* PCI_GNT2 / */ ++#define MCF_GPIO_PPDSDR_PCI_PPDR7 (0x80) /* PCI_GNT3 / ATA_DMACK */ ++ ++/* Bit definitions and macros for PPDSDR_USB */ ++#define MCF_GPIO_PPDSDR_USB_PPDR0 (0x01) /* USB_VBUS_OC / ULPI_STP */ ++#define MCF_GPIO_PPDSDR_USB_PPDR1 (0x02) /* USB_VBUS_EN / USB_PULLUP ++ / ULPI_NXT */ ++ ++/* Bit definitions and macros for PPDSDR_ATAH */ ++#define MCF_GPIO_PPDSDR_ATAH_PPDR0 (0x01) /* ATA_DA0 */ ++#define MCF_GPIO_PPDSDR_ATAH_PPDR1 (0x02) /* ATA_DA1 */ ++#define MCF_GPIO_PPDSDR_ATAH_PPDR2 (0x04) /* ATA_DA2 */ ++#define MCF_GPIO_PPDSDR_ATAH_PPDR3 (0x08) /* ATA_CS0 */ ++#define MCF_GPIO_PPDSDR_ATAH_PPDR4 (0x10) /* ATA_CS1 */ ++#define MCF_GPIO_PPDSDR_ATAH_PPDR5 (0x20) /* ATA_BUFFER_EN */ ++ ++/* Bit definitions and macros for PPDSDR_ATAL */ ++#define MCF_GPIO_PPDSDR_ATAL_PPDR0 (0x01) /* ATA_IORDY */ ++#define MCF_GPIO_PPDSDR_ATAL_PPDR1 (0x02) /* ATA_DMARQ */ ++#define MCF_GPIO_PPDSDR_ATAL_PPDR2 (0x04) /* ATA_RESET */ ++ ++/* Bit definitions and macros for PPDSDR_FEC1H */ ++#define MCF_GPIO_PPDSDR_FEC1H_PPDR0 (0x01) /* FEC1_CRS / ATA_DATA6 */ ++#define MCF_GPIO_PPDSDR_FEC1H_PPDR1 (0x02) /* FEC1_RXD0 / FEC1_RMII_RXD0 ++ / ATA_DATA13 */ ++#define MCF_GPIO_PPDSDR_FEC1H_PPDR2 (0x04) /* FEC1_RXDV / FEC1_RMII_CRS_DV ++ / ATA_DATA15 */ ++#define MCF_GPIO_PPDSDR_FEC1H_PPDR3 (0x08) /* FEC1_RXCLK / ATA_DATA5 */ ++#define MCF_GPIO_PPDSDR_FEC1H_PPDR4 (0x10) /* FEC1_COL / ATA_DATA7 */ ++#define MCF_GPIO_PPDSDR_FEC1H_PPDR5 (0x20) /* FEC1_TXD0 / FEC1_RMII_TXD0 ++ / ATA_DATA9 */ ++#define MCF_GPIO_PPDSDR_FEC1H_PPDR6 (0x40) /* FEC1_TXEN / FEC1_RMII_TXEN ++ / ATA_DATA8 */ ++/* FEC1_TXCLK / FEC1_RMII_REF_CLK / ATA_DATA11 */ ++#define MCF_GPIO_PPDSDR_FEC1H_PPDR7 (0x80) ++ ++/* Bit definitions and macros for PPDSDR_FEC1L */ ++#define MCF_GPIO_PPDSDR_FEC1L_PPDR0 (0x01) /* FEC1_RXER / FEC1_RMII_RXER ++ / ATA_DATA12 */ ++#define MCF_GPIO_PPDSDR_FEC1L_PPDR1 (0x02) /* FEC1_RXD1 / FEC1_RMII_RXD1 ++ / ATA_DATA14 */ ++#define MCF_GPIO_PPDSDR_FEC1L_PPDR2 (0x04) /* FEC1_RXD2 / ATA_DATA3 */ ++#define MCF_GPIO_PPDSDR_FEC1L_PPDR3 (0x08) /* FEC1_RXD3 / ATA_DATA4 */ ++#define MCF_GPIO_PPDSDR_FEC1L_PPDR4 (0x10) /* FEC1_TXER / ATA_DATA0 */ ++#define MCF_GPIO_PPDSDR_FEC1L_PPDR5 (0x20) /* FEC1_TXD1 / FEC1_RMII_TXD1 ++ / ATA_DATA10 */ ++#define MCF_GPIO_PPDSDR_FEC1L_PPDR6 (0x40) /* FEC1_TXD2 / ATA_DATA1 */ ++#define MCF_GPIO_PPDSDR_FEC1L_PPDR7 (0x80) /* FEC1_TXD3 / ATA_DATA2 */ ++ ++/* Bit definitions and macros for PPDSDR_FBADH */ ++#define MCF_GPIO_PPDSDR_FBADH_PPDR0 (0x01) /* FB_AD24 */ ++#define MCF_GPIO_PPDSDR_FBADH_PPDR1 (0x02) /* FB_AD25 */ ++#define MCF_GPIO_PPDSDR_FBADH_PPDR2 (0x04) /* FB_AD26 */ ++#define MCF_GPIO_PPDSDR_FBADH_PPDR3 (0x08) /* FB_AD27 */ ++#define MCF_GPIO_PPDSDR_FBADH_PPDR4 (0x10) /* FB_AD28 */ ++#define MCF_GPIO_PPDSDR_FBADH_PPDR5 (0x20) /* FB_AD29 */ ++#define MCF_GPIO_PPDSDR_FBADH_PPDR6 (0x40) /* FB_AD30 */ ++#define MCF_GPIO_PPDSDR_FBADH_PPDR7 (0x80) /* FB_AD31 */ ++ ++/* Bit definitions and macros for PPDSDR_FBADMH */ ++#define MCF_GPIO_PPDSDR_FBADMH_PPDR0 (0x01) /* FB_AD16 */ ++#define MCF_GPIO_PPDSDR_FBADMH_PPDR1 (0x02) /* FB_AD17 */ ++#define MCF_GPIO_PPDSDR_FBADMH_PPDR2 (0x04) /* FB_AD18 */ ++#define MCF_GPIO_PPDSDR_FBADMH_PPDR3 (0x08) /* FB_AD19 */ ++#define MCF_GPIO_PPDSDR_FBADMH_PPDR4 (0x10) /* FB_AD20 */ ++#define MCF_GPIO_PPDSDR_FBADMH_PPDR5 (0x20) /* FB_AD21 */ ++#define MCF_GPIO_PPDSDR_FBADMH_PPDR6 (0x40) /* FB_AD22 */ ++#define MCF_GPIO_PPDSDR_FBADMH_PPDR7 (0x80) /* FB_AD23 */ ++ ++/* Bit definitions and macros for PPDSDR_FBADML */ ++#define MCF_GPIO_PPDSDR_FBADML_PPDR0 (0x01) /* FB_AD8 */ ++#define MCF_GPIO_PPDSDR_FBADML_PPDR1 (0x02) /* FB_AD9 */ ++#define MCF_GPIO_PPDSDR_FBADML_PPDR2 (0x04) /* FB_AD10 */ ++#define MCF_GPIO_PPDSDR_FBADML_PPDR3 (0x08) /* FB_AD11 */ ++#define MCF_GPIO_PPDSDR_FBADML_PPDR4 (0x10) /* FB_AD12 */ ++#define MCF_GPIO_PPDSDR_FBADML_PPDR5 (0x20) /* FB_AD13 */ ++#define MCF_GPIO_PPDSDR_FBADML_PPDR6 (0x40) /* FB_AD14 */ ++#define MCF_GPIO_PPDSDR_FBADML_PPDR7 (0x80) /* FB_AD15 */ ++ ++/* Bit definitions and macros for PPDSDR_FBADL */ ++#define MCF_GPIO_PPDSDR_FBADL_PPDR0 (0x01) /* FB_AD0 */ ++#define MCF_GPIO_PPDSDR_FBADL_PPDR1 (0x02) /* FB_AD1 */ ++#define MCF_GPIO_PPDSDR_FBADL_PPDR2 (0x04) /* FB_AD2 */ ++#define MCF_GPIO_PPDSDR_FBADL_PPDR3 (0x08) /* FB_AD3 */ ++#define MCF_GPIO_PPDSDR_FBADL_PPDR4 (0x10) /* FB_AD4 */ ++#define MCF_GPIO_PPDSDR_FBADL_PPDR5 (0x20) /* FB_AD5 */ ++#define MCF_GPIO_PPDSDR_FBADL_PPDR6 (0x40) /* FB_AD6 */ ++#define MCF_GPIO_PPDSDR_FBADL_PPDR7 (0x80) /* FB_AD7 */ ++ ++/* Bit definitions and macros for PCLRR_FEC0H */ ++#define MCF_GPIO_PCLRR_FEC0H_PCLRR0 (0x01) /* FEC0_CRS / ULPI_DATA6 */ ++#define MCF_GPIO_PCLRR_FEC0H_PCLRR1 (0x02) /* FEC0_RXD0 / FEC0_RMII_RXD0 */ ++#define MCF_GPIO_PCLRR_FEC0H_PCLRR2 (0x04) /* FEC0_RXDV/FEC0_RMII_CRS_DV */ ++#define MCF_GPIO_PCLRR_FEC0H_PCLRR3 (0x08) /* FEC0_RXCLK / ULPI_DATA1 */ ++#define MCF_GPIO_PCLRR_FEC0H_PCLRR4 (0x10) /* FEC0_COL / ULPI_DATA7 */ ++#define MCF_GPIO_PCLRR_FEC0H_PCLRR5 (0x20) /* FEC0_TXD0 / FEC0_RMII_TXD0 */ ++#define MCF_GPIO_PCLRR_FEC0H_PCLRR6 (0x40) /* FEC0_TXEN / FEC0_RMII_TXEN */ ++#define MCF_GPIO_PCLRR_FEC0H_PCLRR7 (0x80) /* FEC0_TXCLK ++ / FEC0_RMII_REF_CLK */ ++ ++/* Bit definitions and macros for PCLRR_FEC0L */ ++#define MCF_GPIO_PCLRR_FEC0L_PPDR0 (0x01) /* FEC0_RXER / FEC0_RMII_RXER */ ++#define MCF_GPIO_PCLRR_FEC0L_PPDR1 (0x02) /* FEC0_RXD1 / FEC0_RMII_RXD1 */ ++#define MCF_GPIO_PCLRR_FEC0L_PPDR2 (0x04) /* FEC0_RXD2 / ULPI_DATA4 */ ++#define MCF_GPIO_PCLRR_FEC0L_PPDR3 (0x08) /* FEC0_RXD3 / ULPI_DATA5 */ ++#define MCF_GPIO_PCLRR_FEC0L_PPDR4 (0x10) /* FEC0_TXER / ULPI_DATA0 */ ++#define MCF_GPIO_PCLRR_FEC0L_PPDR5 (0x20) /* FEC0_TXD1 / FEC0_RMII_TXD1 */ ++#define MCF_GPIO_PCLRR_FEC0L_PPDR6 (0x40) /* FEC0_TXD2 / ULPI_DATA2 */ ++#define MCF_GPIO_PCLRR_FEC0L_PPDR7 (0x80) /* FEC0_TXD3 / ULPI_DATA3 */ ++ ++/* Bit definitions and macros for PCLRR_SSI */ ++#define MCF_GPIO_PCLRR_SSI_PCLRR0 (0x01) /* SSI_TXD / U1TXD */ ++#define MCF_GPIO_PCLRR_SSI_PCLRR1 (0x02) /* SSI_RXD / U1RXD */ ++#define MCF_GPIO_PCLRR_SSI_PCLRR2 (0x04) /* SSI_FS / U1RTS */ ++#define MCF_GPIO_PCLRR_SSI_PCLRR3 (0x08) /* SSI_BCLK / U1CTS */ ++#define MCF_GPIO_PCLRR_SSI_PCLRR4 (0x10) /* SSI_MCLK */ ++ ++/* Bit definitions and macros for PCLRR_FBCTL */ ++#define MCF_GPIO_PCLRR_FBCTL_PCLRR0 (0x01) /* FB_TS / FB_ALE / FB_TBST */ ++#define MCF_GPIO_PCLRR_FBCTL_PCLRR1 (0x02) /* FB_RW */ ++#define MCF_GPIO_PCLRR_FBCTL_PCLRR2 (0x04) /* FB_TA */ ++#define MCF_GPIO_PCLRR_FBCTL_PCLRR3 (0x08) /* FB_OE */ ++ ++/* Bit definitions and macros for PCLRR_BE */ ++#define MCF_GPIO_PCLRR_BE_PCLRR0 (0x01) /* FB_BE/BWE0 / FB_SIZ0 */ ++#define MCF_GPIO_PCLRR_BE_PCLRR1 (0x02) /* FB_BE/BWE1 / FB_SIZ1 */ ++#define MCF_GPIO_PCLRR_BE_PCLRR2 (0x04) /* FB_BE/BWE2 / FB_SIZ2 */ ++#define MCF_GPIO_PCLRR_BE_PCLRR3 (0x08) /* FB_BE/BWE3 / FB_SIZ3 */ ++ ++/* Bit definitions and macros for PCLRR_CS */ ++#define MCF_GPIO_PCLRR_CS_PCLRR1 (0x02) /* FB_CS1 */ ++#define MCF_GPIO_PCLRR_CS_PCLRR2 (0x04) /* FB_CS2 */ ++#define MCF_GPIO_PCLRR_CS_PCLRR3 (0x08) /* FB_CS3 */ ++ ++/* Bit definitions and macros for PCLRR_DMA */ ++#define MCF_GPIO_PCLRR_DMA_PCLRR0 (0x01) /* DREQ0 */ ++#define MCF_GPIO_PCLRR_DMA_PCLRR1 (0x02) /* DACK0 / DSPI_PCS3 */ ++#define MCF_GPIO_PCLRR_DMA_PCLRR2 (0x04) /* DREQ1 / USB_CLKIN */ ++#define MCF_GPIO_PCLRR_DMA_PCLRR3 (0x08) /* DACK1 / ULPI_DIR */ ++ ++/* Bit definitions and macros for PCLRR_FECI2C */ ++#define MCF_GPIO_PCLRR_FECI2C_PCLRR0 (0x01) /* I2C_SDA / U2RXD */ ++#define MCF_GPIO_PCLRR_FECI2C_PCLRR1 (0x02) /* I2C_SCL / U2TXD */ ++#define MCF_GPIO_PCLRR_FECI2C_PCLRR2 (0x04) /* FEC0_MDIO */ ++#define MCF_GPIO_PCLRR_FECI2C_PCLRR3 (0x08) /* FEC0_MDC */ ++#define MCF_GPIO_PCLRR_FECI2C_PCLRR4 (0x10) /* FEC1_MDIO / ATA_DIOW */ ++#define MCF_GPIO_PCLRR_FECI2C_PCLRR5 (0x20) /* FEC1_MDC / ATA_DIOR */ ++ ++/* Bit definitions and macros for PCLRR_UART */ ++#define MCF_GPIO_PCLRR_UART_PCLRR0 (0x01) /* U1TXD */ ++#define MCF_GPIO_PCLRR_UART_PCLRR1 (0x02) /* U1RXD */ ++#define MCF_GPIO_PCLRR_UART_PCLRR2 (0x04) /* U1RTS */ ++#define MCF_GPIO_PCLRR_UART_PCLRR3 (0x08) /* U0CTS */ ++#define MCF_GPIO_PCLRR_UART_PCLRR4 (0x10) /* U1TXD */ ++#define MCF_GPIO_PCLRR_UART_PCLRR5 (0x20) /* U1RXD */ ++#define MCF_GPIO_PCLRR_UART_PCLRR6 (0x40) /* U1RTS */ ++#define MCF_GPIO_PCLRR_UART_PCLRR7 (0x80) /* U1CTS */ ++ ++/* Bit definitions and macros for PCLRR_DSPI */ ++#define MCF_GPIO_PCLRR_DSPI_PCLRR0 (0x01) /* DSPI_SOUT / SBF_DO */ ++#define MCF_GPIO_PCLRR_DSPI_PCLRR1 (0x02) /* DSPI_SIN / SBF_DI */ ++#define MCF_GPIO_PCLRR_DSPI_PCLRR2 (0x04) /* DSPI_SCK / SBF_CK */ ++#define MCF_GPIO_PCLRR_DSPI_PCLRR3 (0x08) /* DSPI_PCS0/SS */ ++#define MCF_GPIO_PCLRR_DSPI_PCLRR4 (0x10) /* DSPI_PCS1 / SBF_CS */ ++#define MCF_GPIO_PCLRR_DSPI_PCLRR5 (0x20) /* DSPI_PCS2 */ ++#define MCF_GPIO_PCLRR_DSPI_PCLRR6 (0x40) /* DSPI_PCS5/SS */ ++ ++/* Bit definitions and macros for PCLRR_TIMER */ ++#define MCF_GPIO_PCLRR_TIMER_PCLRR0 (0x01) /* T0IN / T0OUT / U2RTS */ ++#define MCF_GPIO_PCLRR_TIMER_PCLRR1 (0x02) /* T1IN / T1OUT / U2CTS */ ++#define MCF_GPIO_PCLRR_TIMER_PCLRR2 (0x04) /* T2IN / T2OUT / U2TXD */ ++#define MCF_GPIO_PCLRR_TIMER_PCLRR3 (0x08) /* T3IN / T3OUT / U2RXD */ ++ ++/* Bit definitions and macros for PCLRR_PCI */ ++#define MCF_GPIO_PCLRR_PCI_PCLRR0 (0x01) /* PCI_REQ0/PCI_EXTGNT */ ++#define MCF_GPIO_PCLRR_PCI_PCLRR1 (0x02) /* PCI_REQ1 */ ++#define MCF_GPIO_PCLRR_PCI_PCLRR2 (0x04) /* PCI_REQ2 */ ++#define MCF_GPIO_PCLRR_PCI_PCLRR3 (0x08) /* PCI_REQ3 / ATA_INTR */ ++#define MCF_GPIO_PCLRR_PCI_PCLRR4 (0x10) /* PCI_GNT0/PCI_EXTREQ */ ++#define MCF_GPIO_PCLRR_PCI_PCLRR5 (0x20) /* PCI_GNT1 / */ ++#define MCF_GPIO_PCLRR_PCI_PCLRR6 (0x40) /* PCI_GNT2 / */ ++#define MCF_GPIO_PCLRR_PCI_PCLRR7 (0x80) /* PCI_GNT3 / ATA_DMACK */ ++ ++/* Bit definitions and macros for PCLRR_USB */ ++#define MCF_GPIO_PCLRR_USB_PCLRR0 (0x01) /* USB_VBUS_OC / ULPI_STP */ ++#define MCF_GPIO_PCLRR_USB_PCLRR1 (0x02) /* USB_VBUS_EN / USB_PULLUP ++ / ULPI_NXT */ ++ ++/* Bit definitions and macros for PCLRR_ATAH */ ++#define MCF_GPIO_PCLRR_ATAH_PCLRR0 (0x01) /* ATA_DA0 */ ++#define MCF_GPIO_PCLRR_ATAH_PCLRR1 (0x02) /* ATA_DA1 */ ++#define MCF_GPIO_PCLRR_ATAH_PCLRR2 (0x04) /* ATA_DA2 */ ++#define MCF_GPIO_PCLRR_ATAH_PCLRR3 (0x08) /* ATA_CS0 */ ++#define MCF_GPIO_PCLRR_ATAH_PCLRR4 (0x10) /* ATA_CS1 */ ++#define MCF_GPIO_PCLRR_ATAH_PCLRR5 (0x20) /* ATA_BUFFER_EN */ ++ ++/* Bit definitions and macros for PCLRR_ATAL */ ++#define MCF_GPIO_PCLRR_ATAL_PCLRR0 (0x01) /* ATA_IORDY */ ++#define MCF_GPIO_PCLRR_ATAL_PCLRR1 (0x02) /* ATA_DMARQ */ ++#define MCF_GPIO_PCLRR_ATAL_PCLRR2 (0x04) /* ATA_RESET */ ++ ++/* Bit definitions and macros for PCLRR_FEC1H */ ++#define MCF_GPIO_PCLRR_FEC1H_PCLRR0 (0x01) /* FEC1_CRS / ATA_DATA6 */ ++#define MCF_GPIO_PCLRR_FEC1H_PCLRR1 (0x02) /* FEC1_RXD0 / FEC1_RMII_RXD0 ++ /ATA_DATA13 */ ++#define MCF_GPIO_PCLRR_FEC1H_PCLRR2 (0x04) /* FEC1_RXDV / FEC1_RMII_CRS_DV ++ / ATA_DATA15 */ ++#define MCF_GPIO_PCLRR_FEC1H_PCLRR3 (0x08) /* FEC1_RXCLK / ATA_DATA5 */ ++#define MCF_GPIO_PCLRR_FEC1H_PCLRR4 (0x10) /* FEC1_COL / ATA_DATA7 */ ++#define MCF_GPIO_PCLRR_FEC1H_PCLRR5 (0x20) /* FEC1_TXD0 / FEC1_RMII_TXD0 ++ / ATA_DATA9 */ ++#define MCF_GPIO_PCLRR_FEC1H_PCLRR6 (0x40) /* FEC1_TXEN / FEC1_RMII_TXEN ++ / ATA_DATA8 */ ++/* FEC1_TXCLK / FEC1_RMII_REF_CLK / ATA_DATA11 */ ++#define MCF_GPIO_PCLRR_FEC1H_PCLRR7 (0x80) ++ ++/* Bit definitions and macros for PCLRR_FEC1L */ ++#define MCF_GPIO_PCLRR_FEC1L_PCLRR0 (0x01) /* FEC1_RXER / FEC1_RMII_RXER ++ / ATA_DATA12 */ ++#define MCF_GPIO_PCLRR_FEC1L_PCLRR1 (0x02) /* FEC1_RXD1 / FEC1_RMII_RXD1 ++ / ATA_DATA14 */ ++#define MCF_GPIO_PCLRR_FEC1L_PCLRR2 (0x04) /* FEC1_RXD2 / ATA_DATA3 */ ++#define MCF_GPIO_PCLRR_FEC1L_PCLRR3 (0x08) /* FEC1_RXD3 / ATA_DATA4 */ ++#define MCF_GPIO_PCLRR_FEC1L_PCLRR4 (0x10) /* FEC1_TXER / ATA_DATA0 */ ++#define MCF_GPIO_PCLRR_FEC1L_PCLRR5 (0x20) /* FEC1_TXD1 / FEC1_RMII_TXD1 ++ / ATA_DATA10 */ ++#define MCF_GPIO_PCLRR_FEC1L_PCLRR6 (0x40) /* FEC1_TXD2 / ATA_DATA1 */ ++#define MCF_GPIO_PCLRR_FEC1L_PCLRR7 (0x80) /* FEC1_TXD3 / ATA_DATA2 */ ++ ++/* Bit definitions and macros for PCLRR_FBADH */ ++#define MCF_GPIO_PCLRR_FBADH_PCLRR0 (0x01) /* FB_AD24 */ ++#define MCF_GPIO_PCLRR_FBADH_PCLRR1 (0x02) /* FB_AD25 */ ++#define MCF_GPIO_PCLRR_FBADH_PCLRR2 (0x04) /* FB_AD26 */ ++#define MCF_GPIO_PCLRR_FBADH_PCLRR3 (0x08) /* FB_AD27 */ ++#define MCF_GPIO_PCLRR_FBADH_PCLRR4 (0x10) /* FB_AD28 */ ++#define MCF_GPIO_PCLRR_FBADH_PCLRR5 (0x20) /* FB_AD29 */ ++#define MCF_GPIO_PCLRR_FBADH_PCLRR6 (0x40) /* FB_AD30 */ ++#define MCF_GPIO_PCLRR_FBADH_PCLRR7 (0x80) /* FB_AD31 */ ++ ++/* Bit definitions and macros for PCLRR_FBADMH */ ++#define MCF_GPIO_PCLRR_FBADMH_PCLRR0 (0x01) /* FB_AD16 */ ++#define MCF_GPIO_PCLRR_FBADMH_PCLRR1 (0x02) /* FB_AD17 */ ++#define MCF_GPIO_PCLRR_FBADMH_PCLRR2 (0x04) /* FB_AD18 */ ++#define MCF_GPIO_PCLRR_FBADMH_PCLRR3 (0x08) /* FB_AD19 */ ++#define MCF_GPIO_PCLRR_FBADMH_PCLRR4 (0x10) /* FB_AD20 */ ++#define MCF_GPIO_PCLRR_FBADMH_PCLRR5 (0x20) /* FB_AD21 */ ++#define MCF_GPIO_PCLRR_FBADMH_PCLRR6 (0x40) /* FB_AD22 */ ++#define MCF_GPIO_PCLRR_FBADMH_PCLRR7 (0x80) /* FB_AD23 */ ++ ++/* Bit definitions and macros for PCLRR_FBADML */ ++#define MCF_GPIO_PCLRR_FBADML_PCLRR0 (0x01) /* FB_AD8 */ ++#define MCF_GPIO_PCLRR_FBADML_PCLRR1 (0x02) /* FB_AD9 */ ++#define MCF_GPIO_PCLRR_FBADML_PCLRR2 (0x04) /* FB_AD10 */ ++#define MCF_GPIO_PCLRR_FBADML_PCLRR3 (0x08) /* FB_AD11 */ ++#define MCF_GPIO_PCLRR_FBADML_PCLRR4 (0x10) /* FB_AD12 */ ++#define MCF_GPIO_PCLRR_FBADML_PCLRR5 (0x20) /* FB_AD13 */ ++#define MCF_GPIO_PCLRR_FBADML_PCLRR6 (0x40) /* FB_AD14 */ ++#define MCF_GPIO_PCLRR_FBADML_PCLRR7 (0x80) /* FB_AD15 */ ++ ++/* Bit definitions and macros for PCLRR_FBADL */ ++#define MCF_GPIO_PCLRR_FBADL_PCLRR0 (0x01) /* FB_AD0 */ ++#define MCF_GPIO_PCLRR_FBADL_PCLRR1 (0x02) /* FB_AD1 */ ++#define MCF_GPIO_PCLRR_FBADL_PCLRR2 (0x04) /* FB_AD2 */ ++#define MCF_GPIO_PCLRR_FBADL_PCLRR3 (0x08) /* FB_AD3 */ ++#define MCF_GPIO_PCLRR_FBADL_PCLRR4 (0x10) /* FB_AD4 */ ++#define MCF_GPIO_PCLRR_FBADL_PCLRR5 (0x20) /* FB_AD5 */ ++#define MCF_GPIO_PCLRR_FBADL_PCLRR6 (0x40) /* FB_AD6 */ ++#define MCF_GPIO_PCLRR_FBADL_PCLRR7 (0x80) /* FB_AD7 */ ++ ++/* Bit definitions and macros for PAR_FEC */ ++#define MCF_GPIO_PAR_FEC_FEC0(x) (((x)&0x07)) ++#define MCF_GPIO_PAR_FEC_FEC1(x) (((x)&0x07)<<4) ++#define MCF_GPIO_PAR_FEC_FEC1_MASK (0x8F) ++#define MCF_GPIO_PAR_FEC_FEC1_MII (0x70) ++#define MCF_GPIO_PAR_FEC_FEC1_RMII_GPIO (0x30) ++#define MCF_GPIO_PAR_FEC_FEC1_RMII_ATA (0x20) ++#define MCF_GPIO_PAR_FEC_FEC1_ATA (0x10) ++#define MCF_GPIO_PAR_FEC_FEC1_GPIO (0x00) ++#define MCF_GPIO_PAR_FEC_FEC0_MASK (0xF8) ++#define MCF_GPIO_PAR_FEC_FEC0_MII (0x07) ++#define MCF_GPIO_PAR_FEC_FEC0_RMII_GPIO (0x03) ++#define MCF_GPIO_PAR_FEC_FEC0_RMII_ULPI (0x02) ++#define MCF_GPIO_PAR_FEC_FEC0_ULPI (0x01) ++#define MCF_GPIO_PAR_FEC_FEC0_GPIO (0x00) ++ ++/* Bit definitions and macros for PAR_DMA */ ++#define MCF_GPIO_PAR_DMA_DREQ0 (0x01) ++#define MCF_GPIO_PAR_DMA_DACK0(x) (((x)&0x03)<<2) ++#define MCF_GPIO_PAR_DMA_DREQ1(x) (((x)&0x03)<<4) ++#define MCF_GPIO_PAR_DMA_DACK1(x) (((x)&0x03)<<6) ++#define MCF_GPIO_PAR_DMA_DACK1_MASK (0x3F) ++#define MCF_GPIO_PAR_DMA_DACK1_DACK1 (0xC0) ++#define MCF_GPIO_PAR_DMA_DACK1_ULPI_DIR (0x40) ++#define MCF_GPIO_PAR_DMA_DACK1_GPIO (0x00) ++#define MCF_GPIO_PAR_DMA_DREQ1_MASK (0xCF) ++#define MCF_GPIO_PAR_DMA_DREQ1_DREQ1 (0x30) ++#define MCF_GPIO_PAR_DMA_DREQ1_USB_CLKIN (0x10) ++#define MCF_GPIO_PAR_DMA_DREQ1_GPIO (0x00) ++#define MCF_GPIO_PAR_DMA_DACK0_MASK (0xF3) ++#define MCF_GPIO_PAR_DMA_DACK0_DACK1 (0x0C) ++#define MCF_GPIO_PAR_DMA_DACK0_ULPI_DIR (0x04) ++#define MCF_GPIO_PAR_DMA_DACK0_GPIO (0x00) ++#define MCF_GPIO_PAR_DMA_DREQ0_DREQ0 (0x01) ++#define MCF_GPIO_PAR_DMA_DREQ0_GPIO (0x00) ++ ++/* Bit definitions and macros for PAR_FBCTL */ ++#define MCF_GPIO_PAR_FBCTL_TS(x) (((x)&0x03)<<3) ++#define MCF_GPIO_PAR_FBCTL_RW (0x20) ++#define MCF_GPIO_PAR_FBCTL_TA (0x40) ++#define MCF_GPIO_PAR_FBCTL_OE (0x80) ++#define MCF_GPIO_PAR_FBCTL_OE_OE (0x80) ++#define MCF_GPIO_PAR_FBCTL_OE_GPIO (0x00) ++#define MCF_GPIO_PAR_FBCTL_TA_TA (0x40) ++#define MCF_GPIO_PAR_FBCTL_TA_GPIO (0x00) ++#define MCF_GPIO_PAR_FBCTL_RW_RW (0x20) ++#define MCF_GPIO_PAR_FBCTL_RW_GPIO (0x00) ++#define MCF_GPIO_PAR_FBCTL_TS_MASK (0xE7) ++#define MCF_GPIO_PAR_FBCTL_TS_TS (0x18) ++#define MCF_GPIO_PAR_FBCTL_TS_ALE (0x10) ++#define MCF_GPIO_PAR_FBCTL_TS_TBST (0x08) ++#define MCF_GPIO_PAR_FBCTL_TS_GPIO (0x80) ++ ++/* Bit definitions and macros for PAR_DSPI */ ++#define MCF_GPIO_PAR_DSPI_SCK (0x01) ++#define MCF_GPIO_PAR_DSPI_SOUT (0x02) ++#define MCF_GPIO_PAR_DSPI_SIN (0x04) ++#define MCF_GPIO_PAR_DSPI_PCS0 (0x08) ++#define MCF_GPIO_PAR_DSPI_PCS1 (0x10) ++#define MCF_GPIO_PAR_DSPI_PCS2 (0x20) ++#define MCF_GPIO_PAR_DSPI_PCS5 (0x40) ++#define MCF_GPIO_PAR_DSPI_PCS5_PCS5 (0x40) ++#define MCF_GPIO_PAR_DSPI_PCS5_GPIO (0x00) ++#define MCF_GPIO_PAR_DSPI_PCS2_PCS2 (0x20) ++#define MCF_GPIO_PAR_DSPI_PCS2_GPIO (0x00) ++#define MCF_GPIO_PAR_DSPI_PCS1_PCS1 (0x10) ++#define MCF_GPIO_PAR_DSPI_PCS1_GPIO (0x00) ++#define MCF_GPIO_PAR_DSPI_PCS0_PCS0 (0x08) ++#define MCF_GPIO_PAR_DSPI_PCS0_GPIO (0x00) ++#define MCF_GPIO_PAR_DSPI_SIN_SIN (0x04) ++#define MCF_GPIO_PAR_DSPI_SIN_GPIO (0x00) ++#define MCF_GPIO_PAR_DSPI_SOUT_SOUT (0x02) ++#define MCF_GPIO_PAR_DSPI_SOUT_GPIO (0x00) ++#define MCF_GPIO_PAR_DSPI_SCK_SCK (0x01) ++#define MCF_GPIO_PAR_DSPI_SCK_GPIO (0x00) ++ ++/* Bit definitions and macros for PAR_BE */ ++#define MCF_GPIO_PAR_BE_BE0 (0x01) ++#define MCF_GPIO_PAR_BE_BE1 (0x04) ++#define MCF_GPIO_PAR_BE_BE2(x) (((x)&0x03)<<4) ++#define MCF_GPIO_PAR_BE_BE3(x) (((x)&0x03)<<6) ++#define MCF_GPIO_PAR_BE_BE3_MASK (0x3F) ++#define MCF_GPIO_PAR_BE_BE3_BE3 (0xC0) ++#define MCF_GPIO_PAR_BE_BE3_TSIZ1 (0x80) ++#define MCF_GPIO_PAR_BE_BE3_GPIO (0x00) ++#define MCF_GPIO_PAR_BE_BE2_MASK (0xCF) ++#define MCF_GPIO_PAR_BE_BE2_BE2 (0x30) ++#define MCF_GPIO_PAR_BE_BE2_TSIZ0 (0x20) ++#define MCF_GPIO_PAR_BE_BE2_GPIO (0x00) ++#define MCF_GPIO_PAR_BE_BE1_BE1 (0x04) ++#define MCF_GPIO_PAR_BE_BE1_GPIO (0x00) ++#define MCF_GPIO_PAR_BE_BE0_BE0 (0x01) ++#define MCF_GPIO_PAR_BE_BE0_GPIO (0x00) ++ ++/* Bit definitions and macros for PAR_CS */ ++#define MCF_GPIO_PAR_CS_CS1 (0x02) ++#define MCF_GPIO_PAR_CS_CS2 (0x04) ++#define MCF_GPIO_PAR_CS_CS3 (0x08) ++#define MCF_GPIO_PAR_CS_CS3_CS3 (0x08) ++#define MCF_GPIO_PAR_CS_CS3_GPIO (0x00) ++#define MCF_GPIO_PAR_CS_CS2_CS2 (0x04) ++#define MCF_GPIO_PAR_CS_CS2_GPIO (0x00) ++#define MCF_GPIO_PAR_CS_CS1_CS1 (0x02) ++#define MCF_GPIO_PAR_CS_CS1_GPIO (0x00) ++ ++/* Bit definitions and macros for PAR_TIMER */ ++#define MCF_GPIO_PAR_TIMER_T0IN(x) (((x)&0x03)) ++#define MCF_GPIO_PAR_TIMER_T1IN(x) (((x)&0x03)<<2) ++#define MCF_GPIO_PAR_TIMER_T2IN(x) (((x)&0x03)<<4) ++#define MCF_GPIO_PAR_TIMER_T3IN(x) (((x)&0x03)<<6) ++#define MCF_GPIO_PAR_TIMER_T3IN_MASK (0x3F) ++#define MCF_GPIO_PAR_TIMER_T3IN_T3IN (0xC0) ++#define MCF_GPIO_PAR_TIMER_T3IN_T3OUT (0x80) ++#define MCF_GPIO_PAR_TIMER_T3IN_U2RXD (0x40) ++#define MCF_GPIO_PAR_TIMER_T3IN_GPIO (0x00) ++#define MCF_GPIO_PAR_TIMER_T2IN_MASK (0xCF) ++#define MCF_GPIO_PAR_TIMER_T2IN_T2IN (0x30) ++#define MCF_GPIO_PAR_TIMER_T2IN_T2OUT (0x20) ++#define MCF_GPIO_PAR_TIMER_T2IN_U2TXD (0x10) ++#define MCF_GPIO_PAR_TIMER_T2IN_GPIO (0x00) ++#define MCF_GPIO_PAR_TIMER_T1IN_MASK (0xF3) ++#define MCF_GPIO_PAR_TIMER_T1IN_T1IN (0x0C) ++#define MCF_GPIO_PAR_TIMER_T1IN_T1OUT (0x08) ++#define MCF_GPIO_PAR_TIMER_T1IN_U2CTS (0x04) ++#define MCF_GPIO_PAR_TIMER_T1IN_GPIO (0x00) ++#define MCF_GPIO_PAR_TIMER_T0IN_MASK (0xFC) ++#define MCF_GPIO_PAR_TIMER_T0IN_T0IN (0x03) ++#define MCF_GPIO_PAR_TIMER_T0IN_T0OUT (0x02) ++#define MCF_GPIO_PAR_TIMER_T0IN_U2RTS (0x01) ++#define MCF_GPIO_PAR_TIMER_T0IN_GPIO (0x00) ++ ++/* Bit definitions and macros for PAR_USB */ ++#define MCF_GPIO_PAR_USB_VBUSOC(x) (((x)&0x03)) ++#define MCF_GPIO_PAR_USB_VBUSEN(x) (((x)&0x03)<<2) ++#define MCF_GPIO_PAR_USB_VBUSEN_MASK (0xF3) ++#define MCF_GPIO_PAR_USB_VBUSEN_VBUSEN (0x0C) ++#define MCF_GPIO_PAR_USB_VBUSEN_USBPULLUP (0x08) ++#define MCF_GPIO_PAR_USB_VBUSEN_ULPI_NXT (0x04) ++#define MCF_GPIO_PAR_USB_VBUSEN_GPIO (0x00) ++#define MCF_GPIO_PAR_USB_VBUSOC_MASK (0xFC) ++#define MCF_GPIO_PAR_USB_VBUSOC_VBUSOC (0x03) ++#define MCF_GPIO_PAR_USB_VBUSOC_ULPI_STP (0x01) ++#define MCF_GPIO_PAR_USB_VBUSOC_GPIO (0x00) ++ ++/* Bit definitions and macros for PAR_UART */ ++#define MCF_GPIO_PAR_UART_U0TXD (0x01) ++#define MCF_GPIO_PAR_UART_U0RXD (0x02) ++#define MCF_GPIO_PAR_UART_U0RTS (0x04) ++#define MCF_GPIO_PAR_UART_U0CTS (0x08) ++#define MCF_GPIO_PAR_UART_U1TXD (0x10) ++#define MCF_GPIO_PAR_UART_U1RXD (0x20) ++#define MCF_GPIO_PAR_UART_U1RTS (0x40) ++#define MCF_GPIO_PAR_UART_U1CTS (0x80) ++#define MCF_GPIO_PAR_UART_U1CTS_U1CTS (0x80) ++#define MCF_GPIO_PAR_UART_U1CTS_GPIO (0x00) ++#define MCF_GPIO_PAR_UART_U1RTS_U1RTS (0x40) ++#define MCF_GPIO_PAR_UART_U1RTS_GPIO (0x00) ++#define MCF_GPIO_PAR_UART_U1RXD_U1RXD (0x20) ++#define MCF_GPIO_PAR_UART_U1RXD_GPIO (0x00) ++#define MCF_GPIO_PAR_UART_U1TXD_U1TXD (0x10) ++#define MCF_GPIO_PAR_UART_U1TXD_GPIO (0x00) ++#define MCF_GPIO_PAR_UART_U0CTS_U0CTS (0x08) ++#define MCF_GPIO_PAR_UART_U0CTS_GPIO (0x00) ++#define MCF_GPIO_PAR_UART_U0RTS_U0RTS (0x04) ++#define MCF_GPIO_PAR_UART_U0RTS_GPIO (0x00) ++#define MCF_GPIO_PAR_UART_U0RXD_U0RXD (0x02) ++#define MCF_GPIO_PAR_UART_U0RXD_GPIO (0x00) ++#define MCF_GPIO_PAR_UART_U0TXD_U0TXD (0x01) ++#define MCF_GPIO_PAR_UART_U0TXD_GPIO (0x00) ++ ++/* Bit definitions and macros for PAR_FECI2C */ ++#define MCF_GPIO_PAR_FECI2C_SDA(x) (((x)&0x0003)) ++#define MCF_GPIO_PAR_FECI2C_SCL(x) (((x)&0x0003)<<2) ++#define MCF_GPIO_PAR_FECI2C_PAR_SDA(x) (((x)&0x0003)) ++#define MCF_GPIO_PAR_FECI2C_PAR_SCL(x) (((x)&0x0003)<<2) ++#define MCF_GPIO_PAR_FECI2C_MDIO0 (0x0010) ++#define MCF_GPIO_PAR_FECI2C_MDC0 (0x0040) ++#define MCF_GPIO_PAR_FECI2C_MDIO1(x) (((x)&0x0003)<<8) ++#define MCF_GPIO_PAR_FECI2C_MDC1(x) (((x)&0x0003)<<10) ++#define MCF_GPIO_PAR_FECI2C_MDC1_MASK (0xF3FF) ++#define MCF_GPIO_PAR_FECI2C_MDC1_MDC1 (0x0C00) ++#define MCF_GPIO_PAR_FECI2C_MDC1_ATA_DIOR (0x0800) ++#define MCF_GPIO_PAR_FECI2C_MDC1_GPIO (0x0000) ++#define MCF_GPIO_PAR_FECI2C_MDIO1_MASK (0xFCFF) ++#define MCF_GPIO_PAR_FECI2C_MDIO1_MDIO1 (0x0300) ++#define MCF_GPIO_PAR_FECI2C_MDIO1_ATA_DIOW (0x0200) ++#define MCF_GPIO_PAR_FECI2C_MDIO1_GPIO (0x0000) ++#define MCF_GPIO_PAR_FECI2C_MDC0_MDC0 (0x0040) ++#define MCF_GPIO_PAR_FECI2C_MDC0_GPIO (0x0000) ++#define MCF_GPIO_PAR_FECI2C_MDIO0_MDIO0 (0x0010) ++#define MCF_GPIO_PAR_FECI2C_MDIO0_GPIO (0x0000) ++#define MCF_GPIO_PAR_FECI2C_SCL_MASK (0xFFF3) ++#define MCF_GPIO_PAR_FECI2C_SCL_SCL (0x000C) ++#define MCF_GPIO_PAR_FECI2C_SCL_U2TXD (0x0004) ++#define MCF_GPIO_PAR_FECI2C_SCL_GPIO (0x0000) ++#define MCF_GPIO_PAR_FECI2C_SDA_MASK (0xFFFC) ++#define MCF_GPIO_PAR_FECI2C_SDA_SDA (0x0003) ++#define MCF_GPIO_PAR_FECI2C_SDA_U2RXD (0x0001) ++#define MCF_GPIO_PAR_FECI2C_SDA_GPIO (0x0000) ++ ++/* Bit definitions and macros for PAR_SSI */ ++#define MCF_GPIO_PAR_SSI_MCLK (0x0001) ++#define MCF_GPIO_PAR_SSI_STXD(x) (((x)&0x0003)<<2) ++#define MCF_GPIO_PAR_SSI_SRXD(x) (((x)&0x0003)<<4) ++#define MCF_GPIO_PAR_SSI_FS(x) (((x)&0x0003)<<6) ++#define MCF_GPIO_PAR_SSI_BCLK(x) (((x)&0x0003)<<8) ++#define MCF_GPIO_PAR_SSI_BCLK_MASK (0xFCFF) ++#define MCF_GPIO_PAR_SSI_BCLK_BCLK (0x0300) ++#define MCF_GPIO_PAR_SSI_BCLK_U1CTS (0x0200) ++#define MCF_GPIO_PAR_SSI_BCLK_GPIO (0x0000) ++#define MCF_GPIO_PAR_SSI_FS_MASK (0xFF3F) ++#define MCF_GPIO_PAR_SSI_FS_FS (0x00C0) ++#define MCF_GPIO_PAR_SSI_FS_U1RTS (0x0080) ++#define MCF_GPIO_PAR_SSI_FS_GPIO (0x0000) ++#define MCF_GPIO_PAR_SSI_SRXD_MASK (0xFFCF) ++#define MCF_GPIO_PAR_SSI_SRXD_SRXD (0x0030) ++#define MCF_GPIO_PAR_SSI_SRXD_U1RXD (0x0020) ++#define MCF_GPIO_PAR_SSI_SRXD_GPIO (0x0000) ++#define MCF_GPIO_PAR_SSI_STXD_MASK (0xFFF3) ++#define MCF_GPIO_PAR_SSI_STXD_STXD (0x000C) ++#define MCF_GPIO_PAR_SSI_STXD_U1TXD (0x0008) ++#define MCF_GPIO_PAR_SSI_STXD_GPIO (0x0000) ++#define MCF_GPIO_PAR_SSI_MCLK_MCLK (0x0001) ++#define MCF_GPIO_PAR_SSI_MCLK_GPIO (0x0000) ++ ++/* Bit definitions and macros for PAR_ATA */ ++#define MCF_GPIO_PAR_ATA_IORDY (0x0001) ++#define MCF_GPIO_PAR_ATA_DMARQ (0x0002) ++#define MCF_GPIO_PAR_ATA_RESET (0x0004) ++#define MCF_GPIO_PAR_ATA_DA0 (0x0020) ++#define MCF_GPIO_PAR_ATA_DA1 (0x0040) ++#define MCF_GPIO_PAR_ATA_DA2 (0x0080) ++#define MCF_GPIO_PAR_ATA_CS0 (0x0100) ++#define MCF_GPIO_PAR_ATA_CS1 (0x0200) ++#define MCF_GPIO_PAR_ATA_BUFEN (0x0400) ++#define MCF_GPIO_PAR_ATA_BUFEN_BUFEN (0x0400) ++#define MCF_GPIO_PAR_ATA_BUFEN_GPIO (0x0000) ++#define MCF_GPIO_PAR_ATA_CS1_CS1 (0x0200) ++#define MCF_GPIO_PAR_ATA_CS1_GPIO (0x0000) ++#define MCF_GPIO_PAR_ATA_CS0_CS0 (0x0100) ++#define MCF_GPIO_PAR_ATA_CS0_GPIO (0x0000) ++#define MCF_GPIO_PAR_ATA_DA2_DA2 (0x0080) ++#define MCF_GPIO_PAR_ATA_DA2_GPIO (0x0000) ++#define MCF_GPIO_PAR_ATA_DA1_DA1 (0x0040) ++#define MCF_GPIO_PAR_ATA_DA1_GPIO (0x0000) ++#define MCF_GPIO_PAR_ATA_DA0_DA0 (0x0020) ++#define MCF_GPIO_PAR_ATA_DA0_GPIO (0x0000) ++#define MCF_GPIO_PAR_ATA_RESET_RESET (0x0004) ++#define MCF_GPIO_PAR_ATA_RESET_GPIO (0x0000) ++#define MCF_GPIO_PAR_ATA_DMARQ_DMARQ (0x0002) ++#define MCF_GPIO_PAR_ATA_DMARQ_GPIO (0x0000) ++#define MCF_GPIO_PAR_ATA_IORDY_IORDY (0x0001) ++#define MCF_GPIO_PAR_ATA_IORDY_GPIO (0x0000) ++ ++/* Bit definitions and macros for PAR_IRQ */ ++#define MCF_GPIO_PAR_IRQ_IRQ1 (0x02) ++#define MCF_GPIO_PAR_IRQ_IRQ4 (0x10) ++#define MCF_GPIO_PAR_IRQ_IRQ4_IRQ4 (0x10) ++#define MCF_GPIO_PAR_IRQ_IRQ4_GPIO (0x00) ++#define MCF_GPIO_PAR_IRQ_IRQ1_IRQ1 (0x02) ++#define MCF_GPIO_PAR_IRQ_IRQ1_GPIO (0x00) ++ ++/* Bit definitions and macros for PAR_PCI */ ++#define MCF_GPIO_PAR_PCI_REQ0 (0x0001) ++#define MCF_GPIO_PAR_PCI_REQ1 (0x0004) ++#define MCF_GPIO_PAR_PCI_REQ2 (0x0010) ++#define MCF_GPIO_PAR_PCI_REQ3(x) (((x)&0x0003)<<6) ++#define MCF_GPIO_PAR_PCI_GNT0 (0x0100) ++#define MCF_GPIO_PAR_PCI_GNT1 (0x0400) ++#define MCF_GPIO_PAR_PCI_GNT2 (0x1000) ++#define MCF_GPIO_PAR_PCI_GNT3(x) (((x)&0x0003)<<14) ++#define MCF_GPIO_PAR_PCI_GNT3_MASK (0x3FFF) ++#define MCF_GPIO_PAR_PCI_GNT3_GNT3 (0xC000) ++#define MCF_GPIO_PAR_PCI_GNT3_ATA_DMACK (0x8000) ++#define MCF_GPIO_PAR_PCI_GNT3_GPIO (0x0000) ++#define MCF_GPIO_PAR_PCI_GNT2_GNT2 (0x1000) ++#define MCF_GPIO_PAR_PCI_GNT2_GPIO (0x0000) ++#define MCF_GPIO_PAR_PCI_GNT1_GNT1 (0x0400) ++#define MCF_GPIO_PAR_PCI_GNT1_GPIO (0x0000) ++#define MCF_GPIO_PAR_PCI_GNT0_GNT0 (0x0100) ++#define MCF_GPIO_PAR_PCI_GNT0_GPIO (0x0000) ++#define MCF_GPIO_PAR_PCI_REQ3_MASK (0xFF3F) ++#define MCF_GPIO_PAR_PCI_REQ3_REQ3 (0x00C0) ++#define MCF_GPIO_PAR_PCI_REQ3_ATA_INTRQ (0x0080) ++#define MCF_GPIO_PAR_PCI_REQ3_GPIO (0x0000) ++#define MCF_GPIO_PAR_PCI_REQ2_REQ2 (0x0010) ++#define MCF_GPIO_PAR_PCI_REQ2_GPIO (0x0000) ++#define MCF_GPIO_PAR_PCI_REQ1_REQ1 (0x0040) ++#define MCF_GPIO_PAR_PCI_REQ1_GPIO (0x0000) ++#define MCF_GPIO_PAR_PCI_REQ0_REQ0 (0x0001) ++#define MCF_GPIO_PAR_PCI_REQ0_GPIO (0x0000) ++ ++/* Bit definitions and macros for MSCR_SDRAM */ ++#define MCF_GPIO_MSCR_SDRAM_SDCTL(x) (((x)&0x03)) ++#define MCF_GPIO_MSCR_SDRAM_SDCLK(x) (((x)&0x03)<<2) ++#define MCF_GPIO_MSCR_SDRAM_SDDQS(x) (((x)&0x03)<<4) ++#define MCF_GPIO_MSCR_SDRAM_SDDATA(x) (((x)&0x03)<<6) ++#define MCF_GPIO_MSCR_SDRAM_SDDATA_MASK (0x3F) ++#define MCF_GPIO_MSCR_SDRAM_SDDATA_DDR1 (0xC0) ++#define MCF_GPIO_MSCR_SDRAM_SDDATA_DDR2 (0x80) ++#define MCF_GPIO_MSCR_SDRAM_SDDATA_FS_LPDDR (0x40) ++#define MCF_GPIO_MSCR_SDRAM_SDDATA_HS_LPDDR (0x00) ++#define MCF_GPIO_MSCR_SDRAM_SDDQS_MASK (0xCF) ++#define MCF_GPIO_MSCR_SDRAM_SDDQS_DDR1 (0x30) ++#define MCF_GPIO_MSCR_SDRAM_SDDQS_DDR2 (0x20) ++#define MCF_GPIO_MSCR_SDRAM_SDDQS_FS_LPDDR (0x10) ++#define MCF_GPIO_MSCR_SDRAM_SDDQS_HS_LPDDR (0x00) ++#define MCF_GPIO_MSCR_SDRAM_SDCLK_MASK (0xF3) ++#define MCF_GPIO_MSCR_SDRAM_SDCLK_DDR1 (0x0C) ++#define MCF_GPIO_MSCR_SDRAM_SDCLK_DDR2 (0x08) ++#define MCF_GPIO_MSCR_SDRAM_SDCLK_FS_LPDDR (0x04) ++#define MCF_GPIO_MSCR_SDRAM_SDCLK_HS_LPDDR (0x00) ++#define MCF_GPIO_MSCR_SDRAM_SDCTL_MASK (0xFC) ++#define MCF_GPIO_MSCR_SDRAM_SDCTL_DDR1 (0x03) ++#define MCF_GPIO_MSCR_SDRAM_SDCTL_DDR2 (0x02) ++#define MCF_GPIO_MSCR_SDRAM_SDCTL_FS_LPDDR (0x01) ++#define MCF_GPIO_MSCR_SDRAM_SDCTL_HS_LPDDR (0x00) ++ ++/* Bit definitions and macros for MSCR_PCI */ ++#define MCF_GPIO_MSCR_PCI_PCI (0x01) ++#define MCF_GPIO_MSCR_PCI_PCI_HI_66MHZ (0x01) ++#define MCF_GPIO_MSCR_PCI_PCI_LO_33MHZ (0x00) ++ ++/* Bit definitions and macros for DSCR_I2C */ ++#define MCF_GPIO_DSCR_I2C_I2C(x) (((x)&0x03)) ++#define MCF_GPIO_DSCR_I2C_I2C_LOAD_50PF (0x03) ++#define MCF_GPIO_DSCR_I2C_I2C_LOAD_30PF (0x02) ++#define MCF_GPIO_DSCR_I2C_I2C_LOAD_20PF (0x01) ++#define MCF_GPIO_DSCR_I2C_I2C_LOAD_10PF (0x00) ++ ++/* Bit definitions and macros for DSCR_FLEXBUS */ ++#define MCF_GPIO_DSCR_FLEXBUS_FBADL(x) (((x)&0x03)) ++#define MCF_GPIO_DSCR_FLEXBUS_FBADH(x) (((x)&0x03)<<2) ++#define MCF_GPIO_DSCR_FLEXBUS_FBCTL(x) (((x)&0x03)<<4) ++#define MCF_GPIO_DSCR_FLEXBUS_FBCLK(x) (((x)&0x03)<<6) ++#define MCF_GPIO_DSCR_FLEXBUS_FBCLK_LOAD_50PF (0xC0) ++#define MCF_GPIO_DSCR_FLEXBUS_FBCLK_LOAD_30P (0x80) ++#define MCF_GPIO_DSCR_FLEXBUS_FBCLK_LOAD_20PF (0x40) ++#define MCF_GPIO_DSCR_FLEXBUS_FBCLK_LOAD_10PF (0x00) ++#define MCF_GPIO_DSCR_FLEXBUS_FBCTL_LOAD_50PF (0x30) ++#define MCF_GPIO_DSCR_FLEXBUS_FBCTL_LOAD_30PF (0x20) ++#define MCF_GPIO_DSCR_FLEXBUS_FBCTL_LOAD_20PF (0x10) ++#define MCF_GPIO_DSCR_FLEXBUS_FBCTL_LOAD_10PF (0x00) ++#define MCF_GPIO_DSCR_FLEXBUS_FBADH_LOAD_50PF (0x0C) ++#define MCF_GPIO_DSCR_FLEXBUS_FBADH_LOAD_30PF (0x08) ++#define MCF_GPIO_DSCR_FLEXBUS_FBADH_LOAD_20PF (0x04) ++#define MCF_GPIO_DSCR_FLEXBUS_FBADH_LOAD_10PF (0x00) ++#define MCF_GPIO_DSCR_FLEXBUS_FBADL_LOAD_50PF (0x03) ++#define MCF_GPIO_DSCR_FLEXBUS_FBADL_LOAD_30PF (0x02) ++#define MCF_GPIO_DSCR_FLEXBUS_FBADL_LOAD_20PF (0x01) ++#define MCF_GPIO_DSCR_FLEXBUS_FBADL_LOAD_10PF (0x00) ++ ++/* Bit definitions and macros for DSCR_FEC */ ++#define MCF_GPIO_DSCR_FEC_FEC0(x) (((x)&0x03)) ++#define MCF_GPIO_DSCR_FEC_FEC1(x) (((x)&0x03)<<2) ++#define MCF_GPIO_DSCR_FEC_FEC1_LOAD_50PF (0x0C) ++#define MCF_GPIO_DSCR_FEC_FEC1_LOAD_30PF (0x08) ++#define MCF_GPIO_DSCR_FEC_FEC1_LOAD_20PF (0x04) ++#define MCF_GPIO_DSCR_FEC_FEC1_LOAD_10PF (0x00) ++#define MCF_GPIO_DSCR_FEC_FEC0_LOAD_50PF (0x03) ++#define MCF_GPIO_DSCR_FEC_FEC0_LOAD_30PF (0x02) ++#define MCF_GPIO_DSCR_FEC_FEC0_LOAD_20PF (0x01) ++#define MCF_GPIO_DSCR_FEC_FEC0_LOAD_10PF (0x00) ++ ++/* Bit definitions and macros for DSCR_UART */ ++#define MCF_GPIO_DSCR_UART_UART0(x) (((x)&0x03)) ++#define MCF_GPIO_DSCR_UART_UART1(x) (((x)&0x03)<<2) ++#define MCF_GPIO_DSCR_UART_UART1_LOAD_50PF (0x0C) ++#define MCF_GPIO_DSCR_UART_UART1_LOAD_30PF (0x08) ++#define MCF_GPIO_DSCR_UART_UART1_LOAD_20PF (0x04) ++#define MCF_GPIO_DSCR_UART_UART1_LOAD_10PF (0x00) ++#define MCF_GPIO_DSCR_UART_UART0_LOAD_50PF (0x03) ++#define MCF_GPIO_DSCR_UART_UART0_LOAD_30PF (0x02) ++#define MCF_GPIO_DSCR_UART_UART0_LOAD_20PF (0x01) ++#define MCF_GPIO_DSCR_UART_UART0_LOAD_10PF (0x00) ++ ++/* Bit definitions and macros for DSCR_DSPI */ ++#define MCF_GPIO_DSCR_DSPI_DSPI(x) (((x)&0x03)) ++#define MCF_GPIO_DSCR_DSPI_DSPI_LOAD_50PF (0x03) ++#define MCF_GPIO_DSCR_DSPI_DSPI_LOAD_30PF (0x02) ++#define MCF_GPIO_DSCR_DSPI_DSPI_LOAD_20PF (0x01) ++#define MCF_GPIO_DSCR_DSPI_DSPI_LOAD_10PF (0x00) ++ ++/* Bit definitions and macros for DSCR_TIMER */ ++#define MCF_GPIO_DSCR_TIMER_TIMER(x) (((x)&0x03)) ++#define MCF_GPIO_DSCR_TIMER_TIMER_LOAD_50PF (0x03) ++#define MCF_GPIO_DSCR_TIMER_TIMER_LOAD_30PF (0x02) ++#define MCF_GPIO_DSCR_TIMER_TIMER_LOAD_20PF (0x01) ++#define MCF_GPIO_DSCR_TIMER_TIMER_LOAD_10PF (0x00) ++ ++/* Bit definitions and macros for DSCR_SSI */ ++#define MCF_GPIO_DSCR_SSI_SSI(x) (((x)&0x03)) ++#define MCF_GPIO_DSCR_SSI_SSI_LOAD_50PF (0x03) ++#define MCF_GPIO_DSCR_SSI_SSI_LOAD_30PF (0x02) ++#define MCF_GPIO_DSCR_SSI_SSI_LOAD_20PF (0x01) ++#define MCF_GPIO_DSCR_SSI_SSI_LOAD_10PF (0x00) ++ ++/* Bit definitions and macros for DSCR_DMA */ ++#define MCF_GPIO_DSCR_DMA_DMA(x) (((x)&0x03)) ++#define MCF_GPIO_DSCR_DMA_DMA_LOAD_50PF (0x03) ++#define MCF_GPIO_DSCR_DMA_DMA_LOAD_30PF (0x02) ++#define MCF_GPIO_DSCR_DMA_DMA_LOAD_20PF (0x01) ++#define MCF_GPIO_DSCR_DMA_DMA_LOAD_10PF (0x00) ++ ++/* Bit definitions and macros for DSCR_DEBUG */ ++#define MCF_GPIO_DSCR_DEBUG_DEBUG(x) (((x)&0x03)) ++#define MCF_GPIO_DSCR_DEBUG_DEBUG_LOAD_50PF (0x03) ++#define MCF_GPIO_DSCR_DEBUG_DEBUG_LOAD_30PF (0x02) ++#define MCF_GPIO_DSCR_DEBUG_DEBUG_LOAD_20PF (0x01) ++#define MCF_GPIO_DSCR_DEBUG_DEBUG_LOAD_10PF (0x00) ++ ++/* Bit definitions and macros for DSCR_RESET */ ++#define MCF_GPIO_DSCR_RESET_RESET(x) (((x)&0x03)) ++#define MCF_GPIO_DSCR_RESET_RESET_LOAD_50PF (0x03) ++#define MCF_GPIO_DSCR_RESET_RESET_LOAD_30PF (0x02) ++#define MCF_GPIO_DSCR_RESET_RESET_LOAD_20PF (0x01) ++#define MCF_GPIO_DSCR_RESET_RESET_LOAD_10PF (0x00) ++ ++/* Bit definitions and macros for DSCR_IRQ */ ++#define MCF_GPIO_DSCR_IRQ_IRQ(x) (((x)&0x03)) ++#define MCF_GPIO_DSCR_IRQ_IRQ_LOAD_50PF (0x03) ++#define MCF_GPIO_DSCR_IRQ_IRQ_LOAD_30PF (0x02) ++#define MCF_GPIO_DSCR_IRQ_IRQ_LOAD_20PF (0x01) ++#define MCF_GPIO_DSCR_IRQ_IRQ_LOAD_10PF (0x00) ++ ++/* Bit definitions and macros for DSCR_USB */ ++#define MCF_GPIO_DSCR_USB_USB(x) (((x)&0x03)) ++#define MCF_GPIO_DSCR_USB_USB_LOAD_50PF (0x03) ++#define MCF_GPIO_DSCR_USB_USB_LOAD_30PF (0x02) ++#define MCF_GPIO_DSCR_USB_USB_LOAD_20PF (0x01) ++#define MCF_GPIO_DSCR_USB_USB_LOAD_10PF (0x00) ++ ++/* Bit definitions and macros for DSCR_ATA */ ++#define MCF_GPIO_DSCR_ATA_ATA(x) (((x)&0x03)) ++#define MCF_GPIO_DSCR_ATA_ATA_LOAD_50PF (0x03) ++#define MCF_GPIO_DSCR_ATA_ATA_LOAD_30PF (0x02) ++#define MCF_GPIO_DSCR_ATA_ATA_LOAD_20PF (0x01) ++#define MCF_GPIO_DSCR_ATA_ATA_LOAD_10PF (0x00) ++ ++/********************************************************************/ ++ ++#endif /* __MCF5445X_GPIO_H__ */ +--- /dev/null ++++ b/arch/m68k/include/asm/mcf5445x_intc.h +@@ -0,0 +1,724 @@ ++/* ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * Matt Waddel Matt.Waddel@freescale.com ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#ifndef __MCF5445X_INTC_H__ ++#define __MCF5445X_INTC_H__ ++ ++/********************************************************************* ++* ++* Interrupt Controller (INTC) ++* ++*********************************************************************/ ++ ++/* Register read/write macros */ ++#define MCF_INTC0_IPRH MCF_REG32(0xFC048000) ++#define MCF_INTC0_IPRL MCF_REG32(0xFC048004) ++#define MCF_INTC0_IMRH MCF_REG32(0xFC048008) ++#define MCF_INTC0_IMRL MCF_REG32(0xFC04800C) ++#define MCF_INTC0_INTFRCH MCF_REG32(0xFC048010) ++#define MCF_INTC0_INTFRCL MCF_REG32(0xFC048014) ++#define MCF_INTC0_ICONFIG MCF_REG16(0xFC04801A) ++#define MCF_INTC0_SIMR MCF_REG08(0xFC04801C) ++#define MCF_INTC0_CIMR MCF_REG08(0xFC04801D) ++#define MCF_INTC0_CLMASK MCF_REG08(0xFC04801E) ++#define MCF_INTC0_SLMASK MCF_REG08(0xFC04801F) ++#define MCF_INTC0_ICR1 MCF_REG08(0xFC048041) ++#define MCF_INTC0_ICR2 MCF_REG08(0xFC048042) ++#define MCF_INTC0_ICR3 MCF_REG08(0xFC048043) ++#define MCF_INTC0_ICR4 MCF_REG08(0xFC048044) ++#define MCF_INTC0_ICR5 MCF_REG08(0xFC048045) ++#define MCF_INTC0_ICR6 MCF_REG08(0xFC048046) ++#define MCF_INTC0_ICR7 MCF_REG08(0xFC048047) ++#define MCF_INTC0_ICR8 MCF_REG08(0xFC048048) ++#define MCF_INTC0_ICR9 MCF_REG08(0xFC048049) ++#define MCF_INTC0_ICR10 MCF_REG08(0xFC04804A) ++#define MCF_INTC0_ICR11 MCF_REG08(0xFC04804B) ++#define MCF_INTC0_ICR12 MCF_REG08(0xFC04804C) ++#define MCF_INTC0_ICR13 MCF_REG08(0xFC04804D) ++#define MCF_INTC0_ICR14 MCF_REG08(0xFC04804E) ++#define MCF_INTC0_ICR15 MCF_REG08(0xFC04804F) ++#define MCF_INTC0_ICR16 MCF_REG08(0xFC048050) ++#define MCF_INTC0_ICR17 MCF_REG08(0xFC048051) ++#define MCF_INTC0_ICR18 MCF_REG08(0xFC048052) ++#define MCF_INTC0_ICR19 MCF_REG08(0xFC048053) ++#define MCF_INTC0_ICR20 MCF_REG08(0xFC048054) ++#define MCF_INTC0_ICR21 MCF_REG08(0xFC048055) ++#define MCF_INTC0_ICR22 MCF_REG08(0xFC048056) ++#define MCF_INTC0_ICR23 MCF_REG08(0xFC048057) ++#define MCF_INTC0_ICR24 MCF_REG08(0xFC048058) ++#define MCF_INTC0_ICR25 MCF_REG08(0xFC048059) ++#define MCF_INTC0_ICR26 MCF_REG08(0xFC04805A) ++#define MCF_INTC0_ICR27 MCF_REG08(0xFC04805B) ++#define MCF_INTC0_ICR28 MCF_REG08(0xFC04805C) ++#define MCF_INTC0_ICR29 MCF_REG08(0xFC04805D) ++#define MCF_INTC0_ICR30 MCF_REG08(0xFC04805E) ++#define MCF_INTC0_ICR31 MCF_REG08(0xFC04805F) ++#define MCF_INTC0_ICR32 MCF_REG08(0xFC048060) ++#define MCF_INTC0_ICR33 MCF_REG08(0xFC048061) ++#define MCF_INTC0_ICR34 MCF_REG08(0xFC048062) ++#define MCF_INTC0_ICR35 MCF_REG08(0xFC048063) ++#define MCF_INTC0_ICR36 MCF_REG08(0xFC048064) ++#define MCF_INTC0_ICR37 MCF_REG08(0xFC048065) ++#define MCF_INTC0_ICR38 MCF_REG08(0xFC048066) ++#define MCF_INTC0_ICR39 MCF_REG08(0xFC048067) ++#define MCF_INTC0_ICR40 MCF_REG08(0xFC048068) ++#define MCF_INTC0_ICR41 MCF_REG08(0xFC048069) ++#define MCF_INTC0_ICR42 MCF_REG08(0xFC04806A) ++#define MCF_INTC0_ICR43 MCF_REG08(0xFC04806B) ++#define MCF_INTC0_ICR44 MCF_REG08(0xFC04806C) ++#define MCF_INTC0_ICR45 MCF_REG08(0xFC04806D) ++#define MCF_INTC0_ICR46 MCF_REG08(0xFC04806E) ++#define MCF_INTC0_ICR47 MCF_REG08(0xFC04806F) ++#define MCF_INTC0_ICR48 MCF_REG08(0xFC048070) ++#define MCF_INTC0_ICR49 MCF_REG08(0xFC048071) ++#define MCF_INTC0_ICR50 MCF_REG08(0xFC048072) ++#define MCF_INTC0_ICR51 MCF_REG08(0xFC048073) ++#define MCF_INTC0_ICR52 MCF_REG08(0xFC048074) ++#define MCF_INTC0_ICR53 MCF_REG08(0xFC048075) ++#define MCF_INTC0_ICR54 MCF_REG08(0xFC048076) ++#define MCF_INTC0_ICR55 MCF_REG08(0xFC048077) ++#define MCF_INTC0_ICR56 MCF_REG08(0xFC048078) ++#define MCF_INTC0_ICR57 MCF_REG08(0xFC048079) ++#define MCF_INTC0_ICR58 MCF_REG08(0xFC04807A) ++#define MCF_INTC0_ICR59 MCF_REG08(0xFC04807B) ++#define MCF_INTC0_ICR60 MCF_REG08(0xFC04807C) ++#define MCF_INTC0_ICR61 MCF_REG08(0xFC04807D) ++#define MCF_INTC0_ICR62 MCF_REG08(0xFC04807E) ++#define MCF_INTC0_ICR63 MCF_REG08(0xFC04807F) ++#define MCF_INTC0_SWIACK MCF_REG08(0xFC0480E0) ++#define MCF_INTC0_L1IACK MCF_REG08(0xFC0480E4) ++#define MCF_INTC0_L2IACK MCF_REG08(0xFC0480E8) ++#define MCF_INTC0_L3IACK MCF_REG08(0xFC0480EC) ++#define MCF_INTC0_L4IACK MCF_REG08(0xFC0480F0) ++#define MCF_INTC0_L5IACK MCF_REG08(0xFC0480F4) ++#define MCF_INTC0_L6IACK MCF_REG08(0xFC0480F8) ++#define MCF_INTC0_L7IACK MCF_REG08(0xFC0480FC) ++#define MCF_INTC1_IPRH MCF_REG32(0xFC04C000) ++#define MCF_INTC1_IPRL MCF_REG32(0xFC04C004) ++#define MCF_INTC1_IMRH MCF_REG32(0xFC04C008) ++#define MCF_INTC1_IMRL MCF_REG32(0xFC04C00C) ++#define MCF_INTC1_INTFRCH MCF_REG32(0xFC04C010) ++#define MCF_INTC1_INTFRCL MCF_REG32(0xFC04C014) ++#define MCF_INTC1_ICONFIG MCF_REG16(0xFC04C01A) ++#define MCF_INTC1_SIMR MCF_REG08(0xFC04C01C) ++#define MCF_INTC1_CIMR MCF_REG08(0xFC04C01D) ++#define MCF_INTC1_CLMASK MCF_REG08(0xFC04C01E) ++#define MCF_INTC1_SLMASK MCF_REG08(0xFC04C01F) ++#define MCF_INTC1_ICR1 MCF_REG08(0xFC04C041) ++#define MCF_INTC1_ICR2 MCF_REG08(0xFC04C042) ++#define MCF_INTC1_ICR3 MCF_REG08(0xFC04C043) ++#define MCF_INTC1_ICR4 MCF_REG08(0xFC04C044) ++#define MCF_INTC1_ICR5 MCF_REG08(0xFC04C045) ++#define MCF_INTC1_ICR6 MCF_REG08(0xFC04C046) ++#define MCF_INTC1_ICR7 MCF_REG08(0xFC04C047) ++#define MCF_INTC1_ICR8 MCF_REG08(0xFC04C048) ++#define MCF_INTC1_ICR9 MCF_REG08(0xFC04C049) ++#define MCF_INTC1_ICR10 MCF_REG08(0xFC04C04A) ++#define MCF_INTC1_ICR11 MCF_REG08(0xFC04C04B) ++#define MCF_INTC1_ICR12 MCF_REG08(0xFC04C04C) ++#define MCF_INTC1_ICR13 MCF_REG08(0xFC04C04D) ++#define MCF_INTC1_ICR14 MCF_REG08(0xFC04C04E) ++#define MCF_INTC1_ICR15 MCF_REG08(0xFC04C04F) ++#define MCF_INTC1_ICR16 MCF_REG08(0xFC04C050) ++#define MCF_INTC1_ICR17 MCF_REG08(0xFC04C051) ++#define MCF_INTC1_ICR18 MCF_REG08(0xFC04C052) ++#define MCF_INTC1_ICR19 MCF_REG08(0xFC04C053) ++#define MCF_INTC1_ICR20 MCF_REG08(0xFC04C054) ++#define MCF_INTC1_ICR21 MCF_REG08(0xFC04C055) ++#define MCF_INTC1_ICR22 MCF_REG08(0xFC04C056) ++#define MCF_INTC1_ICR23 MCF_REG08(0xFC04C057) ++#define MCF_INTC1_ICR24 MCF_REG08(0xFC04C058) ++#define MCF_INTC1_ICR25 MCF_REG08(0xFC04C059) ++#define MCF_INTC1_ICR26 MCF_REG08(0xFC04C05A) ++#define MCF_INTC1_ICR27 MCF_REG08(0xFC04C05B) ++#define MCF_INTC1_ICR28 MCF_REG08(0xFC04C05C) ++#define MCF_INTC1_ICR29 MCF_REG08(0xFC04C05D) ++#define MCF_INTC1_ICR30 MCF_REG08(0xFC04C05E) ++#define MCF_INTC1_ICR31 MCF_REG08(0xFC04C05F) ++#define MCF_INTC1_ICR32 MCF_REG08(0xFC04C060) ++#define MCF_INTC1_ICR33 MCF_REG08(0xFC04C061) ++#define MCF_INTC1_ICR34 MCF_REG08(0xFC04C062) ++#define MCF_INTC1_ICR35 MCF_REG08(0xFC04C063) ++#define MCF_INTC1_ICR36 MCF_REG08(0xFC04C064) ++#define MCF_INTC1_ICR37 MCF_REG08(0xFC04C065) ++#define MCF_INTC1_ICR38 MCF_REG08(0xFC04C066) ++#define MCF_INTC1_ICR39 MCF_REG08(0xFC04C067) ++#define MCF_INTC1_ICR40 MCF_REG08(0xFC04C068) ++#define MCF_INTC1_ICR41 MCF_REG08(0xFC04C069) ++#define MCF_INTC1_ICR42 MCF_REG08(0xFC04C06A) ++#define MCF_INTC1_ICR43 MCF_REG08(0xFC04C06B) ++#define MCF_INTC1_ICR44 MCF_REG08(0xFC04C06C) ++#define MCF_INTC1_ICR45 MCF_REG08(0xFC04C06D) ++#define MCF_INTC1_ICR46 MCF_REG08(0xFC04C06E) ++#define MCF_INTC1_ICR47 MCF_REG08(0xFC04C06F) ++#define MCF_INTC1_ICR48 MCF_REG08(0xFC04C070) ++#define MCF_INTC1_ICR49 MCF_REG08(0xFC04C071) ++#define MCF_INTC1_ICR50 MCF_REG08(0xFC04C072) ++#define MCF_INTC1_ICR51 MCF_REG08(0xFC04C073) ++#define MCF_INTC1_ICR52 MCF_REG08(0xFC04C074) ++#define MCF_INTC1_ICR53 MCF_REG08(0xFC04C075) ++#define MCF_INTC1_ICR54 MCF_REG08(0xFC04C076) ++#define MCF_INTC1_ICR55 MCF_REG08(0xFC04C077) ++#define MCF_INTC1_ICR56 MCF_REG08(0xFC04C078) ++#define MCF_INTC1_ICR57 MCF_REG08(0xFC04C079) ++#define MCF_INTC1_ICR58 MCF_REG08(0xFC04C07A) ++#define MCF_INTC1_ICR59 MCF_REG08(0xFC04C07B) ++#define MCF_INTC1_ICR60 MCF_REG08(0xFC04C07C) ++#define MCF_INTC1_ICR61 MCF_REG08(0xFC04C07D) ++#define MCF_INTC1_ICR62 MCF_REG08(0xFC04C07E) ++#define MCF_INTC1_ICR63 MCF_REG08(0xFC04C07F) ++#define MCF_INTC1_SWIACK MCF_REG08(0xFC04C0E0) ++#define MCF_INTC1_L1IACK MCF_REG08(0xFC04C0E4) ++#define MCF_INTC1_L2IACK MCF_REG08(0xFC04C0E8) ++#define MCF_INTC1_L3IACK MCF_REG08(0xFC04C0EC) ++#define MCF_INTC1_L4IACK MCF_REG08(0xFC04C0F0) ++#define MCF_INTC1_L5IACK MCF_REG08(0xFC04C0F4) ++#define MCF_INTC1_L6IACK MCF_REG08(0xFC04C0F8 ++#define MCF_INTC1_L7IACK MCF_REG08(0xFC04C0FC) ++ ++/* Parameterized register read/write macros for multiple registers */ ++#define MCF_INTC0_ICR(x) MCF_REG08(0xFC048041+((x-1)*0x001)) ++#define MCF_INTC0_LIACK(x) MCF_REG08(0xFC0480E4+((x-1)*0x004)) ++#define MCF_INTC1_ICR(x) MCF_REG08(0xFC04C041+((x-1)*0x001)) ++#define MCF_INTC1_LIACK(x) MCF_REG08(0xFC04C0E4+((x-1)*0x004)) ++ ++/* Parameterized register read/write macros for multiple modules */ ++#define MCF_INTC_IPRH(x) MCF_REG32(0xFC048000+((x)*0x4000)) ++#define MCF_INTC_IPRL(x) MCF_REG32(0xFC048004+((x)*0x4000)) ++#define MCF_INTC_IMRH(x) MCF_REG32(0xFC048008+((x)*0x4000)) ++#define MCF_INTC_IMRL(x) MCF_REG32(0xFC04800C+((x)*0x4000)) ++#define MCF_INTC_INTFRCH(x) MCF_REG32(0xFC048010+((x)*0x4000)) ++#define MCF_INTC_INTFRCL(x) MCF_REG32(0xFC048014+((x)*0x4000)) ++#define MCF_INTC_ICONFIG(x) MCF_REG16(0xFC04801A+((x)*0x4000)) ++#define MCF_INTC_SIMR(x) MCF_REG08(0xFC04801C+((x)*0x4000)) ++#define MCF_INTC_CIMR(x) MCF_REG08(0xFC04801D+((x)*0x4000)) ++#define MCF_INTC_CLMASK(x) MCF_REG08(0xFC04801E+((x)*0x4000)) ++#define MCF_INTC_SLMASK(x) MCF_REG08(0xFC04801F+((x)*0x4000)) ++#define MCF_INTC_ICR1(x) MCF_REG08(0xFC048041+((x)*0x4000)) ++#define MCF_INTC_ICR2(x) MCF_REG08(0xFC048042+((x)*0x4000)) ++#define MCF_INTC_ICR3(x) MCF_REG08(0xFC048043+((x)*0x4000)) ++#define MCF_INTC_ICR4(x) MCF_REG08(0xFC048044+((x)*0x4000)) ++#define MCF_INTC_ICR5(x) MCF_REG08(0xFC048045+((x)*0x4000)) ++#define MCF_INTC_ICR6(x) MCF_REG08(0xFC048046+((x)*0x4000)) ++#define MCF_INTC_ICR7(x) MCF_REG08(0xFC048047+((x)*0x4000)) ++#define MCF_INTC_ICR8(x) MCF_REG08(0xFC048048+((x)*0x4000)) ++#define MCF_INTC_ICR9(x) MCF_REG08(0xFC048049+((x)*0x4000)) ++#define MCF_INTC_ICR10(x) MCF_REG08(0xFC04804A+((x)*0x4000)) ++#define MCF_INTC_ICR11(x) MCF_REG08(0xFC04804B+((x)*0x4000)) ++#define MCF_INTC_ICR12(x) MCF_REG08(0xFC04804C+((x)*0x4000)) ++#define MCF_INTC_ICR13(x) MCF_REG08(0xFC04804D+((x)*0x4000)) ++#define MCF_INTC_ICR14(x) MCF_REG08(0xFC04804E+((x)*0x4000)) ++#define MCF_INTC_ICR15(x) MCF_REG08(0xFC04804F+((x)*0x4000)) ++#define MCF_INTC_ICR16(x) MCF_REG08(0xFC048050+((x)*0x4000)) ++#define MCF_INTC_ICR17(x) MCF_REG08(0xFC048051+((x)*0x4000)) ++#define MCF_INTC_ICR18(x) MCF_REG08(0xFC048052+((x)*0x4000)) ++#define MCF_INTC_ICR19(x) MCF_REG08(0xFC048053+((x)*0x4000)) ++#define MCF_INTC_ICR20(x) MCF_REG08(0xFC048054+((x)*0x4000)) ++#define MCF_INTC_ICR21(x) MCF_REG08(0xFC048055+((x)*0x4000)) ++#define MCF_INTC_ICR22(x) MCF_REG08(0xFC048056+((x)*0x4000)) ++#define MCF_INTC_ICR23(x) MCF_REG08(0xFC048057+((x)*0x4000)) ++#define MCF_INTC_ICR24(x) MCF_REG08(0xFC048058+((x)*0x4000)) ++#define MCF_INTC_ICR25(x) MCF_REG08(0xFC048059+((x)*0x4000)) ++#define MCF_INTC_ICR26(x) MCF_REG08(0xFC04805A+((x)*0x4000)) ++#define MCF_INTC_ICR27(x) MCF_REG08(0xFC04805B+((x)*0x4000)) ++#define MCF_INTC_ICR28(x) MCF_REG08(0xFC04805C+((x)*0x4000)) ++#define MCF_INTC_ICR29(x) MCF_REG08(0xFC04805D+((x)*0x4000)) ++#define MCF_INTC_ICR30(x) MCF_REG08(0xFC04805E+((x)*0x4000)) ++#define MCF_INTC_ICR31(x) MCF_REG08(0xFC04805F+((x)*0x4000)) ++#define MCF_INTC_ICR32(x) MCF_REG08(0xFC048060+((x)*0x4000)) ++#define MCF_INTC_ICR33(x) MCF_REG08(0xFC048061+((x)*0x4000)) ++#define MCF_INTC_ICR34(x) MCF_REG08(0xFC048062+((x)*0x4000)) ++#define MCF_INTC_ICR35(x) MCF_REG08(0xFC048063+((x)*0x4000)) ++#define MCF_INTC_ICR36(x) MCF_REG08(0xFC048064+((x)*0x4000)) ++#define MCF_INTC_ICR37(x) MCF_REG08(0xFC048065+((x)*0x4000)) ++#define MCF_INTC_ICR38(x) MCF_REG08(0xFC048066+((x)*0x4000)) ++#define MCF_INTC_ICR39(x) MCF_REG08(0xFC048067+((x)*0x4000)) ++#define MCF_INTC_ICR40(x) MCF_REG08(0xFC048068+((x)*0x4000)) ++#define MCF_INTC_ICR41(x) MCF_REG08(0xFC048069+((x)*0x4000)) ++#define MCF_INTC_ICR42(x) MCF_REG08(0xFC04806A+((x)*0x4000)) ++#define MCF_INTC_ICR43(x) MCF_REG08(0xFC04806B+((x)*0x4000)) ++#define MCF_INTC_ICR44(x) MCF_REG08(0xFC04806C+((x)*0x4000)) ++#define MCF_INTC_ICR45(x) MCF_REG08(0xFC04806D+((x)*0x4000)) ++#define MCF_INTC_ICR46(x) MCF_REG08(0xFC04806E+((x)*0x4000)) ++#define MCF_INTC_ICR47(x) MCF_REG08(0xFC04806F+((x)*0x4000)) ++#define MCF_INTC_ICR48(x) MCF_REG08(0xFC048070+((x)*0x4000)) ++#define MCF_INTC_ICR49(x) MCF_REG08(0xFC048071+((x)*0x4000)) ++#define MCF_INTC_ICR50(x) MCF_REG08(0xFC048072+((x)*0x4000)) ++#define MCF_INTC_ICR51(x) MCF_REG08(0xFC048073+((x)*0x4000)) ++#define MCF_INTC_ICR52(x) MCF_REG08(0xFC048074+((x)*0x4000)) ++#define MCF_INTC_ICR53(x) MCF_REG08(0xFC048075+((x)*0x4000)) ++#define MCF_INTC_ICR54(x) MCF_REG08(0xFC048076+((x)*0x4000)) ++#define MCF_INTC_ICR55(x) MCF_REG08(0xFC048077+((x)*0x4000)) ++#define MCF_INTC_ICR56(x) MCF_REG08(0xFC048078+((x)*0x4000)) ++#define MCF_INTC_ICR57(x) MCF_REG08(0xFC048079+((x)*0x4000)) ++#define MCF_INTC_ICR58(x) MCF_REG08(0xFC04807A+((x)*0x4000)) ++#define MCF_INTC_ICR59(x) MCF_REG08(0xFC04807B+((x)*0x4000)) ++#define MCF_INTC_ICR60(x) MCF_REG08(0xFC04807C+((x)*0x4000)) ++#define MCF_INTC_ICR61(x) MCF_REG08(0xFC04807D+((x)*0x4000)) ++#define MCF_INTC_ICR62(x) MCF_REG08(0xFC04807E+((x)*0x4000)) ++#define MCF_INTC_ICR63(x) MCF_REG08(0xFC04807F+((x)*0x4000)) ++#define MCF_INTC_SWIACK(x) MCF_REG08(0xFC0480E0+((x)*0x4000)) ++#define MCF_INTC_L1IACK(x) MCF_REG08(0xFC0480E4+((x)*0x4000)) ++#define MCF_INTC_L2IACK(x) MCF_REG08(0xFC0480E8+((x)*0x4000)) ++#define MCF_INTC_L3IACK(x) MCF_REG08(0xFC0480EC+((x)*0x4000)) ++#define MCF_INTC_L4IACK(x) MCF_REG08(0xFC0480F0+((x)*0x4000)) ++#define MCF_INTC_L5IACK(x) MCF_REG08(0xFC0480F4+((x)*0x4000)) ++#define MCF_INTC_L6IACK(x) MCF_REG08(0xFC0480F8+((x)*0x4000)) ++#define MCF_INTC_L7IACK(x) MCF_REG08(0xFC0480FC+((x)*0x4000)) ++ ++/* Bit definitions and macros for IPRH */ ++#define MCF_INTC_IPRH_INT32 (0x00000001) ++#define MCF_INTC_IPRH_INT33 (0x00000002) ++#define MCF_INTC_IPRH_INT34 (0x00000004) ++#define MCF_INTC_IPRH_INT35 (0x00000008) ++#define MCF_INTC_IPRH_INT36 (0x00000010) ++#define MCF_INTC_IPRH_INT37 (0x00000020) ++#define MCF_INTC_IPRH_INT38 (0x00000040) ++#define MCF_INTC_IPRH_INT39 (0x00000080) ++#define MCF_INTC_IPRH_INT40 (0x00000100) ++#define MCF_INTC_IPRH_INT41 (0x00000200) ++#define MCF_INTC_IPRH_INT42 (0x00000400) ++#define MCF_INTC_IPRH_INT43 (0x00000800) ++#define MCF_INTC_IPRH_INT44 (0x00001000) ++#define MCF_INTC_IPRH_INT45 (0x00002000) ++#define MCF_INTC_IPRH_INT46 (0x00004000) ++#define MCF_INTC_IPRH_INT47 (0x00008000) ++#define MCF_INTC_IPRH_INT48 (0x00010000) ++#define MCF_INTC_IPRH_INT49 (0x00020000) ++#define MCF_INTC_IPRH_INT50 (0x00040000) ++#define MCF_INTC_IPRH_INT51 (0x00080000) ++#define MCF_INTC_IPRH_INT52 (0x00100000) ++#define MCF_INTC_IPRH_INT53 (0x00200000) ++#define MCF_INTC_IPRH_INT54 (0x00400000) ++#define MCF_INTC_IPRH_INT55 (0x00800000) ++#define MCF_INTC_IPRH_INT56 (0x01000000) ++#define MCF_INTC_IPRH_INT57 (0x02000000) ++#define MCF_INTC_IPRH_INT58 (0x04000000) ++#define MCF_INTC_IPRH_INT59 (0x08000000) ++#define MCF_INTC_IPRH_INT60 (0x10000000) ++#define MCF_INTC_IPRH_INT61 (0x20000000) ++#define MCF_INTC_IPRH_INT62 (0x40000000) ++#define MCF_INTC_IPRH_INT63 (0x80000000) ++ ++/* Bit definitions and macros for IPRL */ ++#define MCF_INTC_IPRL_INT0 (0x00000001) ++#define MCF_INTC_IPRL_INT1 (0x00000002) ++#define MCF_INTC_IPRL_INT2 (0x00000004) ++#define MCF_INTC_IPRL_INT3 (0x00000008) ++#define MCF_INTC_IPRL_INT4 (0x00000010) ++#define MCF_INTC_IPRL_INT5 (0x00000020) ++#define MCF_INTC_IPRL_INT6 (0x00000040) ++#define MCF_INTC_IPRL_INT7 (0x00000080) ++#define MCF_INTC_IPRL_INT8 (0x00000100) ++#define MCF_INTC_IPRL_INT9 (0x00000200) ++#define MCF_INTC_IPRL_INT10 (0x00000400) ++#define MCF_INTC_IPRL_INT11 (0x00000800) ++#define MCF_INTC_IPRL_INT12 (0x00001000) ++#define MCF_INTC_IPRL_INT13 (0x00002000) ++#define MCF_INTC_IPRL_INT14 (0x00004000) ++#define MCF_INTC_IPRL_INT15 (0x00008000) ++#define MCF_INTC_IPRL_INT16 (0x00010000) ++#define MCF_INTC_IPRL_INT17 (0x00020000) ++#define MCF_INTC_IPRL_INT18 (0x00040000) ++#define MCF_INTC_IPRL_INT19 (0x00080000) ++#define MCF_INTC_IPRL_INT20 (0x00100000) ++#define MCF_INTC_IPRL_INT21 (0x00200000) ++#define MCF_INTC_IPRL_INT22 (0x00400000) ++#define MCF_INTC_IPRL_INT23 (0x00800000) ++#define MCF_INTC_IPRL_INT24 (0x01000000) ++#define MCF_INTC_IPRL_INT25 (0x02000000) ++#define MCF_INTC_IPRL_INT26 (0x04000000) ++#define MCF_INTC_IPRL_INT27 (0x08000000) ++#define MCF_INTC_IPRL_INT28 (0x10000000) ++#define MCF_INTC_IPRL_INT29 (0x20000000) ++#define MCF_INTC_IPRL_INT30 (0x40000000) ++#define MCF_INTC_IPRL_INT31 (0x80000000) ++ ++/* Bit definitions and macros for IMRH */ ++#define MCF_INTC_IMRH_INT_MASK32 (0x00000001) ++#define MCF_INTC_IMRH_INT_MASK33 (0x00000002) ++#define MCF_INTC_IMRH_INT_MASK34 (0x00000004) ++#define MCF_INTC_IMRH_INT_MASK35 (0x00000008) ++#define MCF_INTC_IMRH_INT_MASK36 (0x00000010) ++#define MCF_INTC_IMRH_INT_MASK37 (0x00000020) ++#define MCF_INTC_IMRH_INT_MASK38 (0x00000040) ++#define MCF_INTC_IMRH_INT_MASK39 (0x00000080) ++#define MCF_INTC_IMRH_INT_MASK40 (0x00000100) ++#define MCF_INTC_IMRH_INT_MASK41 (0x00000200) ++#define MCF_INTC_IMRH_INT_MASK42 (0x00000400) ++#define MCF_INTC_IMRH_INT_MASK43 (0x00000800) ++#define MCF_INTC_IMRH_INT_MASK44 (0x00001000) ++#define MCF_INTC_IMRH_INT_MASK45 (0x00002000) ++#define MCF_INTC_IMRH_INT_MASK46 (0x00004000) ++#define MCF_INTC_IMRH_INT_MASK47 (0x00008000) ++#define MCF_INTC_IMRH_INT_MASK48 (0x00010000) ++#define MCF_INTC_IMRH_INT_MASK49 (0x00020000) ++#define MCF_INTC_IMRH_INT_MASK50 (0x00040000) ++#define MCF_INTC_IMRH_INT_MASK51 (0x00080000) ++#define MCF_INTC_IMRH_INT_MASK52 (0x00100000) ++#define MCF_INTC_IMRH_INT_MASK53 (0x00200000) ++#define MCF_INTC_IMRH_INT_MASK54 (0x00400000) ++#define MCF_INTC_IMRH_INT_MASK55 (0x00800000) ++#define MCF_INTC_IMRH_INT_MASK56 (0x01000000) ++#define MCF_INTC_IMRH_INT_MASK57 (0x02000000) ++#define MCF_INTC_IMRH_INT_MASK58 (0x04000000) ++#define MCF_INTC_IMRH_INT_MASK59 (0x08000000) ++#define MCF_INTC_IMRH_INT_MASK60 (0x10000000) ++#define MCF_INTC_IMRH_INT_MASK61 (0x20000000) ++#define MCF_INTC_IMRH_INT_MASK62 (0x40000000) ++#define MCF_INTC_IMRH_INT_MASK63 (0x80000000) ++ ++/* Bit definitions and macros for IMRL */ ++#define MCF_INTC_IMRL_INT_MASK0 (0x00000001) ++#define MCF_INTC_IMRL_INT_MASK1 (0x00000002) ++#define MCF_INTC_IMRL_INT_MASK2 (0x00000004) ++#define MCF_INTC_IMRL_INT_MASK3 (0x00000008) ++#define MCF_INTC_IMRL_INT_MASK4 (0x00000010) ++#define MCF_INTC_IMRL_INT_MASK5 (0x00000020) ++#define MCF_INTC_IMRL_INT_MASK6 (0x00000040) ++#define MCF_INTC_IMRL_INT_MASK7 (0x00000080) ++#define MCF_INTC_IMRL_INT_MASK8 (0x00000100) ++#define MCF_INTC_IMRL_INT_MASK9 (0x00000200) ++#define MCF_INTC_IMRL_INT_MASK10 (0x00000400) ++#define MCF_INTC_IMRL_INT_MASK11 (0x00000800) ++#define MCF_INTC_IMRL_INT_MASK12 (0x00001000) ++#define MCF_INTC_IMRL_INT_MASK13 (0x00002000) ++#define MCF_INTC_IMRL_INT_MASK14 (0x00004000) ++#define MCF_INTC_IMRL_INT_MASK15 (0x00008000) ++#define MCF_INTC_IMRL_INT_MASK16 (0x00010000) ++#define MCF_INTC_IMRL_INT_MASK17 (0x00020000) ++#define MCF_INTC_IMRL_INT_MASK18 (0x00040000) ++#define MCF_INTC_IMRL_INT_MASK19 (0x00080000) ++#define MCF_INTC_IMRL_INT_MASK20 (0x00100000) ++#define MCF_INTC_IMRL_INT_MASK21 (0x00200000) ++#define MCF_INTC_IMRL_INT_MASK22 (0x00400000) ++#define MCF_INTC_IMRL_INT_MASK23 (0x00800000) ++#define MCF_INTC_IMRL_INT_MASK24 (0x01000000) ++#define MCF_INTC_IMRL_INT_MASK25 (0x02000000) ++#define MCF_INTC_IMRL_INT_MASK26 (0x04000000) ++#define MCF_INTC_IMRL_INT_MASK27 (0x08000000) ++#define MCF_INTC_IMRL_INT_MASK28 (0x10000000) ++#define MCF_INTC_IMRL_INT_MASK29 (0x20000000) ++#define MCF_INTC_IMRL_INT_MASK30 (0x40000000) ++#define MCF_INTC_IMRL_INT_MASK31 (0x80000000) ++ ++/* Bit definitions and macros for INTFRCH */ ++#define MCF_INTC_INTFRCH_INTFRC32 (0x00000001) ++#define MCF_INTC_INTFRCH_INTFRC33 (0x00000002) ++#define MCF_INTC_INTFRCH_INTFRC34 (0x00000004) ++#define MCF_INTC_INTFRCH_INTFRC35 (0x00000008) ++#define MCF_INTC_INTFRCH_INTFRC36 (0x00000010) ++#define MCF_INTC_INTFRCH_INTFRC37 (0x00000020) ++#define MCF_INTC_INTFRCH_INTFRC38 (0x00000040) ++#define MCF_INTC_INTFRCH_INTFRC39 (0x00000080) ++#define MCF_INTC_INTFRCH_INTFRC40 (0x00000100) ++#define MCF_INTC_INTFRCH_INTFRC41 (0x00000200) ++#define MCF_INTC_INTFRCH_INTFRC42 (0x00000400) ++#define MCF_INTC_INTFRCH_INTFRC43 (0x00000800) ++#define MCF_INTC_INTFRCH_INTFRC44 (0x00001000) ++#define MCF_INTC_INTFRCH_INTFRC45 (0x00002000) ++#define MCF_INTC_INTFRCH_INTFRC46 (0x00004000) ++#define MCF_INTC_INTFRCH_INTFRC47 (0x00008000) ++#define MCF_INTC_INTFRCH_INTFRC48 (0x00010000) ++#define MCF_INTC_INTFRCH_INTFRC49 (0x00020000) ++#define MCF_INTC_INTFRCH_INTFRC50 (0x00040000) ++#define MCF_INTC_INTFRCH_INTFRC51 (0x00080000) ++#define MCF_INTC_INTFRCH_INTFRC52 (0x00100000) ++#define MCF_INTC_INTFRCH_INTFRC53 (0x00200000) ++#define MCF_INTC_INTFRCH_INTFRC54 (0x00400000) ++#define MCF_INTC_INTFRCH_INTFRC55 (0x00800000) ++#define MCF_INTC_INTFRCH_INTFRC56 (0x01000000) ++#define MCF_INTC_INTFRCH_INTFRC57 (0x02000000) ++#define MCF_INTC_INTFRCH_INTFRC58 (0x04000000) ++#define MCF_INTC_INTFRCH_INTFRC59 (0x08000000) ++#define MCF_INTC_INTFRCH_INTFRC60 (0x10000000) ++#define MCF_INTC_INTFRCH_INTFRC61 (0x20000000) ++#define MCF_INTC_INTFRCH_INTFRC62 (0x40000000) ++#define MCF_INTC_INTFRCH_INTFRC63 (0x80000000) ++ ++/* Bit definitions and macros for INTFRCL */ ++#define MCF_INTC_INTFRCL_INTFRC0 (0x00000001) ++#define MCF_INTC_INTFRCL_INTFRC1 (0x00000002) ++#define MCF_INTC_INTFRCL_INTFRC2 (0x00000004) ++#define MCF_INTC_INTFRCL_INTFRC3 (0x00000008) ++#define MCF_INTC_INTFRCL_INTFRC4 (0x00000010) ++#define MCF_INTC_INTFRCL_INTFRC5 (0x00000020) ++#define MCF_INTC_INTFRCL_INTFRC6 (0x00000040) ++#define MCF_INTC_INTFRCL_INTFRC7 (0x00000080) ++#define MCF_INTC_INTFRCL_INTFRC8 (0x00000100) ++#define MCF_INTC_INTFRCL_INTFRC9 (0x00000200) ++#define MCF_INTC_INTFRCL_INTFRC10 (0x00000400) ++#define MCF_INTC_INTFRCL_INTFRC11 (0x00000800) ++#define MCF_INTC_INTFRCL_INTFRC12 (0x00001000) ++#define MCF_INTC_INTFRCL_INTFRC13 (0x00002000) ++#define MCF_INTC_INTFRCL_INTFRC14 (0x00004000) ++#define MCF_INTC_INTFRCL_INTFRC15 (0x00008000) ++#define MCF_INTC_INTFRCL_INTFRC16 (0x00010000) ++#define MCF_INTC_INTFRCL_INTFRC17 (0x00020000) ++#define MCF_INTC_INTFRCL_INTFRC18 (0x00040000) ++#define MCF_INTC_INTFRCL_INTFRC19 (0x00080000) ++#define MCF_INTC_INTFRCL_INTFRC20 (0x00100000) ++#define MCF_INTC_INTFRCL_INTFRC21 (0x00200000) ++#define MCF_INTC_INTFRCL_INTFRC22 (0x00400000) ++#define MCF_INTC_INTFRCL_INTFRC23 (0x00800000) ++#define MCF_INTC_INTFRCL_INTFRC24 (0x01000000) ++#define MCF_INTC_INTFRCL_INTFRC25 (0x02000000) ++#define MCF_INTC_INTFRCL_INTFRC26 (0x04000000) ++#define MCF_INTC_INTFRCL_INTFRC27 (0x08000000) ++#define MCF_INTC_INTFRCL_INTFRC28 (0x10000000) ++#define MCF_INTC_INTFRCL_INTFRC29 (0x20000000) ++#define MCF_INTC_INTFRCL_INTFRC30 (0x40000000) ++#define MCF_INTC_INTFRCL_INTFRC31 (0x80000000) ++ ++/* Bit definitions and macros for ICONFIG */ ++#define MCF_INTC_ICONFIG_EMASK (0x0020) ++#define MCF_INTC_ICONFIG_ELVLPRI1 (0x0200) ++#define MCF_INTC_ICONFIG_ELVLPRI2 (0x0400) ++#define MCF_INTC_ICONFIG_ELVLPRI3 (0x0800) ++#define MCF_INTC_ICONFIG_ELVLPRI4 (0x1000) ++#define MCF_INTC_ICONFIG_ELVLPRI5 (0x2000) ++#define MCF_INTC_ICONFIG_ELVLPRI6 (0x4000) ++#define MCF_INTC_ICONFIG_ELVLPRI7 (0x8000) ++ ++/* Bit definitions and macros for SIMR */ ++#define MCF_INTC_SIMR_SIMR(x) (((x)&0x7F)) ++ ++/* Bit definitions and macros for CIMR */ ++#define MCF_INTC_CIMR_CIMR(x) (((x)&0x7F)) ++ ++/* Bit definitions and macros for CLMASK */ ++#define MCF_INTC_CLMASK_CLMASK(x) (((x)&0x0F)) ++ ++/* Bit definitions and macros for SLMASK */ ++#define MCF_INTC_SLMASK_SLMASK(x) (((x)&0x0F)) ++ ++/* Bit definitions and macros for ICR group */ ++#define MCF_INTC_ICR_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR1 */ ++#define MCF_INTC_ICR1_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR2 */ ++#define MCF_INTC_ICR2_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR3 */ ++#define MCF_INTC_ICR3_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR4 */ ++#define MCF_INTC_ICR4_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR5 */ ++#define MCF_INTC_ICR5_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR6 */ ++#define MCF_INTC_ICR6_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR7 */ ++#define MCF_INTC_ICR7_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR8 */ ++#define MCF_INTC_ICR8_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR9 */ ++#define MCF_INTC_ICR9_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR10 */ ++#define MCF_INTC_ICR10_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR11 */ ++#define MCF_INTC_ICR11_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR12 */ ++#define MCF_INTC_ICR12_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR13 */ ++#define MCF_INTC_ICR13_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR14 */ ++#define MCF_INTC_ICR14_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR15 */ ++#define MCF_INTC_ICR15_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR16 */ ++#define MCF_INTC_ICR16_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR17 */ ++#define MCF_INTC_ICR17_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR18 */ ++#define MCF_INTC_ICR18_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR19 */ ++#define MCF_INTC_ICR19_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR20 */ ++#define MCF_INTC_ICR20_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR21 */ ++#define MCF_INTC_ICR21_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR22 */ ++#define MCF_INTC_ICR22_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR23 */ ++#define MCF_INTC_ICR23_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR24 */ ++#define MCF_INTC_ICR24_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR25 */ ++#define MCF_INTC_ICR25_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR26 */ ++#define MCF_INTC_ICR26_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR27 */ ++#define MCF_INTC_ICR27_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR28 */ ++#define MCF_INTC_ICR28_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR29 */ ++#define MCF_INTC_ICR29_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR30 */ ++#define MCF_INTC_ICR30_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR31 */ ++#define MCF_INTC_ICR31_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR32 */ ++#define MCF_INTC_ICR32_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR33 */ ++#define MCF_INTC_ICR33_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR34 */ ++#define MCF_INTC_ICR34_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR35 */ ++#define MCF_INTC_ICR35_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR36 */ ++#define MCF_INTC_ICR36_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR37 */ ++#define MCF_INTC_ICR37_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR38 */ ++#define MCF_INTC_ICR38_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR39 */ ++#define MCF_INTC_ICR39_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR40 */ ++#define MCF_INTC_ICR40_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR41 */ ++#define MCF_INTC_ICR41_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR42 */ ++#define MCF_INTC_ICR42_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR43 */ ++#define MCF_INTC_ICR43_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR44 */ ++#define MCF_INTC_ICR44_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR45 */ ++#define MCF_INTC_ICR45_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR46 */ ++#define MCF_INTC_ICR46_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR47 */ ++#define MCF_INTC_ICR47_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR48 */ ++#define MCF_INTC_ICR48_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR49 */ ++#define MCF_INTC_ICR49_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR50 */ ++#define MCF_INTC_ICR50_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR51 */ ++#define MCF_INTC_ICR51_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR52 */ ++#define MCF_INTC_ICR52_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR53 */ ++#define MCF_INTC_ICR53_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR54 */ ++#define MCF_INTC_ICR54_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR55 */ ++#define MCF_INTC_ICR55_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR56 */ ++#define MCF_INTC_ICR56_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR57 */ ++#define MCF_INTC_ICR57_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR58 */ ++#define MCF_INTC_ICR58_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR59 */ ++#define MCF_INTC_ICR59_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR60 */ ++#define MCF_INTC_ICR60_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR61 */ ++#define MCF_INTC_ICR61_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR62 */ ++#define MCF_INTC_ICR62_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR63 */ ++#define MCF_INTC_ICR63_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for SWIACK */ ++#define MCF_INTC_SWIACK_VECTOR(x) (x) ++ ++/* Bit definitions and macros for LIACK group */ ++#define MCF_INTC_LIACK_VECTOR(x) (x) ++ ++/* Bit definitions and macros for L1IACK */ ++#define MCF_INTC_L1IACK_VECTOR(x) (x) ++ ++/* Bit definitions and macros for L2IACK */ ++#define MCF_INTC_L2IACK_VECTOR(x) (x) ++ ++/* Bit definitions and macros for L3IACK */ ++#define MCF_INTC_L3IACK_VECTOR(x) (x) ++ ++/* Bit definitions and macros for L4IACK */ ++#define MCF_INTC_L4IACK_VECTOR(x) (x) ++ ++/* Bit definitions and macros for L5IACK */ ++#define MCF_INTC_L5IACK_VECTOR(x) (x) ++ ++/* Bit definitions and macros for L6IACK */ ++#define MCF_INTC_L6IACK_VECTOR(x) (x) ++ ++/* Bit definitions and macros for L7IACK */ ++#define MCF_INTC_L7IACK_VECTOR(x) (x) ++ ++/********************************************************************/ ++ ++#endif /* __MCF5445X_INTC_H__ */ +--- /dev/null ++++ b/arch/m68k/include/asm/mcf5445x_pci.h +@@ -0,0 +1,238 @@ ++/* ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * Kurt Mahan kmahan@freescale.com ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#ifndef __MCF5445X_PCI_H__ ++#define __MCF5445X_PCI_H__ ++ ++/********************************************************************* ++* ++* PCI Bus Controller (PCI) ++* ++*********************************************************************/ ++ ++/* Register read/write macros */ ++#define MCF_PCI_PCIIDR MCF_REG32(0xFC0A8000) ++#define MCF_PCI_PCISCR MCF_REG32(0xFC0A8004) ++#define MCF_PCI_PCICCRIR MCF_REG32(0xFC0A8008) ++#define MCF_PCI_PCICR1 MCF_REG32(0xFC0A800C) ++#define MCF_PCI_PCIBAR0 MCF_REG32(0xFC0A8010) ++#define MCF_PCI_PCIBAR1 MCF_REG32(0xFC0A8014) ++#define MCF_PCI_PCIBAR2 MCF_REG32(0xFC0A8018) ++#define MCF_PCI_PCIBAR3 MCF_REG32(0xFC0A801C) ++#define MCF_PCI_PCIBAR4 MCF_REG32(0xFC0A8020) ++#define MCF_PCI_PCIBAR5 MCF_REG32(0xFC0A8024) ++#define MCF_PCI_PCISID MCF_REG32(0xFC0A802C) ++#define MCF_PCI_PCICR2 MCF_REG32(0xFC0A803C) ++#define MCF_PCI_PCIGSCR MCF_REG32(0xFC0A8060) ++#define MCF_PCI_PCITBATR0A MCF_REG32(0xFC0A8064) ++#define MCF_PCI_PCITBATR1A MCF_REG32(0xFC0A8068) ++#define MCF_PCI_PCITCR MCF_REG32(0xFC0A806C) ++#define MCF_PCI_PCIIW0BTAR MCF_REG32(0xFC0A8070) ++#define MCF_PCI_PCIIW1BTAR MCF_REG32(0xFC0A8074) ++#define MCF_PCI_PCIIW2BTAR MCF_REG32(0xFC0A8078) ++#define MCF_PCI_PCIIWCR MCF_REG32(0xFC0A8080) ++#define MCF_PCI_PCIICR MCF_REG32(0xFC0A8084) ++#define MCF_PCI_PCIISR MCF_REG32(0xFC0A8088) ++#define MCF_PCI_PCITCR2 MCF_REG32(0xFC0A808C) ++#define MCF_PCI_PCITBATR0 MCF_REG32(0xFC0A8090) ++#define MCF_PCI_PCITBATR1 MCF_REG32(0xFC0A8094) ++#define MCF_PCI_PCITBATR2 MCF_REG32(0xFC0A8098) ++#define MCF_PCI_PCITBATR3 MCF_REG32(0xFC0A809C) ++#define MCF_PCI_PCITBATR4 MCF_REG32(0xFC0A80A0) ++#define MCF_PCI_PCITBATR5 MCF_REG32(0xFC0A80A4) ++#define MCF_PCI_PCICAR MCF_REG32(0xFC0A80F8) ++ ++/* Parameterized register read/write macros for multiple registers */ ++#define MCF_PCI_PCIIWBTAR(x) MCF_REG32(0xFC0A8070+((x)*0x004)) ++ ++/* Bit definitions and macros for PCIIDR */ ++#define MCF_PCI_PCIIDR_VENDORID(x) (((x)&0x0000FFFF)) ++#define MCF_PCI_PCIIDR_DEVICEID(x) (((x)&0x0000FFFF)<<16) ++ ++/* Bit definitions and macros for PCISCR */ ++#define MCF_PCI_PCISCR_M (0x00000002) ++#define MCF_PCI_PCISCR_B (0x00000004) ++#define MCF_PCI_PCISCR_SP (0x00000008) ++#define MCF_PCI_PCISCR_MW (0x00000010) ++#define MCF_PCI_PCISCR_PER (0x00000040) ++#define MCF_PCI_PCISCR_S (0x00000100) ++#define MCF_PCI_PCISCR_F (0x00000200) ++#define MCF_PCI_PCISCR_C (0x00100000) ++#define MCF_PCI_PCISCR_66M (0x00200000) ++#define MCF_PCI_PCISCR_R (0x00400000) ++#define MCF_PCI_PCISCR_FC (0x00800000) ++#define MCF_PCI_PCISCR_DP (0x01000000) ++#define MCF_PCI_PCISCR_DT(x) (((x)&0x00000003)<<25) ++#define MCF_PCI_PCISCR_TS (0x08000000) ++#define MCF_PCI_PCISCR_TR (0x10000000) ++#define MCF_PCI_PCISCR_MA (0x20000000) ++#define MCF_PCI_PCISCR_SE (0x40000000) ++#define MCF_PCI_PCISCR_PE (0x80000000) ++ ++/* Bit definitions and macros for PCICCRIR */ ++#define MCF_PCI_PCICCRIR_REVID(x) (((x)&0x000000FF)) ++#define MCF_PCI_PCICCRIR_CLASSCODE(x) (((x)&0x00FFFFFF)<<8) ++ ++/* Bit definitions and macros for PCICR1 */ ++#define MCF_PCI_PCICR1_CACHELINESIZE(x) (((x)&0x0000000F)) ++#define MCF_PCI_PCICR1_LATTIMER(x) (((x)&0x000000FF)<<8) ++#define MCF_PCI_PCICR1_HEADERTYPE(x) (((x)&0x000000FF)<<16) ++#define MCF_PCI_PCICR1_BIST(x) (((x)&0x000000FF)<<24) ++ ++/* Bit definitions and macros for PCIBAR0 */ ++#define MCF_PCI_PCIBAR0_IO (0x00000001) ++#define MCF_PCI_PCIBAR0_RANGE(x) (((x)&0x00000003)<<1) ++#define MCF_PCI_PCIBAR0_PREF (0x00000008) ++#define MCF_PCI_PCIBAR0_BAR0(x) (((x)&0x00003FFF)<<18) ++ ++/* Bit definitions and macros for PCIBAR1 */ ++#define MCF_PCI_PCIBAR1_IO (0x00000001) ++#define MCF_PCI_PCIBAR1_PREF (0x00000008) ++#define MCF_PCI_PCIBAR1_BAR1(x) (((x)&0x00000FFF)<<20) ++ ++/* Bit definitions and macros for PCIBAR2 */ ++#define MCF_PCI_PCIBAR2_IO (0x00000001) ++#define MCF_PCI_PCIBAR2_RANGE(x) (((x)&0x00000003)<<1) ++#define MCF_PCI_PCIBAR2_PREF (0x00000008) ++#define MCF_PCI_PCIBAR2_BAR2(x) (((x)&0x000003FF)<<22) ++ ++/* Bit definitions and macros for PCIBAR3 */ ++#define MCF_PCI_PCIBAR3_IO (0x00000001) ++#define MCF_PCI_PCIBAR3_PREF (0x00000008) ++#define MCF_PCI_PCIBAR3_BAR3(x) (((x)&0x000000FF)<<24) ++ ++/* Bit definitions and macros for PCIBAR4 */ ++#define MCF_PCI_PCIBAR4_IO (0x00000001) ++#define MCF_PCI_PCIBAR4_RANGE(x) (((x)&0x00000003)<<1) ++#define MCF_PCI_PCIBAR4_PREF (0x00000008) ++#define MCF_PCI_PCIBAR4_BAR4(x) (((x)&0x0000001F)<<27) ++ ++/* Bit definitions and macros for PCIBAR5 */ ++#define MCF_PCI_PCIBAR5_IO (0x00000001) ++#define MCF_PCI_PCIBAR5_PREF (0x00000008) ++#define MCF_PCI_PCIBAR5_BAR5(x) (((x)&0x0000000F)<<28) ++ ++/* Bit definitions and macros for PCISID */ ++#define MCF_PCI_PCISID_VENDORID(x) (((x)&0x0000FFFF)) ++#define MCF_PCI_PCISID_ID(x) (((x)&0x0000FFFF)<<16) ++ ++/* Bit definitions and macros for PCICR2 */ ++#define MCF_PCI_PCICR2_INTLINE(x) (((x)&0x000000FF)) ++#define MCF_PCI_PCICR2_INTPIN(x) (((x)&0x000000FF)<<8) ++#define MCF_PCI_PCICR2_MINGNT(x) (((x)&0x000000FF)<<16) ++#define MCF_PCI_PCICR2_MAXLAT(x) (((x)&0x000000FF)<<24) ++ ++/* Bit definitions and macros for PCIGSCR */ ++#define MCF_PCI_PCIGSCR_PR (0x00000001) ++#define MCF_PCI_PCIGSCR_SEE (0x00001000) ++#define MCF_PCI_PCIGSCR_PEE (0x00002000) ++#define MCF_PCI_PCIGSCR_SE (0x10000000) ++#define MCF_PCI_PCIGSCR_PE (0x20000000) ++ ++/* Bit definitions and macros for PCITBATR0A */ ++#define MCF_PCI_PCITBATR0A_EN (0x00000001) ++#define MCF_PCI_PCITBATR0A_BAT0(x) (((x)&0x00003FFF)<<18) ++ ++/* Bit definitions and macros for PCITBATR1A */ ++#define MCF_PCI_PCITBATR1A_EN (0x00000001) ++#define MCF_PCI_PCITBATR1A_BAT1(x) (((x)&0x00000FFF)<<20) ++ ++/* Bit definitions and macros for PCITCR */ ++#define MCF_PCI_PCITCR_WCT(x) (((x)&0x000000FF)) ++#define MCF_PCI_PCITCR_WCD (0x00000100) ++#define MCF_PCI_PCITCR_P (0x00010000) ++#define MCF_PCI_PCITCR_PID (0x00020000) ++#define MCF_PCI_PCITCR_LD (0x01000000) ++ ++/* Bit definitions and macros for PCIIWBTAR group */ ++#define MCF_PCI_PCIIWBTAR_WBA(x) ((((x)&0xFF000000))) ++#define MCF_PCI_PCIIWBTAR_WAM(x) ((((x)&0xFF000000) ++#define MCF_PCI_PCIIWBTAR_WTA(x) ((((x)&0xFF000000) ++ ++/* Bit definitions and macros for PCIIW0BTAR */ ++#define MCF_PCI_PCIIW0BTAR_WBA(x) ((((x)&0xFF000000))) ++#define MCF_PCI_PCIIW0BTAR_WAM(x) ((((x)&0xFF000000) ++#define MCF_PCI_PCIIW0BTAR_WTA(x) ((((x)&0xFF000000) ++ ++/* Bit definitions and macros for PCIIWCR */ ++#define MCF_PCI_PCIIWCR_WINCTRL2(x) (((x)&0x0000000F)<<8) ++#define MCF_PCI_PCIIWCR_WINCTRL1(x) (((x)&0x0000000F)<<16) ++#define MCF_PCI_PCIIWCR_WINCTRL0(x) (((x)&0x0000000F)<<24) ++#define MCF_PCI_PCIIWCR_WINCTRL0_ENABLE (0x01000000) ++#define MCF_PCI_PCIIWCR_WINCTRL0_MEMREAD (0x01000000) ++#define MCF_PCI_PCIIWCR_WINCTRL0_MEMRDLINE (0x03000000) ++#define MCF_PCI_PCIIWCR_WINCTRL0_MEMRDMUL (0x05000000) ++#define MCF_PCI_PCIIWCR_WINCTRL0_IO (0x09000000) ++#define MCF_PCI_PCIIWCR_WINCTRL1_MEMREAD (0x00010000) ++#define MCF_PCI_PCIIWCR_WINCTRL1_ENABLE (0x00010000) ++#define MCF_PCI_PCIIWCR_WINCTRL1_MEMRDLINE (0x00030000) ++#define MCF_PCI_PCIIWCR_WINCTRL1_MEMRDMUL (0x00050000) ++#define MCF_PCI_PCIIWCR_WINCTRL1_IO (0x00090000) ++#define MCF_PCI_PCIIWCR_WINCTRL2_ENABLE (0x00000100) ++#define MCF_PCI_PCIIWCR_WINCTRL2_MEMREAD (0x00000100) ++#define MCF_PCI_PCIIWCR_WINCTRL2_MEMRDLINE (0x00000300) ++#define MCF_PCI_PCIIWCR_WINCTRL2_MEMRDMUL (0x00000500) ++#define MCF_PCI_PCIIWCR_WINCTRL2_IO (0x00000900) ++ ++/* Bit definitions and macros for PCIICR */ ++#define MCF_PCI_PCIICR_MAXRETRY(x) (((x)&0x000000FF)) ++#define MCF_PCI_PCIICR_TAE (0x01000000) ++#define MCF_PCI_PCIICR_IAE (0x02000000) ++#define MCF_PCI_PCIICR_REE (0x04000000) ++ ++/* Bit definitions and macros for PCIISR */ ++#define MCF_PCI_PCIISR_TA (0x01000000) ++#define MCF_PCI_PCIISR_IA (0x02000000) ++#define MCF_PCI_PCIISR_RE (0x04000000) ++ ++/* Bit definitions and macros for PCITCR2 */ ++#define MCF_PCI_PCITCR2_CR (0x00000001) ++#define MCF_PCI_PCITCR2_B0E (0x00000100) ++#define MCF_PCI_PCITCR2_B1E (0x00000200) ++#define MCF_PCI_PCITCR2_B2E (0x00000400) ++#define MCF_PCI_PCITCR2_B3E (0x00000800) ++#define MCF_PCI_PCITCR2_B4E (0x00001000) ++#define MCF_PCI_PCITCR2_B5E (0x00002000) ++ ++/* Bit definitions and macros for PCITBATR0 */ ++#define MCF_PCI_PCITBATR0_EN (0x00000001) ++#define MCF_PCI_PCITBATR0_BAT0(x) (((x)&0x00003FFF)<<18) ++ ++/* Bit definitions and macros for PCITBATR1 */ ++#define MCF_PCI_PCITBATR1_EN (0x00000001) ++#define MCF_PCI_PCITBATR1_BAT1(x) (((x)&0x00000FFF)<<20) ++ ++/* Bit definitions and macros for PCITBATR2 */ ++#define MCF_PCI_PCITBATR2_EN (0x00000001) ++#define MCF_PCI_PCITBATR2_BAT2(x) (((x)&0x000003FF)<<22) ++ ++/* Bit definitions and macros for PCITBATR3 */ ++#define MCF_PCI_PCITBATR3_EN (0x00000001) ++#define MCF_PCI_PCITBATR3_BAT3(x) (((x)&0x000000FF)<<24) ++ ++/* Bit definitions and macros for PCITBATR4 */ ++#define MCF_PCI_PCITBATR4_EN (0x00000001) ++#define MCF_PCI_PCITBATR4_BAT4(x) (((x)&0x0000001F)<<27) ++ ++/* Bit definitions and macros for PCITBATR5 */ ++#define MCF_PCI_PCITBATR5_EN (0x00000001) ++#define MCF_PCI_PCITBATR5_BAT5(x) (((x)&0x0000000F)<<28) ++ ++/* Bit definitions and macros for PCICAR */ ++#define MCF_PCI_PCICAR_DWORD(x) ((x)&0x000000FC) ++#define MCF_PCI_PCICAR_FUNCNUM(x) (((x)&0x00000007)<<8) ++#define MCF_PCI_PCICAR_DEVNUM(x) (((x)&0x0000001F)<<11) ++#define MCF_PCI_PCICAR_BUSNUM(x) (((x)&0x000000FF)<<16) ++#define MCF_PCI_PCICAR_E (0x80000000) ++ ++/********************************************************************/ ++ ++#endif /* __MCF5445X_PCI_H__ */ +--- /dev/null ++++ b/arch/m68k/include/asm/mcf5445x_pciarb.h +@@ -0,0 +1,40 @@ ++/* ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * Kurt Mahan kmahan@freescale.com ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#ifndef __MCF5445X_PCIARB_H__ ++#define __MCF5445X_PCIARB_H__ ++ ++/********************************************************************* ++* ++* PCI Arbiter Module (PCIARB) ++* ++*********************************************************************/ ++ ++/* Register read/write macros */ ++#define MCF_PCIARB_PACR MCF_REG32(0xFC0AC000) ++#define MCF_PCIARB_PASR MCF_REG32(0xFC0AC004) ++ ++/* Bit definitions and macros for PACR */ ++#define MCF_PCIARB_PACR_INTMPRI (0x00000001) ++#define MCF_PCIARB_PACR_EXTMPRI(x) (((x)&0x0000001F)<<1) ++#define MCF_PCIARB_PACR_RA (0x00008000) ++#define MCF_PCIARB_PACR_INTMINTEN (0x00010000) ++#define MCF_PCIARB_PACR_EXTMINTEN(x) (((x)&0x0000001F)<<17) ++#define MCF_PCIARB_PACR_PKMD (0x40000000) ++#define MCF_PCIARB_PACR_DS (0x80000000) ++ ++/* Bit definitions and macros for PASR */ ++#define MCF_PCIARB_PASR_ITLMBK (0x00010000) ++#define MCF_PCIARB_PASR_EXTMBK(x) (((x)&0x0000001F)<<17) ++ ++/********************************************************************/ ++ ++#endif /* __MCF5445X_PCIARB_H__ */ +--- /dev/null ++++ b/arch/m68k/include/asm/mcf5445x_rtc.h +@@ -0,0 +1,114 @@ ++/* ++ * Copyright (C) 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * Author: ChengJu Cai, B22600@freescale.com ++ * ++ * Description: ++ * This file is the register definition of m5445x RTC module ++ * ++ * Changelog: ++ * ++ * ++ * This file is part of the Linux kernel ++ * ++ * This is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ */ ++ ++#ifndef __MCF5445X_RTC_H__ ++#define __MCF5445X_RTC_H__ ++ ++/********************************************************************* ++* ++* Real-time Clock (RTC) ++* ++*********************************************************************/ ++#ifndef MCFINT_VECBASE ++#define MCFINT_VECBASE 64 ++#endif ++ ++#define MCFSIM_ICR_RTC (0xFC048040 + 63) ++ ++/* Register read/write macros */ ++#define MCF_RTC_HOURMIN 0xFC03C000 ++#define MCF_RTC_SECONDS 0xFC03C004 ++#define MCF_RTC_ALRM_HM 0xFC03C008 ++#define MCF_RTC_ALRM_SEC 0xFC03C00C ++#define MCF_RTC_CR 0xFC03C010 ++#define MCF_RTC_ISR 0xFC03C014 ++#define MCF_RTC_IER 0xFC03C018 ++#define MCF_RTC_STPWCH 0xFC03C01C ++#define MCF_RTC_DAYS 0xFC03C020 ++#define MCF_RTC_ALRM_DAY 0xFC03C024 ++#define MCF_RTC_GOCU 0xFC03C034 ++#define MCF_RTC_GOCL 0xFC03C038 ++ ++/* Bit definitions and macros for MCF_RTC_HOURMIN */ ++#define MCF_RTC_HOURMIN_MINUTES(x) (((x) & 0x0000003F) << 0) ++#define MCF_RTC_HOURMIN_HOURS(x) (((x) & 0x0000001F) << 8) ++ ++/* Bit definitions and macros for MCF_RTC_SECONDS */ ++#define MCF_RTC_SECONDS_SECONDS(x) (((x) & 0x0000003F) << 0) ++ ++/* Bit definitions and macros for MCF_RTC_ALRM_HM */ ++#define MCF_RTC_ALRM_HM_MINUTES(x) (((x) & 0x0000003F) << 0) ++#define MCF_RTC_ALRM_HM_HOURS(x) (((x) & 0x0000001F) << 8) ++ ++/* Bit definitions and macros for MCF_RTC_ALRM_SEC */ ++#define MCF_RTC_ALRM_SEC_SECONDS(x) (((x) & 0x0000003F) << 0) ++ ++/* Bit definitions and macros for MCF_RTC_CR */ ++#define MCF_RTC_CR_SWR 0x00000001 ++#define MCF_RTC_CR_EN 0x00000080 ++ ++/* Bit definitions and macros for MCF_RTC_ISR */ ++#define MCF_RTC_ISR_SW 0x00000001 ++#define MCF_RTC_ISR_MIN 0x00000002 ++#define MCF_RTC_ISR_ALM 0x00000004 ++#define MCF_RTC_ISR_DAY 0x00000008 ++#define MCF_RTC_ISR_1HZ 0x00000010 ++#define MCF_RTC_ISR_HR 0x00000020 ++#define MCF_RTC_ISR_2HZ 0x00000080 ++#define MCF_RTC_ISR_SAM0 0x00000100 ++#define MCF_RTC_ISR_SAM1 0x00000200 ++#define MCF_RTC_ISR_SAM2 0x00000400 ++#define MCF_RTC_ISR_SAM3 0x00000800 ++#define MCF_RTC_ISR_SAM4 0x00001000 ++#define MCF_RTC_ISR_SAM5 0x00002000 ++#define MCF_RTC_ISR_SAM6 0x00004000 ++#define MCF_RTC_ISR_SAM7 0x00008000 ++ ++/* Bit definitions and macros for MCF_RTC_IER */ ++#define MCF_RTC_IER_SW 0x00000001 ++#define MCF_RTC_IER_MIN 0x00000002 ++#define MCF_RTC_IER_ALM 0x00000004 ++#define MCF_RTC_IER_DAY 0x00000008 ++#define MCF_RTC_IER_1HZ 0x00000010 ++#define MCF_RTC_IER_HR 0x00000020 ++#define MCF_RTC_IER_2HZ 0x00000080 ++#define MCF_RTC_IER_SAM0 0x00000100 ++#define MCF_RTC_IER_SAM1 0x00000200 ++#define MCF_RTC_IER_SAM2 0x00000400 ++#define MCF_RTC_IER_SAM3 0x00000800 ++#define MCF_RTC_IER_SAM4 0x00001000 ++#define MCF_RTC_IER_SAM5 0x00002000 ++#define MCF_RTC_IER_SAM6 0x00004000 ++#define MCF_RTC_IER_SAM7 0x00008000 ++ ++/* Bit definitions and macros for MCF_RTC_STPWCH */ ++#define MCF_RTC_STPWCH_CNT(x) (((x) & 0x0000003F) << 0) ++ ++/* Bit definitions and macros for MCF_RTC_DAYS */ ++#define MCF_RTC_DAYS_DAYS(x) (((x) & 0x0000FFFF) << 0) ++ ++/* Bit definitions and macros for MCF_RTC_ALRM_DAY */ ++#define MCF_RTC_ALRM_DAY_DAYS(x) (((x) & 0x0000FFFF) << 0) ++ ++/* Interrupt source */ ++#define MCFINT_RTC 63 ++/*********************************************************************/ ++ ++#endif +--- /dev/null ++++ b/arch/m68k/include/asm/mcf5445x_scm.h +@@ -0,0 +1,48 @@ ++/* ++ * Copyright (C) 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * Author: ChengJu Cai<B22600@freescale.com> ++ * ++ * Description: ++ * This file is the register definition of m5445x's SCM module ++ * ++ * Changelog: ++ * Thur Sep 03 2009 ChengJu Cai <B22600@freescale.com> ++ * - create ++ * ++ * This file is part of the Linux kernel ++ * ++ * This is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ */ ++#ifndef __MCF5445X_SCM_H__ ++#define __MCF5445X_SCM_H__ ++ ++/********************************************************************* ++* ++* System Control Module (SCM) ++* ++*********************************************************************/ ++ ++/* Core Watchdog(CW) Register read/write macros */ ++#define MCF_SCM_CWCR MCF_REG16(0xFC040016) /* CW Control Register */ ++#define MCF_SCM_CWSR MCF_REG08(0xFC04001B) /* CW Service Register */ ++ ++/* CW Bit definitions and macros for SWCR */ ++#define MCF_SCM_CWCR_RO (0x8000) /* CWCR is read-only */ ++#define MCF_SCM_CWCR_CWRWR (0x0100) /* CW run when halted */ ++#define MCF_SCM_CWCR_CWE (0x0080) /* CW timer enable */ ++#define MCF_SCM_CWCR_CWRI(x) (((x) & 0x03) << 5) /* CW reset/interrupt */ ++#define MCF_SCM_CWCR_CWT(x) (((x) & 0x1F) << 0) /* CW time-out period */ ++ ++#ifdef CONFIG_M54455 ++#define MCF_GPT_MAX_TIMEOUT 16 ++#elif defined(CONFIG_M54451) ++#define MCF_GPT_MAX_TIMEOUT 17 ++#endif ++/********************************************************************/ ++ ++#endif /* __MCF5445X_SCM_H__ */ +--- /dev/null ++++ b/arch/m68k/include/asm/mcf5445x_sdramc.h +@@ -0,0 +1,142 @@ ++/* ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * Matt Waddel Matt.Waddel@freescale.com ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#ifndef __MCF5445X_SDRAMC_H__ ++#define __MCF5445X_SDRAMC_H__ ++ ++/********************************************************************* ++* ++* SDRAM Controller (SDRAMC) ++* ++*********************************************************************/ ++ ++/* Register read/write macros */ ++#define MCF_SDRAMC_SDMR \ ++ (*(vuint32 *)(0xFC0B8000)) /* SDRAM Mode/Extended Mode Register */ ++#define MCF_SDRAMC_SDCR \ ++ (*(vuint32 *)(0xFC0B8004)) /* SDRAM Control Register */ ++#define MCF_SDRAMC_SDCFG1 \ ++ (*(vuint32 *)(0xFC0B8008)) /* SDRAM Configuration Register 1 */ ++#define MCF_SDRAMC_SDCFG2 \ ++ (*(vuint32 *)(0xFC0B800C)) /* SDRAM Configuration Register 2 */ ++#define MCF_SDRAMC_SDCS0 \ ++ (*(vuint32 *)(0xFC0B8110)) /* SDRAM Chip Select Register */ ++#define MCF_SDRAMC_SDCS1 \ ++ (*(vuint32 *)(0xFC0B8114)) /* SDRAM Chip Select Register */ ++ ++/* Parameterized register read/write macros for multiple registers */ ++/* SDRAM Chip Select Register */ ++#define MCF_SDRAMC_SDCS(x) (*(vuint32 *)(0xFC0B8110+((x)*0x004))) ++ ++/* Bit definitions and macros for SDMR */ ++#define MCF_SDRAMC_SDMR_DDR2_AD(x) (((x)&0x00003FFF)) /* Address for DDR2 */ ++#define MCF_SDRAMC_SDMR_CMD (0x00010000) /* Command */ ++#define MCF_SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) /* Address */ ++#define MCF_SDRAMC_SDMR_BK(x) (((x)&0x00000003)<<30) /* Bank Address */ ++#define MCF_SDRAMC_SDMR_BK_LMR (0x00000000) ++#define MCF_SDRAMC_SDMR_BK_LEMR (0x40000000) ++ ++/* Bit definitions and macros for SDCR */ ++#define MCF_SDRAMC_SDCR_DPD (0x00000001) /* Deep Power-Down Mode */ ++#define MCF_SDRAMC_SDCR_IPALL (0x00000002) /* Initiate Precharge All */ ++#define MCF_SDRAMC_SDCR_IREF (0x00000004) /* Initiate Refresh */ ++#define MCF_SDRAMC_SDCR_DQS_OE(x) (((x)&0x00000003)<<10) /* DQS Output Enable */ ++#define MCF_SDRAMC_SDCR_MEM_PS (0x00002000) /* Data Port Size */ ++#define MCF_SDRAMC_SDCR_REF_CNT(x) \ ++ (((x)&0x0000003F)<<16) /* Periodic Refresh Counter */ ++#define MCF_SDRAMC_SDCR_OE_RULE (0x00400000) /* Drive Rule Selection */ ++#define MCF_SDRAMC_SDCR_ADDR_MUX(x) \ ++ (((x)&0x00000003)<<24) /* Internal Address Mux Select */ ++#define MCF_SDRAMC_SDCR_DDR2_MODE (0x08000000) /* DDR2 Mode Select */ ++#define MCF_SDRAMC_SDCR_REF_EN (0x10000000) /* Refresh Enable */ ++#define MCF_SDRAMC_SDCR_DDR_MODE (0x20000000) /* DDR Mode Select */ ++#define MCF_SDRAMC_SDCR_CKE (0x40000000) /* Clock Enable */ ++/* SDRAM Mode Register Programming Enable */ ++#define MCF_SDRAMC_SDCR_MODE_EN (0x80000000) ++#define MCF_SDRAMC_SDCR_DQS_OE_BOTH (0x00000C00) ++ ++/* Bit definitions and macros for SDCFG1 */ ++#define MCF_SDRAMC_SDCFG1_WT_LAT(x) \ ++ (((x)&0x00000007)<<4) /* Write Latency */ ++#define MCF_SDRAMC_SDCFG1_REF2ACT(x) \ ++ (((x)&0x0000000F)<<8) /* Refresh to active delay */ ++#define MCF_SDRAMC_SDCFG1_PRE2ACT(x) \ ++ (((x)&0x00000007)<<12) /* Precharge to active delay */ ++#define MCF_SDRAMC_SDCFG1_ACT2RW(x) \ ++ (((x)&0x00000007)<<16) /* Active to read/write delay */ ++#define MCF_SDRAMC_SDCFG1_RD_LAT(x) \ ++ (((x)&0x0000000F)<<20) /* Read CAS Latency */ ++#define MCF_SDRAMC_SDCFG1_SWT2RWP(x) \ ++ (((x)&0x00000007)<<24) /* Single write to read/write/precharge delay */ ++#define MCF_SDRAMC_SDCFG1_SRD2RWP(x) \ ++ (((x)&0x0000000F)<<28) /* Single read to read/write/precharge delay */ ++ ++/* Bit definitions and macros for SDCFG2 */ ++#define MCF_SDRAMC_SDCFG2_BL(x) \ ++ (((x)&0x0000000F)<<16) /* Burst Length */ ++#define MCF_SDRAMC_SDCFG2_BRD2W(x) \ ++ (((x)&0x0000000F)<<20) /* Burst read to write delay */ ++#define MCF_SDRAMC_SDCFG2_BWT2RWP(x) \ ++ (((x)&0x0000000F)<<24) /* Burst write to read/write/precharge delay */ ++#define MCF_SDRAMC_SDCFG2_BRD2RP(x) \ ++ (((x)&0x0000000F)<<28) /* Burst read to read/precharge delay */ ++ ++/* Bit definitions and macros for SDCS group */ ++#define MCF_SDRAMC_SDCS_CSSZ(x) \ ++ (((x)&0x0000001F)) /* Chip-Select Size */ ++#define MCF_SDRAMC_SDCS_CSBA(x) \ ++ (((x)&0x00000FFF)<<20) /* Chip-Select Base Address */ ++#define MCF_SDRAMC_SDCS_BA(x) ((x)&0xFFF00000) ++#define MCF_SDRAMC_SDCS_CSSZ_DISABLE (0x00000000) ++#define MCF_SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013) ++#define MCF_SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014) ++#define MCF_SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015) ++#define MCF_SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016) ++#define MCF_SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017) ++#define MCF_SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018) ++#define MCF_SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019) ++#define MCF_SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A) ++#define MCF_SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B) ++#define MCF_SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C) ++#define MCF_SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D) ++#define MCF_SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E) ++#define MCF_SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F) ++ ++/* Bit definitions and macros for SDCS0 */ ++#define MCF_SDRAMC_SDCS0_CSSZ(x) \ ++ (((x)&0x0000001F)) /* Chip-Select Size */ ++#define MCF_SDRAMC_SDCS0_CSBA(x) \ ++ (((x)&0x00000FFF)<<20) /* Chip-Select Base Address */ ++#define MCF_SDRAMC_SDCS0_BA(x) ((x)&0xFFF00000) ++#define MCF_SDRAMC_SDCS0_CSSZ_DISABLE (0x00000000) ++#define MCF_SDRAMC_SDCS0_CSSZ_1MBYTE (0x00000013) ++#define MCF_SDRAMC_SDCS0_CSSZ_2MBYTE (0x00000014) ++#define MCF_SDRAMC_SDCS0_CSSZ_4MBYTE (0x00000015) ++#define MCF_SDRAMC_SDCS0_CSSZ_8MBYTE (0x00000016) ++#define MCF_SDRAMC_SDCS0_CSSZ_16MBYTE (0x00000017) ++#define MCF_SDRAMC_SDCS0_CSSZ_32MBYTE (0x00000018) ++#define MCF_SDRAMC_SDCS0_CSSZ_64MBYTE (0x00000019) ++#define MCF_SDRAMC_SDCS0_CSSZ_128MBYTE (0x0000001A) ++#define MCF_SDRAMC_SDCS0_CSSZ_256MBYTE (0x0000001B) ++#define MCF_SDRAMC_SDCS0_CSSZ_512MBYTE (0x0000001C) ++#define MCF_SDRAMC_SDCS0_CSSZ_1GBYTE (0x0000001D) ++#define MCF_SDRAMC_SDCS0_CSSZ_2GBYTE (0x0000001E) ++#define MCF_SDRAMC_SDCS0_CSSZ_4GBYTE (0x0000001F) ++ ++/* Bit definitions and macros for SDCS1 */ ++#define MCF_SDRAMC_SDCS1_CSSZ(x) \ ++ (((x)&0x0000001F)) /* Chip-Select Size */ ++#define MCF_SDRAMC_SDCS1_CSBA(x) \ ++ (((x)&0x00000FFF)<<20) /* Chip-Select Base Address */ ++ ++/********************************************************************/ ++ ++#endif /* __MCF5445X_SDRAMC_H__ */ +--- /dev/null ++++ b/arch/m68k/include/asm/mcf5445x_ssi.h +@@ -0,0 +1,187 @@ ++/* ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * Yaroslav Vinogradov yaroslav.vinogradov@freescale.com ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#ifndef __MCF5445X_SSI_H__ ++#define __MCF5445X_SSI_H__ ++ ++/********************************************************************* ++* ++* Synchronous Serial Interface (SSI) ++* ++*********************************************************************/ ++ ++/* Register read/write macros */ ++#define MCF_SSI_TX0 MCF_REG32(0xFC0BC000) ++#define MCF_SSI_TX1 MCF_REG32(0xFC0BC004) ++#define MCF_SSI_RX0 MCF_REG32(0xFC0BC008) ++#define MCF_SSI_RX1 MCF_REG32(0xFC0BC00C) ++#define MCF_SSI_CR MCF_REG32(0xFC0BC010) ++#define MCF_SSI_ISR MCF_REG32(0xFC0BC014) ++#define MCF_SSI_IER MCF_REG32(0xFC0BC018) ++#define MCF_SSI_TCR MCF_REG32(0xFC0BC01C) ++#define MCF_SSI_RCR MCF_REG32(0xFC0BC020) ++#define MCF_SSI_CCR MCF_REG32(0xFC0BC024) ++#define MCF_SSI_FCSR MCF_REG32(0xFC0BC02C) ++#define MCF_SSI_ACR MCF_REG32(0xFC0BC038) ++#define MCF_SSI_ACADD MCF_REG32(0xFC0BC03C) ++#define MCF_SSI_ACDAT MCF_REG32(0xFC0BC040) ++#define MCF_SSI_ATAG MCF_REG32(0xFC0BC044) ++#define MCF_SSI_TMASK MCF_REG32(0xFC0BC048) ++#define MCF_SSI_RMASK MCF_REG32(0xFC0BC04C) ++ ++/* Parameterized register read/write macros for multiple registers */ ++#define MCF_SSI_TX(x) MCF_REG32(0xFC0BC000+((x)*0x004)) ++#define MCF_SSI_RX(x) MCF_REG32(0xFC0BC008+((x)*0x004)) ++ ++/* Bit definitions and macros for TX group */ ++#define MCF_SSI_TX_SSI_TX(x) (x) ++ ++/* Bit definitions and macros for TX0 */ ++#define MCF_SSI_TX0_SSI_TX(x) (x) ++ ++/* Bit definitions and macros for TX1 */ ++#define MCF_SSI_TX1_SSI_TX(x) (x) ++ ++/* Bit definitions and macros for RX group */ ++#define MCF_SSI_RX_SSI_RX(x) (x) ++ ++/* Bit definitions and macros for RX0 */ ++#define MCF_SSI_RX0_SSI_RX(x) (x) ++ ++/* Bit definitions and macros for RX1 */ ++#define MCF_SSI_RX1_SSI_RX(x) (x) ++ ++/* Bit definitions and macros for CR */ ++#define MCF_SSI_CR_SSI_EN (0x00000001) ++#define MCF_SSI_CR_TE (0x00000002) ++#define MCF_SSI_CR_RE (0x00000004) ++#define MCF_SSI_CR_NET (0x00000008) ++#define MCF_SSI_CR_SYN (0x00000010) ++#define MCF_SSI_CR_I2S(x) (((x)&0x00000003)<<5) ++#define MCF_SSI_CR_MCE (0x00000080) ++#define MCF_SSI_CR_TCH (0x00000100) ++#define MCF_SSI_CR_CIS (0x00000200) ++#define MCF_SSI_CR_I2S_NORMAL (0x00000000) ++#define MCF_SSI_CR_I2S_MASTER (0x00000020) ++#define MCF_SSI_CR_I2S_SLAVE (0x00000040) ++ ++/* Bit definitions and macros for ISR */ ++#define MCF_SSI_ISR_TFE0 (0x00000001) ++#define MCF_SSI_ISR_TFE1 (0x00000002) ++#define MCF_SSI_ISR_RFF0 (0x00000004) ++#define MCF_SSI_ISR_RFF1 (0x00000008) ++#define MCF_SSI_ISR_RLS (0x00000010) ++#define MCF_SSI_ISR_TLS (0x00000020) ++#define MCF_SSI_ISR_RFS (0x00000040) ++#define MCF_SSI_ISR_TFS (0x00000080) ++#define MCF_SSI_ISR_TUE0 (0x00000100) ++#define MCF_SSI_ISR_TUE1 (0x00000200) ++#define MCF_SSI_ISR_ROE0 (0x00000400) ++#define MCF_SSI_ISR_ROE1 (0x00000800) ++#define MCF_SSI_ISR_TDE0 (0x00001000) ++#define MCF_SSI_ISR_TDE1 (0x00002000) ++#define MCF_SSI_ISR_RDR0 (0x00004000) ++#define MCF_SSI_ISR_RDR1 (0x00008000) ++#define MCF_SSI_ISR_RXT (0x00010000) ++#define MCF_SSI_ISR_CMDDU (0x00020000) ++#define MCF_SSI_ISR_CMDAU (0x00040000) ++ ++/* Bit definitions and macros for IER */ ++#define MCF_SSI_IER_TFE0 (0x00000001) ++#define MCF_SSI_IER_TFE1 (0x00000002) ++#define MCF_SSI_IER_RFF0 (0x00000004) ++#define MCF_SSI_IER_RFF1 (0x00000008) ++#define MCF_SSI_IER_RLS (0x00000010) ++#define MCF_SSI_IER_TLS (0x00000020) ++#define MCF_SSI_IER_RFS (0x00000040) ++#define MCF_SSI_IER_TFS (0x00000080) ++#define MCF_SSI_IER_TUE0 (0x00000100) ++#define MCF_SSI_IER_TUE1 (0x00000200) ++#define MCF_SSI_IER_ROE0 (0x00000400) ++#define MCF_SSI_IER_ROE1 (0x00000800) ++#define MCF_SSI_IER_TDE0 (0x00001000) ++#define MCF_SSI_IER_TDE1 (0x00002000) ++#define MCF_SSI_IER_RDR0 (0x00004000) ++#define MCF_SSI_IER_RDR1 (0x00008000) ++#define MCF_SSI_IER_RXT (0x00010000) ++#define MCF_SSI_IER_CMDU (0x00020000) ++#define MCF_SSI_IER_CMDAU (0x00040000) ++#define MCF_SSI_IER_TIE (0x00080000) ++#define MCF_SSI_IER_TDMAE (0x00100000) ++#define MCF_SSI_IER_RIE (0x00200000) ++#define MCF_SSI_IER_RDMAE (0x00400000) ++ ++/* Bit definitions and macros for TCR */ ++#define MCF_SSI_TCR_TEFS (0x00000001) ++#define MCF_SSI_TCR_TFSL (0x00000002) ++#define MCF_SSI_TCR_TFSI (0x00000004) ++#define MCF_SSI_TCR_TSCKP (0x00000008) ++#define MCF_SSI_TCR_TSHFD (0x00000010) ++#define MCF_SSI_TCR_TXDIR (0x00000020) ++#define MCF_SSI_TCR_TFDIR (0x00000040) ++#define MCF_SSI_TCR_TFEN0 (0x00000080) ++#define MCF_SSI_TCR_TFEN1 (0x00000100) ++#define MCF_SSI_TCR_TXBIT0 (0x00000200) ++ ++/* Bit definitions and macros for RCR */ ++#define MCF_SSI_RCR_REFS (0x00000001) ++#define MCF_SSI_RCR_RFSL (0x00000002) ++#define MCF_SSI_RCR_RFSI (0x00000004) ++#define MCF_SSI_RCR_RSCKP (0x00000008) ++#define MCF_SSI_RCR_RSHFD (0x00000010) ++#define MCF_SSI_RCR_RFEN0 (0x00000080) ++#define MCF_SSI_RCR_RFEN1 (0x00000100) ++#define MCF_SSI_RCR_RXBIT0 (0x00000200) ++#define MCF_SSI_RCR_RXEXT (0x00000400) ++ ++/* Bit definitions and macros for CCR */ ++#define MCF_SSI_CCR_PM(x) (((x)&0x000000FF)) ++#define MCF_SSI_CCR_DC(x) (((x)&0x0000001F)<<8) ++#define MCF_SSI_CCR_WL(x) (((x)&0x0000000F)<<13) ++#define MCF_SSI_CCR_PSR (0x00020000) ++#define MCF_SSI_CCR_DIV2 (0x00040000) ++ ++/* Bit definitions and macros for FCSR */ ++#define MCF_SSI_FCSR_TFWM0(x) (((x)&0x0000000F)) ++#define MCF_SSI_FCSR_RFWM0(x) (((x)&0x0000000F)<<4) ++#define MCF_SSI_FCSR_TFCNT0(x) (((x)&0x0000000F)<<8) ++#define MCF_SSI_FCSR_RFCNT0(x) (((x)&0x0000000F)<<12) ++#define MCF_SSI_FCSR_TFWM1(x) (((x)&0x0000000F)<<16) ++#define MCF_SSI_FCSR_RFWM1(x) (((x)&0x0000000F)<<20) ++#define MCF_SSI_FCSR_TFCNT1(x) (((x)&0x0000000F)<<24) ++#define MCF_SSI_FCSR_RFCNT1(x) (((x)&0x0000000F)<<28) ++ ++/* Bit definitions and macros for ACR */ ++#define MCF_SSI_ACR_AC97EN (0x00000001) ++#define MCF_SSI_ACR_FV (0x00000002) ++#define MCF_SSI_ACR_TIF (0x00000004) ++#define MCF_SSI_ACR_RD (0x00000008) ++#define MCF_SSI_ACR_WR (0x00000010) ++#define MCF_SSI_ACR_FRDIV(x) (((x)&0x0000003F)<<5) ++ ++/* Bit definitions and macros for ACADD */ ++#define MCF_SSI_ACADD_SSI_ACADD(x) (((x)&0x0007FFFF)) ++ ++/* Bit definitions and macros for ACDAT */ ++#define MCF_SSI_ACDAT_SSI_ACDAT(x) (((x)&0x0007FFFF)) ++ ++/* Bit definitions and macros for ATAG */ ++#define MCF_SSI_ATAG_DDI_ATAG(x) (((x)&0x0000FFFF)) ++ ++/* Bit definitions and macros for TMASK */ ++#define MCF_SSI_TMASK_SSI_TMASK(x) (x) ++ ++/* Bit definitions and macros for RMASK */ ++#define MCF_SSI_RMASK_SSI_RMASK(x) (x) ++ ++/********************************************************************/ ++ ++#endif /* __MCF5445X_SSI_H__ */ +--- /dev/null ++++ b/arch/m68k/include/asm/mcf5445x_xbs.h +@@ -0,0 +1,81 @@ ++/* ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * Kurt Mahan kmahan@freescale.com ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#ifndef __MCF5445X_XBS_H__ ++#define __MCF5445X_XBS_H__ ++ ++/* ++ * Crossbar Switch (XBS) ++ */ ++ ++/* Register read/write macros */ ++#define MCF_XBS_PRS1 MCF_REG32(0xFC004100) /* Flexbus Priority */ ++#define MCF_XBS_CRS1 MCF_REG32(0xFC004110) /* Flexbus Control */ ++#define MCF_XBS_PRS2 MCF_REG32(0xFC004200) /* SDRam Priority */ ++#define MCF_XBS_CRS2 MCF_REG32(0xFC004210) /* SDRam Control */ ++#define MCF_XBS_PRS3 MCF_REG32(0xFC004300) /* ATA Priority */ ++#define MCF_XBS_CRS3 MCF_REG32(0xFC004310) /* ATA Control */ ++#define MCF_XBS_PRS4 MCF_REG32(0xFC004400) /* SRAM Priority */ ++#define MCF_XBS_CRS4 MCF_REG32(0xFC004410) /* SRAM Control */ ++#define MCF_XBS_PRS5 MCF_REG32(0xFC004500) /* PCI Priority */ ++#define MCF_XBS_CRS5 MCF_REG32(0xFC004510) /* PCI Control */ ++#define MCF_XBS_PRS6 MCF_REG32(0xFC004600) /* Slave6 Priority */ ++#define MCF_XBS_CRS6 MCF_REG32(0xFC004610) /* Slave6 Control */ ++#define MCF_XBS_PRS7 MCF_REG32(0xFC004700) /* Other Priority */ ++#define MCF_XBS_CRS7 MCF_REG32(0xFC004710) /* Other Control */ ++ ++/* Priorities */ ++#define MCF_XBS_PRI_1 0 /* Level 1 (highest) */ ++#define MCF_XBS_PRI_2 1 /* Level 2 */ ++#define MCF_XBS_PRI_3 2 /* Level 3 */ ++#define MCF_XBS_PRI_4 3 /* Level 4 */ ++#define MCF_XBS_PRI_5 4 /* Level 5 */ ++#define MCF_XBS_PRI_6 5 /* Level 6 */ ++#define MCF_XBS_PRI_7 6 /* Level 7 (lowest) */ ++#define MCF_XBS_PRI_MASK 7 /* Mask (Not a valid level) */ ++ ++/* Priority Register (PRSn) Defs */ ++#define MCF_XBS_PRS_MACRO(m, p) ((p)<<((m)<<2)) ++#define MCF_XBS_PRS_M0(p) MCF_XBS_PRS_MACRO(0, p) /* Coldfire Core */ ++#define MCF_XBS_PRS_M1(p) MCF_XBS_PRS_MACRO(1, p) /* eDMA */ ++#define MCF_XBS_PRS_M2(p) MCF_XBS_PRS_MACRO(2, p) /* FEC0 */ ++#define MCF_XBS_PRS_M3(p) MCF_XBS_PRS_MACRO(3, p) /* FEC1 */ ++#define MCF_XBS_PRS_M4(p) MCF_XBS_PRS_MACRO(4, p) /* Master 4 */ ++#define MCF_XBS_PRS_M5(p) MCF_XBS_PRS_MACRO(5, p) /* PCI */ ++#define MCF_XBS_PRS_M6(p) MCF_XBS_PRS_MACRO(6, p) /* USB OTG */ ++#define MCF_XBS_PRS_M7(p) MCF_XBS_PRS_MACRO(7, p) /* Serial Boot */ ++ ++/* Control Register (CRSn) Defs */ ++#define MCF_XBS_CRS_RO 0x80000000 /* Read Only */ ++#define MCF_XBS_CRS_ARB 0x00000100 /* Arbitration Mode */ ++#define MCF_XBS_CRS_PCTL 0x00000030 /* Parking Control */ ++#define MCF_XBS_CRS_PARK 0x00000007 /* Park Location */ ++ ++/* MCF_XBS_CRS_ARB Defs */ ++#define MCF_ABS_CRS_ARB_FIXED 0x00000000 /* Fixed priority */ ++#define MCF_ABS_CRS_ARB_ROUND 0x00000100 /* Round Robin priority */ ++ ++/* MCF_XBS_CRS_PCTL Defs */ ++#define MCF_ABS_CRS_PCTL_PARK 0x00000000 /* Park on the defined PARK */ ++#define MCF_ABS_CRS_PCTL_LAST 0x00000010 /* Park on the last master */ ++#define MCF_ABS_CRS_PCTL_NONE 0x00000020 /* Don't park */ ++ ++/* MCF_XBS_CRS_PARK Defs */ ++#define MCF_ABS_CRS_PARK_M0 0x00000000 /* Park on Coldfire Core */ ++#define MCF_ABS_CRS_PARK_M1 0x00000001 /* Park on eDMA */ ++#define MCF_ABS_CRS_PARK_M2 0x00000002 /* Park on FEC0 */ ++#define MCF_ABS_CRS_PARK_M3 0x00000003 /* Park on FEC1 */ ++#define MCF_ABS_CRS_PARK_M4 0x00000004 /* Park on Reserved */ ++#define MCF_ABS_CRS_PARK_M5 0x00000005 /* Park on PCI */ ++#define MCF_ABS_CRS_PARK_M6 0x00000006 /* Park on USB OTG */ ++#define MCF_ABS_CRS_PARK_M7 0x00000007 /* Park on Serial Boot */ ++ ++#endif /* __MCF5445X_XBS_H__ */ |