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Diffstat (limited to 'target/linux/brcm47xx-2.6/patches-2.6.22/150-cpu_fixes.patch')
-rw-r--r--target/linux/brcm47xx-2.6/patches-2.6.22/150-cpu_fixes.patch643
1 files changed, 0 insertions, 643 deletions
diff --git a/target/linux/brcm47xx-2.6/patches-2.6.22/150-cpu_fixes.patch b/target/linux/brcm47xx-2.6/patches-2.6.22/150-cpu_fixes.patch
deleted file mode 100644
index ebc40f9f9..000000000
--- a/target/linux/brcm47xx-2.6/patches-2.6.22/150-cpu_fixes.patch
+++ /dev/null
@@ -1,643 +0,0 @@
-Index: linux-2.6.22/arch/mips/kernel/genex.S
-===================================================================
---- linux-2.6.22.orig/arch/mips/kernel/genex.S 2007-07-26 06:29:25.057170943 +0200
-+++ linux-2.6.22/arch/mips/kernel/genex.S 2007-07-26 06:29:40.890073208 +0200
-@@ -51,6 +51,10 @@
- NESTED(except_vec3_generic, 0, sp)
- .set push
- .set noat
-+#ifdef CONFIG_BCM947XX
-+ nop
-+ nop
-+#endif
- #if R5432_CP0_INTERRUPT_WAR
- mfc0 k0, CP0_INDEX
- #endif
-Index: linux-2.6.22/arch/mips/mm/c-r4k.c
-===================================================================
---- linux-2.6.22.orig/arch/mips/mm/c-r4k.c 2007-07-26 06:29:40.826069560 +0200
-+++ linux-2.6.22/arch/mips/mm/c-r4k.c 2007-07-26 06:32:45.956619550 +0200
-@@ -29,6 +29,9 @@
- #include <asm/cacheflush.h> /* for run_uncached() */
-
-
-+/* For enabling BCM4710 cache workarounds */
-+int bcm4710 = 0;
-+
- /*
- * Special Variant of smp_call_function for use by cache functions:
- *
-@@ -85,14 +88,21 @@
-
- static inline void r4k_blast_dcache_page_dc32(unsigned long addr)
- {
-+ unsigned long flags;
-+
-+ local_irq_save(flags);
- R4600_HIT_CACHEOP_WAR_IMPL;
- blast_dcache32_page(addr);
-+ local_irq_restore(flags);
- }
-
- static void __init r4k_blast_dcache_page_setup(void)
- {
- unsigned long dc_lsize = cpu_dcache_line_size();
-
-+ if (bcm4710)
-+ r4k_blast_dcache_page = blast_dcache_page;
-+ else
- if (dc_lsize == 0)
- r4k_blast_dcache_page = (void *)cache_noop;
- else if (dc_lsize == 16)
-@@ -107,6 +117,9 @@
- {
- unsigned long dc_lsize = cpu_dcache_line_size();
-
-+ if (bcm4710)
-+ r4k_blast_dcache_page_indexed = blast_dcache_page_indexed;
-+ else
- if (dc_lsize == 0)
- r4k_blast_dcache_page_indexed = (void *)cache_noop;
- else if (dc_lsize == 16)
-@@ -121,6 +134,9 @@
- {
- unsigned long dc_lsize = cpu_dcache_line_size();
-
-+ if (bcm4710)
-+ r4k_blast_dcache = blast_dcache;
-+ else
- if (dc_lsize == 0)
- r4k_blast_dcache = (void *)cache_noop;
- else if (dc_lsize == 16)
-@@ -202,8 +218,12 @@
-
- static void (* r4k_blast_icache_page)(unsigned long addr);
-
-+static void r4k_flush_cache_all(void);
- static void __init r4k_blast_icache_page_setup(void)
- {
-+#ifdef CONFIG_BCM947XX
-+ r4k_blast_icache_page = (void *)r4k_flush_cache_all;
-+#else
- unsigned long ic_lsize = cpu_icache_line_size();
-
- if (ic_lsize == 0)
-@@ -214,6 +234,7 @@
- r4k_blast_icache_page = blast_icache32_page;
- else if (ic_lsize == 64)
- r4k_blast_icache_page = blast_icache64_page;
-+#endif
- }
-
-
-@@ -221,6 +242,9 @@
-
- static void __init r4k_blast_icache_page_indexed_setup(void)
- {
-+#ifdef CONFIG_BCM947XX
-+ r4k_blast_icache_page_indexed = (void *)r4k_flush_cache_all;
-+#else
- unsigned long ic_lsize = cpu_icache_line_size();
-
- if (ic_lsize == 0)
-@@ -239,6 +263,7 @@
- blast_icache32_page_indexed;
- } else if (ic_lsize == 64)
- r4k_blast_icache_page_indexed = blast_icache64_page_indexed;
-+#endif
- }
-
- static void (* r4k_blast_icache)(void);
-@@ -322,12 +347,17 @@
- */
- static inline void local_r4k_flush_cache_all(void * args)
- {
-+ unsigned long flags;
-+
-+ local_irq_save(flags);
- r4k_blast_dcache();
-+ r4k_blast_icache();
-+ local_irq_restore(flags);
- }
-
- static void r4k_flush_cache_all(void)
- {
-- if (!cpu_has_dc_aliases)
-+ if (!cpu_has_dc_aliases && cpu_use_kmap_coherent)
- return;
-
- r4k_on_each_cpu(local_r4k_flush_cache_all, NULL, 1, 1);
-@@ -335,6 +365,9 @@
-
- static inline void local_r4k___flush_cache_all(void * args)
- {
-+ unsigned long flags;
-+
-+ local_irq_save(flags);
- r4k_blast_dcache();
- r4k_blast_icache();
-
-@@ -348,6 +381,7 @@
- case CPU_R14000:
- r4k_blast_scache();
- }
-+ local_irq_restore(flags);
- }
-
- static void r4k___flush_cache_all(void)
-@@ -358,17 +392,21 @@
- static inline void local_r4k_flush_cache_range(void * args)
- {
- struct vm_area_struct *vma = args;
-+ unsigned long flags;
-
- if (!(cpu_context(smp_processor_id(), vma->vm_mm)))
- return;
-
-+ local_irq_save(flags);
- r4k_blast_dcache();
-+ r4k_blast_icache();
-+ local_irq_restore(flags);
- }
-
- static void r4k_flush_cache_range(struct vm_area_struct *vma,
- unsigned long start, unsigned long end)
- {
-- if (!cpu_has_dc_aliases)
-+ if (!cpu_has_dc_aliases && cpu_use_kmap_coherent)
- return;
-
- r4k_on_each_cpu(local_r4k_flush_cache_range, vma, 1, 1);
-@@ -377,6 +415,7 @@
- static inline void local_r4k_flush_cache_mm(void * args)
- {
- struct mm_struct *mm = args;
-+ unsigned long flags;
-
- if (!cpu_context(smp_processor_id(), mm))
- return;
-@@ -395,12 +434,15 @@
- return;
- }
-
-+ local_irq_save(flags);
- r4k_blast_dcache();
-+ r4k_blast_icache();
-+ local_irq_restore(flags);
- }
-
- static void r4k_flush_cache_mm(struct mm_struct *mm)
- {
-- if (!cpu_has_dc_aliases)
-+ if (!cpu_has_dc_aliases && cpu_use_kmap_coherent)
- return;
-
- r4k_on_each_cpu(local_r4k_flush_cache_mm, mm, 1, 1);
-@@ -420,6 +462,7 @@
- unsigned long paddr = fcp_args->pfn << PAGE_SHIFT;
- int exec = vma->vm_flags & VM_EXEC;
- struct mm_struct *mm = vma->vm_mm;
-+ unsigned long flags;
- pgd_t *pgdp;
- pud_t *pudp;
- pmd_t *pmdp;
-@@ -451,8 +494,9 @@
- * for every cache flush operation. So we do indexed flushes
- * in that case, which doesn't overly flush the cache too much.
- */
-+ local_irq_save(flags);
- if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) {
-- if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
-+ if (!cpu_use_kmap_coherent || cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
- r4k_blast_dcache_page(addr);
- if (exec && !cpu_icache_snoops_remote_store)
- r4k_blast_scache_page(addr);
-@@ -460,14 +504,14 @@
- if (exec)
- r4k_blast_icache_page(addr);
-
-- return;
-+ goto done;
- }
-
- /*
- * Do indexed flush, too much work to get the (possible) TLB refills
- * to work correctly.
- */
-- if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
-+ if (!cpu_use_kmap_coherent || cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
- r4k_blast_dcache_page_indexed(cpu_has_pindexed_dcache ?
- paddr : addr);
- if (exec && !cpu_icache_snoops_remote_store) {
-@@ -483,6 +527,8 @@
- } else
- r4k_blast_icache_page_indexed(addr);
- }
-+done:
-+ local_irq_restore(flags);
- }
-
- static void r4k_flush_cache_page(struct vm_area_struct *vma,
-@@ -499,7 +545,11 @@
-
- static inline void local_r4k_flush_data_cache_page(void * addr)
- {
-+ unsigned long flags;
-+
-+ local_irq_save(flags);
- r4k_blast_dcache_page((unsigned long) addr);
-+ local_irq_restore(flags);
- }
-
- static void r4k_flush_data_cache_page(unsigned long addr)
-@@ -542,6 +592,9 @@
-
- static void r4k_flush_icache_range(unsigned long start, unsigned long end)
- {
-+#ifdef CONFIG_BCM947XX
-+ r4k_flush_cache_all();
-+#else
- struct flush_icache_range_args args;
-
- args.start = start;
-@@ -549,12 +602,15 @@
-
- r4k_on_each_cpu(local_r4k_flush_icache_range, &args, 1, 1);
- instruction_hazard();
-+#endif
- }
-
- #ifdef CONFIG_DMA_NONCOHERENT
-
- static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
- {
-+ unsigned long flags;
-+
- /* Catch bad driver code */
- BUG_ON(size == 0);
-
-@@ -571,18 +627,21 @@
- * subset property so we have to flush the primary caches
- * explicitly
- */
-+ local_irq_save(flags);
- if (size >= dcache_size) {
- r4k_blast_dcache();
- } else {
- R4600_HIT_CACHEOP_WAR_IMPL;
- blast_dcache_range(addr, addr + size);
- }
--
- bc_wback_inv(addr, size);
-+ local_irq_restore(flags);
- }
-
- static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
- {
-+ unsigned long flags;
-+
- /* Catch bad driver code */
- BUG_ON(size == 0);
-
-@@ -594,6 +653,7 @@
- return;
- }
-
-+ local_irq_save(flags);
- if (size >= dcache_size) {
- r4k_blast_dcache();
- } else {
-@@ -602,6 +662,7 @@
- }
-
- bc_inv(addr, size);
-+ local_irq_restore(flags);
- }
- #endif /* CONFIG_DMA_NONCOHERENT */
-
-@@ -616,8 +677,12 @@
- unsigned long dc_lsize = cpu_dcache_line_size();
- unsigned long sc_lsize = cpu_scache_line_size();
- unsigned long addr = (unsigned long) arg;
-+ unsigned long flags;
-
-+ local_irq_save(flags);
- R4600_HIT_CACHEOP_WAR_IMPL;
-+ BCM4710_PROTECTED_FILL_TLB(addr);
-+ BCM4710_PROTECTED_FILL_TLB(addr + 4);
- if (dc_lsize)
- protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
- if (!cpu_icache_snoops_remote_store && scache_size)
-@@ -644,6 +709,7 @@
- }
- if (MIPS_CACHE_SYNC_WAR)
- __asm__ __volatile__ ("sync");
-+ local_irq_restore(flags);
- }
-
- static void r4k_flush_cache_sigtramp(unsigned long addr)
-@@ -1144,6 +1210,17 @@
- * silly idea of putting something else there ...
- */
- switch (current_cpu_data.cputype) {
-+ case CPU_BCM3302:
-+ {
-+ u32 cm;
-+ cm = read_c0_diag();
-+ /* Enable icache */
-+ cm |= (1 << 31);
-+ /* Enable dcache */
-+ cm |= (1 << 30);
-+ write_c0_diag(cm);
-+ }
-+ break;
- case CPU_R4000PC:
- case CPU_R4000SC:
- case CPU_R4000MC:
-@@ -1174,6 +1251,15 @@
- /* Default cache error handler for R4000 and R5000 family */
- set_uncached_handler (0x100, &except_vec2_generic, 0x80);
-
-+ /* Check if special workarounds are required */
-+#ifdef CONFIG_BCM947XX
-+ if (current_cpu_data.cputype == CPU_BCM4710 && (current_cpu_data.processor_id & 0xff) == 0) {
-+ printk("Enabling BCM4710A0 cache workarounds.\n");
-+ bcm4710 = 1;
-+ } else
-+#endif
-+ bcm4710 = 0;
-+
- probe_pcache();
- setup_scache();
-
-@@ -1219,5 +1305,13 @@
- build_clear_page();
- build_copy_page();
- local_r4k___flush_cache_all(NULL);
-+#ifdef CONFIG_BCM947XX
-+ {
-+ static void (*_coherency_setup)(void);
-+ _coherency_setup = (void (*)(void)) KSEG1ADDR(coherency_setup);
-+ _coherency_setup();
-+ }
-+#else
- coherency_setup();
-+#endif
- }
-Index: linux-2.6.22/arch/mips/mm/tlbex.c
-===================================================================
---- linux-2.6.22.orig/arch/mips/mm/tlbex.c 2007-07-26 06:29:40.582055658 +0200
-+++ linux-2.6.22/arch/mips/mm/tlbex.c 2007-07-26 06:32:45.964620005 +0200
-@@ -1229,6 +1229,10 @@
- #endif
- }
-
-+#ifdef CONFIG_BCM947XX
-+extern int bcm4710;
-+#endif
-+
- static void __init build_r4000_tlb_refill_handler(void)
- {
- u32 *p = tlb_handler;
-@@ -1243,6 +1247,10 @@
- memset(relocs, 0, sizeof(relocs));
- memset(final_handler, 0, sizeof(final_handler));
-
-+#ifdef CONFIG_BCM947XX
-+ i_nop(&p);
-+#endif
-+
- /*
- * create the plain linear handler
- */
-@@ -1736,6 +1744,9 @@
- memset(labels, 0, sizeof(labels));
- memset(relocs, 0, sizeof(relocs));
-
-+#ifdef CONFIG_BCM947XX
-+ i_nop(&p);
-+#endif
- if (bcm1250_m3_war()) {
- i_MFC0(&p, K0, C0_BADVADDR);
- i_MFC0(&p, K1, C0_ENTRYHI);
-Index: linux-2.6.22/include/asm-mips/r4kcache.h
-===================================================================
---- linux-2.6.22.orig/include/asm-mips/r4kcache.h 2007-07-26 06:29:25.085172538 +0200
-+++ linux-2.6.22/include/asm-mips/r4kcache.h 2007-07-26 06:29:40.938075943 +0200
-@@ -17,6 +17,20 @@
- #include <asm/cpu-features.h>
- #include <asm/mipsmtregs.h>
-
-+#ifdef CONFIG_BCM947XX
-+#include <asm/paccess.h>
-+#include <linux/ssb/ssb.h>
-+#define BCM4710_DUMMY_RREG() ((void) *((u8 *) KSEG1ADDR(SSB_ENUM_BASE + SSB_IMSTATE)))
-+
-+#define BCM4710_FILL_TLB(addr) (*(volatile unsigned long *)(addr))
-+#define BCM4710_PROTECTED_FILL_TLB(addr) ({ unsigned long x; get_dbe(x, (volatile unsigned long *)(addr)); })
-+#else
-+#define BCM4710_DUMMY_RREG()
-+
-+#define BCM4710_FILL_TLB(addr)
-+#define BCM4710_PROTECTED_FILL_TLB(addr)
-+#endif
-+
- /*
- * This macro return a properly sign-extended address suitable as base address
- * for indexed cache operations. Two issues here:
-@@ -150,6 +164,7 @@
- static inline void flush_dcache_line_indexed(unsigned long addr)
- {
- __dflush_prologue
-+ BCM4710_DUMMY_RREG();
- cache_op(Index_Writeback_Inv_D, addr);
- __dflush_epilogue
- }
-@@ -169,6 +184,7 @@
- static inline void flush_dcache_line(unsigned long addr)
- {
- __dflush_prologue
-+ BCM4710_DUMMY_RREG();
- cache_op(Hit_Writeback_Inv_D, addr);
- __dflush_epilogue
- }
-@@ -176,6 +192,7 @@
- static inline void invalidate_dcache_line(unsigned long addr)
- {
- __dflush_prologue
-+ BCM4710_DUMMY_RREG();
- cache_op(Hit_Invalidate_D, addr);
- __dflush_epilogue
- }
-@@ -208,6 +225,7 @@
- */
- static inline void protected_flush_icache_line(unsigned long addr)
- {
-+ BCM4710_DUMMY_RREG();
- protected_cache_op(Hit_Invalidate_I, addr);
- }
-
-@@ -219,6 +237,7 @@
- */
- static inline void protected_writeback_dcache_line(unsigned long addr)
- {
-+ BCM4710_DUMMY_RREG();
- protected_cache_op(Hit_Writeback_Inv_D, addr);
- }
-
-@@ -339,8 +358,52 @@
- : "r" (base), \
- "i" (op));
-
-+static inline void blast_dcache(void)
-+{
-+ unsigned long start = KSEG0;
-+ unsigned long dcache_size = current_cpu_data.dcache.waysize * current_cpu_data.dcache.ways;
-+ unsigned long end = (start + dcache_size);
-+
-+ do {
-+ BCM4710_DUMMY_RREG();
-+ cache_op(Index_Writeback_Inv_D, start);
-+ start += current_cpu_data.dcache.linesz;
-+ } while(start < end);
-+}
-+
-+static inline void blast_dcache_page(unsigned long page)
-+{
-+ unsigned long start = page;
-+ unsigned long end = start + PAGE_SIZE;
-+
-+ BCM4710_FILL_TLB(start);
-+ do {
-+ BCM4710_DUMMY_RREG();
-+ cache_op(Hit_Writeback_Inv_D, start);
-+ start += current_cpu_data.dcache.linesz;
-+ } while(start < end);
-+}
-+
-+static inline void blast_dcache_page_indexed(unsigned long page)
-+{
-+ unsigned long start = page;
-+ unsigned long end = start + PAGE_SIZE;
-+ unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
-+ unsigned long ws_end = current_cpu_data.dcache.ways <<
-+ current_cpu_data.dcache.waybit;
-+ unsigned long ws, addr;
-+ for (ws = 0; ws < ws_end; ws += ws_inc) {
-+ start = page + ws;
-+ for (addr = start; addr < end; addr += current_cpu_data.dcache.linesz) {
-+ BCM4710_DUMMY_RREG();
-+ cache_op(Index_Writeback_Inv_D, addr);
-+ }
-+ }
-+}
-+
-+
- /* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */
--#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize) \
-+#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, war) \
- static inline void blast_##pfx##cache##lsize(void) \
- { \
- unsigned long start = INDEX_BASE; \
-@@ -352,6 +415,7 @@
- \
- __##pfx##flush_prologue \
- \
-+ war \
- for (ws = 0; ws < ws_end; ws += ws_inc) \
- for (addr = start; addr < end; addr += lsize * 32) \
- cache##lsize##_unroll32(addr|ws,indexop); \
-@@ -366,6 +430,7 @@
- \
- __##pfx##flush_prologue \
- \
-+ war \
- do { \
- cache##lsize##_unroll32(start,hitop); \
- start += lsize * 32; \
-@@ -384,6 +449,8 @@
- current_cpu_data.desc.waybit; \
- unsigned long ws, addr; \
- \
-+ war \
-+ \
- __##pfx##flush_prologue \
- \
- for (ws = 0; ws < ws_end; ws += ws_inc) \
-@@ -393,28 +460,30 @@
- __##pfx##flush_epilogue \
- }
-
--__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16)
--__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16)
--__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16)
--__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32)
--__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32)
--__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32)
--__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
--__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64)
--__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128)
-+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, )
-+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, BCM4710_FILL_TLB(start);)
-+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, )
-+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, )
-+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, BCM4710_FILL_TLB(start);)
-+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, )
-+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, BCM4710_FILL_TLB(start);)
-+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, )
-+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, )
-
- /* build blast_xxx_range, protected_blast_xxx_range */
--#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot) \
-+#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, war, war2) \
- static inline void prot##blast_##pfx##cache##_range(unsigned long start, \
- unsigned long end) \
- { \
- unsigned long lsize = cpu_##desc##_line_size(); \
- unsigned long addr = start & ~(lsize - 1); \
- unsigned long aend = (end - 1) & ~(lsize - 1); \
-+ war \
- \
- __##pfx##flush_prologue \
- \
- while (1) { \
-+ war2 \
- prot##cache_op(hitop, addr); \
- if (addr == aend) \
- break; \
-@@ -424,13 +493,13 @@
- __##pfx##flush_epilogue \
- }
-
--__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_)
--__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_)
--__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_)
--__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, )
--__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, )
-+__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, BCM4710_PROTECTED_FILL_TLB(addr); BCM4710_PROTECTED_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
-+__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_,, )
-+__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_,, )
-+__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D,, BCM4710_FILL_TLB(addr); BCM4710_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
-+__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD,,, )
- /* blast_inv_dcache_range */
--__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, )
--__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, )
-+__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D,,,BCM4710_DUMMY_RREG();)
-+__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD,,, )
-
- #endif /* _ASM_R4KCACHE_H */
-Index: linux-2.6.22/include/asm-mips/stackframe.h
-===================================================================
---- linux-2.6.22.orig/include/asm-mips/stackframe.h 2007-07-26 06:29:25.093172994 +0200
-+++ linux-2.6.22/include/asm-mips/stackframe.h 2007-07-26 06:29:40.962077312 +0200
-@@ -350,6 +350,10 @@
- .macro RESTORE_SP_AND_RET
- LONG_L sp, PT_R29(sp)
- .set mips3
-+#ifdef CONFIG_BCM947XX
-+ nop
-+ nop
-+#endif
- eret
- .set mips0
- .endm