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Diffstat (limited to 'target/linux/ar71xx/patches-3.2/125-MIPS-ath79-add-GPIO-support-code-for-AR934X.patch')
-rw-r--r--target/linux/ar71xx/patches-3.2/125-MIPS-ath79-add-GPIO-support-code-for-AR934X.patch98
1 files changed, 98 insertions, 0 deletions
diff --git a/target/linux/ar71xx/patches-3.2/125-MIPS-ath79-add-GPIO-support-code-for-AR934X.patch b/target/linux/ar71xx/patches-3.2/125-MIPS-ath79-add-GPIO-support-code-for-AR934X.patch
new file mode 100644
index 000000000..f406db90e
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.2/125-MIPS-ath79-add-GPIO-support-code-for-AR934X.patch
@@ -0,0 +1,98 @@
+From c01b6005cfa2d762c2de33d5be2e82f91afaa66f Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Fri, 9 Dec 2011 20:53:47 +0100
+Subject: [PATCH 25/35] MIPS: ath79: add GPIO support code for AR934X
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
+---
+ arch/mips/ath79/gpio.c | 47 +++++++++++++++++++++++-
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 1 +
+ 2 files changed, 47 insertions(+), 1 deletions(-)
+
+--- a/arch/mips/ath79/gpio.c
++++ b/arch/mips/ath79/gpio.c
+@@ -1,9 +1,12 @@
+ /*
+ * Atheros AR71XX/AR724X/AR913X GPIO API support
+ *
+- * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
++ * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
++ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
++ * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
++ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+@@ -89,6 +92,42 @@ static int ath79_gpio_direction_output(s
+ return 0;
+ }
+
++static int ar934x_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
++{
++ void __iomem *base = ath79_gpio_base;
++ unsigned long flags;
++
++ spin_lock_irqsave(&ath79_gpio_lock, flags);
++
++ __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) | (1 << offset),
++ base + AR71XX_GPIO_REG_OE);
++
++ spin_unlock_irqrestore(&ath79_gpio_lock, flags);
++
++ return 0;
++}
++
++static int ar934x_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
++ int value)
++{
++ void __iomem *base = ath79_gpio_base;
++ unsigned long flags;
++
++ spin_lock_irqsave(&ath79_gpio_lock, flags);
++
++ if (value)
++ __raw_writel(1 << offset, base + AR71XX_GPIO_REG_SET);
++ else
++ __raw_writel(1 << offset, base + AR71XX_GPIO_REG_CLEAR);
++
++ __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << offset),
++ base + AR71XX_GPIO_REG_OE);
++
++ spin_unlock_irqrestore(&ath79_gpio_lock, flags);
++
++ return 0;
++}
++
+ static struct gpio_chip ath79_gpio_chip = {
+ .label = "ath79",
+ .get = ath79_gpio_get_value,
+@@ -155,11 +194,17 @@ void __init ath79_gpio_init(void)
+ ath79_gpio_count = AR913X_GPIO_COUNT;
+ else if (soc_is_ar933x())
+ ath79_gpio_count = AR933X_GPIO_COUNT;
++ else if (soc_is_ar934x())
++ ath79_gpio_count = AR934X_GPIO_COUNT;
+ else
+ BUG();
+
+ ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
+ ath79_gpio_chip.ngpio = ath79_gpio_count;
++ if (soc_is_ar934x()) {
++ ath79_gpio_chip.direction_input = ar934x_gpio_direction_input;
++ ath79_gpio_chip.direction_output = ar934x_gpio_direction_output;
++ }
+
+ err = gpiochip_add(&ath79_gpio_chip);
+ if (err)
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -367,5 +367,6 @@
+ #define AR724X_GPIO_COUNT 18
+ #define AR913X_GPIO_COUNT 22
+ #define AR933X_GPIO_COUNT 30
++#define AR934X_GPIO_COUNT 23
+
+ #endif /* __ASM_MACH_AR71XX_REGS_H */