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-rw-r--r--target/linux/ar71xx/files/arch/mips/include/asm/mach-ath79/ag71xx_platform.h54
-rw-r--r--target/linux/ar71xx/files/arch/mips/include/asm/mach-ath79/mach-rb750.h68
-rw-r--r--target/linux/ar71xx/files/arch/mips/include/asm/mach-ath79/rb4xx_cpld.h48
3 files changed, 170 insertions, 0 deletions
diff --git a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ath79/ag71xx_platform.h b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ath79/ag71xx_platform.h
new file mode 100644
index 000000000..43e67557a
--- /dev/null
+++ b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ath79/ag71xx_platform.h
@@ -0,0 +1,54 @@
+/*
+ * Atheros AR71xx SoC specific platform data definitions
+ *
+ * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#ifndef __ASM_MACH_ATH79_PLATFORM_H
+#define __ASM_MACH_ATH79_PLATFORM_H
+
+#include <linux/if_ether.h>
+#include <linux/skbuff.h>
+#include <linux/phy.h>
+#include <linux/spi/spi.h>
+
+struct ag71xx_switch_platform_data {
+ u8 phy4_mii_en:1;
+};
+
+struct ag71xx_platform_data {
+ phy_interface_t phy_if_mode;
+ u32 phy_mask;
+ int speed;
+ int duplex;
+ u32 reset_bit;
+ u8 mac_addr[ETH_ALEN];
+ struct device *mii_bus_dev;
+
+ u8 has_gbit:1;
+ u8 is_ar91xx:1;
+ u8 is_ar7240:1;
+ u8 is_ar724x:1;
+ u8 has_ar8216:1;
+
+ struct ag71xx_switch_platform_data *switch_data;
+
+ void (*ddr_flush)(void);
+ void (*set_speed)(int speed);
+
+ u32 fifo_cfg1;
+ u32 fifo_cfg2;
+ u32 fifo_cfg3;
+};
+
+struct ag71xx_mdio_platform_data {
+ u32 phy_mask;
+ int is_ar7240;
+};
+
+#endif /* __ASM_MACH_ATH79_PLATFORM_H */
diff --git a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ath79/mach-rb750.h b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ath79/mach-rb750.h
new file mode 100644
index 000000000..3e6fc50c5
--- /dev/null
+++ b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ath79/mach-rb750.h
@@ -0,0 +1,68 @@
+/*
+ * MikroTik RouterBOARD 750 definitions
+ *
+ * Copyright (C) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+#ifndef _MACH_RB750_H
+#define _MACH_RB750_H
+
+#include <linux/bitops.h>
+
+#define RB750_GPIO_LVC573_LE 0 /* Latch enable on LVC573 */
+#define RB750_GPIO_NAND_IO0 1 /* NAND I/O 0 */
+#define RB750_GPIO_NAND_IO1 2 /* NAND I/O 1 */
+#define RB750_GPIO_NAND_IO2 3 /* NAND I/O 2 */
+#define RB750_GPIO_NAND_IO3 4 /* NAND I/O 3 */
+#define RB750_GPIO_NAND_IO4 5 /* NAND I/O 4 */
+#define RB750_GPIO_NAND_IO5 6 /* NAND I/O 5 */
+#define RB750_GPIO_NAND_IO6 7 /* NAND I/O 6 */
+#define RB750_GPIO_NAND_IO7 8 /* NAND I/O 7 */
+#define RB750_GPIO_NAND_NCE 11 /* NAND Chip Enable (active low) */
+#define RB750_GPIO_NAND_RDY 12 /* NAND Ready */
+#define RB750_GPIO_NAND_CLE 14 /* NAND Command Latch Enable */
+#define RB750_GPIO_NAND_ALE 15 /* NAND Address Latch Enable */
+#define RB750_GPIO_NAND_NRE 16 /* NAND Read Enable (active low) */
+#define RB750_GPIO_NAND_NWE 17 /* NAND Write Enable (active low) */
+
+#define RB750_GPIO_BTN_RESET 1
+#define RB750_GPIO_SPI_CS0 2
+#define RB750_GPIO_LED_ACT 12
+#define RB750_GPIO_LED_PORT1 13
+#define RB750_GPIO_LED_PORT2 14
+#define RB750_GPIO_LED_PORT3 15
+#define RB750_GPIO_LED_PORT4 16
+#define RB750_GPIO_LED_PORT5 17
+
+#define RB750_LED_ACT BIT(RB750_GPIO_LED_ACT)
+#define RB750_LED_PORT1 BIT(RB750_GPIO_LED_PORT1)
+#define RB750_LED_PORT2 BIT(RB750_GPIO_LED_PORT2)
+#define RB750_LED_PORT3 BIT(RB750_GPIO_LED_PORT3)
+#define RB750_LED_PORT4 BIT(RB750_GPIO_LED_PORT4)
+#define RB750_LED_PORT5 BIT(RB750_GPIO_LED_PORT5)
+
+#define RB750_LVC573_LE BIT(RB750_GPIO_LVC573_LE)
+
+#define RB750_LED_BITS (RB750_LED_PORT1 | RB750_LED_PORT2 | RB750_LED_PORT3 | \
+ RB750_LED_PORT4 | RB750_LED_PORT5 | RB750_LED_ACT)
+
+struct rb750_led_data {
+ char *name;
+ char *default_trigger;
+ u32 mask;
+ int active_low;
+};
+
+struct rb750_led_platform_data {
+ int num_leds;
+ struct rb750_led_data *leds;
+};
+
+int rb750_latch_change(u32 mask_clr, u32 mask_set);
+void rb750_nand_pins_enable(void);
+void rb750_nand_pins_disable(void);
+
+#endif /* _MACH_RB750_H */ \ No newline at end of file
diff --git a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ath79/rb4xx_cpld.h b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ath79/rb4xx_cpld.h
new file mode 100644
index 000000000..5b17e94b6
--- /dev/null
+++ b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ath79/rb4xx_cpld.h
@@ -0,0 +1,48 @@
+/*
+ * SPI driver definitions for the CPLD chip on the Mikrotik RB4xx boards
+ *
+ * Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This file was based on the patches for Linux 2.6.27.39 published by
+ * MikroTik for their RouterBoard 4xx series devices.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#define CPLD_GPIO_nLED1 0
+#define CPLD_GPIO_nLED2 1
+#define CPLD_GPIO_nLED3 2
+#define CPLD_GPIO_nLED4 3
+#define CPLD_GPIO_FAN 4
+#define CPLD_GPIO_ALE 5
+#define CPLD_GPIO_CLE 6
+#define CPLD_GPIO_nCE 7
+#define CPLD_GPIO_nLED5 8
+
+#define CPLD_NUM_GPIOS 9
+
+#define CPLD_CFG_nLED1 BIT(CPLD_GPIO_nLED1)
+#define CPLD_CFG_nLED2 BIT(CPLD_GPIO_nLED2)
+#define CPLD_CFG_nLED3 BIT(CPLD_GPIO_nLED3)
+#define CPLD_CFG_nLED4 BIT(CPLD_GPIO_nLED4)
+#define CPLD_CFG_FAN BIT(CPLD_GPIO_FAN)
+#define CPLD_CFG_ALE BIT(CPLD_GPIO_ALE)
+#define CPLD_CFG_CLE BIT(CPLD_GPIO_CLE)
+#define CPLD_CFG_nCE BIT(CPLD_GPIO_nCE)
+#define CPLD_CFG_nLED5 BIT(CPLD_GPIO_nLED5)
+
+struct rb4xx_cpld_platform_data {
+ unsigned gpio_base;
+};
+
+extern int rb4xx_cpld_change_cfg(unsigned mask, unsigned value);
+extern int rb4xx_cpld_read(unsigned char *rx_buf,
+ const unsigned char *verify_buf,
+ unsigned cnt);
+extern int rb4xx_cpld_read_from(unsigned addr,
+ unsigned char *rx_buf,
+ const unsigned char *verify_buf,
+ unsigned cnt);
+extern int rb4xx_cpld_write(const unsigned char *buf, unsigned count);