summaryrefslogtreecommitdiffstats
path: root/target/linux/adm5120-2.6/files/include/asm-mips
diff options
context:
space:
mode:
Diffstat (limited to 'target/linux/adm5120-2.6/files/include/asm-mips')
-rw-r--r--target/linux/adm5120-2.6/files/include/asm-mips/mach-adm5120/adm5120_info.h6
-rw-r--r--target/linux/adm5120-2.6/files/include/asm-mips/mach-adm5120/adm5120_mpmc.h87
-rw-r--r--target/linux/adm5120-2.6/files/include/asm-mips/mach-adm5120/adm5120_switch.h22
3 files changed, 111 insertions, 4 deletions
diff --git a/target/linux/adm5120-2.6/files/include/asm-mips/mach-adm5120/adm5120_info.h b/target/linux/adm5120-2.6/files/include/asm-mips/mach-adm5120/adm5120_info.h
index b4730dc0f..5c6424418 100644
--- a/target/linux/adm5120-2.6/files/include/asm-mips/mach-adm5120/adm5120_info.h
+++ b/target/linux/adm5120-2.6/files/include/asm-mips/mach-adm5120/adm5120_info.h
@@ -22,6 +22,7 @@ struct adm5120_board {
unsigned long mach_type;
unsigned int iface_num; /* Number of Ethernet interfaces */
unsigned int has_usb; /* USB controller presence flag */
+ u32 mem_size; /* onboard memory size */
u32 flash0_size; /* Flash 0 size */
};
@@ -79,4 +80,9 @@ static inline char *adm5120_board_name(void)
return adm5120_board.name;
}
+static inline u32 adm5120_board_memsize(void)
+{
+ return adm5120_board.mem_size;
+}
+
#endif /* _ADM5120_INFO_H */
diff --git a/target/linux/adm5120-2.6/files/include/asm-mips/mach-adm5120/adm5120_mpmc.h b/target/linux/adm5120-2.6/files/include/asm-mips/mach-adm5120/adm5120_mpmc.h
new file mode 100644
index 000000000..df536520c
--- /dev/null
+++ b/target/linux/adm5120-2.6/files/include/asm-mips/mach-adm5120/adm5120_mpmc.h
@@ -0,0 +1,87 @@
+/*
+ * $Id$
+ *
+ * ADM5120 MPMC (Multiport Memory Controller) register definitions
+ *
+ * Copyright (C) 2007 OpenWrt.org
+ * Copyright (C) 2007 Gabor Juhos <juhosg@freemail.hu>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the
+ * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ * Boston, MA 02110-1301, USA.
+ *
+ */
+
+#ifndef _ADM5120_MPMC_H_
+#define _ADM5120_MPMC_H_
+
+#define MPMC_REG_CTRL 0x0000
+#define MPMC_REG_STATUS 0x0004
+#define MPMC_REG_CONF 0x0008
+#define MPMC_REG_DC 0x0020
+#define MPMC_REG_DR 0x0024
+#define MPMC_REG_DRP 0x0030
+
+#define MPMC_REG_DC0 0x0100
+#define MPMC_REG_DRC0 0x0104
+#define MPMC_REG_DC1 0x0120
+#define MPMC_REG_DRC1 0x0124
+#define MPMC_REG_DC2 0x0140
+#define MPMC_REG_DRC2 0x0144
+#define MPMC_REG_DC3 0x0160
+#define MPMC_REG_DRC3 0x0164
+#define MPMC_REG_SC0 0x0200 /* for F_CS1_N */
+#define MPMC_REG_SC1 0x0220 /* for F_CS0_N */
+#define MPMC_REG_SC2 0x0240
+#define MPMC_REG_SC3 0x0260
+
+#define MPMC_CTRL_AM ( 1 << 1 )
+
+/* Dynamic Control register bits */
+#define MPMC_DC_CE ( 1 << 0 )
+#define MPMC_DC_DMC ( 1 << 1 )
+#define MPMC_DC_SRR ( 1 << 2 )
+#define MPMC_DC_SI_SHIFT 7
+#define MPMC_DC_SI_MASK ( 3 << 7 )
+#define MPMC_DC_SI_NORMAL ( 0 << 7 )
+#define MPMC_DC_SI_MODE ( 1 << 7 )
+#define MPMC_DC_SI_PALL ( 2 << 7 )
+#define MPMC_DC_SI_NOP ( 3 << 7 )
+
+#define SRAM_REG_CONF 0x00
+#define SRAM_REG_WWE 0x04
+#define SRAM_REG_WOE 0x08
+#define SRAM_REG_WRD 0x0C
+#define SRAM_REG_WPG 0x10
+#define SRAM_REG_WWR 0x14
+#define SRAM_REG_WTR 0x18
+
+/* Dynamic Configuration register bits */
+#define DC_BE (1 << 19) /* buffer enable */
+#define DC_RW_SHIFT 28 /* shift for number of rows */
+#define DC_RW_MASK 0x03
+#define DC_NB_SHIFT 26 /* shift for number of banks */
+#define DC_NB_MASK 0x01
+#define DC_CW_SHIFT 22 /* shift for number of columns */
+#define DC_CW_MASK 0x07
+#define DC_DW_SHIFT 7 /* shift for device width */
+#define DC_DW_MASK 0x03
+
+/* Static Configuration register bits */
+#define SC_MW_MASK 0x03 /* memory width mask */
+#define SC_MW_8 0x00 /* 8 bit memory width */
+#define SC_MW_16 0x01 /* 16 bit memory width */
+#define SC_MW_32 0x02 /* 32 bit memory width */
+
+#endif /* _ADM5120_MPMC_H_ */
diff --git a/target/linux/adm5120-2.6/files/include/asm-mips/mach-adm5120/adm5120_switch.h b/target/linux/adm5120-2.6/files/include/asm-mips/mach-adm5120/adm5120_switch.h
index f7664587d..c796475c4 100644
--- a/target/linux/adm5120-2.6/files/include/asm-mips/mach-adm5120/adm5120_switch.h
+++ b/target/linux/adm5120-2.6/files/include/asm-mips/mach-adm5120/adm5120_switch.h
@@ -93,10 +93,15 @@
#define MEMCTRL_SDRS_64M 0x04
#define MEMCTRL_SDRS_128M 0x05
#define MEMCTRL_SDR1_ENABLE ONEBIT(5) /* enable SDRAM bank 1 */
-#define MEMCTRL_SR0S_MASK BITMASK(3) /* SRAM0 size */
-#define MEMCTRL_SR0S_SHIFT 8
-#define MEMCTRL_SR1S_MASK BITMAKS(3) /* SRAM1 size */
-#define MEMCTRL_SR1S_SHIFT 16
+
+#define MEMCTRL_SRS0_SHIFT 8 /* shift for SRAM0 size */
+#define MEMCTRL_SRS1_SHIFT 16 /* shift for SRAM1 size */
+#define MEMCTRL_SRS_MASK BITMASK(3) /* SRAM size mask */
+#define MEMCTRL_SRS_DISABLED 0x00 /* Disabled */
+#define MEMCTRL_SRS_512K 0x01 /* 512KB*/
+#define MEMCTRL_SRS_1M 0x02 /* 1MB */
+#define MEMCTRL_SRS_2M 0x03 /* 2MB */
+#define MEMCTRL_SRS_4M 0x04 /* 4MB */
/* GPIO_CONF0 register bits */
#define GPIO_CONF0_MASK BITMASK(8)
@@ -109,6 +114,15 @@
#define GPIO_CONF0_OE_MASK (0xFF << GPIO_CONF0_OE_SHIFT)
#define GPIO_CONF0_OV_MASK (0xFF << GPIO_CONF0_OV_SHIFT)
+/* TIMER_INT register bits */
+#define TIMER_INT_TOS ONEBIT(1) /* time-out status */
+#define TIMER_INT_TOM ONEBIT(16) /* mask time-out interrupt */
+
+/* TIMER register bits */
+#define TIMER_PERIOD_MASK BITMASK(16) /* mask for timer period */
+#define TIMER_PERIOD_DEFAULT 0xFFFF /* default timer period */
+#define TIMER_TE ONEBIT(16) /* timer enable bit */
+
/* PORTx_LED register bits */
#define LED_MODE_MASK BITMASK(4)
#define LED_MODE_INPUT 0