diff options
Diffstat (limited to 'package/uboot-ifxmips/files/board/ifx/danube')
19 files changed, 0 insertions, 2527 deletions
diff --git a/package/uboot-ifxmips/files/board/ifx/danube/Makefile b/package/uboot-ifxmips/files/board/ifx/danube/Makefile deleted file mode 100644 index 565511773..000000000 --- a/package/uboot-ifxmips/files/board/ifx/danube/Makefile +++ /dev/null @@ -1,44 +0,0 @@ -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).a - -COBJS = $(BOARD).o flash.o -SOBJS = lowlevel_init.o pmuenable.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) - -######################################################################### - -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/package/uboot-ifxmips/files/board/ifx/danube/README b/package/uboot-ifxmips/files/board/ifx/danube/README deleted file mode 100644 index d1c5c1e88..000000000 --- a/package/uboot-ifxmips/files/board/ifx/danube/README +++ /dev/null @@ -1,55 +0,0 @@ -/* -** Copyright (C) 2005 Wu Qi Ming <Qi-Ming.Wu@infineon.com> -** -** This program is free software; you can redistribute it and/or modify -** it under the terms of the GNU General Public License as published by -** the Free Software Foundation; either version 2 of the License, or -** (at your option) any later version. -** -** This program is distributed in the hope that it will be useful, -** but WITHOUT ANY WARRANTY; without even the implied warranty of -** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -** GNU General Public License for more details. -** -** You should have received a copy of the GNU General Public License -** along with this program; if not, write to the Free Software -** Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. -*/ - -To build a u-boot for danube board, user need to do the following things: -To configure u-boot for a proper board, user need to modify two files accordingly. - -To configure u-boot for evaluation board, in danube-uboot/include/configs/danube.h, set -#define USE_EVALUATION_BOARD -#undef USE_REFERENCE_BOARD -and vice-versa. - -To let u-boot boot from ebu(flash,e.g), in danube-uboot/include/configus/danube.h, set -#define DANUBE_BOOT_FROM_EBU -Otherwise u-boot will be compiled for booting from RAM. - -To use DDR RAM running at 111M, in danube-uboot/include/configus/danube. -h, set -#define DANUBE_DDR_RAM_111M -#undef DANUBE_DDR_RAM_166M -and vice-versa. - -To define RAM size of RAM, in danube-uboot/include/configus/danube. -h, set -#define RAM_SIZE 0x2000000 /*32M ram*/ -This is an example for a 32M RAM. - - -Besides above settings, user need to change danube-uboot/board/danube/config.mk to set the loading address of u-boot. -If U-Boot is to boot from EBU(flash), user needs to set -TEXT_BASE=0xB0000000 -If u-boot is to boot from RAM, user needs to set -TEXT_BASE=0xa0400000 - -Use the script gct to build a uart downloadable u-boot image: -./gct danube_ref_ddr166.conf u-boot.srec u-boot.asc - - - - - diff --git a/package/uboot-ifxmips/files/board/ifx/danube/config.mk b/package/uboot-ifxmips/files/board/ifx/danube/config.mk deleted file mode 100644 index 88680e14f..000000000 --- a/package/uboot-ifxmips/files/board/ifx/danube/config.mk +++ /dev/null @@ -1,33 +0,0 @@ -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# Danube board with MIPS 24Kec CPU core -#boot from ebu -#TEXT_BASE = 0xB0000000 -BOOTSTRAP_TEXT_BASE = 0xB0000000 - -#boot from ram -#TEXT_BASE = 0xa0400000 -#TEXT_BASE = 0x807c0000 - diff --git a/package/uboot-ifxmips/files/board/ifx/danube/danube.c b/package/uboot-ifxmips/files/board/ifx/danube/danube.c deleted file mode 100644 index b6174ba6d..000000000 --- a/package/uboot-ifxmips/files/board/ifx/danube/danube.c +++ /dev/null @@ -1,208 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <command.h> -#include <asm/addrspace.h> -#include <asm/danube.h> - -#ifdef DANUBE_USE_DDR_RAM -long int initdram(int board_type) -{ - return (1024*1024*DANUBE_DDR_RAM_SIZE); -} -#else -extern uint danube_get_cpuclk(void); - -static ulong max_sdram_size(void) /* per Chip Select */ -{ - /* The only supported SDRAM data width is 16bit. - */ -#define CFG_DW 4 - - /* The only supported number of SDRAM banks is 4. - */ -#define CFG_NB 4 - - ulong cfgpb0 = *DANUBE_SDRAM_MC_CFGPB0; - int cols = cfgpb0 & 0xF; - int rows = (cfgpb0 & 0xF0) >> 4; - ulong size = (1 << (rows + cols)) * CFG_DW * CFG_NB; - - return size; -} - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. - */ - -static long int dram_size(long int *base, long int maxsize) -{ - volatile long int *addr; - ulong cnt, val; - ulong save[32]; /* to make test non-destructive */ - unsigned char i = 0; - - for (cnt = (maxsize / sizeof (long)) >> 1; cnt > 0; cnt >>= 1) { - addr = base + cnt; /* pointer arith! */ - - save[i++] = *addr; - *addr = ~cnt; - } - - /* write 0 to base address */ - addr = base; - save[i] = *addr; - *addr = 0; - - /* check at base address */ - if ((val = *addr) != 0) { - *addr = save[i]; - return (0); - } - - for (cnt = 1; cnt < maxsize / sizeof (long); cnt <<= 1) { - addr = base + cnt; /* pointer arith! */ - - val = *addr; - *addr = save[--i]; - - if (val != (~cnt)) { - return (cnt * sizeof (long)); - } - } - return (maxsize); -} - -long int initdram(int board_type) -{ - int rows, cols, best_val = *DANUBE_SDRAM_MC_CFGPB0; - ulong size, max_size = 0; - ulong our_address; - - /* load t9 into our_address */ - asm volatile ("move %0, $25" : "=r" (our_address) :); - - /* Can't probe for RAM size unless we are running from Flash. - * find out whether running from DRAM or Flash. - */ - if (PHYSADDR(our_address) < PHYSADDR(PHYS_FLASH_1)) - { - return max_sdram_size(); - } - - for (cols = 0x8; cols <= 0xC; cols++) - { - for (rows = 0xB; rows <= 0xD; rows++) - { - *DANUBE_SDRAM_MC_CFGPB0 = (0x14 << 8) | - (rows << 4) | cols; - size = dram_size((ulong *)CFG_SDRAM_BASE, - max_sdram_size()); - - if (size > max_size) - { - best_val = *DANUBE_SDRAM_MC_CFGPB0; - max_size = size; - } - } - } - - *DANUBE_SDRAM_MC_CFGPB0 = best_val; - return max_size; -} -#endif - -int checkboard (void) -{ - /* No such register in Amazon */ -#if 0 - unsigned long chipid = *AMAZON_MCD_CHIPID; - int part_num; - - puts ("Board: AMAZON "); - part_num = AMAZON_MCD_CHIPID_PART_NUMBER_GET(chipid); - switch (part_num) { - case AMAZON_CHIPID_STANDARD: - printf ("Standard Version, "); - break; - case AMAZON_CHIPID_YANGTSE: - printf ("Yangtse Version, "); - break; - default: - printf ("Unknown Part Number 0x%x ", part_num); - break; - } - - printf ("Chip V1.%ld, ", AMAZON_MCD_CHIPID_VERSION_GET(chipid)); - - - printf("CPU Speed %d MHz\n", danube_get_cpuclk()/1000000); - -#endif - return 0; -} - - -/* - * Disk On Chip (NAND) Millenium initialization. - * The NAND lives in the CS2* space - */ -#if (CONFIG_COMMANDS & CFG_CMD_NAND) -extern void -nand_probe(ulong physadr); - -#define AT91_SMARTMEDIA_BASE 0x40000000 /* physical address to access memory on NCS3 */ -void -nand_init(void) -{ - int devtype; - /* Configure EBU */ -//TODO: should we keep this? - //Set GPIO23 to be Flash CS1; - *DANUBE_GPIO_P1_ALTSEL0 = *DANUBE_GPIO_P1_ALTSEL0 | (1<<7); - *DANUBE_GPIO_P1_ALTSEL1 = *DANUBE_GPIO_P1_ALTSEL1 & ~(1<<7); - *DANUBE_GPIO_P1_DIR = *DANUBE_GPIO_P1_DIR | (1<<7) ; - *DANUBE_GPIO_P1_OD = *DANUBE_GPIO_P1_OD | (1<<7) ; - - *EBU_ADDR_SEL_1 = (NAND_BASE_ADDRESS&0x1fffff00)|0x31; - /* byte swap;minimum delay*/ - *EBU_CON_1 = 0x40C155; - *EBU_NAND_CON = 0x000005F3; - - /* Set bus signals to inactive */ - NAND_READY_CLEAR; - - NAND_CE_CLEAR; - nand_probe(NAND_BASE_ADDRESS); - - - - //nand_probe(AT91_SMARTMEDIA_BASE); -} -#endif - - - diff --git a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings.h b/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings.h deleted file mode 100644 index 3a4b1350e..000000000 --- a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings.h +++ /dev/null @@ -1,50 +0,0 @@ -/* Settings for Denali DDR SDRAM controller */ -/* Optimise for Danube Eval Board DDR 167 Mhz - by Ng Aik Ann 29th April */ -#define MC_DC0_VALUE 0x1B1B -#define MC_DC1_VALUE 0x0 -#define MC_DC2_VALUE 0x0 -#define MC_DC3_VALUE 0x0 -#define MC_DC4_VALUE 0x0 -#define MC_DC5_VALUE 0x200 -#define MC_DC6_VALUE 0x605 -#define MC_DC7_VALUE 0x303 -#define MC_DC8_VALUE 0x102 -#define MC_DC9_VALUE 0x70a -#define MC_DC10_VALUE 0x203 -#define MC_DC11_VALUE 0xc02 -#define MC_DC12_VALUE 0x1C8 -#define MC_DC13_VALUE 0x1 -#define MC_DC14_VALUE 0x0 -#define MC_DC15_VALUE 0xf3c -#define MC_DC16_VALUE 0xC800 -#define MC_DC17_VALUE 0xd -#define MC_DC18_VALUE 0x300 -#define MC_DC19_VALUE 0x200 -#define MC_DC20_VALUE 0xA03 -#define MC_DC21_VALUE 0x1d00 -#define MC_DC22_VALUE 0x1d1d -#define MC_DC23_VALUE 0x0 -#define MC_DC24_VALUE 0x5e /* was 0x7f */ -#define MC_DC25_VALUE 0x0 -#define MC_DC26_VALUE 0x0 -#define MC_DC27_VALUE 0x0 -#define MC_DC28_VALUE 0x510 -#define MC_DC29_VALUE 0x2d89 -#define MC_DC30_VALUE 0x8300 -#define MC_DC31_VALUE 0x0 -#define MC_DC32_VALUE 0x0 -#define MC_DC33_VALUE 0x0 -#define MC_DC34_VALUE 0x0 -#define MC_DC35_VALUE 0x0 -#define MC_DC36_VALUE 0x0 -#define MC_DC37_VALUE 0x0 -#define MC_DC38_VALUE 0x0 -#define MC_DC39_VALUE 0x0 -#define MC_DC40_VALUE 0x0 -#define MC_DC41_VALUE 0x0 -#define MC_DC42_VALUE 0x0 -#define MC_DC43_VALUE 0x0 -#define MC_DC44_VALUE 0x0 -#define MC_DC45_VALUE 0x500 -//#define MC_DC45_VALUE 0x400 -#define MC_DC46_VALUE 0x0 diff --git a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_111.h b/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_111.h deleted file mode 100644 index b655ca289..000000000 --- a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_111.h +++ /dev/null @@ -1,50 +0,0 @@ -/* Settings for Denali DDR SDRAM controller */ -/* Optimise for Danube Eval Board DDR 167 Mhz - by Ng Aik Ann 29th April */ -#define MC_DC0_VALUE 0x1B1B -#define MC_DC1_VALUE 0x0 -#define MC_DC2_VALUE 0x0 -#define MC_DC3_VALUE 0x0 -#define MC_DC4_VALUE 0x0 -#define MC_DC5_VALUE 0x200 -#define MC_DC6_VALUE 0x605 -#define MC_DC7_VALUE 0x303 -#define MC_DC8_VALUE 0x102 -#define MC_DC9_VALUE 0x70a -#define MC_DC10_VALUE 0x203 -#define MC_DC11_VALUE 0xc02 -#define MC_DC12_VALUE 0x1C8 -#define MC_DC13_VALUE 0x1 -#define MC_DC14_VALUE 0x0 -#define MC_DC15_VALUE 0xf3c /* WDQS tuning for clk_wr*/ -#define MC_DC16_VALUE 0xC800 -#define MC_DC17_VALUE 0xd -#define MC_DC18_VALUE 0x300 -#define MC_DC19_VALUE 0x200 -#define MC_DC20_VALUE 0xA03 /* A04 for reference board, A03 for Eval board */ -#define MC_DC21_VALUE 0x1800 -#define MC_DC22_VALUE 0x1818 -#define MC_DC23_VALUE 0x0 -#define MC_DC24_VALUE 0x5e /* WDQS Tuning for DQS */ -#define MC_DC25_VALUE 0x0 -#define MC_DC26_VALUE 0x0 -#define MC_DC27_VALUE 0x0 -#define MC_DC28_VALUE 0x510 -#define MC_DC29_VALUE 0x2d89 -#define MC_DC30_VALUE 0x8300 -#define MC_DC31_VALUE 0x0 -#define MC_DC32_VALUE 0x0 -#define MC_DC33_VALUE 0x0 -#define MC_DC34_VALUE 0x0 -#define MC_DC35_VALUE 0x0 -#define MC_DC36_VALUE 0x0 -#define MC_DC37_VALUE 0x0 -#define MC_DC38_VALUE 0x0 -#define MC_DC39_VALUE 0x0 -#define MC_DC40_VALUE 0x0 -#define MC_DC41_VALUE 0x0 -#define MC_DC42_VALUE 0x0 -#define MC_DC43_VALUE 0x0 -#define MC_DC44_VALUE 0x0 -#define MC_DC45_VALUE 0x500 -//#define MC_DC45_VALUE 0x400 -#define MC_DC46_VALUE 0x0 diff --git a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_166.h b/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_166.h deleted file mode 100644 index b655ca289..000000000 --- a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_166.h +++ /dev/null @@ -1,50 +0,0 @@ -/* Settings for Denali DDR SDRAM controller */ -/* Optimise for Danube Eval Board DDR 167 Mhz - by Ng Aik Ann 29th April */ -#define MC_DC0_VALUE 0x1B1B -#define MC_DC1_VALUE 0x0 -#define MC_DC2_VALUE 0x0 -#define MC_DC3_VALUE 0x0 -#define MC_DC4_VALUE 0x0 -#define MC_DC5_VALUE 0x200 -#define MC_DC6_VALUE 0x605 -#define MC_DC7_VALUE 0x303 -#define MC_DC8_VALUE 0x102 -#define MC_DC9_VALUE 0x70a -#define MC_DC10_VALUE 0x203 -#define MC_DC11_VALUE 0xc02 -#define MC_DC12_VALUE 0x1C8 -#define MC_DC13_VALUE 0x1 -#define MC_DC14_VALUE 0x0 -#define MC_DC15_VALUE 0xf3c /* WDQS tuning for clk_wr*/ -#define MC_DC16_VALUE 0xC800 -#define MC_DC17_VALUE 0xd -#define MC_DC18_VALUE 0x300 -#define MC_DC19_VALUE 0x200 -#define MC_DC20_VALUE 0xA03 /* A04 for reference board, A03 for Eval board */ -#define MC_DC21_VALUE 0x1800 -#define MC_DC22_VALUE 0x1818 -#define MC_DC23_VALUE 0x0 -#define MC_DC24_VALUE 0x5e /* WDQS Tuning for DQS */ -#define MC_DC25_VALUE 0x0 -#define MC_DC26_VALUE 0x0 -#define MC_DC27_VALUE 0x0 -#define MC_DC28_VALUE 0x510 -#define MC_DC29_VALUE 0x2d89 -#define MC_DC30_VALUE 0x8300 -#define MC_DC31_VALUE 0x0 -#define MC_DC32_VALUE 0x0 -#define MC_DC33_VALUE 0x0 -#define MC_DC34_VALUE 0x0 -#define MC_DC35_VALUE 0x0 -#define MC_DC36_VALUE 0x0 -#define MC_DC37_VALUE 0x0 -#define MC_DC38_VALUE 0x0 -#define MC_DC39_VALUE 0x0 -#define MC_DC40_VALUE 0x0 -#define MC_DC41_VALUE 0x0 -#define MC_DC42_VALUE 0x0 -#define MC_DC43_VALUE 0x0 -#define MC_DC44_VALUE 0x0 -#define MC_DC45_VALUE 0x500 -//#define MC_DC45_VALUE 0x400 -#define MC_DC46_VALUE 0x0 diff --git a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_PROMOSDDR400.h b/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_PROMOSDDR400.h deleted file mode 100644 index 54bb6c9e3..000000000 --- a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_PROMOSDDR400.h +++ /dev/null @@ -1,50 +0,0 @@ -/* Settings for Denali DDR SDRAM controller */ -/* Optimise for Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 29th April */ -#define MC_DC0_VALUE 0x1B1B -#define MC_DC1_VALUE 0x0 -#define MC_DC2_VALUE 0x0 -#define MC_DC3_VALUE 0x0 -#define MC_DC4_VALUE 0x0 -#define MC_DC5_VALUE 0x200 -#define MC_DC6_VALUE 0x605 -#define MC_DC7_VALUE 0x303 -#define MC_DC8_VALUE 0x102 -#define MC_DC9_VALUE 0x70a -#define MC_DC10_VALUE 0x203 -#define MC_DC11_VALUE 0xa02 -#define MC_DC12_VALUE 0x1C8 -#define MC_DC13_VALUE 0x0 -#define MC_DC14_VALUE 0x0 -#define MC_DC15_VALUE 0xf3c /* WDQS tuning for clk_wr*/ -#define MC_DC16_VALUE 0xC800 -#define MC_DC17_VALUE 0xd -#define MC_DC18_VALUE 0x300 -#define MC_DC19_VALUE 0x200 -#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */ -#define MC_DC21_VALUE 0x1200 -#define MC_DC22_VALUE 0x1212 -#define MC_DC23_VALUE 0x0 -#define MC_DC24_VALUE 0x62 /* WDQS Tuning for DQS */ -#define MC_DC25_VALUE 0x0 -#define MC_DC26_VALUE 0x0 -#define MC_DC27_VALUE 0x0 -#define MC_DC28_VALUE 0x510 -#define MC_DC29_VALUE 0x4e20 -#define MC_DC30_VALUE 0x8300 -#define MC_DC31_VALUE 0x0 -#define MC_DC32_VALUE 0x0 -#define MC_DC33_VALUE 0x0 -#define MC_DC34_VALUE 0x0 -#define MC_DC35_VALUE 0x0 -#define MC_DC36_VALUE 0x0 -#define MC_DC37_VALUE 0x0 -#define MC_DC38_VALUE 0x0 -#define MC_DC39_VALUE 0x0 -#define MC_DC40_VALUE 0x0 -#define MC_DC41_VALUE 0x0 -#define MC_DC42_VALUE 0x0 -#define MC_DC43_VALUE 0x0 -#define MC_DC44_VALUE 0x0 -#define MC_DC45_VALUE 0x500 -//#define MC_DC45_VALUE 0x400 -#define MC_DC46_VALUE 0x0 diff --git a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_Samsung_166.h b/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_Samsung_166.h deleted file mode 100644 index 7975c3ec0..000000000 --- a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_Samsung_166.h +++ /dev/null @@ -1,51 +0,0 @@ -/* Settings for Denali DDR SDRAM controller */ -/* Optimise for Samsung DDR K4H561638H Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 27th Nov 2006 */ - -#define MC_DC0_VALUE 0x1B1B -#define MC_DC1_VALUE 0x0 -#define MC_DC2_VALUE 0x0 -#define MC_DC3_VALUE 0x0 -#define MC_DC4_VALUE 0x0 -#define MC_DC5_VALUE 0x200 -#define MC_DC6_VALUE 0x605 -#define MC_DC7_VALUE 0x303 -#define MC_DC8_VALUE 0x102 -#define MC_DC9_VALUE 0x70a -#define MC_DC10_VALUE 0x203 -#define MC_DC11_VALUE 0xc02 -#define MC_DC12_VALUE 0x1C8 -#define MC_DC13_VALUE 0x1 -#define MC_DC14_VALUE 0x0 -#define MC_DC15_VALUE 0x120 /* WDQS tuning for clk_wr*/ -#define MC_DC16_VALUE 0xC800 -#define MC_DC17_VALUE 0xd -#define MC_DC18_VALUE 0x301 -#define MC_DC19_VALUE 0x200 -#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */ -#define MC_DC21_VALUE 0x1400 -#define MC_DC22_VALUE 0x1414 -#define MC_DC23_VALUE 0x0 -#define MC_DC24_VALUE 0x4e /* WDQS Tuning for DQS */ -#define MC_DC25_VALUE 0x0 -#define MC_DC26_VALUE 0x0 -#define MC_DC27_VALUE 0x0 -#define MC_DC28_VALUE 0x510 -#define MC_DC29_VALUE 0x2d93 -#define MC_DC30_VALUE 0x8235 -#define MC_DC31_VALUE 0x0 -#define MC_DC32_VALUE 0x0 -#define MC_DC33_VALUE 0x0 -#define MC_DC34_VALUE 0x0 -#define MC_DC35_VALUE 0x0 -#define MC_DC36_VALUE 0x0 -#define MC_DC37_VALUE 0x0 -#define MC_DC38_VALUE 0x0 -#define MC_DC39_VALUE 0x0 -#define MC_DC40_VALUE 0x0 -#define MC_DC41_VALUE 0x0 -#define MC_DC42_VALUE 0x0 -#define MC_DC43_VALUE 0x0 -#define MC_DC44_VALUE 0x0 -#define MC_DC45_VALUE 0x500 -//#define MC_DC45_VALUE 0x400 -#define MC_DC46_VALUE 0x0 diff --git a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_e111.h b/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_e111.h deleted file mode 100644 index b655ca289..000000000 --- a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_e111.h +++ /dev/null @@ -1,50 +0,0 @@ -/* Settings for Denali DDR SDRAM controller */ -/* Optimise for Danube Eval Board DDR 167 Mhz - by Ng Aik Ann 29th April */ -#define MC_DC0_VALUE 0x1B1B -#define MC_DC1_VALUE 0x0 -#define MC_DC2_VALUE 0x0 -#define MC_DC3_VALUE 0x0 -#define MC_DC4_VALUE 0x0 -#define MC_DC5_VALUE 0x200 -#define MC_DC6_VALUE 0x605 -#define MC_DC7_VALUE 0x303 -#define MC_DC8_VALUE 0x102 -#define MC_DC9_VALUE 0x70a -#define MC_DC10_VALUE 0x203 -#define MC_DC11_VALUE 0xc02 -#define MC_DC12_VALUE 0x1C8 -#define MC_DC13_VALUE 0x1 -#define MC_DC14_VALUE 0x0 -#define MC_DC15_VALUE 0xf3c /* WDQS tuning for clk_wr*/ -#define MC_DC16_VALUE 0xC800 -#define MC_DC17_VALUE 0xd -#define MC_DC18_VALUE 0x300 -#define MC_DC19_VALUE 0x200 -#define MC_DC20_VALUE 0xA03 /* A04 for reference board, A03 for Eval board */ -#define MC_DC21_VALUE 0x1800 -#define MC_DC22_VALUE 0x1818 -#define MC_DC23_VALUE 0x0 -#define MC_DC24_VALUE 0x5e /* WDQS Tuning for DQS */ -#define MC_DC25_VALUE 0x0 -#define MC_DC26_VALUE 0x0 -#define MC_DC27_VALUE 0x0 -#define MC_DC28_VALUE 0x510 -#define MC_DC29_VALUE 0x2d89 -#define MC_DC30_VALUE 0x8300 -#define MC_DC31_VALUE 0x0 -#define MC_DC32_VALUE 0x0 -#define MC_DC33_VALUE 0x0 -#define MC_DC34_VALUE 0x0 -#define MC_DC35_VALUE 0x0 -#define MC_DC36_VALUE 0x0 -#define MC_DC37_VALUE 0x0 -#define MC_DC38_VALUE 0x0 -#define MC_DC39_VALUE 0x0 -#define MC_DC40_VALUE 0x0 -#define MC_DC41_VALUE 0x0 -#define MC_DC42_VALUE 0x0 -#define MC_DC43_VALUE 0x0 -#define MC_DC44_VALUE 0x0 -#define MC_DC45_VALUE 0x500 -//#define MC_DC45_VALUE 0x400 -#define MC_DC46_VALUE 0x0 diff --git a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_e166.h b/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_e166.h deleted file mode 100644 index b655ca289..000000000 --- a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_e166.h +++ /dev/null @@ -1,50 +0,0 @@ -/* Settings for Denali DDR SDRAM controller */ -/* Optimise for Danube Eval Board DDR 167 Mhz - by Ng Aik Ann 29th April */ -#define MC_DC0_VALUE 0x1B1B -#define MC_DC1_VALUE 0x0 -#define MC_DC2_VALUE 0x0 -#define MC_DC3_VALUE 0x0 -#define MC_DC4_VALUE 0x0 -#define MC_DC5_VALUE 0x200 -#define MC_DC6_VALUE 0x605 -#define MC_DC7_VALUE 0x303 -#define MC_DC8_VALUE 0x102 -#define MC_DC9_VALUE 0x70a -#define MC_DC10_VALUE 0x203 -#define MC_DC11_VALUE 0xc02 -#define MC_DC12_VALUE 0x1C8 -#define MC_DC13_VALUE 0x1 -#define MC_DC14_VALUE 0x0 -#define MC_DC15_VALUE 0xf3c /* WDQS tuning for clk_wr*/ -#define MC_DC16_VALUE 0xC800 -#define MC_DC17_VALUE 0xd -#define MC_DC18_VALUE 0x300 -#define MC_DC19_VALUE 0x200 -#define MC_DC20_VALUE 0xA03 /* A04 for reference board, A03 for Eval board */ -#define MC_DC21_VALUE 0x1800 -#define MC_DC22_VALUE 0x1818 -#define MC_DC23_VALUE 0x0 -#define MC_DC24_VALUE 0x5e /* WDQS Tuning for DQS */ -#define MC_DC25_VALUE 0x0 -#define MC_DC26_VALUE 0x0 -#define MC_DC27_VALUE 0x0 -#define MC_DC28_VALUE 0x510 -#define MC_DC29_VALUE 0x2d89 -#define MC_DC30_VALUE 0x8300 -#define MC_DC31_VALUE 0x0 -#define MC_DC32_VALUE 0x0 -#define MC_DC33_VALUE 0x0 -#define MC_DC34_VALUE 0x0 -#define MC_DC35_VALUE 0x0 -#define MC_DC36_VALUE 0x0 -#define MC_DC37_VALUE 0x0 -#define MC_DC38_VALUE 0x0 -#define MC_DC39_VALUE 0x0 -#define MC_DC40_VALUE 0x0 -#define MC_DC41_VALUE 0x0 -#define MC_DC42_VALUE 0x0 -#define MC_DC43_VALUE 0x0 -#define MC_DC44_VALUE 0x0 -#define MC_DC45_VALUE 0x500 -//#define MC_DC45_VALUE 0x400 -#define MC_DC46_VALUE 0x0 diff --git a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_psc_166.h b/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_psc_166.h deleted file mode 100644 index 445b7dac1..000000000 --- a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_psc_166.h +++ /dev/null @@ -1,51 +0,0 @@ -/* Settings for Denali DDR SDRAM controller */ -/* Optimise for PSC DDR A2S56D40CTP for Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 27th Nov 2006 */ - -#define MC_DC0_VALUE 0x1B1B -#define MC_DC1_VALUE 0x0 -#define MC_DC2_VALUE 0x0 -#define MC_DC3_VALUE 0x0 -#define MC_DC4_VALUE 0x0 -#define MC_DC5_VALUE 0x200 -#define MC_DC6_VALUE 0x605 -#define MC_DC7_VALUE 0x303 -#define MC_DC8_VALUE 0x102 -#define MC_DC9_VALUE 0x70a -#define MC_DC10_VALUE 0x203 -#define MC_DC11_VALUE 0xc02 -#define MC_DC12_VALUE 0x1C8 -#define MC_DC13_VALUE 0x1 -#define MC_DC14_VALUE 0x0 -#define MC_DC15_VALUE 0x120 /* WDQS tuning for clk_wr*/ -#define MC_DC16_VALUE 0xC800 -#define MC_DC17_VALUE 0xd -#define MC_DC18_VALUE 0x301 -#define MC_DC19_VALUE 0x200 -#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */ -#define MC_DC21_VALUE 0x1700 -#define MC_DC22_VALUE 0x1717 -#define MC_DC23_VALUE 0x0 -#define MC_DC24_VALUE 0x52 /* WDQS Tuning for DQS */ -#define MC_DC25_VALUE 0x0 -#define MC_DC26_VALUE 0x0 -#define MC_DC27_VALUE 0x0 -#define MC_DC28_VALUE 0x510 -#define MC_DC29_VALUE 0x4e20 -#define MC_DC30_VALUE 0x8235 -#define MC_DC31_VALUE 0x0 -#define MC_DC32_VALUE 0x0 -#define MC_DC33_VALUE 0x0 -#define MC_DC34_VALUE 0x0 -#define MC_DC35_VALUE 0x0 -#define MC_DC36_VALUE 0x0 -#define MC_DC37_VALUE 0x0 -#define MC_DC38_VALUE 0x0 -#define MC_DC39_VALUE 0x0 -#define MC_DC40_VALUE 0x0 -#define MC_DC41_VALUE 0x0 -#define MC_DC42_VALUE 0x0 -#define MC_DC43_VALUE 0x0 -#define MC_DC44_VALUE 0x0 -#define MC_DC45_VALUE 0x500 -//#define MC_DC45_VALUE 0x400 -#define MC_DC46_VALUE 0x0 diff --git a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_r111.h b/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_r111.h deleted file mode 100644 index fd155973e..000000000 --- a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_r111.h +++ /dev/null @@ -1,50 +0,0 @@ -/* Settings for Denali DDR SDRAM controller */ -/* Optimise for Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 29th April */ -#define MC_DC0_VALUE 0x1B1B -#define MC_DC1_VALUE 0x0 -#define MC_DC2_VALUE 0x0 -#define MC_DC3_VALUE 0x0 -#define MC_DC4_VALUE 0x0 -#define MC_DC5_VALUE 0x200 -#define MC_DC6_VALUE 0x605 -#define MC_DC7_VALUE 0x303 -#define MC_DC8_VALUE 0x102 -#define MC_DC9_VALUE 0x70a -#define MC_DC10_VALUE 0x203 -#define MC_DC11_VALUE 0xc02 -#define MC_DC12_VALUE 0x1C8 -#define MC_DC13_VALUE 0x1 -#define MC_DC14_VALUE 0x0 -#define MC_DC15_VALUE 0xf3c /* WDQS tuning for clk_wr*/ -#define MC_DC16_VALUE 0xC800 -#define MC_DC17_VALUE 0xd -#define MC_DC18_VALUE 0x300 -#define MC_DC19_VALUE 0x200 -#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */ -#define MC_DC21_VALUE 0x1200 -#define MC_DC22_VALUE 0x1212 -#define MC_DC23_VALUE 0x0 -#define MC_DC24_VALUE 0x5e /* WDQS Tuning for DQS */ -#define MC_DC25_VALUE 0x0 -#define MC_DC26_VALUE 0x0 -#define MC_DC27_VALUE 0x0 -#define MC_DC28_VALUE 0x510 -#define MC_DC29_VALUE 0x2d89 -#define MC_DC30_VALUE 0x8300 -#define MC_DC31_VALUE 0x0 -#define MC_DC32_VALUE 0x0 -#define MC_DC33_VALUE 0x0 -#define MC_DC34_VALUE 0x0 -#define MC_DC35_VALUE 0x0 -#define MC_DC36_VALUE 0x0 -#define MC_DC37_VALUE 0x0 -#define MC_DC38_VALUE 0x0 -#define MC_DC39_VALUE 0x0 -#define MC_DC40_VALUE 0x0 -#define MC_DC41_VALUE 0x0 -#define MC_DC42_VALUE 0x0 -#define MC_DC43_VALUE 0x0 -#define MC_DC44_VALUE 0x0 -#define MC_DC45_VALUE 0x500 -//#define MC_DC45_VALUE 0x400 -#define MC_DC46_VALUE 0x0 diff --git a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_r166.h b/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_r166.h deleted file mode 100644 index 742d34f1d..000000000 --- a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_r166.h +++ /dev/null @@ -1,50 +0,0 @@ -/* Settings for Denali DDR SDRAM controller */ -/* Optimise for Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 29th April */ -#define MC_DC0_VALUE 0x1B1B -#define MC_DC1_VALUE 0x0 -#define MC_DC2_VALUE 0x0 -#define MC_DC3_VALUE 0x0 -#define MC_DC4_VALUE 0x0 -#define MC_DC5_VALUE 0x200 -#define MC_DC6_VALUE 0x605 -#define MC_DC7_VALUE 0x303 -#define MC_DC8_VALUE 0x102 -#define MC_DC9_VALUE 0x70a -#define MC_DC10_VALUE 0x203 -#define MC_DC11_VALUE 0xc02 -#define MC_DC12_VALUE 0x1C8 -#define MC_DC13_VALUE 0x1 -#define MC_DC14_VALUE 0x0 -#define MC_DC15_VALUE 0xf3c /* WDQS tuning for clk_wr*/ -#define MC_DC16_VALUE 0xC800 -#define MC_DC17_VALUE 0xd -#define MC_DC18_VALUE 0x300 -#define MC_DC19_VALUE 0x200 -#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */ -#define MC_DC21_VALUE 0xd00 -#define MC_DC22_VALUE 0xd0d -#define MC_DC23_VALUE 0x0 -#define MC_DC24_VALUE 0x62 /* WDQS Tuning for DQS */ -#define MC_DC25_VALUE 0x0 -#define MC_DC26_VALUE 0x0 -#define MC_DC27_VALUE 0x0 -#define MC_DC28_VALUE 0x510 -#define MC_DC29_VALUE 0x2d89 -#define MC_DC30_VALUE 0x8300 -#define MC_DC31_VALUE 0x0 -#define MC_DC32_VALUE 0x0 -#define MC_DC33_VALUE 0x0 -#define MC_DC34_VALUE 0x0 -#define MC_DC35_VALUE 0x0 -#define MC_DC36_VALUE 0x0 -#define MC_DC37_VALUE 0x0 -#define MC_DC38_VALUE 0x0 -#define MC_DC39_VALUE 0x0 -#define MC_DC40_VALUE 0x0 -#define MC_DC41_VALUE 0x0 -#define MC_DC42_VALUE 0x0 -#define MC_DC43_VALUE 0x0 -#define MC_DC44_VALUE 0x0 -#define MC_DC45_VALUE 0x500 -//#define MC_DC45_VALUE 0x400 -#define MC_DC46_VALUE 0x0 diff --git a/package/uboot-ifxmips/files/board/ifx/danube/flash.c b/package/uboot-ifxmips/files/board/ifx/danube/flash.c deleted file mode 100644 index d95888fdf..000000000 --- a/package/uboot-ifxmips/files/board/ifx/danube/flash.c +++ /dev/null @@ -1,917 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -//joelin 10/07/2004 for MXIC MX29LV320ABTC-90 -#include <common.h> -#include <asm/danube.h> - -/* -#ifdef CONFIG_AMAZON - #define FLASH_DELAY {int i; \ - for(i=0;i<800;i++) \ - *((volatile u32 *)CFG_SDRAM_BASE_UNCACHE); \ - } -#else - #define FLASH_DELAY -#endif -*/ - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it - * has nothing to do with the flash chip being 8-bit or 16-bit. - */ -#ifdef CONFIG_FLASH_16BIT -typedef unsigned short FLASH_PORT_WIDTH; -typedef volatile unsigned short FLASH_PORT_WIDTHV; -#define FLASH_ID_MASK 0xFFFF -#else -typedef unsigned long FLASH_PORT_WIDTH; -typedef volatile unsigned long FLASH_PORT_WIDTHV; -#define FLASH_ID_MASK 0xFFFFFFFF -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define ORMASK(size) ((-size) & OR_AM_MSK) // 0xffff8000 - -#if 0 -#define FLASH_CYCLE1 0x0555 -#define FLASH_CYCLE2 0x02aa -#else -#define FLASH_CYCLE1 0x0554 //joelin for MX29LV320AT/B 0x0555 -#define FLASH_CYCLE2 0x02ab //joelin for MX29LV320AT/B 0x02aa -#endif - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(FPWV *addr, flash_info_t *info); -static void flash_reset(flash_info_t *info); -static int write_word_intel(flash_info_t *info, FPWV *dest, FPW data); -static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data); -static void flash_get_offsets(ulong base, flash_info_t *info); -static flash_info_t *flash_get_info(ulong base); - -/*----------------------------------------------------------------------- - * flash_init() - * - * sets up flash_info and returns size of FLASH (bytes) - */ -unsigned long flash_init (void) -{ - unsigned long size = 0; - int i; - - /* Init: no FLASHes known */ - for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) { // 1 bank - ulong flashbase = (i == 0) ? PHYS_FLASH_1 : PHYS_FLASH_2; // 0xb0000000, 0xb4000000 - - volatile ulong * buscon = (ulong *) - ((i == 0) ? DANUBE_EBU_BUSCON0 : DANUBE_EBU_BUSCON1); - - /* Disable write protection */ -// *buscon &= ~AMAZON_EBU_BUSCON0_WRDIS; - /* Enable write protection */ - *buscon |= DANUBE_EBU_BUSCON0_WRDIS; - -#if 1 - memset(&flash_info[i], 0, sizeof(flash_info_t)); -#endif - - flash_info[i].size = - flash_get_size((FPW *)flashbase, &flash_info[i]); - - if (flash_info[i].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx\n", - i, flash_info[i].size); - } - - size += flash_info[i].size; - } - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE // TEXT_BASE >= 0xB3000000 - /* monitor protection ON by default */ /* only use software protection, info->protect[i]=0/1 */ -/* flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+CFG_MONITOR_LEN-1, - flash_get_info(CFG_MONITOR_BASE)); -*/ - flash_protect(FLAG_PROTECT_CLEAR, // clear protect - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+CFG_MONITOR_LEN-1, - flash_get_info(CFG_MONITOR_BASE)); - -#endif - -#ifdef CFG_ENV_IS_IN_FLASH /* 1 */ - /* ENV protection ON by default */ -/* flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SIZE-1, - flash_get_info(CFG_ENV_ADDR)); -*/ - flash_protect(FLAG_PROTECT_CLEAR, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SIZE-1, - flash_get_info(CFG_ENV_ADDR)); - -#endif - - - return size; -} - -/*----------------------------------------------------------------------- - */ -static void flash_reset(flash_info_t *info) -{ - FPWV *base = (FPWV *)(info->start[0]); - - (*DANUBE_EBU_BUSCON0)&=(~0x80000000); // enable writing - (*DANUBE_EBU_BUSCON1)&=(~0x80000000); // enable writing - (*EBU_NAND_CON)=0; - /* Put FLASH back in read mode */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL){ - *base = (FPW)0x00FF00FF; /* Intel Read Mode */ - asm("SYNC"); - } - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD){ - *base = (FPW)0x00F000F0; /* AMD Read Mode */ - asm("SYNC"); //joelin - } - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_MX){ - *base = (FPW)0x00F000F0; /* MXIC Read Mode */ - asm("SYNC"); //joelin - } - - (*DANUBE_EBU_BUSCON0)|=0x80000000; // disable writing - (*DANUBE_EBU_BUSCON1)|=0x80000000; // disable writing - -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start address table */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL - && (info->flash_id & FLASH_BTYPE)) { - int bootsect_size; /* number of bytes/boot sector */ - int sect_size; /* number of bytes/regular sector */ - - bootsect_size = 0x00002000 * (sizeof(FPW)/2); - sect_size = 0x00010000 * (sizeof(FPW)/2); - - /* set sector offsets for bottom boot block type */ - for (i = 0; i < 8; ++i) { - info->start[i] = base + (i * bootsect_size); - } - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + ((i - 7) * sect_size); - } - } - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD - && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) { - - int sect_size; /* number of bytes/sector */ - - sect_size = 0x00010000 * (sizeof(FPW)/2); - - /* set up sector start address table (uniform sector type) */ - for( i = 0; i < info->sector_count; i++ ) - info->start[i] = base + (i * sect_size); - } - else if(((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) - && ((info->flash_id & FLASH_TYPEMASK)==FLASH_28F128J3A)){ - int sect_size; - sect_size = 0x20000; - for(i=0;i < info->sector_count; i++) - info->start[i]= base + (i*sect_size); - } - else if(((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) - && ((info->flash_id & FLASH_TYPEMASK)==FLASH_28F320J3A)){ - int sect_size; - sect_size = 0x20000; - for(i=0;i < info->sector_count; i++) - info->start[i]= base + (i*sect_size); - } -//joelin add for MX29LV320AB-- SA0~SA7:sector size=8K bytes ,SA9~SA70 :sector size=64k bytes - else if(((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_MX) - && ((info->flash_id & FLASH_TYPEMASK)==FLASH_29LV320AB)){ - int bootsect_size; /* number of bytes/boot sector */ - int sect_size; /* number of bytes/regular sector */ - - bootsect_size = 0x00002000 * (sizeof(FPW)/2); - sect_size = 0x00010000 * (sizeof(FPW)/2); - - /* set sector offsets for bottom boot block type */ - for (i = 0; i < 8; ++i) { - info->start[i] = base + (i * bootsect_size); - } - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + ((i - 7) * sect_size); - } - } - else if(((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) - && ((info->flash_id & FLASH_TYPEMASK)==FLASH_29LV320B)){ - int bootsect_size; /* number of bytes/boot sector */ - int sect_size; /* number of bytes/regular sector */ - - bootsect_size = 0x00002000 * (sizeof(FPW)/2); - sect_size = 0x00010000 * (sizeof(FPW)/2); - - /* set sector offsets for bottom boot block type */ - for (i = 0; i < 8; ++i) { - info->start[i] = base + (i * bootsect_size); - } - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + ((i - 7) * sect_size); - } - } -//joelin add for MX29LV160BB-- SA0=16K,SA1,SA2=8K,SA3=32K bytes ,SA4~SA34 :sector size=64k bytes - else if(((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_MX) - && ((info->flash_id & FLASH_TYPEMASK)==FLASH_29LV160BB)){ - int bootsect_size; /* number of bytes/boot sector */ - int sect_size; /* number of bytes/regular sector */ - - bootsect_size = 0x00002000 * (sizeof(FPW)/2); - sect_size = 0x00010000 * (sizeof(FPW)/2); -/* set sector offsets for bottom boot block type */ -//MX29LV160BB - info->start[0] = base ; //SA0=16K bytes - info->start[1] = info->start[0] + (1 * 0x00004000 * (sizeof(FPW)/2)); //SA1=8K bytes - info->start[2] = info->start[1] + (1 * 0x00002000 * (sizeof(FPW)/2)); //SA2=8K bytes - info->start[3] = info->start[2] + (1 * 0x00002000 * (sizeof(FPW)/2)); //SA3=32K bytes - - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + ((i - 3) * sect_size); - } - } -//liupeng add for MX29LV640BB-- SA0~SA7:sector size=8k bytes ,SA8~SA134 :sector size=64k bytes - else if(((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_MX) - && ((info->flash_id & FLASH_TYPEMASK)==FLASH_29LV640BB)){ - int bootsect_size; /* number of bytes/boot sector */ - int sect_size; /* number of bytes/regular sector */ - - bootsect_size = 0x00002000 * (sizeof(FPW)/2); - sect_size = 0x00010000 * (sizeof(FPW)/2); - - /* set sector offsets for bottom boot block type */ - for (i = 0; i < 8; ++i) { - info->start[i] = base + (i * bootsect_size); - } - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + ((i - 7) * sect_size); - } - } - else{ - printf("flash get offsets fail\n"); - } -} - -/*----------------------------------------------------------------------- - */ - -static flash_info_t *flash_get_info(ulong base) -{ - int i; - flash_info_t * info; - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) { - info = & flash_info[i]; - if (info->start[0] <= base && base < info->start[0] + info->size) - break; - } - - return i == CFG_MAX_FLASH_BANKS ? 0 : info; -} - -/*----------------------------------------------------------------------- - */ - -void flash_print_info (flash_info_t *info) -{ - int i; - uchar *boottype; - uchar *bootletter; - uchar *fmt; - uchar botbootletter[] = "B"; - uchar topbootletter[] = "T"; - uchar botboottype[] = "bottom boot sector"; - uchar topboottype[] = "top boot sector"; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_SST: printf ("SST "); break; - case FLASH_MAN_STM: printf ("STM "); break; - case FLASH_MAN_INTEL: printf ("INTEL "); break; - case FLASH_MAN_MX: printf ("MXIC "); break; - default: printf ("Unknown Vendor "); break; - } - - /* check for top or bottom boot, if it applies */ - if (info->flash_id & FLASH_BTYPE) { - boottype = botboottype; - bootletter = botbootletter; - } - else { - boottype = topboottype; - bootletter = topbootletter; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM640U: - fmt = "29LV641D (64 Mbit, uniform sectors)\n"; - break; - case FLASH_28F800C3B: - case FLASH_28F800C3T: - fmt = "28F800C3%s (8 Mbit, %s)\n"; - break; - case FLASH_INTEL800B: - case FLASH_INTEL800T: - fmt = "28F800B3%s (8 Mbit, %s)\n"; - break; - case FLASH_28F160C3B: - case FLASH_28F160C3T: - fmt = "28F160C3%s (16 Mbit, %s)\n"; - break; - case FLASH_INTEL160B: - case FLASH_INTEL160T: - fmt = "28F160B3%s (16 Mbit, %s)\n"; - break; - case FLASH_28F320C3B: - case FLASH_28F320C3T: - fmt = "28F320C3%s (32 Mbit, %s)\n"; - break; - case FLASH_INTEL320B: - case FLASH_INTEL320T: - fmt = "28F320B3%s (32 Mbit, %s)\n"; - break; - case FLASH_28F640C3B: - case FLASH_28F640C3T: - fmt = "28F640C3%s (64 Mbit, %s)\n"; - break; - case FLASH_INTEL640B: - case FLASH_INTEL640T: - fmt = "28F640B3%s (64 Mbit, %s)\n"; - break; - case FLASH_28F128J3A: - fmt = "28F128J3A (128 Mbit, 128 uniform sectors)\n"; - break; - case FLASH_28F320J3A: - fmt = "28F320J3A (32 Mbit, 32 uniform sectors)\n"; - break; - case FLASH_29LV640BB: //liupeng for MXIC FLASH_29LV640BB - fmt = "29LV640BB (64 Mbit, boot sector SA0~SA126 size 64k bytes,other sectors SA127~SA135 size 8k bytes)\n"; - break; - case FLASH_29LV320B: //joelin for MXIC FLASH_29LV320AB - case FLASH_29LV320AB: //joelin for MXIC FLASH_29LV320AB - fmt = "29LV320AB (32 Mbit, boot sector SA0~SA7 size 8K bytes,other sectors SA8~SA70 size 64K bytes)\n"; - break; - case FLASH_29LV160BB: //joelin for MXIC FLASH_29LV160BB - fmt = "29LV160BB (16 Mbit, boot sector SA0 size 16K bytes,SA1,SA2 size 8K bytes,SA3 size 32k bytes,other sectors SA4~SA34 size 64K bytes)\n"; - break; - default: - fmt = "Unknown Chip Type\n"; - break; - } - - printf (fmt, bootletter, boottype); - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, - info->sector_count); - - printf (" Sector Start Addresses:"); - - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) { - printf ("\n "); - } - - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -ulong flash_get_size (FPWV *addr, flash_info_t *info) -{ - (*DANUBE_EBU_BUSCON0)=0x1d7ff; //value from Aikann, should be used on the real chip - (*EBU_ADDR_SEL_0) = 0x10000031; //starting address from 0xb0000000 - (*EBU_NAND_CON)=0; - (*DANUBE_EBU_BUSCON0)&=(~0x80000000); // enable writing - (*DANUBE_EBU_BUSCON1)&=(~0x80000000); // enable writing - /* Write auto select command: read Manufacturer ID */ - - /* Write auto select command sequence and test FLASH answer */ - addr[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */ - asm("SYNC"); - addr[FLASH_CYCLE2] = (FPW)0x00550055; /* for AMD, Intel ignores this */ - asm("SYNC"); - addr[FLASH_CYCLE1] = (FPW)0x00900090; /* selects Intel or AMD */ - asm("SYNC"); - - /* The manufacturer codes are only 1 byte, so just use 1 byte. - * This works for any bus width and any FLASH device width. - */ - - printf("\n type is %08lx", addr[1] & 0xff); //joelin 10/06/2004 flash type - printf("\n type is %08lx", addr[0] & 0xff); //joelin 10/06/2004 flash type -// asm("SYNC"); - switch (addr[1] & 0xff) { - case (uchar)AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - - case (uchar)INTEL_MANUFACT: // 0x0089 - info->flash_id = FLASH_MAN_INTEL; //0x00300000 - break; - -//joelin for MXIC - case (uchar)MX_MANUFACT: // 0x00c2 - info->flash_id = FLASH_MAN_MX ;//0x00030000 - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - break; -/* default: - info->flash_id = FLASH_MAN_INTEL; //0x00300000 - break;*/ - } - - /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */ - if (info->flash_id != FLASH_UNKNOWN) switch (addr[0]) { - case (FPW)EON_ID_EN29LV320B: - info->flash_id += FLASH_29LV320B; - info->sector_count = 71; - info->size = 0x00400000 * (sizeof(FPW)/2); - break; - case (FPW)AMD_ID_LV640U: /* 29LV640 and 29LV641 have same ID */ - info->flash_id += FLASH_AM640U; - info->sector_count = 128; - info->size = 0x00800000 * (sizeof(FPW)/2); - break; /* => 8 or 16 MB */ - - case (FPW)INTEL_ID_28F800C3B: - info->flash_id += FLASH_28F800C3B; - info->sector_count = 23; - info->size = 0x00100000 * (sizeof(FPW)/2); - break; /* => 1 or 2 MB */ - - case (FPW)INTEL_ID_28F800B3B: - info->flash_id += FLASH_INTEL800B; - info->sector_count = 23; - info->size = 0x00100000 * (sizeof(FPW)/2); - break; /* => 1 or 2 MB */ - - case (FPW)INTEL_ID_28F160C3B: - info->flash_id += FLASH_28F160C3B; - info->sector_count = 39; - info->size = 0x00200000 * (sizeof(FPW)/2); - break; /* => 2 or 4 MB */ - - case (FPW)INTEL_ID_28F160B3B: - info->flash_id += FLASH_INTEL160B; - info->sector_count = 39; - info->size = 0x00200000 * (sizeof(FPW)/2); - break; /* => 2 or 4 MB */ - - case (FPW)INTEL_ID_28F320C3B: - info->flash_id += FLASH_28F320C3B; - info->sector_count = 71; - info->size = 0x00400000 * (sizeof(FPW)/2); - break; /* => 4 or 8 MB */ - - case (FPW)INTEL_ID_28F320B3B: - info->flash_id += FLASH_INTEL320B; - info->sector_count = 71; - info->size = 0x00400000 * (sizeof(FPW)/2); - break; /* => 4 or 8 MB */ - - case (FPW)INTEL_ID_28F640C3B: - info->flash_id += FLASH_28F640C3B; - info->sector_count = 135; - info->size = 0x00800000 * (sizeof(FPW)/2); - break; /* => 8 or 16 MB */ - - case (FPW)INTEL_ID_28F640B3B: - info->flash_id += FLASH_INTEL640B; - info->sector_count = 135; - info->size = 0x00800000 * (sizeof(FPW)/2); - break; /* => 8 or 16 MB */ - - case (FPW)INTEL_ID_28F128J3A: - info->flash_id +=FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x01000000 * (sizeof(FPW)/2); - break; /* => 16 MB */ - case (FPW)INTEL_ID_28F320J3A: - info->flash_id += FLASH_28F320J3A; - info->sector_count = 32; - info->size = 0x00400000 * (sizeof(FPW)/2); - break; -//joelin for MXIC - case (FPW)MX_ID_29LV320AB: - info->flash_id += FLASH_29LV320AB; - info->sector_count = 71; - info->size = 0x00400000 * (sizeof(FPW)/2); - break; /* => 4 MB */ - /* => 4 MB */ -//joelin for MXIC - case (FPW)MX_ID_29LV160BB: - info->flash_id += FLASH_29LV160BB; - info->sector_count = 35; - info->size = 0x00200000 * (sizeof(FPW)/2); - break; /* => 2 MB */ - /* => 2 MB */ - /* liupeng*/ - case (FPW)MX_ID_29LV640BB: - info->flash_id += FLASH_29LV640BB; - info->sector_count = 135; - info->size = 0x00800000 * (sizeof(FPW)/2); - break; /* => 2 MB */ - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* => no or unknown flash */ -/* default: - info->flash_id += FLASH_28F320J3A; - info->sector_count = 32; - info->size = 0x00400000 * (sizeof(FPW)/2); - break;*/ - } - - - (*DANUBE_EBU_BUSCON0)|=0x80000000; // disable writing - (*DANUBE_EBU_BUSCON1)|=0x80000000; // disable writing - - flash_get_offsets((ulong)addr, info); - - /* Put FLASH back in read mode */ - flash_reset(info); - - return (info->size); -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - FPWV *addr; - int flag, prot, sect; - int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL; - ulong start, now, last; - int rcode = 0; - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_INTEL800B: - case FLASH_INTEL160B: - case FLASH_INTEL320B: - case FLASH_INTEL640B: - case FLASH_28F800C3B: - case FLASH_28F160C3B: - case FLASH_28F320C3B: - case FLASH_28F640C3B: - case FLASH_28F128J3A: - case FLASH_28F320J3A: - case FLASH_AM640U: - case FLASH_29LV640BB: //liupeng for MXIC MX29LV640BB - case FLASH_29LV320B: - case FLASH_29LV320AB: //joelin for MXIC MX29LV320AB - case FLASH_29LV160BB: //joelin for MXIC MX29LV160BB - break; - case FLASH_UNKNOWN: - default: - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - last = get_timer(0); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last && rcode == 0; sect++) { - - if (info->protect[sect] != 0) /* protected, skip it */ - continue; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - (*DANUBE_EBU_BUSCON0)&=(~0x80000000); // enable writing - (*DANUBE_EBU_BUSCON1)&=(~0x80000000); // enable writing - (*EBU_NAND_CON)=0; - addr = (FPWV *)(info->start[sect]); - if (intel) { - *addr = (FPW)0x00500050; /* clear status register */ - *addr = (FPW)0x00200020; /* erase setup */ - *addr = (FPW)0x00D000D0; /* erase confirm */ - asm("SYNC"); - } - else { - /* must be AMD style if not Intel */ - FPWV *base; /* first address in bank */ - - base = (FPWV *)(info->start[0]); - base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ - base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ - base[FLASH_CYCLE1] = (FPW)0x00800080; /* erase mode */ - base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ - base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ - *addr = (FPW)0x00300030; /* erase sector */ - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer(0); - - /* wait at least 50us for AMD, 80us for Intel. - * Let's wait 1 ms. - */ - udelay (1000); - - while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Erase Timeout\n"); - - if (intel) { - /* suspend erase */ - *addr = (FPW)0x00B000B0; - } - - flash_reset(info); /* reset to read mode */ - rcode = 1; /* failed */ - break; - } - - /* show that we're waiting */ - if ((get_timer(last)) > CFG_HZ) {/* every second */ - putc ('.'); - last = get_timer(0); - } - } - - -//joelin for MXIC - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_MX: //joelin for MXIC - break; - default: - if((*addr & (FPW)0x00200020) != (FPW)0x0) - printf("Erase Error\n"); - break; - } - - - - /* show that we're waiting */ - if ((get_timer(last)) > CFG_HZ) { /* every second */ - putc ('.'); - last = get_timer(0); - } - - //flash_reset(info); /* reset to read mode */ - } - - (*DANUBE_EBU_BUSCON0)|=0x80000000; // disable writing - (*DANUBE_EBU_BUSCON1)|=0x80000000; // disable writing - - flash_reset(info); /* Homebox Black with JS28F128J3D75 had trouble reading after erase */ - - printf (" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */ - int bytes; /* number of bytes to program in current word */ - int left; /* number of bytes left to program */ - int i, res; - - for (left = cnt, res = 0; - left > 0 && res == 0; - addr += sizeof(data), left -= sizeof(data) - bytes) { - - bytes = addr & (sizeof(data) - 1); - addr &= ~(sizeof(data) - 1); - - /* combine source and destination data so can program - * an entire word of 16 or 32 bits - */ - for (i = 0; i < sizeof(data); i++) { - data <<= 8; - if (i < bytes || i - bytes >= left ) - data += *((uchar *)addr + i); - else - data += *src++; - } - - /* write one word to the flash */ - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - case FLASH_MAN_MX: //joelin for MXIC - res = write_word_amd(info, (FPWV *)addr, data); - break; - case FLASH_MAN_INTEL: - res = write_word_intel(info, (FPWV *)addr, data); - break; - default: - /* unknown flash type, error! */ - printf ("missing or unknown FLASH type\n"); - res = 1; /* not really a timeout, but gives error */ - break; - } - } - - return (res); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash for AMD FLASH - * A word is 16 or 32 bits, whichever the bus width of the flash bank - * (not an individual chip) is. - * - * returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data) -{ - ulong start; - int flag; - int res = 0; /* result, assume success */ - FPWV *base; /* first address in flash bank */ - - /* Check if Flash is (sufficiently) erased */ - if ((*dest & data) != data) { - return (2); - } - - base = (FPWV *)(info->start[0]); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - (*DANUBE_EBU_BUSCON0)&=(~0x80000000); // enable writing - (*DANUBE_EBU_BUSCON1)&=(~0x80000000); // enable writing - (*EBU_NAND_CON)=0; - - base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ - base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ - base[FLASH_CYCLE1] = (FPW)0x00A000A0; /* selects program mode */ - - *dest = data; /* start programming the data */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer (0); - - /* data polling for D7 */ - while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - *dest = (FPW)0x00F000F0; /* reset bank */ - res = 1; - } - } - - (*DANUBE_EBU_BUSCON0)|=0x80000000; // disable writing - (*DANUBE_EBU_BUSCON1)|=0x80000000; // disable writing - - return (res); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash for Intel FLASH - * A word is 16 or 32 bits, whichever the bus width of the flash bank - * (not an individual chip) is. - * - * returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word_intel (flash_info_t *info, FPWV *dest, FPW data) -{ - ulong start; - int flag; - int res = 0; /* result, assume success */ - - /* Check if Flash is (sufficiently) erased */ - if ((*dest & data) != data) { - return (2); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - (*DANUBE_EBU_BUSCON0)&=(~0x80000000); // enable writing - (*DANUBE_EBU_BUSCON1)&=(~0x80000000); // enable writing - (*EBU_NAND_CON)=0; - *dest = (FPW)0x00500050; /* clear status register */ - *dest = (FPW)0x00FF00FF; /* make sure in read mode */ - *dest = (FPW)0x00400040; /* program setup */ - *dest = data; /* start programming the data */ - asm("SYNC"); - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer (0); - - while (res == 0 && (*dest & (FPW)0x00800080) != (FPW)0x00800080) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - *dest = (FPW)0x00B000B0; /* Suspend program */ - res = 1; - } - } - - if (res == 0 && (*dest & (FPW)0x00100010)) - res = 1; /* write failed, time out error is close enough */ - - *dest = (FPW)0x00500050; /* clear status register */ - flash_reset(info); - - (*DANUBE_EBU_BUSCON0)|=0x80000000; // disable writing - (*DANUBE_EBU_BUSCON1)|=0x80000000; // disable writing - - return (res); -} diff --git a/package/uboot-ifxmips/files/board/ifx/danube/lowlevel_init.S b/package/uboot-ifxmips/files/board/ifx/danube/lowlevel_init.S deleted file mode 100644 index f5f24a40c..000000000 --- a/package/uboot-ifxmips/files/board/ifx/danube/lowlevel_init.S +++ /dev/null @@ -1,582 +0,0 @@ - -/* - * Memory sub-system initialization code for INCA-IP2 development board. - * Andre Messerschmidt - * Copyright (c) 2005 Infineon Technologies AG - * - * Based on Inca-IP code - * Copyright (c) 2003 Wolfgang Denk <wd@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -/* History: - peng liu May 25, 2006, for PLL setting after reset, 05252006 - */ -#include <config.h> -#include <version.h> -#include <asm/regdef.h> -#include <configs/danube.h> - - -#ifdef USE_REFERENCE_BOARD -#ifdef DANUBE_DDR_RAM_111M -#include "ddr_settings_r111.h" -#elif defined(PROMOSDDR400) -#include "ddr_settings_PROMOSDDR400.h" -#elif defined(DDR_SAMSUNG_166M) -#include "ddr_settings_Samsung_166.h" -#elif defined(DDR_PSC_166M) -#include "ddr_settings_psc_166.h" -#else -#include "ddr_settings_r166.h" -#endif -#endif - -#ifdef USE_EVALUATION_BOARD -#ifdef DANUBE_DDR_RAM_111M -#include "ddr_settings_e111.h" -#else -#include "ddr_settings_e166.h" -#endif -#endif - - - -/*TODO: liupeng check !!! */ -#define EBU_MODUL_BASE 0xB4102000 -#define EBU_CLC(value) 0x0000(value) -#define EBU_CON(value) 0x0010(value) -#define EBU_ADDSEL0(value) 0x0020(value) -#define EBU_ADDSEL1(value) 0x0024(value) -#define EBU_ADDSEL2(value) 0x0028(value) -#define EBU_ADDSEL3(value) 0x002C(value) -#define EBU_BUSCON0(value) 0x0060(value) -#define EBU_BUSCON1(value) 0x0064(value) -#define EBU_BUSCON2(value) 0x0068(value) -#define EBU_BUSCON3(value) 0x006C(value) - -#define MC_MODUL_BASE 0xBF800000 -#define MC_ERRCAUSE(value) 0x0010(value) -#define MC_ERRADDR(value) 0x0020(value) -#define MC_CON(value) 0x0060(value) - -#define MC_SRAM_ENABLE 0x00000004 -#define MC_SDRAM_ENABLE 0x00000002 -#define MC_DDRRAM_ENABLE 0x00000001 - -#define MC_SDR_MODUL_BASE 0xBF800200 -#define MC_IOGP(value) 0x0000(value) -#define MC_CTRLENA(value) 0x0010(value) -#define MC_MRSCODE(value) 0x0020(value) -#define MC_CFGDW(value) 0x0030(value) -#define MC_CFGPB0(value) 0x0040(value) -#define MC_LATENCY(value) 0x0080(value) -#define MC_TREFRESH(value) 0x0090(value) -#define MC_SELFRFSH(value) 0x00A0(value) - -#define MC_DDR_MODUL_BASE 0xBF801000 -#define MC_DC00(value) 0x0000(value) -#define MC_DC01(value) 0x0010(value) -#define MC_DC02(value) 0x0020(value) -#define MC_DC03(value) 0x0030(value) -#define MC_DC04(value) 0x0040(value) -#define MC_DC05(value) 0x0050(value) -#define MC_DC06(value) 0x0060(value) -#define MC_DC07(value) 0x0070(value) -#define MC_DC08(value) 0x0080(value) -#define MC_DC09(value) 0x0090(value) -#define MC_DC10(value) 0x00A0(value) -#define MC_DC11(value) 0x00B0(value) -#define MC_DC12(value) 0x00C0(value) -#define MC_DC13(value) 0x00D0(value) -#define MC_DC14(value) 0x00E0(value) -#define MC_DC15(value) 0x00F0(value) -#define MC_DC16(value) 0x0100(value) -#define MC_DC17(value) 0x0110(value) -#define MC_DC18(value) 0x0120(value) -#define MC_DC19(value) 0x0130(value) -#define MC_DC20(value) 0x0140(value) -#define MC_DC21(value) 0x0150(value) -#define MC_DC22(value) 0x0160(value) -#define MC_DC23(value) 0x0170(value) -#define MC_DC24(value) 0x0180(value) -#define MC_DC25(value) 0x0190(value) -#define MC_DC26(value) 0x01A0(value) -#define MC_DC27(value) 0x01B0(value) -#define MC_DC28(value) 0x01C0(value) -#define MC_DC29(value) 0x01D0(value) -#define MC_DC30(value) 0x01E0(value) -#define MC_DC31(value) 0x01F0(value) -#define MC_DC32(value) 0x0200(value) -#define MC_DC33(value) 0x0210(value) -#define MC_DC34(value) 0x0220(value) -#define MC_DC35(value) 0x0230(value) -#define MC_DC36(value) 0x0240(value) -#define MC_DC37(value) 0x0250(value) -#define MC_DC38(value) 0x0260(value) -#define MC_DC39(value) 0x0270(value) -#define MC_DC40(value) 0x0280(value) -#define MC_DC41(value) 0x0290(value) -#define MC_DC42(value) 0x02A0(value) -#define MC_DC43(value) 0x02B0(value) -#define MC_DC44(value) 0x02C0(value) -#define MC_DC45(value) 0x02D0(value) -#define MC_DC46(value) 0x02E0(value) - -#define RCU_OFFSET 0xBF203000 -#define RCU_RST_REQ (RCU_OFFSET + 0x0010) -#define RCU_STS (RCU_OFFSET + 0x0014) - -#define CGU_OFFSET 0xBF103000 -#define PLL0_CFG (CGU_OFFSET + 0x0004) -#define PLL1_CFG (CGU_OFFSET + 0x0008) -#define PLL2_CFG (CGU_OFFSET + 0x000C) -#define CGU_SYS (CGU_OFFSET + 0x0010) -#define CGU_UPDATE (CGU_OFFSET + 0x0014) -#define IF_CLK (CGU_OFFSET + 0x0018) -#define CGU_SMD (CGU_OFFSET + 0x0020) -#define CGU_CT1SR (CGU_OFFSET + 0x0028) -#define CGU_CT2SR (CGU_OFFSET + 0x002C) -#define CGU_PCMCR (CGU_OFFSET + 0x0030) -#define PCI_CR_PCI (CGU_OFFSET + 0x0034) -#define CGU_OSC_CTRL (CGU_OFFSET + 0x001C) -#define CGU_MIPS_PWR_DWN (CGU_OFFSET + 0x0038) -#define CLK_MEASURE (CGU_OFFSET + 0x003C) - -//05252006 -#define pll0_35MHz_CONFIG 0x9D861059 -#define pll1_35MHz_CONFIG 0x1A260CD9 -#define pll2_35MHz_CONFIG 0x8000f1e5 -#define pll0_36MHz_CONFIG 0x1000125D -#define pll1_36MHz_CONFIG 0x1B1E0C99 -#define pll2_36MHz_CONFIG 0x8002f2a1 -//05252006 - -//06063001-joelin disable the PCI CFRAME mask -start -/*CFRAME is an I/O signal, in the chip, the output CFRAME is selected via GPIO altsel pins, so if you select MII1 RXD1, the CFRAME will not come out. -But the CFRAME input still take the signal from the pad and not disabled when altsel choose other function. So when MII1_RXD1 is low from other device, the EBU interface will be disabled. - -The chip function in such a way that disable the CFRAME mask mean EBU not longer check CFRAME to be the device using the bus. -The side effect is the entire PCI block will see CFRAME low all the time meaning PCI cannot use the bus at all so no more PCI function. -*/ -#define PCI_CR_PR_OFFSET 0xBE105400 -#define PCI_CR_PCI_MOD_REG (PCI_CR_PR_OFFSET + 0x0030) -#define PCI_CONFIG_SPACE 0xB7000000 -#define CS_CFM (PCI_CONFIG_SPACE + 0x6C) -//06063001-joelin disable the PCI CFRAME mask -end - .set noreorder - - -/* - * void ebu_init(long) - * - * a0 has the clock value we are going to run at - */ - .globl ebu_init - .ent ebu_init -ebu_init: -/*TODO:liupeng */ - j ra - nop - - .end ebu_init - - -/* - * void cgu_init(long) - * - * a0 has the clock value - */ - .globl cgu_init - .ent cgu_init -cgu_init: - li t2, CGU_SYS - lw t2,0(t2) - beq t2,a0,freq_up2date - nop - - li t2, RCU_STS - lw t2, 0(t2) - and t2,0x00020000 - beq t2,0x00020000,boot_36MHZ - nop -//05252006 - li t1, PLL0_CFG - li t2, pll0_35MHz_CONFIG - sw t2,0(t1) - li t1, PLL1_CFG - li t2, pll1_35MHz_CONFIG - sw t2,0(t1) - li t1, PLL2_CFG - li t2, pll2_35MHz_CONFIG - sw t2,0(t1) - li t1, CGU_SYS - sw a0,0(t1) - li t1, RCU_RST_REQ - li t2, 0x40000008 - sw t2,0(t1) - b wait_reset - nop -boot_36MHZ: - li t1, PLL0_CFG - li t2, pll0_36MHz_CONFIG - sw t2,0(t1) - li t1, PLL1_CFG - li t2, pll1_36MHz_CONFIG - sw t2,0(t1) - li t1, PLL2_CFG - li t2, pll2_36MHz_CONFIG - sw t2,0(t1) - li t1, CGU_SYS - sw a0,0(t1) - li t1, RCU_RST_REQ - li t2, 0x40000008 - sw t2,0(t1) -//05252006 - -wait_reset: - b wait_reset - nop -freq_up2date: - j ra - nop - .end cgu_init - - -/* - * void sdram_init(long) - * - * a0 has the clock value - */ - .globl sdram_init - .ent sdram_init -sdram_init: - - /* SDRAM Initialization - */ - li t1, MC_MODUL_BASE - - /* Clear Error log registers */ - sw zero, MC_ERRCAUSE(t1) - sw zero, MC_ERRADDR(t1) - - /* Enable SDRAM module in memory controller */ - li t3, MC_SDRAM_ENABLE - lw t2, MC_CON(t1) - or t3, t2, t3 - sw t3, MC_CON(t1) - - li t1, MC_SDR_MODUL_BASE - - /* disable the controller */ - li t2, 0 - sw t2, MC_CTRLENA(t1) - - li t2, 0x822 - sw t2, MC_IOGP(t1) - - li t2, 0x2 - sw t2, MC_CFGDW(t1) - - /* Set CAS Latency */ - li t2, 0x00000020 - sw t2, MC_MRSCODE(t1) - - /* Set CS0 to SDRAM parameters */ - li t2, 0x000014d8 - sw t2, MC_CFGPB0(t1) - - /* Set SDRAM latency parameters */ - li t2, 0x00036325; /* BC PC100 */ - sw t2, MC_LATENCY(t1) - - /* Set SDRAM refresh rate */ - li t2, 0x00000C30 - sw t2, MC_TREFRESH(t1) - - /* Clear Power-down registers */ - sw zero, MC_SELFRFSH(t1) - - /* Finally enable the controller */ - li t2, 1 - sw t2, MC_CTRLENA(t1) - - - j ra - nop - - - .end sdram_init - -/* - * void ddrram_init(long) - * - * a0 has the clock value - */ - .globl ddrram_init - .ent ddrram_init -ddrram_init: - - /* DDR-DRAM Initialization - */ - li t1, MC_MODUL_BASE - - /* Clear Error log registers */ - sw zero, MC_ERRCAUSE(t1) - sw zero, MC_ERRADDR(t1) - - /* Enable DDR module in memory controller */ - li t3, MC_DDRRAM_ENABLE - lw t2, MC_CON(t1) - or t3, t2, t3 - sw t3, MC_CON(t1) - - li t1, MC_DDR_MODUL_BASE - - /* Write configuration to DDR controller registers */ - li t2, MC_DC0_VALUE - sw t2, MC_DC00(t1) - - li t2, MC_DC1_VALUE - sw t2, MC_DC01(t1) - - li t2, MC_DC2_VALUE - sw t2, MC_DC02(t1) - - li t2, MC_DC3_VALUE - sw t2, MC_DC03(t1) - - li t2, MC_DC4_VALUE - sw t2, MC_DC04(t1) - - li t2, MC_DC5_VALUE - sw t2, MC_DC05(t1) - - li t2, MC_DC6_VALUE - sw t2, MC_DC06(t1) - - li t2, MC_DC7_VALUE - sw t2, MC_DC07(t1) - - li t2, MC_DC8_VALUE - sw t2, MC_DC08(t1) - - li t2, MC_DC9_VALUE - sw t2, MC_DC09(t1) - - li t2, MC_DC10_VALUE - sw t2, MC_DC10(t1) - - li t2, MC_DC11_VALUE - sw t2, MC_DC11(t1) - - li t2, MC_DC12_VALUE - sw t2, MC_DC12(t1) - - li t2, MC_DC13_VALUE - sw t2, MC_DC13(t1) - - li t2, MC_DC14_VALUE - sw t2, MC_DC14(t1) - - li t2, MC_DC15_VALUE - sw t2, MC_DC15(t1) - - li t2, MC_DC16_VALUE - sw t2, MC_DC16(t1) - - li t2, MC_DC17_VALUE - sw t2, MC_DC17(t1) - - li t2, MC_DC18_VALUE - sw t2, MC_DC18(t1) - - li t2, MC_DC19_VALUE - sw t2, MC_DC19(t1) - - li t2, MC_DC20_VALUE - sw t2, MC_DC20(t1) - - li t2, MC_DC21_VALUE - sw t2, MC_DC21(t1) - - li t2, MC_DC22_VALUE - sw t2, MC_DC22(t1) - - li t2, MC_DC23_VALUE - sw t2, MC_DC23(t1) - - li t2, MC_DC24_VALUE - sw t2, MC_DC24(t1) - - li t2, MC_DC25_VALUE - sw t2, MC_DC25(t1) - - li t2, MC_DC26_VALUE - sw t2, MC_DC26(t1) - - li t2, MC_DC27_VALUE - sw t2, MC_DC27(t1) - - li t2, MC_DC28_VALUE - sw t2, MC_DC28(t1) - - li t2, MC_DC29_VALUE - sw t2, MC_DC29(t1) - - li t2, MC_DC30_VALUE - sw t2, MC_DC30(t1) - - li t2, MC_DC31_VALUE - sw t2, MC_DC31(t1) - - li t2, MC_DC32_VALUE - sw t2, MC_DC32(t1) - - li t2, MC_DC33_VALUE - sw t2, MC_DC33(t1) - - li t2, MC_DC34_VALUE - sw t2, MC_DC34(t1) - - li t2, MC_DC35_VALUE - sw t2, MC_DC35(t1) - - li t2, MC_DC36_VALUE - sw t2, MC_DC36(t1) - - li t2, MC_DC37_VALUE - sw t2, MC_DC37(t1) - - li t2, MC_DC38_VALUE - sw t2, MC_DC38(t1) - - li t2, MC_DC39_VALUE - sw t2, MC_DC39(t1) - - li t2, MC_DC40_VALUE - sw t2, MC_DC40(t1) - - li t2, MC_DC41_VALUE - sw t2, MC_DC41(t1) - - li t2, MC_DC42_VALUE - sw t2, MC_DC42(t1) - - li t2, MC_DC43_VALUE - sw t2, MC_DC43(t1) - - li t2, MC_DC44_VALUE - sw t2, MC_DC44(t1) - - li t2, MC_DC45_VALUE - sw t2, MC_DC45(t1) - - li t2, MC_DC46_VALUE - sw t2, MC_DC46(t1) - - li t2, 0x00000100 - sw t2, MC_DC03(t1) - - j ra - nop - - - .end ddrram_init - - .globl lowlevel_init - .ent lowlevel_init -lowlevel_init: - /* EBU, CGU and SDRAM/DDR-RAM Initialization. - */ - move t0, ra - /* We rely on the fact that neither cgu_init() nor sdram_init() - * modify t0 - */ -#ifdef DANUBE_BOOT_FROM_EBU -#ifdef DANUBE_DDR_RAM_166M -//05252006 - /* 0xe8 means CPU0/CPU1 333M, DDR 167M, FPI 83M, PPE 240M */ - li a0,0xe8 - bal cgu_init - nop -#endif -#ifdef PROMOSDDR400 - li a0,0xe8 - bal cgu_init - nop -#endif -#ifdef DDR_SAMSUNG_166M - li a0,0xe8 - bal cgu_init - nop -#endif -#ifdef DDR_PSC_166M - li a0,0xe8 - bal cgu_init - nop -#endif -#ifdef DANUBE_DDR_RAM_133M - li a0,0xe9 -//05252006 - bal cgu_init - nop -#endif -#endif -/*TODO:liupeng add this define !!!! */ -/* - #define DANUBE_BOOT_FROM_EBU - #define DANUBE_USE_DDR_RAM -*/ - -//06063001-joelin disable the PCI CFRAME mask-start -#ifdef DISABLE_CFRAME - li t1, PCI_CR_PCI //mw bf103034 80000000 - li t2, 0x80000000 - sw t2,0(t1) - - li t1, PCI_CR_PCI_MOD_REG //mw be105430 103 - li t2, 0x103 - sw t2,0(t1) - - li t1, CS_CFM //mw b700006c 0 - li t2, 0x00 - sw t2, 0(t1) - - li t1, PCI_CR_PCI_MOD_REG //mw be105430 103 - li t2, 0x1000103 - sw t2, 0(t1) -#endif -//06063001-joelin disable the PCI CFRAME mask-end - -#ifdef DANUBE_BOOT_FROM_EBU -#ifdef DANUBE_USE_DDR_RAM - bal ddrram_init - nop -#else - bal sdram_init - nop -#endif -#endif - - move ra, t0 - j ra - nop - - .end lowlevel_init diff --git a/package/uboot-ifxmips/files/board/ifx/danube/pmuenable.S b/package/uboot-ifxmips/files/board/ifx/danube/pmuenable.S deleted file mode 100644 index e0d7971d8..000000000 --- a/package/uboot-ifxmips/files/board/ifx/danube/pmuenable.S +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Power Management unit initialization code for AMAZON development board. - * - * Copyright (c) 2003 Ou Ke, Infineon. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <version.h> -#include <asm/regdef.h> - -#define PMU_PWDCR 0xBF10201C -#define PMU_SR 0xBF102020 - - .globl pmuenable - -pmuenable: - li t0, PMU_PWDCR - li t1, 0x2 /* enable everything */ - sw t1, 0(t0) -#if 0 -1: - li t0, PMU_SR - lw t2, 0(t0) - bne t1, t2, 1b - nop -#endif - j ra - nop - - diff --git a/package/uboot-ifxmips/files/board/ifx/danube/u-boot-bootstrap.lds b/package/uboot-ifxmips/files/board/ifx/danube/u-boot-bootstrap.lds deleted file mode 100644 index 36c658b18..000000000 --- a/package/uboot-ifxmips/files/board/ifx/danube/u-boot-bootstrap.lds +++ /dev/null @@ -1,69 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk Engineering, <wd@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* -OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") -*/ -OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips") -OUTPUT_ARCH(mips) -ENTRY(_start_bootstrap) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata*) } - - . = ALIGN(4); - .data : { *(.data*) } - - . = ALIGN(4); - .sdata : { *(.sdata) } - - _gp = ALIGN(16); - - __got_start_bootstrap = .; - .got : { *(.got) } - __got_end_bootstrap = .; - - .sdata : { *(.sdata) } - - . = .; - __u_boot_cmd_start_bootstrap = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end_bootstrap = .; - - uboot_end_data_bootstrap = .; - num_got_entries = (__got_end_bootstrap - __got_start_bootstrap) >> 2; - - . = ALIGN(4); - .sbss : { *(.sbss) } - .bss : { *(.bss) } - uboot_end_bootstrap = .; -} diff --git a/package/uboot-ifxmips/files/board/ifx/danube/u-boot.lds b/package/uboot-ifxmips/files/board/ifx/danube/u-boot.lds deleted file mode 100644 index 40645166c..000000000 --- a/package/uboot-ifxmips/files/board/ifx/danube/u-boot.lds +++ /dev/null @@ -1,69 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk Engineering, <wd@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* -OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") -*/ -OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips") -OUTPUT_ARCH(mips) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata*) } - - . = ALIGN(4); - .data : { *(.data*) } - - . = ALIGN(4); - .sdata : { *(.sdata) } - - _gp = ALIGN(16); - - __got_start = .; - .got : { *(.got) } - __got_end = .; - - .sdata : { *(.sdata) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - uboot_end_data = .; - num_got_entries = (__got_end - __got_start) >> 2; - - . = ALIGN(4); - .sbss : { *(.sbss) } - .bss : { *(.bss) } - uboot_end = .; -} |