diff options
| -rw-r--r-- | target/linux/ar71xx/files/arch/mips/ar71xx/irq.c | 162 | ||||
| -rw-r--r-- | target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c | 69 | ||||
| -rw-r--r-- | target/linux/ar71xx/files/arch/mips/pci/pci-ar724x.c | 81 |
3 files changed, 149 insertions, 163 deletions
diff --git a/target/linux/ar71xx/files/arch/mips/ar71xx/irq.c b/target/linux/ar71xx/files/arch/mips/ar71xx/irq.c index d5d9a6806..2ad652f27 100644 --- a/target/linux/ar71xx/files/arch/mips/ar71xx/irq.c +++ b/target/linux/ar71xx/files/arch/mips/ar71xx/irq.c @@ -21,155 +21,6 @@ #include <asm/mach-ar71xx/ar71xx.h> -#ifdef CONFIG_PCI -static void ar71xx_pci_irq_handler(unsigned int irq, struct irq_desc *desc) -{ - u32 pending; - - pending = ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_STATUS) & - ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE); - - if (pending & PCI_INT_DEV0) - generic_handle_irq(AR71XX_PCI_IRQ_DEV0); - - else if (pending & PCI_INT_DEV1) - generic_handle_irq(AR71XX_PCI_IRQ_DEV1); - - else if (pending & PCI_INT_DEV2) - generic_handle_irq(AR71XX_PCI_IRQ_DEV2); - - else if (pending & PCI_INT_CORE) - generic_handle_irq(AR71XX_PCI_IRQ_CORE); - - else - spurious_interrupt(); -} - -static void ar71xx_pci_irq_unmask(unsigned int irq) -{ - irq -= AR71XX_PCI_IRQ_BASE; - ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE, - ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE) | (1 << irq)); - - /* flush write */ - ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE); -} - -static void ar71xx_pci_irq_mask(unsigned int irq) -{ - irq -= AR71XX_PCI_IRQ_BASE; - ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE, - ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE) & ~(1 << irq)); - - /* flush write */ - ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE); -} - -static struct irq_chip ar71xx_pci_irq_chip = { - .name = "AR71XX PCI ", - .mask = ar71xx_pci_irq_mask, - .unmask = ar71xx_pci_irq_unmask, - .mask_ack = ar71xx_pci_irq_mask, -}; - -static void __init ar71xx_pci_irq_init(void) -{ - int i; - - ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE, 0); - ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_STATUS, 0); - - for (i = AR71XX_PCI_IRQ_BASE; - i < AR71XX_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++) { - irq_desc[i].status = IRQ_DISABLED; - set_irq_chip_and_handler(i, &ar71xx_pci_irq_chip, - handle_level_irq); - } - - set_irq_chained_handler(AR71XX_CPU_IRQ_IP2, ar71xx_pci_irq_handler); -} - -static void ar724x_pci_irq_handler(unsigned int irq, struct irq_desc *desc) -{ - u32 pending; - - pending = ar724x_pci_rr(AR724X_PCI_REG_INT_STATUS) & - ar724x_pci_rr(AR724X_PCI_REG_INT_MASK); - - if (pending & AR724X_PCI_INT_DEV0) - generic_handle_irq(AR71XX_PCI_IRQ_DEV0); - - else - spurious_interrupt(); -} - -static void ar724x_pci_irq_unmask(unsigned int irq) -{ - switch (irq) { - case AR71XX_PCI_IRQ_DEV0: - irq -= AR71XX_PCI_IRQ_BASE; - ar724x_pci_wr(AR724X_PCI_REG_INT_MASK, - ar724x_pci_rr(AR724X_PCI_REG_INT_MASK) | - AR724X_PCI_INT_DEV0); - /* flush write */ - ar724x_pci_rr(AR724X_PCI_REG_INT_MASK); - } -} - -static void ar724x_pci_irq_mask(unsigned int irq) -{ - switch (irq) { - case AR71XX_PCI_IRQ_DEV0: - irq -= AR71XX_PCI_IRQ_BASE; - ar724x_pci_wr(AR724X_PCI_REG_INT_MASK, - ar724x_pci_rr(AR724X_PCI_REG_INT_MASK) & - ~AR724X_PCI_INT_DEV0); - /* flush write */ - ar724x_pci_rr(AR724X_PCI_REG_INT_MASK); - - ar724x_pci_wr(AR724X_PCI_REG_INT_STATUS, - ar724x_pci_rr(AR724X_PCI_REG_INT_STATUS) | - AR724X_PCI_INT_DEV0); - /* flush write */ - ar724x_pci_rr(AR724X_PCI_REG_INT_STATUS); - } -} - -static struct irq_chip ar724x_pci_irq_chip = { - .name = "AR724X PCI ", - .mask = ar724x_pci_irq_mask, - .unmask = ar724x_pci_irq_unmask, - .mask_ack = ar724x_pci_irq_mask, -}; - -static void __init ar724x_pci_irq_init(void) -{ - u32 t; - int i; - - t = ar71xx_reset_rr(AR724X_RESET_REG_RESET_MODULE); - if (t & (AR724X_RESET_PCIE | AR724X_RESET_PCIE_PHY | - AR724X_RESET_PCIE_PHY_SERIAL)) { - return; - } - - ar724x_pci_wr(AR724X_PCI_REG_INT_MASK, 0); - ar724x_pci_wr(AR724X_PCI_REG_INT_STATUS, 0); - - for (i = AR71XX_PCI_IRQ_BASE; - i < AR71XX_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++) { - irq_desc[i].status = IRQ_DISABLED; - set_irq_chip_and_handler(i, &ar724x_pci_irq_chip, - handle_level_irq); - } - - set_irq_chained_handler(AR71XX_CPU_IRQ_IP2, ar724x_pci_irq_handler); -} -#else -static inline void ar71xx_pci_irq_init(void) {}; -static inline void ar724x_pci_irq_init(void) {}; -#endif /* CONFIG_PCI */ - static void ar71xx_gpio_irq_dispatch(void) { u32 pending; @@ -386,18 +237,5 @@ void __init arch_init_irq(void) cp0_perfcount_irq = AR71XX_MISC_IRQ_PERFC; - switch (ar71xx_soc) { - case AR71XX_SOC_AR7130: - case AR71XX_SOC_AR7141: - case AR71XX_SOC_AR7161: - ar71xx_pci_irq_init(); - break; - case AR71XX_SOC_AR7240: - ar724x_pci_irq_init(); - break; - default: - break; - } - ar71xx_gpio_irq_init(); } diff --git a/target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c b/target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c index b2d36caa0..ac94da986 100644 --- a/target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c +++ b/target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c @@ -17,6 +17,7 @@ #include <linux/bitops.h> #include <linux/pci.h> #include <linux/pci_regs.h> +#include <linux/interrupt.h> #include <asm/mach-ar71xx/ar71xx.h> #include <asm/mach-ar71xx/pci.h> @@ -300,6 +301,73 @@ static struct pci_controller ar71xx_pci_controller = { .io_resource = &ar71xx_pci_io_resource, }; +static void ar71xx_pci_irq_handler(unsigned int irq, struct irq_desc *desc) +{ + u32 pending; + + pending = ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_STATUS) & + ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE); + + if (pending & PCI_INT_DEV0) + generic_handle_irq(AR71XX_PCI_IRQ_DEV0); + + else if (pending & PCI_INT_DEV1) + generic_handle_irq(AR71XX_PCI_IRQ_DEV1); + + else if (pending & PCI_INT_DEV2) + generic_handle_irq(AR71XX_PCI_IRQ_DEV2); + + else if (pending & PCI_INT_CORE) + generic_handle_irq(AR71XX_PCI_IRQ_CORE); + + else + spurious_interrupt(); +} + +static void ar71xx_pci_irq_unmask(unsigned int irq) +{ + irq -= AR71XX_PCI_IRQ_BASE; + ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE, + ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE) | (1 << irq)); + + /* flush write */ + ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE); +} + +static void ar71xx_pci_irq_mask(unsigned int irq) +{ + irq -= AR71XX_PCI_IRQ_BASE; + ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE, + ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE) & ~(1 << irq)); + + /* flush write */ + ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE); +} + +static struct irq_chip ar71xx_pci_irq_chip = { + .name = "AR71XX PCI ", + .mask = ar71xx_pci_irq_mask, + .unmask = ar71xx_pci_irq_unmask, + .mask_ack = ar71xx_pci_irq_mask, +}; + +static void __init ar71xx_pci_irq_init(void) +{ + int i; + + ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE, 0); + ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_STATUS, 0); + + for (i = AR71XX_PCI_IRQ_BASE; + i < AR71XX_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++) { + irq_desc[i].status = IRQ_DISABLED; + set_irq_chip_and_handler(i, &ar71xx_pci_irq_chip, + handle_level_irq); + } + + set_irq_chained_handler(AR71XX_CPU_IRQ_IP2, ar71xx_pci_irq_handler); +} + int __init ar71xx_pcibios_init(void) { ar71xx_device_stop(RESET_MODULE_PCI_BUS | RESET_MODULE_PCI_CORE); @@ -326,6 +394,7 @@ int __init ar71xx_pcibios_init(void) (void)ar71xx_pci_be_handler(1); ar71xx_pci_fixup_enable = 1; + ar71xx_pci_irq_init(); register_pci_controller(&ar71xx_pci_controller); return 0; diff --git a/target/linux/ar71xx/files/arch/mips/pci/pci-ar724x.c b/target/linux/ar71xx/files/arch/mips/pci/pci-ar724x.c index 5fcfc8738..617d1eb8b 100644 --- a/target/linux/ar71xx/files/arch/mips/pci/pci-ar724x.c +++ b/target/linux/ar71xx/files/arch/mips/pci/pci-ar724x.c @@ -1,7 +1,7 @@ /* * Atheros AR724x PCI host controller driver * - * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org> * * Parts of this file are based on Atheros' 2.6.15 BSP * @@ -16,6 +16,7 @@ #include <linux/bitops.h> #include <linux/pci.h> #include <linux/pci_regs.h> +#include <linux/interrupt.h> #include <asm/mach-ar71xx/ar71xx.h> #include <asm/mach-ar71xx/pci.h> @@ -246,6 +247,83 @@ static int __init ar724x_pci_setup(void) return 0; } +static void ar724x_pci_irq_handler(unsigned int irq, struct irq_desc *desc) +{ + u32 pending; + + pending = ar724x_pci_rr(AR724X_PCI_REG_INT_STATUS) & + ar724x_pci_rr(AR724X_PCI_REG_INT_MASK); + + if (pending & AR724X_PCI_INT_DEV0) + generic_handle_irq(AR71XX_PCI_IRQ_DEV0); + + else + spurious_interrupt(); +} + +static void ar724x_pci_irq_unmask(unsigned int irq) +{ + switch (irq) { + case AR71XX_PCI_IRQ_DEV0: + irq -= AR71XX_PCI_IRQ_BASE; + ar724x_pci_wr(AR724X_PCI_REG_INT_MASK, + ar724x_pci_rr(AR724X_PCI_REG_INT_MASK) | + AR724X_PCI_INT_DEV0); + /* flush write */ + ar724x_pci_rr(AR724X_PCI_REG_INT_MASK); + } +} + +static void ar724x_pci_irq_mask(unsigned int irq) +{ + switch (irq) { + case AR71XX_PCI_IRQ_DEV0: + irq -= AR71XX_PCI_IRQ_BASE; + ar724x_pci_wr(AR724X_PCI_REG_INT_MASK, + ar724x_pci_rr(AR724X_PCI_REG_INT_MASK) & + ~AR724X_PCI_INT_DEV0); + /* flush write */ + ar724x_pci_rr(AR724X_PCI_REG_INT_MASK); + + ar724x_pci_wr(AR724X_PCI_REG_INT_STATUS, + ar724x_pci_rr(AR724X_PCI_REG_INT_STATUS) | + AR724X_PCI_INT_DEV0); + /* flush write */ + ar724x_pci_rr(AR724X_PCI_REG_INT_STATUS); + } +} + +static struct irq_chip ar724x_pci_irq_chip = { + .name = "AR724X PCI ", + .mask = ar724x_pci_irq_mask, + .unmask = ar724x_pci_irq_unmask, + .mask_ack = ar724x_pci_irq_mask, +}; + +static void __init ar724x_pci_irq_init(void) +{ + u32 t; + int i; + + t = ar71xx_reset_rr(AR724X_RESET_REG_RESET_MODULE); + if (t & (AR724X_RESET_PCIE | AR724X_RESET_PCIE_PHY | + AR724X_RESET_PCIE_PHY_SERIAL)) { + return; + } + + ar724x_pci_wr(AR724X_PCI_REG_INT_MASK, 0); + ar724x_pci_wr(AR724X_PCI_REG_INT_STATUS, 0); + + for (i = AR71XX_PCI_IRQ_BASE; + i < AR71XX_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++) { + irq_desc[i].status = IRQ_DISABLED; + set_irq_chip_and_handler(i, &ar724x_pci_irq_chip, + handle_level_irq); + } + + set_irq_chained_handler(AR71XX_CPU_IRQ_IP2, ar724x_pci_irq_handler); +} + int __init ar724x_pcibios_init(void) { int ret; @@ -262,6 +340,7 @@ int __init ar724x_pcibios_init(void) return ret; ar724x_pci_fixup_enable = 1; + ar724x_pci_irq_init(); register_pci_controller(&ar724x_pci_controller); return 0; |