diff options
12 files changed, 3927 insertions, 18 deletions
diff --git a/package/mac80211/patches/830-b43-workaround-pcie-bcm4716.patch b/package/mac80211/patches/830-b43-workaround-pcie-bcm4716.patch new file mode 100644 index 000000000..834a253be --- /dev/null +++ b/package/mac80211/patches/830-b43-workaround-pcie-bcm4716.patch @@ -0,0 +1,133 @@ +From 8a0e33bd81eafd86252acf7d7ff1bd5362208d7a Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens <hauke@hauke-m.de> +Date: Sat, 21 Jan 2012 18:48:38 +0100 +Subject: [PATCH 33/34] b43: add workaround for b43 on pcie bus of bcm4716. + +bcm4716 (which includes 4717 & 4718), plus 4706 on PCIe can reorder +transactions. As a fix, a read after write is performed on certain +places in the code. Older chips and the newer 5357 family don't require +this fix. +This code is based on the brcmsmac driver. + +Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> +--- + drivers/net/wireless/b43/b43.h | 25 +++++++++++++++++++++++++ + drivers/net/wireless/b43/bus.h | 10 ++++++++++ + drivers/net/wireless/b43/phy_common.c | 6 ++++++ + drivers/net/wireless/b43/phy_n.c | 10 +++++----- + 4 files changed, 46 insertions(+), 5 deletions(-) + +--- a/drivers/net/wireless/b43/b43.h ++++ b/drivers/net/wireless/b43/b43.h +@@ -1016,6 +1016,31 @@ static inline bool b43_using_pio_transfe + return dev->__using_pio_transfers; + } + ++/* ++ * bcm4716 (which includes 4717 & 4718), plus 4706 on PCIe can reorder ++ * transactions. As a fix, a read after write is performed on certain places ++ * in the code. Older chips and the newer 5357 family don't require this fix. ++ */ ++#ifdef CONFIG_BCM47XX ++#include <asm/mach-bcm47xx/bcm47xx.h> ++static inline void b43_wflush16(struct b43_wldev *dev, u16 offset, u16 value) ++{ ++ if (b43_bus_host_is_pci(dev->dev) && ++ (bcm47xx_bus.bcma.bus.chipinfo.id == 0x4716 || ++ bcm47xx_bus.bcma.bus.chipinfo.id == 0x5300)) { ++ b43_write16(dev, offset, value); ++ b43_read16(dev, offset); ++ } else { ++ b43_write16(dev, offset, value); ++ } ++} ++#else ++static inline void b43_wflush16(struct b43_wldev *dev, u16 offset, u16 value) ++{ ++ b43_write16(dev, offset, value); ++} ++#endif ++ + /* Message printing */ + __printf(2, 3) void b43info(struct b43_wl *wl, const char *fmt, ...); + __printf(2, 3) void b43err(struct b43_wl *wl, const char *fmt, ...); +--- a/drivers/net/wireless/b43/bus.h ++++ b/drivers/net/wireless/b43/bus.h +@@ -60,6 +60,16 @@ static inline bool b43_bus_host_is_sdio( + return (dev->bus_type == B43_BUS_SSB && + dev->sdev->bus->bustype == SSB_BUSTYPE_SDIO); + } ++static inline bool b43_bus_host_is_pci(struct b43_bus_dev *dev) ++{ ++ if (dev->bus_type == B43_BUS_SSB) ++ return (dev->sdev->bus->bustype == SSB_BUSTYPE_PCI); ++#ifdef CONFIG_B43_BCMA ++ if (dev->bus_type == B43_BUS_BCMA) ++ return (dev->bdev->bus->hosttype == BCMA_HOSTTYPE_PCI); ++#endif ++ return false; ++} + + struct b43_bus_dev *b43_bus_dev_bcma_init(struct bcma_device *core); + struct b43_bus_dev *b43_bus_dev_ssb_init(struct ssb_device *sdev); +--- a/drivers/net/wireless/b43/phy_common.c ++++ b/drivers/net/wireless/b43/phy_common.c +@@ -251,6 +251,12 @@ void b43_phy_write(struct b43_wldev *dev + { + assert_mac_suspended(dev); + dev->phy.ops->phy_write(dev, reg, value); ++#ifdef CONFIG_BCM47XX ++ if (b43_bus_host_is_pci(dev->dev) && reg == 0x72) { ++ b43_read16(dev, B43_MMIO_PHY_VER); ++ return; ++ } ++#endif + if (++dev->phy.writes_counter == B43_MAX_WRITES_IN_ROW) { + b43_read16(dev, B43_MMIO_PHY_VER); + dev->phy.writes_counter = 0; +--- a/drivers/net/wireless/b43/phy_n.c ++++ b/drivers/net/wireless/b43/phy_n.c +@@ -4104,14 +4104,14 @@ static inline void check_phyreg(struct b + static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg) + { + check_phyreg(dev, reg); +- b43_write16(dev, B43_MMIO_PHY_CONTROL, reg); ++ b43_wflush16(dev, B43_MMIO_PHY_CONTROL, reg); + return b43_read16(dev, B43_MMIO_PHY_DATA); + } + + static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value) + { + check_phyreg(dev, reg); +- b43_write16(dev, B43_MMIO_PHY_CONTROL, reg); ++ b43_wflush16(dev, B43_MMIO_PHY_CONTROL, reg); + b43_write16(dev, B43_MMIO_PHY_DATA, value); + } + +@@ -4119,7 +4119,7 @@ static void b43_nphy_op_maskset(struct b + u16 set) + { + check_phyreg(dev, reg); +- b43_write16(dev, B43_MMIO_PHY_CONTROL, reg); ++ b43_wflush16(dev, B43_MMIO_PHY_CONTROL, reg); + b43_write16(dev, B43_MMIO_PHY_DATA, + (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set); + } +@@ -4131,7 +4131,7 @@ static u16 b43_nphy_op_radio_read(struct + /* N-PHY needs 0x100 for read access */ + reg |= 0x100; + +- b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg); ++ b43_wflush16(dev, B43_MMIO_RADIO_CONTROL, reg); + return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW); + } + +@@ -4140,7 +4140,7 @@ static void b43_nphy_op_radio_write(stru + /* Register 1 is a 32-bit register. */ + B43_WARN_ON(reg == 1); + +- b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg); ++ b43_wflush16(dev, B43_MMIO_RADIO_CONTROL, reg); + b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value); + } + diff --git a/target/linux/brcm47xx/patches-3.2/0000-pci-backport.patch b/target/linux/brcm47xx/patches-3.2/0000-pci-backport.patch new file mode 100644 index 000000000..5a6a9aeda --- /dev/null +++ b/target/linux/brcm47xx/patches-3.2/0000-pci-backport.patch @@ -0,0 +1,2210 @@ +--- a/Documentation/feature-removal-schedule.txt ++++ b/Documentation/feature-removal-schedule.txt +@@ -551,3 +551,15 @@ When: 3.5 + Why: The iwlagn module has been renamed iwlwifi. The alias will be around + for backward compatibility for several cycles and then dropped. + Who: Don Fry <donald.h.fry@intel.com> ++ ++---------------------------- ++ ++What: pci_scan_bus_parented() ++When: 3.5 ++Why: The pci_scan_bus_parented() interface creates a new root bus. The ++ bus is created with default resources (ioport_resource and ++ iomem_resource) that are always wrong, so we rely on arch code to ++ correct them later. Callers of pci_scan_bus_parented() should ++ convert to using pci_scan_root_bus() so they can supply a list of ++ bus resources when the bus is created. ++Who: Bjorn Helgaas <bhelgaas@google.com> +--- a/arch/alpha/kernel/pci.c ++++ b/arch/alpha/kernel/pci.c +@@ -281,27 +281,9 @@ pcibios_fixup_device_resources(struct pc + void __devinit + pcibios_fixup_bus(struct pci_bus *bus) + { +- /* Propagate hose info into the subordinate devices. */ +- +- struct pci_controller *hose = bus->sysdata; + struct pci_dev *dev = bus->self; + +- if (!dev) { +- /* Root bus. */ +- u32 pci_mem_end; +- u32 sg_base = hose->sg_pci ? hose->sg_pci->dma_base : ~0; +- unsigned long end; +- +- bus->resource[0] = hose->io_space; +- bus->resource[1] = hose->mem_space; +- +- /* Adjust hose mem_space limit to prevent PCI allocations +- in the iommu windows. */ +- pci_mem_end = min((u32)__direct_map_base, sg_base) - 1; +- end = hose->mem_space->start + pci_mem_end; +- if (hose->mem_space->end > end) +- hose->mem_space->end = end; +- } else if (pci_probe_only && ++ if (pci_probe_only && dev && + (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { + pci_read_bridge_bases(bus); + pcibios_fixup_device_resources(dev, bus); +@@ -414,13 +396,31 @@ void __init + common_init_pci(void) + { + struct pci_controller *hose; ++ struct list_head resources; + struct pci_bus *bus; + int next_busno; + int need_domain_info = 0; ++ u32 pci_mem_end; ++ u32 sg_base; ++ unsigned long end; + + /* Scan all of the recorded PCI controllers. */ + for (next_busno = 0, hose = hose_head; hose; hose = hose->next) { +- bus = pci_scan_bus(next_busno, alpha_mv.pci_ops, hose); ++ sg_base = hose->sg_pci ? hose->sg_pci->dma_base : ~0; ++ ++ /* Adjust hose mem_space limit to prevent PCI allocations ++ in the iommu windows. */ ++ pci_mem_end = min((u32)__direct_map_base, sg_base) - 1; ++ end = hose->mem_space->start + pci_mem_end; ++ if (hose->mem_space->end > end) ++ hose->mem_space->end = end; ++ ++ INIT_LIST_HEAD(&resources); ++ pci_add_resource(&resources, hose->io_space); ++ pci_add_resource(&resources, hose->mem_space); ++ ++ bus = pci_scan_root_bus(NULL, next_busno, alpha_mv.pci_ops, ++ hose, &resources); + hose->bus = bus; + hose->need_domain_info = need_domain_info; + next_busno = bus->subordinate + 1; +--- a/arch/arm/common/it8152.c ++++ b/arch/arm/common/it8152.c +@@ -299,8 +299,8 @@ int __init it8152_pci_setup(int nr, stru + goto err1; + } + +- sys->resource[0] = &it8152_io; +- sys->resource[1] = &it8152_mem; ++ pci_add_resource(&sys->resources, &it8152_io); ++ pci_add_resource(&sys->resources, &it8152_mem); + + if (platform_notify || platform_notify_remove) { + printk(KERN_ERR "PCI: Can't use platform_notify\n"); +@@ -352,7 +352,7 @@ void pcibios_set_master(struct pci_dev * + + struct pci_bus * __init it8152_pci_scan_bus(int nr, struct pci_sys_data *sys) + { +- return pci_scan_bus(nr, &it8152_ops, sys); ++ return pci_scan_root_bus(NULL, nr, &it8152_ops, sys, &sys->resources); + } + + EXPORT_SYMBOL(dma_set_coherent_mask); +--- a/arch/arm/common/via82c505.c ++++ b/arch/arm/common/via82c505.c +@@ -86,7 +86,8 @@ int __init via82c505_setup(int nr, struc + struct pci_bus * __init via82c505_scan_bus(int nr, struct pci_sys_data *sysdata) + { + if (nr == 0) +- return pci_scan_bus(0, &via82c505_ops, sysdata); ++ return pci_scan_root_bus(NULL, 0, &via82c505_ops, sysdata, ++ &sysdata->resources); + + return NULL; + } +--- a/arch/arm/include/asm/mach/pci.h ++++ b/arch/arm/include/asm/mach/pci.h +@@ -40,7 +40,7 @@ struct pci_sys_data { + u64 mem_offset; /* bus->cpu memory mapping offset */ + unsigned long io_offset; /* bus->cpu IO mapping offset */ + struct pci_bus *bus; /* PCI bus */ +- struct resource *resource[3]; /* Primary PCI bus resources */ ++ struct list_head resources; /* root bus resources (apertures) */ + /* Bridge swizzling */ + u8 (*swizzle)(struct pci_dev *, u8 *); + /* IRQ mapping */ +--- a/arch/arm/kernel/bios32.c ++++ b/arch/arm/kernel/bios32.c +@@ -316,21 +316,6 @@ pdev_fixup_device_resources(struct pci_s + } + } + +-static void __devinit +-pbus_assign_bus_resources(struct pci_bus *bus, struct pci_sys_data *root) +-{ +- struct pci_dev *dev = bus->self; +- int i; +- +- if (!dev) { +- /* +- * Assign root bus resources. +- */ +- for (i = 0; i < 3; i++) +- bus->resource[i] = root->resource[i]; +- } +-} +- + /* + * pcibios_fixup_bus - Called after each bus is probed, + * but before its children are examined. +@@ -341,8 +326,6 @@ void pcibios_fixup_bus(struct pci_bus *b + struct pci_dev *dev; + u16 features = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_FAST_BACK; + +- pbus_assign_bus_resources(bus, root); +- + /* + * Walk the devices on this bus, working out what we can + * and can't support. +@@ -508,12 +491,18 @@ static void __init pcibios_init_hw(struc + sys->busnr = busnr; + sys->swizzle = hw->swizzle; + sys->map_irq = hw->map_irq; +- sys->resource[0] = &ioport_resource; +- sys->resource[1] = &iomem_resource; ++ INIT_LIST_HEAD(&sys->resources); + + ret = hw->setup(nr, sys); + + if (ret > 0) { ++ if (list_empty(&sys->resources)) { ++ pci_add_resource(&sys->resources, ++ &ioport_resource); ++ pci_add_resource(&sys->resources, ++ &iomem_resource); ++ } ++ + sys->bus = hw->scan(nr, sys); + + if (!sys->bus) +--- a/arch/arm/mach-cns3xxx/pcie.c ++++ b/arch/arm/mach-cns3xxx/pcie.c +@@ -151,13 +151,12 @@ static int cns3xxx_pci_setup(int nr, str + struct cns3xxx_pcie *cnspci = sysdata_to_cnspci(sys); + struct resource *res_io = &cnspci->res_io; + struct resource *res_mem = &cnspci->res_mem; +- struct resource **sysres = sys->resource; + + BUG_ON(request_resource(&iomem_resource, res_io) || + request_resource(&iomem_resource, res_mem)); + +- sysres[0] = res_io; +- sysres[1] = res_mem; ++ pci_add_resource(&sys->resources, res_io); ++ pci_add_resource(&sys->resources, res_mem); + + return 1; + } +@@ -169,7 +168,8 @@ static struct pci_ops cns3xxx_pcie_ops = + + static struct pci_bus *cns3xxx_pci_scan_bus(int nr, struct pci_sys_data *sys) + { +- return pci_scan_bus(sys->busnr, &cns3xxx_pcie_ops, sys); ++ return pci_scan_root_bus(NULL, sys->busnr, &cns3xxx_pcie_ops, sys, ++ &sys->resources); + } + + static int cns3xxx_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +--- a/arch/arm/mach-dove/pcie.c ++++ b/arch/arm/mach-dove/pcie.c +@@ -69,7 +69,7 @@ static int __init dove_pcie_setup(int nr + pp->res[0].flags = IORESOURCE_IO; + if (request_resource(&ioport_resource, &pp->res[0])) + panic("Request PCIe IO resource failed\n"); +- sys->resource[0] = &pp->res[0]; ++ pci_add_resource(&sys->resources, &pp->res[0]); + + /* + * IORESOURCE_MEM +@@ -88,9 +88,7 @@ static int __init dove_pcie_setup(int nr + pp->res[1].flags = IORESOURCE_MEM; + if (request_resource(&iomem_resource, &pp->res[1])) + panic("Request PCIe Memory resource failed\n"); +- sys->resource[1] = &pp->res[1]; +- +- sys->resource[2] = NULL; ++ pci_add_resource(&sys->resources, &pp->res[1]); + + return 1; + } +@@ -184,7 +182,8 @@ dove_pcie_scan_bus(int nr, struct pci_sy + struct pci_bus *bus; + + if (nr < num_pcie_ports) { +- bus = pci_scan_bus(sys->busnr, &pcie_ops, sys); ++ bus = pci_scan_root_bus(NULL, sys->busnr, &pcie_ops, sys, ++ &sys->resources); + } else { + bus = NULL; + BUG(); +--- a/arch/arm/mach-footbridge/dc21285.c ++++ b/arch/arm/mach-footbridge/dc21285.c +@@ -275,9 +275,9 @@ int __init dc21285_setup(int nr, struct + allocate_resource(&iomem_resource, &res[0], 0x40000000, + 0x80000000, 0xffffffff, 0x40000000, NULL, NULL); + +- sys->resource[0] = &ioport_resource; +- sys->resource[1] = &res[0]; +- sys->resource[2] = &res[1]; ++ pci_add_resource(&sys->resources, &ioport_resource); ++ pci_add_resource(&sys->resources, &res[0]); ++ pci_add_resource(&sys->resources, &res[1]); + sys->mem_offset = DC21285_PCI_MEM; + + return 1; +@@ -285,7 +285,7 @@ int __init dc21285_setup(int nr, struct + + struct pci_bus * __init dc21285_scan_bus(int nr, struct pci_sys_data *sys) + { +- return pci_scan_bus(0, &dc21285_ops, sys); ++ return pci_scan_root_bus(NULL, 0, &dc21285_ops, sys, &sys->resources); + } + + #define dc21285_request_irq(_a, _b, _c, _d, _e) \ +--- a/arch/arm/mach-integrator/pci_v3.c ++++ b/arch/arm/mach-integrator/pci_v3.c +@@ -359,7 +359,7 @@ static struct resource pre_mem = { + .flags = IORESOURCE_MEM | IORESOURCE_PREFETCH, + }; + +-static int __init pci_v3_setup_resources(struct resource **resource) ++static int __init pci_v3_setup_resources(struct pci_sys_data *sys) + { + if (request_resource(&iomem_resource, &non_mem)) { + printk(KERN_ERR "PCI: unable to allocate non-prefetchable " +@@ -374,13 +374,13 @@ static int __init pci_v3_setup_resources + } + + /* +- * bus->resource[0] is the IO resource for this bus +- * bus->resource[1] is the mem resource for this bus +- * bus->resource[2] is the prefetch mem resource for this bus ++ * the IO resource for this bus ++ * the mem resource for this bus ++ * the prefetch mem resource for this bus + */ +- resource[0] = &ioport_resource; +- resource[1] = &non_mem; +- resource[2] = &pre_mem; ++ pci_add_resource(&sys->resources, &ioport_resource); ++ pci_add_resource(&sys->resources, &non_mem); ++ pci_add_resource(&sys->resources, &pre_mem); + + return 1; + } +@@ -481,7 +481,7 @@ int __init pci_v3_setup(int nr, struct p + + if (nr == 0) { + sys->mem_offset = PHYS_PCI_MEM_BASE; +- ret = pci_v3_setup_resources(sys->resource); ++ ret = pci_v3_setup_resources(sys); + } + + return ret; +@@ -489,7 +489,8 @@ int __init pci_v3_setup(int nr, struct p + + struct pci_bus * __init pci_v3_scan_bus(int nr, struct pci_sys_data *sys) + { +- return pci_scan_bus(sys->busnr, &pci_v3_ops, sys); ++ return pci_scan_root_bus(NULL, sys->busnr, &pci_v3_ops, sys, ++ &sys->resources); + } + + /* +--- a/arch/arm/mach-iop13xx/pci.c ++++ b/arch/arm/mach-iop13xx/pci.c +@@ -537,14 +537,14 @@ struct pci_bus *iop13xx_scan_bus(int nr, + while(time_before(jiffies, atux_trhfa_timeout)) + udelay(100); + +- bus = pci_bus_atux = pci_scan_bus(sys->busnr, +- &iop13xx_atux_ops, +- sys); ++ bus = pci_bus_atux = pci_scan_root_bus(NULL, sys->busnr, ++ &iop13xx_atux_ops, ++ sys, &sys->resources); + break; + case IOP13XX_INIT_ATU_ATUE: +- bus = pci_bus_atue = pci_scan_bus(sys->busnr, +- &iop13xx_atue_ops, +- sys); ++ bus = pci_bus_atue = pci_scan_root_bus(NULL, sys->busnr, ++ &iop13xx_atue_ops, ++ sys, &sys->resources); + break; + } + +@@ -1084,9 +1084,8 @@ int iop13xx_pci_setup(int nr, struct pci + request_resource(&ioport_resource, &res[0]); + request_resource(&iomem_resource, &res[1]); + +- sys->resource[0] = &res[0]; +- sys->resource[1] = &res[1]; +- sys->resource[2] = NULL; ++ pci_add_resource(&sys->resources, &res[0]); ++ pci_add_resource(&sys->resources, &res[1]); + + return 1; + } +--- a/arch/arm/mach-ixp2000/enp2611.c ++++ b/arch/arm/mach-ixp2000/enp2611.c +@@ -145,7 +145,8 @@ static struct pci_ops enp2611_pci_ops = + static struct pci_bus * __init enp2611_pci_scan_bus(int nr, + struct pci_sys_data *sys) + { +- return pci_scan_bus(sys->busnr, &enp2611_pci_ops, sys); ++ return pci_scan_root_bus(NULL, sys->busnr, &enp2611_pci_ops, sys, ++ &sys->resources); + } + + static int __init enp2611_pci_map_irq(const struct pci_dev *dev, u8 slot, +--- a/arch/arm/mach-ixp2000/pci.c ++++ b/arch/arm/mach-ixp2000/pci.c +@@ -132,7 +132,8 @@ static struct pci_ops ixp2000_pci_ops = + + struct pci_bus *ixp2000_pci_scan_bus(int nr, struct pci_sys_data *sysdata) + { +- return pci_scan_bus(sysdata->busnr, &ixp2000_pci_ops, sysdata); ++ return pci_scan_root_bus(NULL, sysdata->busnr, &ixp2000_pci_ops, ++ sysdata, &sysdata->resources); + } + + +@@ -242,9 +243,8 @@ int ixp2000_pci_setup(int nr, struct pci + if (nr >= 1) + return 0; + +- sys->resource[0] = &ixp2000_pci_io_space; +- sys->resource[1] = &ixp2000_pci_mem_space; +- sys->resource[2] = NULL; ++ pci_add_resource(&sys->resources, &ixp2000_pci_io_space); ++ pci_add_resource(&sys->resources, &ixp2000_pci_mem_space); + + return 1; + } +--- a/arch/arm/mach-ixp23xx/pci.c ++++ b/arch/arm/mach-ixp23xx/pci.c +@@ -143,7 +143,8 @@ struct pci_ops ixp23xx_pci_ops = { + + struct pci_bus *ixp23xx_pci_scan_bus(int nr, struct pci_sys_data *sysdata) + { +- return pci_scan_bus(sysdata->busnr, &ixp23xx_pci_ops, sysdata); ++ return pci_scan_root_bus(NULL, sysdata->busnr, &ixp23xx_pci_ops, ++ sysdata, &sysdata->resources); + } + + int ixp23xx_pci_abort_handler(unsigned long addr, unsigned int fsr, struct pt_regs *regs) +@@ -280,9 +281,8 @@ int ixp23xx_pci_setup(int nr, struct pci + if (nr >= 1) + return 0; + +- sys->resource[0] = &ixp23xx_pci_io_space; +- sys->resource[1] = &ixp23xx_pci_mem_space; +- sys->resource[2] = NULL; ++ pci_add_resource(&sys->resources, &ixp23xx_pci_io_space); ++ pci_add_resource(&sys->resources, &ixp23xx_pci_mem_space); + + return 1; + } +--- a/arch/arm/mach-ixp4xx/common-pci.c ++++ b/arch/arm/mach-ixp4xx/common-pci.c +@@ -472,9 +472,8 @@ int ixp4xx_setup(int nr, struct pci_sys_ + request_resource(&ioport_resource, &res[0]); + request_resource(&iomem_resource, &res[1]); + +- sys->resource[0] = &res[0]; +- sys->resource[1] = &res[1]; +- sys->resource[2] = NULL; ++ pci_add_resource(&sys->resources, &res[0]); ++ pci_add_resource(&sys->resources, &res[1]); + + platform_notify = ixp4xx_pci_platform_notify; + platform_notify_remove = ixp4xx_pci_platform_notify_remove; +@@ -484,7 +483,8 @@ int ixp4xx_setup(int nr, struct pci_sys_ + + struct pci_bus * __devinit ixp4xx_scan_bus(int nr, struct pci_sys_data *sys) + { +- return pci_scan_bus(sys->busnr, &ixp4xx_ops, sys); ++ return pci_scan_root_bus(NULL, sys->busnr, &ixp4xx_ops, sys, ++ &sys->resources); + } + + int dma_set_coherent_mask(struct device *dev, u64 mask) +--- a/arch/arm/mach-kirkwood/pcie.c ++++ b/arch/arm/mach-kirkwood/pcie.c +@@ -198,9 +198,8 @@ static int __init kirkwood_pcie_setup(in + if (request_resource(&iomem_resource, &pp->res[1])) + panic("Request PCIe%d Memory resource failed\n", index); + +- sys->resource[0] = &pp->res[0]; +- sys->resource[1] = &pp->res[1]; +- sys->resource[2] = NULL; ++ pci_add_resource(&sys->resources, &pp->res[0]); ++ pci_add_resource(&sys->resources, &pp->res[1]); + sys->io_offset = 0; + + /* +@@ -236,7 +235,8 @@ kirkwood_pcie_scan_bus(int nr, struct pc + struct pci_bus *bus; + + if (nr < num_pcie_ports) { +- bus = pci_scan_bus(sys->busnr, &pcie_ops, sys); ++ bus = pci_scan_root_bus(NULL, sys->busnr, &pcie_ops, sys, ++ &sys->resources); + } else { + bus = NULL; + BUG(); +--- a/arch/arm/mach-ks8695/pci.c ++++ b/arch/arm/mach-ks8695/pci.c +@@ -143,7 +143,8 @@ static struct pci_ops ks8695_pci_ops = { + + static struct pci_bus* __init ks8695_pci_scan_bus(int nr, struct pci_sys_data *sys) + { +- return pci_scan_bus(sys->busnr, &ks8695_pci_ops, sys); ++ return pci_scan_root_bus(NULL, sys->busnr, &ks8695_pci_ops, sys, ++ &sys->resources); + } + + static struct resource pci_mem = { +@@ -168,9 +169,8 @@ static int __init ks8695_pci_setup(int n + request_resource(&iomem_resource, &pci_mem); + request_resource(&ioport_resource, &pci_io); + +- sys->resource[0] = &pci_io; +- sys->resource[1] = &pci_mem; +- sys->resource[2] = NULL; ++ pci_add_resource(&sys->resources, &pci_io); ++ pci_add_resource(&sys->resources, &pci_mem); + + /* Assign and enable processor bridge */ + ks8695_local_writeconfig(PCI_BASE_ADDRESS_0, KS8695_PCIMEM_PA); +--- a/arch/arm/mach-mv78xx0/pcie.c ++++ b/arch/arm/mach-mv78xx0/pcie.c +@@ -155,9 +155,8 @@ static int __init mv78xx0_pcie_setup(int + orion_pcie_set_local_bus_nr(pp->base, sys->busnr); + orion_pcie_setup(pp->base, &mv78xx0_mbus_dram_info); + +- sys->resource[0] = &pp->res[0]; +- sys->resource[1] = &pp->res[1]; +- sys->resource[2] = NULL; ++ pci_add_resource(&sys->resources, &pp->res[0]); ++ pci_add_resource(&sys->resources, &pp->res[1]); + + return 1; + } +@@ -251,7 +250,8 @@ mv78xx0_pcie_scan_bus(int nr, struct pci + struct pci_bus *bus; + + if (nr < num_pcie_ports) { +- bus = pci_scan_bus(sys->busnr, &pcie_ops, sys); ++ bus = pci_scan_root_bus(NULL, sys->busnr, &pcie_ops, sys, ++ &sys->resources); + } else { + bus = NULL; + BUG(); +--- a/arch/arm/mach-orion5x/pci.c ++++ b/arch/arm/mach-orion5x/pci.c +@@ -176,7 +176,7 @@ static int __init pcie_setup(struct pci_ + res[0].end = res[0].start + ORION5X_PCIE_IO_SIZE - 1; + if (request_resource(&ioport_resource, &res[0])) + panic("Request PCIe IO resource failed\n"); +- sys->resource[0] = &res[0]; ++ pci_add_resource(&sys->resources, &res[0]); + + /* + * IORESOURCE_MEM +@@ -187,9 +187,8 @@ static int __init pcie_setup(struct pci_ + res[1].end = res[1].start + ORION5X_PCIE_MEM_SIZE - 1; + if (request_resource(&iomem_resource, &res[1])) + panic("Request PCIe Memory resource failed\n"); +- sys->resource[1] = &res[1]; ++ pci_add_resource(&sys->resources, &res[1]); + +- sys->resource[2] = NULL; + sys->io_offset = 0; + + return 1; +@@ -505,7 +504,7 @@ static int __init pci_setup(struct pci_s + res[0].end = res[0].start + ORION5X_PCI_IO_SIZE - 1; + if (request_resource(&ioport_resource, &res[0])) + panic("Request PCI IO resource failed\n"); +- sys->resource[0] = &res[0]; ++ pci_add_resource(&sys->resources, &res[0]); + + /* + * IORESOURCE_MEM +@@ -516,9 +515,8 @@ static int __init pci_setup(struct pci_s + res[1].end = res[1].start + ORION5X_PCI_MEM_SIZE - 1; + if (request_resource(&iomem_resource, &res[1])) + panic("Request PCI Memory resource failed\n"); +- sys->resource[1] = &res[1]; ++ pci_add_resource(&sys->resources, &res[1]); + +- sys->resource[2] = NULL; + sys->io_offset = 0; + + return 1; +@@ -579,9 +577,11 @@ struct pci_bus __init *orion5x_pci_sys_s + struct pci_bus *bus; + + if (nr == 0) { +- bus = pci_scan_bus(sys->busnr, &pcie_ops, sys); ++ bus = pci_scan_root_bus(NULL, sys->busnr, &pcie_ops, sys, ++ &sys->resources); + } else if (nr == 1 && !orion5x_pci_disabled) { +- bus = pci_scan_bus(sys->busnr, &pci_ops, sys); ++ bus = pci_scan_root_bus(NULL, sys->busnr, &pci_ops, sys, ++ &sys->resources); + } else { + bus = NULL; + BUG(); +--- a/arch/arm/mach-sa1100/pci-nanoengine.c ++++ b/arch/arm/mach-sa1100/pci-nanoengine.c +@@ -131,7 +131,8 @@ static int __init pci_nanoengine_map_irq + + struct pci_bus * __init pci_nanoengine_scan_bus(int nr, struct pci_sys_data *sys) + { +- return pci_scan_bus(sys->busnr, &pci_nano_ops, sys); ++ return pci_scan_root_bus(NULL, sys->busnr, &pci_nano_ops, sys, ++ &sys->resources); + } + + static struct resource pci_io_ports = { +@@ -226,7 +227,7 @@ static struct resource pci_prefetchable_ + .flags = IORESOURCE_MEM | IORESOURCE_PREFETCH, + }; + +-static int __init pci_nanoengine_setup_resources(struct resource **resource) ++static int __init pci_nanoengine_setup_resources(struct pci_sys_data *sys) + { + if (request_resource(&ioport_resource, &pci_io_ports)) { + printk(KERN_ERR "PCI: unable to allocate io port region\n"); +@@ -243,9 +244,9 @@ static int __init pci_nanoengine_setup_r + printk(KERN_ERR "PCI: unable to allocate prefetchable\n"); + return -EBUSY; + } +- resource[0] = &pci_io_ports; +- resource[1] = &pci_non_prefetchable_memory; +- resource[2] = &pci_prefetchable_memory; ++ pci_add_resource(&sys->resources, &pci_io_ports); ++ pci_add_resource(&sys->resources, &pci_non_prefetchable_memory); ++ pci_add_resource(&sys->resources, &pci_prefetchable_memory); + + return 1; + } +@@ -260,7 +261,7 @@ int __init pci_nanoengine_setup(int nr, + if (nr == 0) { + sys->mem_offset = NANO_PCI_MEM_RW_PHYS; + sys->io_offset = 0x400; +- ret = pci_nanoengine_setup_resources(sys->resource); ++ ret = pci_nanoengine_setup_resources(sys); + /* Enable alternate memory bus master mode, see + * "Intel StrongARM SA1110 Developer's Manual", + * section 10.8, "Alternate Memory Bus Master Mode". */ +--- a/arch/arm/mach-tegra/pcie.c ++++ b/arch/arm/mach-tegra/pcie.c +@@ -409,7 +409,7 @@ static int tegra_pcie_setup(int nr, stru + pp->res[0].flags = IORESOURCE_IO; + if (request_resource(&ioport_resource, &pp->res[0])) + panic("Request PCIe IO resource failed\n"); +- sys->resource[0] = &pp->res[0]; ++ pci_add_resource(&sys->resources, &pp->res[0]); + + /* + * IORESOURCE_MEM +@@ -428,7 +428,7 @@ static int tegra_pcie_setup(int nr, stru + pp->res[1].flags = IORESOURCE_MEM; + if (request_resource(&iomem_resource, &pp->res[1])) + panic("Request PCIe Memory resource failed\n"); +- sys->resource[1] = &pp->res[1]; ++ pci_add_resource(&sys->resources, &pp->res[1]); + + /* + * IORESOURCE_MEM | IORESOURCE_PREFETCH +@@ -447,7 +447,7 @@ static int tegra_pcie_setup(int nr, stru + pp->res[2].flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; + if (request_resource(&iomem_resource, &pp->res[2])) + panic("Request PCIe Prefetch Memory resource failed\n"); +- sys->resource[2] = &pp->res[2]; ++ pci_add_resource(&sys->resources, &pp->res[2]); + + return 1; + } +@@ -468,7 +468,8 @@ static struct pci_bus __init *tegra_pcie + pp = tegra_pcie.port + nr; + pp->root_bus_nr = sys->busnr; + +- return pci_scan_bus(sys->busnr, &tegra_pcie_ops, sys); ++ return pci_scan_root_bus(NULL, sys->busnr, &tegra_pcie_ops, sys, ++ &sys->resources); + } + + static struct hw_pci tegra_pcie_hw __initdata = { +--- a/arch/arm/mach-versatile/pci.c ++++ b/arch/arm/mach-versatile/pci.c +@@ -191,7 +191,7 @@ static struct resource pre_mem = { + .flags = IORESOURCE_MEM | IORESOURCE_PREFETCH, + }; + +-static int __init pci_versatile_setup_resources(struct resource **resource) ++static int __init pci_versatile_setup_resources(struct list_head *resources) + { + int ret = 0; + +@@ -215,13 +215,13 @@ static int __init pci_versatile_setup_re + } + + /* +- * bus->resource[0] is the IO resource for this bus +- * bus->resource[1] is the mem resource for this bus +- * bus->resource[2] is the prefetch mem resource for this bus ++ * the IO resource for this bus ++ * the mem resource for this bus ++ * the prefetch mem resource for this bus + */ +- resource[0] = &io_mem; +- resource[1] = &non_mem; +- resource[2] = &pre_mem; ++ pci_add_resource(resources, &io_mem); ++ pci_add_resource(resources, &non_mem); ++ pci_add_resource(resources, &pre_mem); + + goto out; + +@@ -250,7 +250,7 @@ int __init pci_versatile_setup(int nr, s + + if (nr == 0) { + sys->mem_offset = 0; +- ret = pci_versatile_setup_resources(sys->resource); ++ ret = pci_versatile_setup_resources(&sys->resources); + if (ret < 0) { + printk("pci_versatile_setup: resources... oops?\n"); + goto out; +@@ -306,7 +306,8 @@ int __init pci_versatile_setup(int nr, s + + struct pci_bus * __init pci_versatile_scan_bus(int nr, struct pci_sys_data *sys) + { +- return pci_scan_bus(sys->busnr, &pci_versatile_ops, sys); ++ return pci_scan_root_bus(NULL, sys->busnr, &pci_versatile_ops, sys, ++ &sys->resources); + } + + void __init pci_versatile_preinit(void) +--- a/arch/arm/plat-iop/pci.c ++++ b/arch/arm/plat-iop/pci.c +@@ -215,16 +215,16 @@ int iop3xx_pci_setup(int nr, struct pci_ + sys->mem_offset = IOP3XX_PCI_LOWER_MEM_PA - *IOP3XX_OMWTVR0; + sys->io_offset = IOP3XX_PCI_LOWER_IO_PA - *IOP3XX_OIOWTVR; + +- sys->resource[0] = &res[0]; +- sys->resource[1] = &res[1]; +- sys->resource[2] = NULL; ++ pci_add_resource(&sys->resources, &res[0]); ++ pci_add_resource(&sys->resources, &res[1]); + + return 1; + } + + struct pci_bus *iop3xx_pci_scan_bus(int nr, struct pci_sys_data *sys) + { +- return pci_scan_bus(sys->busnr, &iop3xx_ops, sys); ++ return pci_scan_root_bus(NULL, sys->busnr, &iop3xx_ops, sys, ++ &sys->resources); + } + + void __init iop3xx_atu_setup(void) +--- a/arch/frv/mb93090-mb00/pci-vdk.c ++++ b/arch/frv/mb93090-mb00/pci-vdk.c +@@ -327,11 +327,6 @@ void __init pcibios_fixup_bus(struct pci + printk("### PCIBIOS_FIXUP_BUS(%d)\n",bus->number); + #endif + +- if (bus->number == 0) { +- bus->resource[0] = &pci_ioport_resource; +- bus->resource[1] = &pci_iomem_resource; +- } +- + pci_read_bridge_bases(bus); + + if (bus->number == 0) { +@@ -357,6 +352,7 @@ void __init pcibios_fixup_bus(struct pci + int __init pcibios_init(void) + { + struct pci_ops *dir = NULL; ++ LIST_HEAD(resources); + + if (!mb93090_mb00_detected) + return -ENXIO; +@@ -420,7 +416,10 @@ int __init pcibios_init(void) + } + + printk("PCI: Probing PCI hardware\n"); +- pci_root_bus = pci_scan_bus(0, pci_root_ops, NULL); ++ pci_add_resource(&resources, &pci_ioport_resource); ++ pci_add_resource(&resources, &pci_iomem_resource); ++ pci_root_bus = pci_scan_root_bus(NULL, 0, pci_root_ops, NULL, ++ &resources); + + pcibios_irq_init(); + pcibios_fixup_peer_bridges(); +--- a/arch/ia64/pci/pci.c ++++ b/arch/ia64/pci/pci.c +@@ -134,6 +134,7 @@ alloc_pci_controller (int seg) + struct pci_root_info { + struct acpi_device *bridge; + struct pci_controller *controller; ++ struct list_head resources; + char *name; + }; + +@@ -315,24 +316,13 @@ static __devinit acpi_status add_window( + &window->resource); + } + +- return AE_OK; +-} ++ /* HP's firmware has a hack to work around a Windows bug. ++ * Ignore these tiny memory ranges */ ++ if (!((window->resource.flags & IORESOURCE_MEM) && ++ (window->resource.end - window->resource.start < 16))) ++ pci_add_resource(&info->resources, &window->resource); + +-static void __devinit +-pcibios_setup_root_windows(struct pci_bus *bus, struct pci_controller *ctrl) +-{ +- int i; +- +- pci_bus_remove_resources(bus); +- for (i = 0; i < ctrl->windows; i++) { +- struct resource *res = &ctrl->window[i].resource; +- /* HP's firmware has a hack to work around a Windows bug. +- * Ignore these tiny memory ranges */ +- if ((res->flags & IORESOURCE_MEM) && +- (res->end - res->start < 16)) +- continue; +- pci_bus_add_resource(bus, res, 0); +- } ++ return AE_OK; + } + + struct pci_bus * __devinit +@@ -343,6 +333,7 @@ pci_acpi_scan_root(struct acpi_pci_root + int bus = root->secondary.start; + struct pci_controller *controller; + unsigned int windows = 0; ++ struct pci_root_info info; + struct pci_bus *pbus; + char *name; + int pxm; +@@ -359,11 +350,10 @@ pci_acpi_scan_root(struct acpi_pci_root + controller->node = pxm_to_node(pxm); + #endif + ++ INIT_LIST_HEAD(&info.resources); + acpi_walk_resources(device->handle, METHOD_NAME__CRS, count_window, + &windows); + if (windows) { +- struct pci_root_info info; +- + controller->window = + kmalloc_node(sizeof(*controller->window) * windows, + GFP_KERNEL, controller->node); +@@ -387,8 +377,14 @@ pci_acpi_scan_root(struct acpi_pci_root + * should handle the case here, but it appears that IA64 hasn't + * such quirk. So we just ignore the case now. + */ +- pbus = pci_scan_bus_parented(NULL, bus, &pci_root_ops, controller); ++ pbus = pci_create_root_bus(NULL, bus, &pci_root_ops, controller, ++ &info.resources); ++ if (!pbus) { ++ pci_free_resource_list(&info.resources); ++ return NULL; ++ } + ++ pbus->subordinate = pci_scan_child_bus(pbus); + return pbus; + + out3: +@@ -504,14 +500,10 @@ pcibios_fixup_bus (struct pci_bus *b) + if (b->self) { + pci_read_bridge_bases(b); + pcibios_fixup_bridge_resources(b->self); +- } else { +- pcibios_setup_root_windows(b, b->sysdata); + } + list_for_each_entry(dev, &b->devices, bus_list) + pcibios_fixup_device_resources(dev); + platform_pci_fixup_bus(b); +- +- return; + } + + void __devinit +--- a/arch/microblaze/include/asm/pci-bridge.h ++++ b/arch/microblaze/include/asm/pci-bridge.h +@@ -140,7 +140,6 @@ extern void pci_process_bridge_OF_ranges + /* Allocate & free a PCI host bridge structure */ + extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev); + extern void pcibios_free_controller(struct pci_controller *phb); +-extern void pcibios_setup_phb_resources(struct pci_controller *hose); + + #endif /* __KERNEL__ */ + #endif /* _ASM_MICROBLAZE_PCI_BRIDGE_H */ +--- a/arch/microblaze/pci/pci-common.c ++++ b/arch/microblaze/pci/pci-common.c +@@ -1019,7 +1019,6 @@ static void __devinit pcibios_fixup_brid + struct pci_dev *dev = bus->self; + + pci_bus_for_each_resource(bus, res, i) { +- res = bus->resource[i]; + if (!res) + continue; + if (!res->flags) +@@ -1219,7 +1218,6 @@ void pcibios_allocate_bus_resources(stru + pci_domain_nr(bus), bus->number); + + pci_bus_for_each_resource(bus, res, i) { +- res = bus->resource[i]; + if (!res || !res->flags + || res->start > res->end || res->parent) + continue; +@@ -1510,14 +1508,18 @@ int pcibios_enable_device(struct pci_dev + return pci_enable_resources(dev, mask); + } + +-void __devinit pcibios_setup_phb_resources(struct pci_controller *hose) ++static void __devinit pcibios_setup_phb_resources(struct pci_controller *hose, struct list_head *resources) + { +- struct pci_bus *bus = hose->bus; + struct resource *res; + int i; + + /* Hookup PHB IO resource */ +- bus->resource[0] = res = &hose->io_resource; ++ res = &hose->io_resource; ++ ++ /* Fixup IO space offset */ ++ io_offset = (unsigned long)hose->io_base_virt - isa_io_base; ++ res->start = (res->start + io_offset) & 0xffffffffu; ++ res->end = (res->end + io_offset) & 0xffffffffu; + + if (!res->flags) { + printk(KERN_WARNING "PCI: I/O resource not set for host" +@@ -1528,6 +1530,7 @@ void __devinit pcibios_setup_phb_resourc + res->end = res->start + IO_SPACE_LIMIT; + res->flags = IORESOURCE_IO; + } ++ pci_add_resource(resources, res); + + pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n", + (unsigned long long)res->start, +@@ -1550,7 +1553,7 @@ void __devinit pcibios_setup_phb_resourc + res->flags = IORESOURCE_MEM; + + } +- bus->resource[i+1] = res; ++ pci_add_resource(resources, res); + + pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n", + i, (unsigned long long)res->start, +@@ -1573,34 +1576,27 @@ struct device_node *pcibios_get_phb_of_n + + static void __devinit pcibios_scan_phb(struct pci_controller *hose) + { ++ LIST_HEAD(resources); + struct pci_bus *bus; + struct device_node *node = hose->dn; +- unsigned long io_offset; +- struct resource *res = &hose->io_resource; + + pr_debug("PCI: Scanning PHB %s\n", + node ? node->full_name : "<NO NAME>"); + +- /* Create an empty bus for the toplevel */ +- bus = pci_create_bus(hose->parent, hose->first_busno, hose->ops, hose); ++ pcibios_setup_phb_resources(hose, &resources); ++ ++ bus = pci_scan_root_bus(hose->parent, hose->first_busno, ++ hose->ops, hose, &resources); + if (bus == NULL) { + printk(KERN_ERR "Failed to create bus for PCI domain %04x\n", + hose->global_number); ++ pci_free_resource_list(&resources); + return; + } + bus->secondary = hose->first_busno; + hose->bus = bus; + +- /* Fixup IO space offset */ +- io_offset = (unsigned long)hose->io_base_virt - isa_io_base; +- res->start = (res->start + io_offset) & 0xffffffffu; +- res->end = (res->end + io_offset) & 0xffffffffu; +- +- /* Wire up PHB bus resources */ +- pcibios_setup_phb_resources(hose); +- +- /* Scan children */ +- hose->last_busno = bus->subordinate = pci_scan_child_bus(bus); ++ hose->last_busno = bus->subordinate; + } + + static int __init pcibios_init(void) +@@ -1614,8 +1610,6 @@ static int __init pcibios_init(void) + list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { + hose->last_busno = 0xff; + pcibios_scan_phb(hose); +- printk(KERN_INFO "calling pci_bus_add_devices()\n"); +- pci_bus_add_devices(hose->bus); + if (next_busno <= hose->last_busno) + next_busno = hose->last_busno + 1; + } +--- a/arch/mips/pci/pci.c ++++ b/arch/mips/pci/pci.c +@@ -81,6 +81,7 @@ static void __devinit pcibios_scanbus(st + { + static int next_busno; + static int need_domain_info; ++ LIST_HEAD(resources); + struct pci_bus *bus; + + if (!hose->iommu) +@@ -89,7 +90,13 @@ static void __devinit pcibios_scanbus(st + if (hose->get_busno && pci_probe_only) + next_busno = (*hose->get_busno)(); + +- bus = pci_scan_bus(next_busno, hose->pci_ops, hose); ++ pci_add_resource(&resources, hose->mem_resource); ++ pci_add_resource(&resources, hose->io_resource); ++ bus = pci_scan_root_bus(NULL, next_busno, hose->pci_ops, hose, ++ &resources); ++ if (!bus) ++ pci_free_resource_list(&resources); ++ + hose->bus = bus; + + need_domain_info = need_domain_info || hose->index; +@@ -266,15 +273,11 @@ void __devinit pcibios_fixup_bus(struct + { + /* Propagate hose info into the subordinate devices. */ + +- struct pci_controller *hose = bus->sysdata; + struct list_head *ln; + struct pci_dev *dev = bus->self; + +- if (!dev) { +- bus->resource[0] = hose->io_resource; +- bus->resource[1] = hose->mem_resource; +- } else if (pci_probe_only && +- (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { ++ if (pci_probe_only && dev && ++ (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { + pci_read_bridge_bases(bus); + pcibios_fixup_device_resources(dev, bus); + } +--- a/arch/mn10300/unit-asb2305/pci.c ++++ b/arch/mn10300/unit-asb2305/pci.c +@@ -380,11 +380,6 @@ void __devinit pcibios_fixup_bus(struct + { + struct pci_dev *dev; + +- if (bus->number == 0) { +- bus->resource[0] = &pci_ioport_resource; +- bus->resource[1] = &pci_iomem_resource; +- } +- + if (bus->self) { + pci_read_bridge_bases(bus); + pcibios_fixup_device_resources(bus->self); +@@ -402,6 +397,8 @@ void __devinit pcibios_fixup_bus(struct + */ + static int __init pcibios_init(void) + { ++ LIST_HEAD(resources); ++ + ioport_resource.start = 0xA0000000; + ioport_resource.end = 0xDFFFFFFF; + iomem_resource.start = 0xA0000000; +@@ -423,7 +420,10 @@ static int __init pcibios_init(void) + printk(KERN_INFO "PCI: Probing PCI hardware [mempage %08x]\n", + MEM_PAGING_REG); + +- pci_root_bus = pci_scan_bus(0, &pci_direct_ampci, NULL); ++ pci_add_resource(&resources, &pci_ioport_resource); ++ pci_add_resource(&resources, &pci_iomem_resource); ++ pci_root_bus = pci_scan_root_bus(NULL, 0, &pci_direct_ampci, NULL, ++ &resources); + + pcibios_irq_init(); + pcibios_fixup_irqs(); +--- a/arch/powerpc/include/asm/pci-bridge.h ++++ b/arch/powerpc/include/asm/pci-bridge.h +@@ -222,7 +222,6 @@ extern void pci_process_bridge_OF_ranges + /* Allocate & free a PCI host bridge structure */ + extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev); + extern void pcibios_free_controller(struct pci_controller *phb); +-extern void pcibios_setup_phb_resources(struct pci_controller *hose); + + #ifdef CONFIG_PCI + extern int pcibios_vaddr_is_ioport(void __iomem *address); +--- a/arch/powerpc/kernel/pci-common.c ++++ b/arch/powerpc/kernel/pci-common.c +@@ -1555,14 +1555,13 @@ int pcibios_enable_device(struct pci_dev + return pci_enable_resources(dev, mask); + } + +-void __devinit pcibios_setup_phb_resources(struct pci_controller *hose) ++static void __devinit pcibios_setup_phb_resources(struct pci_controller *hose, struct list_head *resources) + { +- struct pci_bus *bus = hose->bus; + struct resource *res; + int i; + + /* Hookup PHB IO resource */ +- bus->resource[0] = res = &hose->io_resource; ++ res = &hose->io_resource; + + if (!res->flags) { + printk(KERN_WARNING "PCI: I/O resource not set for host" +@@ -1580,6 +1579,7 @@ void __devinit pcibios_setup_phb_resourc + (unsigned long long)res->start, + (unsigned long long)res->end, + (unsigned long)res->flags); ++ pci_add_resource(resources, res); + + /* Hookup PHB Memory resources */ + for (i = 0; i < 3; ++i) { +@@ -1597,12 +1597,12 @@ void __devinit pcibios_setup_phb_resourc + res->flags = IORESOURCE_MEM; + #endif /* CONFIG_PPC32 */ + } +- bus->resource[i+1] = res; + + pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n", i, + (unsigned long long)res->start, + (unsigned long long)res->end, + (unsigned long)res->flags); ++ pci_add_resource(resources, res); + } + + pr_debug("PCI: PHB MEM offset = %016llx\n", +@@ -1696,6 +1696,7 @@ struct device_node *pcibios_get_phb_of_n + */ + void __devinit pcibios_scan_phb(struct pci_controller *hose) + { ++ LIST_HEAD(resources); + struct pci_bus *bus; + struct device_node *node = hose->dn; + int mode; +@@ -1703,22 +1704,24 @@ void __devinit pcibios_scan_phb(struct p + pr_debug("PCI: Scanning PHB %s\n", + node ? node->full_name : "<NO NAME>"); + ++ /* Get some IO space for the new PHB */ ++ pcibios_setup_phb_io_space(hose); ++ ++ /* Wire up PHB bus resources */ ++ pcibios_setup_phb_resources(hose, &resources); ++ + /* Create an empty bus for the toplevel */ +- bus = pci_create_bus(hose->parent, hose->first_busno, hose->ops, hose); ++ bus = pci_create_root_bus(hose->parent, hose->first_busno, ++ hose->ops, hose, &resources); + if (bus == NULL) { + pr_err("Failed to create bus for PCI domain %04x\n", + hose->global_number); ++ pci_free_resource_list(&resources); + return; + } + bus->secondary = hose->first_busno; + hose->bus = bus; + +- /* Get some IO space for the new PHB */ +- pcibios_setup_phb_io_space(hose); +- +- /* Wire up PHB bus resources */ +- pcibios_setup_phb_resources(hose); +- + /* Get probe mode and perform scan */ + mode = PCI_PROBE_NORMAL; + if (node && ppc_md.pci_probe_mode) +--- a/arch/powerpc/kernel/pci_64.c ++++ b/arch/powerpc/kernel/pci_64.c +@@ -131,30 +131,13 @@ EXPORT_SYMBOL_GPL(pcibios_unmap_io_space + + #endif /* CONFIG_HOTPLUG */ + +-int __devinit pcibios_map_io_space(struct pci_bus *bus) ++static int __devinit pcibios_map_phb_io_space(struct pci_controller *hose) + { + struct vm_struct *area; + unsigned long phys_page; + unsigned long size_page; + unsigned long io_virt_offset; +- struct pci_controller *hose; +- +- WARN_ON(bus == NULL); + +- /* If this not a PHB, nothing to do, page tables still exist and +- * thus HPTEs will be faulted in when needed +- */ +- if (bus->self) { +- pr_debug("IO mapping for PCI-PCI bridge %s\n", +- pci_name(bus->self)); +- pr_debug(" virt=0x%016llx...0x%016llx\n", +- bus->resource[0]->start + _IO_BASE, +- bus->resource[0]->end + _IO_BASE); +- return 0; +- } +- +- /* Get the host bridge */ +- hose = pci_bus_to_host(bus); + phys_page = _ALIGN_DOWN(hose->io_base_phys, PAGE_SIZE); + size_page = _ALIGN_UP(hose->pci_io_size, PAGE_SIZE); + +@@ -198,11 +181,30 @@ int __devinit pcibios_map_io_space(struc + + return 0; + } ++ ++int __devinit pcibios_map_io_space(struct pci_bus *bus) ++{ ++ WARN_ON(bus == NULL); ++ ++ /* If this not a PHB, nothing to do, page tables still exist and ++ * thus HPTEs will be faulted in when needed ++ */ ++ if (bus->self) { ++ pr_debug("IO mapping for PCI-PCI bridge %s\n", ++ pci_name(bus->self)); ++ pr_debug(" virt=0x%016llx...0x%016llx\n", ++ bus->resource[0]->start + _IO_BASE, ++ bus->resource[0]->end + _IO_BASE); ++ return 0; ++ } ++ ++ return pcibios_map_phb_io_space(pci_bus_to_host(bus)); ++} + EXPORT_SYMBOL_GPL(pcibios_map_io_space); + + void __devinit pcibios_setup_phb_io_space(struct pci_controller *hose) + { +- pcibios_map_io_space(hose->bus); ++ pcibios_map_phb_io_space(hose); + } + + #define IOBASE_BRIDGE_NUMBER 0 +--- a/arch/sh/drivers/pci/pci.c ++++ b/arch/sh/drivers/pci/pci.c +@@ -36,9 +36,15 @@ static void __devinit pcibios_scanbus(st + { + static int next_busno; + static int need_domain_info; ++ LIST_HEAD(resources); ++ int i; + struct pci_bus *bus; + +- bus = pci_scan_bus(next_busno, hose->pci_ops, hose); ++ for (i = 0; i < hose->nr_resources; i++) ++ pci_add_resource(&resources, hose->resources + i); ++ ++ bus = pci_scan_root_bus(NULL, next_busno, hose->pci_ops, hose, ++ &resources); + hose->bus = bus; + + need_domain_info = need_domain_info || hose->index; +@@ -55,6 +61,8 @@ static void __devinit pcibios_scanbus(st + pci_bus_size_bridges(bus); + pci_bus_assign_resources(bus); + pci_enable_bridges(bus); ++ } else { ++ pci_free_resource_list(&resources); + } + } + +@@ -162,16 +170,8 @@ static void pcibios_fixup_device_resourc + */ + void __devinit pcibios_fixup_bus(struct pci_bus *bus) + { +- struct pci_dev *dev = bus->self; ++ struct pci_dev *dev; + struct list_head *ln; +- struct pci_channel *hose = bus->sysdata; +- +- if (!dev) { +- int i; +- +- for (i = 0; i < hose->nr_resources; i++) +- bus->resource[i] = hose->resources + i; +- } + + for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) { + dev = pci_dev_b(ln); +--- a/arch/sparc/kernel/leon_pci.c ++++ b/arch/sparc/kernel/leon_pci.c +@@ -19,22 +19,22 @@ + */ + void leon_pci_init(struct platform_device *ofdev, struct leon_pci_info *info) + { ++ LIST_HEAD(resources); + struct pci_bus *root_bus; + +- root_bus = pci_scan_bus_parented(&ofdev->dev, 0, info->ops, info); +- if (root_bus) { +- root_bus->resource[0] = &info->io_space; +- root_bus->resource[1] = &info->mem_space; +- root_bus->resource[2] = NULL; +- +- /* Init all PCI devices into PCI tree */ +- pci_bus_add_devices(root_bus); ++ pci_add_resource(&resources, &info->io_space); ++ pci_add_resource(&resources, &info->mem_space); + ++ root_bus = pci_scan_root_bus(&ofdev->dev, 0, info->ops, info, ++ &resources); ++ if (root_bus) { + /* Setup IRQs of all devices using custom routines */ + pci_fixup_irqs(pci_common_swizzle, info->map_irq); + + /* Assign devices with resources */ + pci_assign_unassigned_resources(); ++ } else { ++ pci_free_resource_list(&resources); + } + } + +@@ -83,15 +83,6 @@ void __devinit pcibios_fixup_bus(struct + int i, has_io, has_mem; + u16 cmd; + +- /* Generic PCI bus probing sets these to point at +- * &io{port,mem}_resouce which is wrong for us. +- */ +- if (pbus->self == NULL) { +- pbus->resource[0] = &info->io_space; +- pbus->resource[1] = &info->mem_space; +- pbus->resource[2] = NULL; +- } +- + list_for_each_entry(dev, &pbus->devices, bus_list) { + /* + * We can not rely on that the bootloader has enabled I/O +--- a/arch/sparc/kernel/pci.c ++++ b/arch/sparc/kernel/pci.c +@@ -685,23 +685,25 @@ static void __devinit pci_bus_register_o + struct pci_bus * __devinit pci_scan_one_pbm(struct pci_pbm_info *pbm, + struct device *parent) + { ++ LIST_HEAD(resources); + struct device_node *node = pbm->op->dev.of_node; + struct pci_bus *bus; + + printk("PCI: Scanning PBM %s\n", node->full_name); + +- bus = pci_create_bus(parent, pbm->pci_first_busno, pbm->pci_ops, pbm); ++ pci_add_resource(&resources, &pbm->io_space); ++ pci_add_resource(&resources, &pbm->mem_space); ++ bus = pci_create_root_bus(parent, pbm->pci_first_busno, pbm->pci_ops, ++ pbm, &resources); + if (!bus) { + printk(KERN_ERR "Failed to create bus for %s\n", + node->full_name); ++ pci_free_resource_list(&resources); + return NULL; + } + bus->secondary = pbm->pci_first_busno; + bus->subordinate = pbm->pci_last_busno; + +- bus->resource[0] = &pbm->io_space; +- bus->resource[1] = &pbm->mem_space; +- + pci_of_scan_bus(pbm, node, bus); + pci_bus_add_devices(bus); + pci_bus_register_of_sysfs(bus); +@@ -711,13 +713,6 @@ struct pci_bus * __devinit pci_scan_one_ + + void __devinit pcibios_fixup_bus(struct pci_bus *pbus) + { +- struct pci_pbm_info *pbm = pbus->sysdata; +- +- /* Generic PCI bus probing sets these to point at +- * &io{port,mem}_resouce which is wrong for us. +- */ +- pbus->resource[0] = &pbm->io_space; +- pbus->resource[1] = &pbm->mem_space; + } + + void pcibios_update_irq(struct pci_dev *pdev, int irq) +--- a/arch/x86/include/asm/topology.h ++++ b/arch/x86/include/asm/topology.h +@@ -174,7 +174,7 @@ static inline void arch_fix_phys_package + } + + struct pci_bus; +-void x86_pci_root_bus_res_quirks(struct pci_bus *b); ++void x86_pci_root_bus_resources(int bus, struct list_head *resources); + + #ifdef CONFIG_SMP + #define mc_capable() ((boot_cpu_data.x86_max_cores > 1) && \ +--- a/arch/x86/pci/acpi.c ++++ b/arch/x86/pci/acpi.c +@@ -12,7 +12,7 @@ struct pci_root_info { + char *name; + unsigned int res_num; + struct resource *res; +- struct pci_bus *bus; ++ struct list_head *resources; + int busnum; + }; + +@@ -261,23 +261,20 @@ static void add_resources(struct pci_roo + "ignoring host bridge window %pR (conflicts with %s %pR)\n", + res, conflict->name, conflict); + else +- pci_bus_add_resource(info->bus, res, 0); ++ pci_add_resource(info->resources, res); + } + } + + static void + get_current_resources(struct acpi_device *device, int busnum, +- int domain, struct pci_bus *bus) ++ int domain, struct list_head *resources) + { + struct pci_root_info info; + size_t size; + +- if (pci_use_crs) +- pci_bus_remove_resources(bus); +- + info.bridge = device; +- info.bus = bus; + info.res_num = 0; ++ info.resources = resources; + acpi_walk_resources(device->handle, METHOD_NAME__CRS, count_resource, + &info); + if (!info.res_num) +@@ -286,7 +283,7 @@ get_current_resources(struct acpi_device + size = sizeof(*info.res) * info.res_num; + info.res = kmalloc(size, GFP_KERNEL); + if (!info.res) +- goto res_alloc_fail; ++ return; + + info.name = kasprintf(GFP_KERNEL, "PCI Bus %04x:%02x", domain, busnum); + if (!info.name) +@@ -301,8 +298,6 @@ get_current_resources(struct acpi_device + + name_alloc_fail: + kfree(info.res); +-res_alloc_fail: +- return; + } + + struct pci_bus * __devinit pci_acpi_scan_root(struct acpi_pci_root *root) +@@ -310,6 +305,7 @@ struct pci_bus * __devinit pci_acpi_scan + struct acpi_device *device = root->device; + int domain = root->segment; + int busnum = root->secondary.start; ++ LIST_HEAD(resources); + struct pci_bus *bus; + struct pci_sysdata *sd; + int node; +@@ -364,11 +360,15 @@ struct pci_bus * __devinit pci_acpi_scan + memcpy(bus->sysdata, sd, sizeof(*sd)); + kfree(sd); + } else { +- bus = pci_create_bus(NULL, busnum, &pci_root_ops, sd); +- if (bus) { +- get_current_resources(device, busnum, domain, bus); ++ get_current_resources(device, busnum, domain, &resources); ++ if (list_empty(&resources)) ++ x86_pci_root_bus_resources(busnum, &resources); ++ bus = pci_create_root_bus(NULL, busnum, &pci_root_ops, sd, ++ &resources); ++ if (bus) + bus->subordinate = pci_scan_child_bus(bus); +- } ++ else ++ pci_free_resource_list(&resources); + } + + /* After the PCI-E bus has been walked and all devices discovered, +--- a/arch/x86/pci/broadcom_bus.c ++++ b/arch/x86/pci/broadcom_bus.c +@@ -15,10 +15,11 @@ + #include <linux/pci.h> + #include <linux/init.h> + #include <asm/pci_x86.h> ++#include <asm/pci-direct.h> + + #include "bus_numa.h" + +-static void __devinit cnb20le_res(struct pci_dev *dev) ++static void __init cnb20le_res(u8 bus, u8 slot, u8 func) + { + struct pci_root_info *info; + struct resource res; +@@ -26,21 +27,12 @@ static void __devinit cnb20le_res(struct + u8 fbus, lbus; + int i; + +-#ifdef CONFIG_ACPI +- /* +- * We should get host bridge information from ACPI unless the BIOS +- * doesn't support it. +- */ +- if (acpi_os_get_root_pointer()) +- return; +-#endif +- + info = &pci_root_info[pci_root_num]; + pci_root_num++; + + /* read the PCI bus numbers */ +- pci_read_config_byte(dev, 0x44, &fbus); +- pci_read_config_byte(dev, 0x45, &lbus); ++ fbus = read_pci_config_byte(bus, slot, func, 0x44); ++ lbus = read_pci_config_byte(bus, slot, func, 0x45); + info->bus_min = fbus; + info->bus_max = lbus; + +@@ -59,8 +51,8 @@ static void __devinit cnb20le_res(struct + } + + /* read the non-prefetchable memory window */ +- pci_read_config_word(dev, 0xc0, &word1); +- pci_read_config_word(dev, 0xc2, &word2); ++ word1 = read_pci_config_16(bus, slot, func, 0xc0); ++ word2 = read_pci_config_16(bus, slot, func, 0xc2); + if (word1 != word2) { + res.start = (word1 << 16) | 0x0000; + res.end = (word2 << 16) | 0xffff; +@@ -69,8 +61,8 @@ static void __devinit cnb20le_res(struct + } + + /* read the prefetchable memory window */ +- pci_read_config_word(dev, 0xc4, &word1); +- pci_read_config_word(dev, 0xc6, &word2); ++ word1 = read_pci_config_16(bus, slot, func, 0xc4); ++ word2 = read_pci_config_16(bus, slot, func, 0xc6); + if (word1 != word2) { + res.start = (word1 << 16) | 0x0000; + res.end = (word2 << 16) | 0xffff; +@@ -79,8 +71,8 @@ static void __devinit cnb20le_res(struct + } + + /* read the IO port window */ +- pci_read_config_word(dev, 0xd0, &word1); +- pci_read_config_word(dev, 0xd2, &word2); ++ word1 = read_pci_config_16(bus, slot, func, 0xd0); ++ word2 = read_pci_config_16(bus, slot, func, 0xd2); + if (word1 != word2) { + res.start = word1; + res.end = word2; +@@ -92,13 +84,37 @@ static void __devinit cnb20le_res(struct + res.start = fbus; + res.end = lbus; + res.flags = IORESOURCE_BUS; +- dev_info(&dev->dev, "CNB20LE PCI Host Bridge (domain %04x %pR)\n", +- pci_domain_nr(dev->bus), &res); ++ printk(KERN_INFO "CNB20LE PCI Host Bridge (domain 0000 %pR)\n", &res); + + for (i = 0; i < info->res_num; i++) +- dev_info(&dev->dev, "host bridge window %pR\n", &info->res[i]); ++ printk(KERN_INFO "host bridge window %pR\n", &info->res[i]); + } + +-DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_LE, +- cnb20le_res); ++static int __init broadcom_postcore_init(void) ++{ ++ u8 bus = 0, slot = 0; ++ u32 id; ++ u16 vendor, device; ++ ++#ifdef CONFIG_ACPI ++ /* ++ * We should get host bridge information from ACPI unless the BIOS ++ * doesn't support it. ++ */ ++ if (acpi_os_get_root_pointer()) ++ return 0; ++#endif ++ ++ id = read_pci_config(bus, slot, 0, PCI_VENDOR_ID); ++ vendor = id & 0xffff; ++ device = (id >> 16) & 0xffff; ++ ++ if (vendor == PCI_VENDOR_ID_SERVERWORKS && ++ device == PCI_DEVICE_ID_SERVERWORKS_LE) { ++ cnb20le_res(bus, slot, 0); ++ cnb20le_res(bus, slot, 1); ++ } ++ return 0; ++} + ++postcore_initcall(broadcom_postcore_init); +--- a/arch/x86/pci/bus_numa.c ++++ b/arch/x86/pci/bus_numa.c +@@ -7,45 +7,50 @@ + int pci_root_num; + struct pci_root_info pci_root_info[PCI_ROOT_NR]; + +-void x86_pci_root_bus_res_quirks(struct pci_bus *b) ++void x86_pci_root_bus_resources(int bus, struct list_head *resources) + { + int i; + int j; + struct pci_root_info *info; + +- /* don't go for it if _CRS is used already */ +- if (b->resource[0] != &ioport_resource || +- b->resource[1] != &iomem_resource) +- return; +- + if (!pci_root_num) +- return; ++ goto default_resources; + + for (i = 0; i < pci_root_num; i++) { +- if (pci_root_info[i].bus_min == b->number) ++ if (pci_root_info[i].bus_min == bus) + break; + } + + if (i == pci_root_num) +- return; ++ goto default_resources; + +- printk(KERN_DEBUG "PCI: peer root bus %02x res updated from pci conf\n", +- b->number); ++ printk(KERN_DEBUG "PCI: root bus %02x: hardware-probed resources\n", ++ bus); + +- pci_bus_remove_resources(b); + info = &pci_root_info[i]; + for (j = 0; j < info->res_num; j++) { + struct resource *res; + struct resource *root; + + res = &info->res[j]; +- pci_bus_add_resource(b, res, 0); ++ pci_add_resource(resources, res); + if (res->flags & IORESOURCE_IO) + root = &ioport_resource; + else + root = &iomem_resource; + insert_resource(root, res); + } ++ return; ++ ++default_resources: ++ /* ++ * We don't have any host bridge aperture information from the ++ * "native host bridge drivers," e.g., amd_bus or broadcom_bus, ++ * so fall back to the defaults historically used by pci_create_bus(). ++ */ ++ printk(KERN_DEBUG "PCI: root bus %02x: using default resources\n", bus); ++ pci_add_resource(resources, &ioport_resource); ++ pci_add_resource(resources, &iomem_resource); + } + + void __devinit update_res(struct pci_root_info *info, resource_size_t start, +--- a/arch/x86/pci/common.c ++++ b/arch/x86/pci/common.c +@@ -164,9 +164,6 @@ void __devinit pcibios_fixup_bus(struct + { + struct pci_dev *dev; + +- /* root bus? */ +- if (!b->parent) +- x86_pci_root_bus_res_quirks(b); + pci_read_bridge_bases(b); + list_for_each_entry(dev, &b->devices, bus_list) + pcibios_fixup_device_resources(dev); +@@ -433,6 +430,7 @@ void __init dmi_check_pciprobe(void) + + struct pci_bus * __devinit pcibios_scan_root(int busnum) + { ++ LIST_HEAD(resources); + struct pci_bus *bus = NULL; + struct pci_sysdata *sd; + +@@ -456,9 +454,12 @@ struct pci_bus * __devinit pcibios_scan_ + sd->node = get_mp_bus_to_node(busnum); + + printk(KERN_DEBUG "PCI: Probing PCI hardware (bus %02x)\n", busnum); +- bus = pci_scan_bus_parented(NULL, busnum, &pci_root_ops, sd); +- if (!bus) ++ x86_pci_root_bus_resources(busnum, &resources); ++ bus = pci_scan_root_bus(NULL, busnum, &pci_root_ops, sd, &resources); ++ if (!bus) { ++ pci_free_resource_list(&resources); + kfree(sd); ++ } + + return bus; + } +@@ -639,6 +640,7 @@ int pci_ext_cfg_avail(struct pci_dev *de + + struct pci_bus * __devinit pci_scan_bus_on_node(int busno, struct pci_ops *ops, int node) + { ++ LIST_HEAD(resources); + struct pci_bus *bus = NULL; + struct pci_sysdata *sd; + +@@ -653,9 +655,12 @@ struct pci_bus * __devinit pci_scan_bus_ + return NULL; + } + sd->node = node; +- bus = pci_scan_bus(busno, ops, sd); +- if (!bus) ++ x86_pci_root_bus_resources(busno, &resources); ++ bus = pci_scan_root_bus(NULL, busno, ops, sd, &resources); ++ if (!bus) { ++ pci_free_resource_list(&resources); + kfree(sd); ++ } + + return bus; + } +--- a/arch/x86/pci/legacy.c ++++ b/arch/x86/pci/legacy.c +@@ -31,9 +31,6 @@ int __init pci_legacy_init(void) + + printk("PCI: Probing PCI hardware\n"); + pci_root_bus = pcibios_scan_root(0); +- if (pci_root_bus) +- pci_bus_add_devices(pci_root_bus); +- + return 0; + } + +--- a/arch/x86/pci/numaq_32.c ++++ b/arch/x86/pci/numaq_32.c +@@ -153,8 +153,6 @@ int __init pci_numaq_init(void) + raw_pci_ops = &pci_direct_conf1_mq; + + pci_root_bus = pcibios_scan_root(0); +- if (pci_root_bus) +- pci_bus_add_devices(pci_root_bus); + if (num_online_nodes() > 1) + for_each_online_node(quad) { + if (quad == 0) +--- a/arch/xtensa/kernel/pci.c ++++ b/arch/xtensa/kernel/pci.c +@@ -134,9 +134,46 @@ struct pci_controller * __init pcibios_a + return pci_ctrl; + } + ++static void __init pci_controller_apertures(struct pci_controller *pci_ctrl, ++ struct list_head *resources) ++{ ++ struct resource *res; ++ unsigned long io_offset; ++ int i; ++ ++ io_offset = (unsigned long)pci_ctrl->io_space.base; ++ res = &pci_ctrl->io_resource; ++ if (!res->flags) { ++ if (io_offset) ++ printk (KERN_ERR "I/O resource not set for host" ++ " bridge %d\n", pci_ctrl->index); ++ res->start = 0; ++ res->end = IO_SPACE_LIMIT; ++ res->flags = IORESOURCE_IO; ++ } ++ res->start += io_offset; ++ res->end += io_offset; ++ pci_add_resource(resources, res); ++ ++ for (i = 0; i < 3; i++) { ++ res = &pci_ctrl->mem_resources[i]; ++ if (!res->flags) { ++ if (i > 0) ++ continue; ++ printk(KERN_ERR "Memory resource not set for " ++ "host bridge %d\n", pci_ctrl->index); ++ res->start = 0; ++ res->end = ~0U; ++ res->flags = IORESOURCE_MEM; ++ } ++ pci_add_resource(resources, res); ++ } ++} ++ + static int __init pcibios_init(void) + { + struct pci_controller *pci_ctrl; ++ struct list_head resources; + struct pci_bus *bus; + int next_busno = 0, i; + +@@ -145,19 +182,10 @@ static int __init pcibios_init(void) + /* Scan all of the recorded PCI controllers. */ + for (pci_ctrl = pci_ctrl_head; pci_ctrl; pci_ctrl = pci_ctrl->next) { + pci_ctrl->last_busno = 0xff; +- bus = pci_scan_bus(pci_ctrl->first_busno, pci_ctrl->ops, +- pci_ctrl); +- if (pci_ctrl->io_resource.flags) { +- unsigned long offs; +- +- offs = (unsigned long)pci_ctrl->io_space.base; +- pci_ctrl->io_resource.start += offs; +- pci_ctrl->io_resource.end += offs; +- bus->resource[0] = &pci_ctrl->io_resource; +- } +- for (i = 0; i < 3; ++i) +- if (pci_ctrl->mem_resources[i].flags) +- bus->resource[i+1] =&pci_ctrl->mem_resources[i]; ++ INIT_LIST_HEAD(&resources); ++ pci_controller_apertures(pci_ctrl, &resources); ++ bus = pci_scan_root_bus(NULL, pci_ctrl->first_busno, ++ pci_ctrl->ops, pci_ctrl, &resources); + pci_ctrl->bus = bus; + pci_ctrl->last_busno = bus->subordinate; + if (next_busno <= pci_ctrl->last_busno) +@@ -178,36 +206,7 @@ void __init pcibios_fixup_bus(struct pci + int i; + + io_offset = (unsigned long)pci_ctrl->io_space.base; +- if (bus->parent == NULL) { +- /* this is a host bridge - fill in its resources */ +- pci_ctrl->bus = bus; +- +- bus->resource[0] = res = &pci_ctrl->io_resource; +- if (!res->flags) { +- if (io_offset) +- printk (KERN_ERR "I/O resource not set for host" +- " bridge %d\n", pci_ctrl->index); +- res->start = 0; +- res->end = IO_SPACE_LIMIT; +- res->flags = IORESOURCE_IO; +- } +- res->start += io_offset; +- res->end += io_offset; +- +- for (i = 0; i < 3; i++) { +- res = &pci_ctrl->mem_resources[i]; +- if (!res->flags) { +- if (i > 0) +- continue; +- printk(KERN_ERR "Memory resource not set for " +- "host bridge %d\n", pci_ctrl->index); +- res->start = 0; +- res->end = ~0U; +- res->flags = IORESOURCE_MEM; +- } +- bus->resource[i+1] = res; +- } +- } else { ++ if (bus->parent) { + /* This is a subordinate bridge */ + pci_read_bridge_bases(bus); + +--- a/drivers/parisc/dino.c ++++ b/drivers/parisc/dino.c +@@ -562,19 +562,6 @@ dino_fixup_bus(struct pci_bus *bus) + /* Firmware doesn't set up card-mode dino, so we have to */ + if (is_card_dino(&dino_dev->hba.dev->id)) { + dino_card_setup(bus, dino_dev->hba.base_addr); +- } else if(bus->parent == NULL) { +- /* must have a dino above it, reparent the resources +- * into the dino window */ +- int i; +- struct resource *res = &dino_dev->hba.lmmio_space; +- +- bus->resource[0] = &(dino_dev->hba.io_space); +- for(i = 0; i < DINO_MAX_LMMIO_RESOURCES; i++) { +- if(res[i].flags == 0) +- break; +- bus->resource[i+1] = &res[i]; +- } +- + } else if (bus->parent) { + int i; + +@@ -927,6 +914,7 @@ static int __init dino_probe(struct pari + const char *version = "unknown"; + char *name; + int is_cujo = 0; ++ LIST_HEAD(resources); + struct pci_bus *bus; + unsigned long hpa = dev->hpa.start; + +@@ -1003,26 +991,37 @@ static int __init dino_probe(struct pari + + dev->dev.platform_data = dino_dev; + ++ pci_add_resource(&resources, &dino_dev->hba.io_space); ++ if (dino_dev->hba.lmmio_space.flags) ++ pci_add_resource(&resources, &dino_dev->hba.lmmio_space); ++ if (dino_dev->hba.elmmio_space.flags) ++ pci_add_resource(&resources, &dino_dev->hba.elmmio_space); ++ if (dino_dev->hba.gmmio_space.flags) ++ pci_add_resource(&resources, &dino_dev->hba.gmmio_space); ++ + /* + ** It's not used to avoid chicken/egg problems + ** with configuration accessor functions. + */ +- dino_dev->hba.hba_bus = bus = pci_scan_bus_parented(&dev->dev, +- dino_current_bus, &dino_cfg_ops, NULL); +- +- if(bus) { +- /* This code *depends* on scanning being single threaded +- * if it isn't, this global bus number count will fail +- */ +- dino_current_bus = bus->subordinate + 1; +- pci_bus_assign_resources(bus); +- pci_bus_add_devices(bus); +- } else { ++ dino_dev->hba.hba_bus = bus = pci_create_root_bus(&dev->dev, ++ dino_current_bus, &dino_cfg_ops, NULL, &resources); ++ if (!bus) { + printk(KERN_ERR "ERROR: failed to scan PCI bus on %s (duplicate bus number %d?)\n", + dev_name(&dev->dev), dino_current_bus); ++ pci_free_resource_list(&resources); + /* increment the bus number in case of duplicates */ + dino_current_bus++; ++ return 0; + } ++ ++ bus->subordinate = pci_scan_child_bus(bus); ++ ++ /* This code *depends* on scanning being single threaded ++ * if it isn't, this global bus number count will fail ++ */ ++ dino_current_bus = bus->subordinate + 1; ++ pci_bus_assign_resources(bus); ++ pci_bus_add_devices(bus); + return 0; + } + +--- a/drivers/parisc/lba_pci.c ++++ b/drivers/parisc/lba_pci.c +@@ -653,7 +653,7 @@ lba_fixup_bus(struct pci_bus *bus) + } + } else { + /* Host-PCI Bridge */ +- int err, i; ++ int err; + + DBG("lba_fixup_bus() %s [%lx/%lx]/%lx\n", + ldev->hba.io_space.name, +@@ -669,9 +669,6 @@ lba_fixup_bus(struct pci_bus *bus) + lba_dump_res(&ioport_resource, 2); + BUG(); + } +- /* advertize Host bridge resources to PCI bus */ +- bus->resource[0] = &(ldev->hba.io_space); +- i = 1; + + if (ldev->hba.elmmio_space.start) { + err = request_resource(&iomem_resource, +@@ -685,35 +682,17 @@ lba_fixup_bus(struct pci_bus *bus) + + /* lba_dump_res(&iomem_resource, 2); */ + /* BUG(); */ +- } else +- bus->resource[i++] = &(ldev->hba.elmmio_space); ++ } + } + +- +- /* Overlaps with elmmio can (and should) fail here. +- * We will prune (or ignore) the distributed range. +- * +- * FIXME: SBA code should register all elmmio ranges first. +- * that would take care of elmmio ranges routed +- * to a different rope (already discovered) from +- * getting registered *after* LBA code has already +- * registered it's distributed lmmio range. +- */ +- if (truncate_pat_collision(&iomem_resource, +- &(ldev->hba.lmmio_space))) { +- +- printk(KERN_WARNING "LBA: lmmio_space [%lx/%lx] duplicate!\n", +- (long)ldev->hba.lmmio_space.start, +- (long)ldev->hba.lmmio_space.end); +- } else { ++ if (ldev->hba.lmmio_space.flags) { + err = request_resource(&iomem_resource, &(ldev->hba.lmmio_space)); + if (err < 0) { + printk(KERN_ERR "FAILED: lba_fixup_bus() request for " + "lmmio_space [%lx/%lx]\n", + (long)ldev->hba.lmmio_space.start, + (long)ldev->hba.lmmio_space.end); +- } else +- bus->resource[i++] = &(ldev->hba.lmmio_space); ++ } + } + + #ifdef CONFIG_64BIT +@@ -728,7 +707,6 @@ lba_fixup_bus(struct pci_bus *bus) + lba_dump_res(&iomem_resource, 2); + BUG(); + } +- bus->resource[i++] = &(ldev->hba.gmmio_space); + } + #endif + +@@ -1404,6 +1382,7 @@ static int __init + lba_driver_probe(struct parisc_device *dev) + { + struct lba_device *lba_dev; ++ LIST_HEAD(resources); + struct pci_bus *lba_bus; + struct pci_ops *cfg_ops; + u32 func_class; +@@ -1518,10 +1497,41 @@ lba_driver_probe(struct parisc_device *d + if (lba_dev->hba.bus_num.start < lba_next_bus) + lba_dev->hba.bus_num.start = lba_next_bus; + ++ /* Overlaps with elmmio can (and should) fail here. ++ * We will prune (or ignore) the distributed range. ++ * ++ * FIXME: SBA code should register all elmmio ranges first. ++ * that would take care of elmmio ranges routed ++ * to a different rope (already discovered) from ++ * getting registered *after* LBA code has already ++ * registered it's distributed lmmio range. ++ */ ++ if (truncate_pat_collision(&iomem_resource, ++ &(lba_dev->hba.lmmio_space))) { ++ printk(KERN_WARNING "LBA: lmmio_space [%lx/%lx] duplicate!\n", ++ (long)lba_dev->hba.lmmio_space.start, ++ (long)lba_dev->hba.lmmio_space.end); ++ lba_dev->hba.lmmio_space.flags = 0; ++ } ++ ++ pci_add_resource(&resources, &lba_dev->hba.io_space); ++ if (lba_dev->hba.elmmio_space.start) ++ pci_add_resource(&resources, &lba_dev->hba.elmmio_space); ++ if (lba_dev->hba.lmmio_space.flags) ++ pci_add_resource(&resources, &lba_dev->hba.lmmio_space); ++ if (lba_dev->hba.gmmio_space.flags) ++ pci_add_resource(&resources, &lba_dev->hba.gmmio_space); ++ + dev->dev.platform_data = lba_dev; + lba_bus = lba_dev->hba.hba_bus = +- pci_scan_bus_parented(&dev->dev, lba_dev->hba.bus_num.start, +- cfg_ops, NULL); ++ pci_create_root_bus(&dev->dev, lba_dev->hba.bus_num.start, ++ cfg_ops, NULL, &resources); ++ if (!lba_bus) { ++ pci_free_resource_list(&resources); ++ return 0; ++ } ++ ++ lba_bus->subordinate = pci_scan_child_bus(lba_bus); + + /* This is in lieu of calling pci_assign_unassigned_resources() */ + if (is_pdc_pat()) { +@@ -1551,10 +1561,8 @@ lba_driver_probe(struct parisc_device *d + lba_dev->flags |= LBA_FLAG_SKIP_PROBE; + } + +- if (lba_bus) { +- lba_next_bus = lba_bus->subordinate + 1; +- pci_bus_add_devices(lba_bus); +- } ++ lba_next_bus = lba_bus->subordinate + 1; ++ pci_bus_add_devices(lba_bus); + + /* Whew! Finally done! Tell services we got this one covered. */ + return 0; +--- a/drivers/pci/bus.c ++++ b/drivers/pci/bus.c +@@ -18,6 +18,32 @@ + + #include "pci.h" + ++void pci_add_resource(struct list_head *resources, struct resource *res) ++{ ++ struct pci_bus_resource *bus_res; ++ ++ bus_res = kzalloc(sizeof(struct pci_bus_resource), GFP_KERNEL); ++ if (!bus_res) { ++ printk(KERN_ERR "PCI: can't add bus resource %pR\n", res); ++ return; ++ } ++ ++ bus_res->res = res; ++ list_add_tail(&bus_res->list, resources); ++} ++EXPORT_SYMBOL(pci_add_resource); ++ ++void pci_free_resource_list(struct list_head *resources) ++{ ++ struct pci_bus_resource *bus_res, *tmp; ++ ++ list_for_each_entry_safe(bus_res, tmp, resources, list) { ++ list_del(&bus_res->list); ++ kfree(bus_res); ++ } ++} ++EXPORT_SYMBOL(pci_free_resource_list); ++ + void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, + unsigned int flags) + { +@@ -52,16 +78,12 @@ EXPORT_SYMBOL_GPL(pci_bus_resource_n); + + void pci_bus_remove_resources(struct pci_bus *bus) + { +- struct pci_bus_resource *bus_res, *tmp; + int i; + + for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) + bus->resource[i] = NULL; + +- list_for_each_entry_safe(bus_res, tmp, &bus->resources, list) { +- list_del(&bus_res->list); +- kfree(bus_res); +- } ++ pci_free_resource_list(&bus->resources); + } + + /** +--- a/drivers/pci/probe.c ++++ b/drivers/pci/probe.c +@@ -1522,12 +1522,14 @@ unsigned int __devinit pci_scan_child_bu + return max; + } + +-struct pci_bus * pci_create_bus(struct device *parent, +- int bus, struct pci_ops *ops, void *sysdata) ++struct pci_bus *pci_create_root_bus(struct device *parent, int bus, ++ struct pci_ops *ops, void *sysdata, struct list_head *resources) + { +- int error; ++ int error, i; + struct pci_bus *b, *b2; + struct device *dev; ++ struct pci_bus_resource *bus_res, *n; ++ struct resource *res; + + b = pci_alloc_bus(); + if (!b) +@@ -1577,8 +1579,20 @@ struct pci_bus * pci_create_bus(struct d + pci_create_legacy_files(b); + + b->number = b->secondary = bus; +- b->resource[0] = &ioport_resource; +- b->resource[1] = &iomem_resource; ++ ++ /* Add initial resources to the bus */ ++ list_for_each_entry_safe(bus_res, n, resources, list) ++ list_move_tail(&bus_res->list, &b->resources); ++ ++ if (parent) ++ dev_info(parent, "PCI host bridge to bus %s\n", dev_name(&b->dev)); ++ else ++ printk(KERN_INFO "PCI host bridge to bus %s\n", dev_name(&b->dev)); ++ ++ pci_bus_for_each_resource(b, res, i) { ++ if (res) ++ dev_info(&b->dev, "root bus resource %pR\n", res); ++ } + + return b; + +@@ -1594,18 +1608,58 @@ err_out: + return NULL; + } + ++struct pci_bus * __devinit pci_scan_root_bus(struct device *parent, int bus, ++ struct pci_ops *ops, void *sysdata, struct list_head *resources) ++{ ++ struct pci_bus *b; ++ ++ b = pci_create_root_bus(parent, bus, ops, sysdata, resources); ++ if (!b) ++ return NULL; ++ ++ b->subordinate = pci_scan_child_bus(b); ++ pci_bus_add_devices(b); ++ return b; ++} ++EXPORT_SYMBOL(pci_scan_root_bus); ++ ++/* Deprecated; use pci_scan_root_bus() instead */ + struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent, + int bus, struct pci_ops *ops, void *sysdata) + { ++ LIST_HEAD(resources); + struct pci_bus *b; + +- b = pci_create_bus(parent, bus, ops, sysdata); ++ pci_add_resource(&resources, &ioport_resource); ++ pci_add_resource(&resources, &iomem_resource); ++ b = pci_create_root_bus(parent, bus, ops, sysdata, &resources); + if (b) + b->subordinate = pci_scan_child_bus(b); ++ else ++ pci_free_resource_list(&resources); + return b; + } + EXPORT_SYMBOL(pci_scan_bus_parented); + ++struct pci_bus * __devinit pci_scan_bus(int bus, struct pci_ops *ops, ++ void *sysdata) ++{ ++ LIST_HEAD(resources); ++ struct pci_bus *b; ++ ++ pci_add_resource(&resources, &ioport_resource); ++ pci_add_resource(&resources, &iomem_resource); ++ b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources); ++ if (b) { ++ b->subordinate = pci_scan_child_bus(b); ++ pci_bus_add_devices(b); ++ } else { ++ pci_free_resource_list(&resources); ++ } ++ return b; ++} ++EXPORT_SYMBOL(pci_scan_bus); ++ + #ifdef CONFIG_HOTPLUG + /** + * pci_rescan_bus - scan a PCI bus for devices. +--- a/include/linux/pci.h ++++ b/include/linux/pci.h +@@ -660,17 +660,13 @@ extern struct pci_bus *pci_find_bus(int + void pci_bus_add_devices(const struct pci_bus *bus); + struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus, + struct pci_ops *ops, void *sysdata); +-static inline struct pci_bus * __devinit pci_scan_bus(int bus, struct pci_ops *ops, +- void *sysdata) +-{ +- struct pci_bus *root_bus; +- root_bus = pci_scan_bus_parented(NULL, bus, ops, sysdata); +- if (root_bus) +- pci_bus_add_devices(root_bus); +- return root_bus; +-} +-struct pci_bus *pci_create_bus(struct device *parent, int bus, +- struct pci_ops *ops, void *sysdata); ++struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata); ++struct pci_bus *pci_create_root_bus(struct device *parent, int bus, ++ struct pci_ops *ops, void *sysdata, ++ struct list_head *resources); ++struct pci_bus * __devinit pci_scan_root_bus(struct device *parent, int bus, ++ struct pci_ops *ops, void *sysdata, ++ struct list_head *resources); + struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, + int busnr); + void pcie_update_link_speed(struct pci_bus *bus, u16 link_status); +@@ -910,6 +906,8 @@ int pci_request_selected_regions_exclusi + void pci_release_selected_regions(struct pci_dev *, int); + + /* drivers/pci/bus.c */ ++void pci_add_resource(struct list_head *resources, struct resource *res); ++void pci_free_resource_list(struct list_head *resources); + void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, unsigned int flags); + struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n); + void pci_bus_remove_resources(struct pci_bus *bus); diff --git a/target/linux/brcm47xx/patches-3.2/0036-bcma-add-the-core-unit-number.patch b/target/linux/brcm47xx/patches-3.2/0036-bcma-add-the-core-unit-number.patch new file mode 100644 index 000000000..2c41a3008 --- /dev/null +++ b/target/linux/brcm47xx/patches-3.2/0036-bcma-add-the-core-unit-number.patch @@ -0,0 +1,61 @@ +From 7b9116eeaf44c0d368b5eeaa06eb101465284596 Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens <hauke@hauke-m.de> +Date: Wed, 11 Jan 2012 15:26:11 +0100 +Subject: [PATCH 23/31] bcma: add the core unit number + +Some SoCs have two pcie or gmac cores and we need to know the number of +the specific core on the bus. This is the case for the BCM4706. + +Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> +--- + drivers/bcma/scan.c | 14 ++++++++++++++ + include/linux/bcma/bcma.h | 1 + + 2 files changed, 15 insertions(+), 0 deletions(-) + +--- a/drivers/bcma/scan.c ++++ b/drivers/bcma/scan.c +@@ -212,6 +212,17 @@ static struct bcma_device *bcma_find_cor + return NULL; + } + ++static struct bcma_device *bcma_find_core_reverse(struct bcma_bus *bus, u16 coreid) ++{ ++ struct bcma_device *core; ++ ++ list_for_each_entry_reverse(core, &bus->cores, list) { ++ if (core->id.id == coreid) ++ return core; ++ } ++ return NULL; ++} ++ + static int bcma_get_next_core(struct bcma_bus *bus, u32 __iomem **eromptr, + struct bcma_device_id *match, int core_num, + struct bcma_device *core) +@@ -407,6 +418,7 @@ int bcma_bus_scan(struct bcma_bus *bus) + bcma_scan_switch_core(bus, erombase); + + while (eromptr < eromend) { ++ struct bcma_device *other_core; + struct bcma_device *core = kzalloc(sizeof(*core), GFP_KERNEL); + if (!core) + return -ENOMEM; +@@ -426,6 +438,8 @@ int bcma_bus_scan(struct bcma_bus *bus) + + core->core_index = core_num++; + bus->nr_cores++; ++ other_core = bcma_find_core_reverse(bus, core->id.id); ++ core->core_unit = (other_core == NULL) ? 0 : other_core->core_unit + 1; + + pr_info("Core %d found: %s " + "(manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n", +--- a/include/linux/bcma/bcma.h ++++ b/include/linux/bcma/bcma.h +@@ -136,6 +136,7 @@ struct bcma_device { + bool dev_registered; + + u8 core_index; ++ u8 core_unit; + + u32 addr; + u32 addr1; diff --git a/target/linux/brcm47xx/patches-3.2/0037-bcma-constants-for-PCI-and-use-them.patch b/target/linux/brcm47xx/patches-3.2/0037-bcma-constants-for-PCI-and-use-them.patch new file mode 100644 index 000000000..ab5f48198 --- /dev/null +++ b/target/linux/brcm47xx/patches-3.2/0037-bcma-constants-for-PCI-and-use-them.patch @@ -0,0 +1,334 @@ +From 300efafa8e1381a208c723bb9d03d46bf29f1ec0 Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens <hauke@hauke-m.de> +Date: Sat, 14 Jan 2012 20:02:15 +0100 +Subject: [PATCH 24/31] bcma: constants for PCI and use them + +There are loots of magic numbers used in the PCIe code. These constants +are from the Broadcom SDK and will also used in the host controller. + +Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> +--- + drivers/bcma/driver_pci.c | 124 +++++++++++++++++++--------------- + include/linux/bcma/bcma_driver_pci.h | 85 +++++++++++++++++++++++ + 2 files changed, 155 insertions(+), 54 deletions(-) + +--- a/drivers/bcma/driver_pci.c ++++ b/drivers/bcma/driver_pci.c +@@ -4,6 +4,7 @@ + * + * Copyright 2005, Broadcom Corporation + * Copyright 2006, 2007, Michael Buesch <m@bues.ch> ++ * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de> + * + * Licensed under the GNU/GPL. See COPYING for details. + */ +@@ -18,38 +19,39 @@ + + static u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address) + { +- pcicore_write32(pc, 0x130, address); +- pcicore_read32(pc, 0x130); +- return pcicore_read32(pc, 0x134); ++ pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_ADDR, address); ++ pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_ADDR); ++ return pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_DATA); + } + + #if 0 + static void bcma_pcie_write(struct bcma_drv_pci *pc, u32 address, u32 data) + { +- pcicore_write32(pc, 0x130, address); +- pcicore_read32(pc, 0x130); +- pcicore_write32(pc, 0x134, data); ++ pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_ADDR, address); ++ pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_ADDR); ++ pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_DATA, data); + } + #endif + + static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u8 phy) + { +- const u16 mdio_control = 0x128; +- const u16 mdio_data = 0x12C; + u32 v; + int i; + +- v = (1 << 30); /* Start of Transaction */ +- v |= (1 << 28); /* Write Transaction */ +- v |= (1 << 17); /* Turnaround */ +- v |= (0x1F << 18); ++ v = BCMA_CORE_PCI_MDIODATA_START; ++ v |= BCMA_CORE_PCI_MDIODATA_WRITE; ++ v |= (BCMA_CORE_PCI_MDIODATA_DEV_ADDR << ++ BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF); ++ v |= (BCMA_CORE_PCI_MDIODATA_BLK_ADDR << ++ BCMA_CORE_PCI_MDIODATA_REGADDR_SHF); ++ v |= BCMA_CORE_PCI_MDIODATA_TA; + v |= (phy << 4); +- pcicore_write32(pc, mdio_data, v); ++ pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v); + + udelay(10); + for (i = 0; i < 200; i++) { +- v = pcicore_read32(pc, mdio_control); +- if (v & 0x100 /* Trans complete */) ++ v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL); ++ if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE) + break; + msleep(1); + } +@@ -57,79 +59,84 @@ static void bcma_pcie_mdio_set_phy(struc + + static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u8 device, u8 address) + { +- const u16 mdio_control = 0x128; +- const u16 mdio_data = 0x12C; + int max_retries = 10; + u16 ret = 0; + u32 v; + int i; + +- v = 0x80; /* Enable Preamble Sequence */ +- v |= 0x2; /* MDIO Clock Divisor */ +- pcicore_write32(pc, mdio_control, v); ++ /* enable mdio access to SERDES */ ++ v = BCMA_CORE_PCI_MDIOCTL_PREAM_EN; ++ v |= BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL; ++ pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, v); + + if (pc->core->id.rev >= 10) { + max_retries = 200; + bcma_pcie_mdio_set_phy(pc, device); ++ v = (BCMA_CORE_PCI_MDIODATA_DEV_ADDR << ++ BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF); ++ v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF); ++ } else { ++ v = (device << BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD); ++ v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD); + } + +- v = (1 << 30); /* Start of Transaction */ +- v |= (1 << 29); /* Read Transaction */ +- v |= (1 << 17); /* Turnaround */ +- if (pc->core->id.rev < 10) +- v |= (u32)device << 22; +- v |= (u32)address << 18; +- pcicore_write32(pc, mdio_data, v); ++ v = BCMA_CORE_PCI_MDIODATA_START; ++ v |= BCMA_CORE_PCI_MDIODATA_READ; ++ v |= BCMA_CORE_PCI_MDIODATA_TA; ++ ++ pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v); + /* Wait for the device to complete the transaction */ + udelay(10); + for (i = 0; i < max_retries; i++) { +- v = pcicore_read32(pc, mdio_control); +- if (v & 0x100 /* Trans complete */) { ++ v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL); ++ if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE) { + udelay(10); +- ret = pcicore_read32(pc, mdio_data); ++ ret = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_DATA); + break; + } + msleep(1); + } +- pcicore_write32(pc, mdio_control, 0); ++ pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0); + return ret; + } + + static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u8 device, + u8 address, u16 data) + { +- const u16 mdio_control = 0x128; +- const u16 mdio_data = 0x12C; + int max_retries = 10; + u32 v; + int i; + +- v = 0x80; /* Enable Preamble Sequence */ +- v |= 0x2; /* MDIO Clock Divisor */ +- pcicore_write32(pc, mdio_control, v); ++ /* enable mdio access to SERDES */ ++ v = BCMA_CORE_PCI_MDIOCTL_PREAM_EN; ++ v |= BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL; ++ pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, v); + + if (pc->core->id.rev >= 10) { + max_retries = 200; + bcma_pcie_mdio_set_phy(pc, device); ++ v = (BCMA_CORE_PCI_MDIODATA_DEV_ADDR << ++ BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF); ++ v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF); ++ } else { ++ v = (device << BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD); ++ v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD); + } + +- v = (1 << 30); /* Start of Transaction */ +- v |= (1 << 28); /* Write Transaction */ +- v |= (1 << 17); /* Turnaround */ +- if (pc->core->id.rev < 10) +- v |= (u32)device << 22; +- v |= (u32)address << 18; ++ v = BCMA_CORE_PCI_MDIODATA_START; ++ v |= BCMA_CORE_PCI_MDIODATA_WRITE; ++ v |= BCMA_CORE_PCI_MDIODATA_TA; + v |= data; +- pcicore_write32(pc, mdio_data, v); ++ pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v); + /* Wait for the device to complete the transaction */ + udelay(10); + for (i = 0; i < max_retries; i++) { +- v = pcicore_read32(pc, mdio_control); +- if (v & 0x100 /* Trans complete */) ++ v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL); ++ if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE) + break; + msleep(1); + } +- pcicore_write32(pc, mdio_control, 0); ++ pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0); + } + + /************************************************** +@@ -138,20 +145,29 @@ static void bcma_pcie_mdio_write(struct + + static u8 bcma_pcicore_polarity_workaround(struct bcma_drv_pci *pc) + { +- return (bcma_pcie_read(pc, 0x204) & 0x10) ? 0xC0 : 0x80; ++ u32 tmp; ++ ++ tmp = bcma_pcie_read(pc, BCMA_CORE_PCI_PLP_STATUSREG); ++ if (tmp & BCMA_CORE_PCI_PLP_POLARITYINV_STAT) ++ return BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE | ++ BCMA_CORE_PCI_SERDES_RX_CTRL_POLARITY; ++ else ++ return BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE; + } + + static void bcma_pcicore_serdes_workaround(struct bcma_drv_pci *pc) + { +- const u8 serdes_pll_device = 0x1D; +- const u8 serdes_rx_device = 0x1F; + u16 tmp; + +- bcma_pcie_mdio_write(pc, serdes_rx_device, 1 /* Control */, +- bcma_pcicore_polarity_workaround(pc)); +- tmp = bcma_pcie_mdio_read(pc, serdes_pll_device, 1 /* Control */); +- if (tmp & 0x4000) +- bcma_pcie_mdio_write(pc, serdes_pll_device, 1, tmp & ~0x4000); ++ bcma_pcie_mdio_write(pc, BCMA_CORE_PCI_MDIODATA_DEV_RX, ++ BCMA_CORE_PCI_SERDES_RX_CTRL, ++ bcma_pcicore_polarity_workaround(pc)); ++ tmp = bcma_pcie_mdio_read(pc, BCMA_CORE_PCI_MDIODATA_DEV_PLL, ++ BCMA_CORE_PCI_SERDES_PLL_CTRL); ++ if (tmp & BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN) ++ bcma_pcie_mdio_write(pc, BCMA_CORE_PCI_MDIODATA_DEV_PLL, ++ BCMA_CORE_PCI_SERDES_PLL_CTRL, ++ tmp & ~BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN); + } + + /************************************************** +--- a/include/linux/bcma/bcma_driver_pci.h ++++ b/include/linux/bcma/bcma_driver_pci.h +@@ -53,6 +53,35 @@ struct pci_dev; + #define BCMA_CORE_PCI_SBTOPCI1_MASK 0xFC000000 + #define BCMA_CORE_PCI_SBTOPCI2 0x0108 /* Backplane to PCI translation 2 (sbtopci2) */ + #define BCMA_CORE_PCI_SBTOPCI2_MASK 0xC0000000 ++#define BCMA_CORE_PCI_CONFIG_ADDR 0x0120 /* pcie config space access */ ++#define BCMA_CORE_PCI_CONFIG_DATA 0x0124 /* pcie config space access */ ++#define BCMA_CORE_PCI_MDIO_CONTROL 0x0128 /* controls the mdio access */ ++#define BCMA_CORE_PCI_MDIOCTL_DIVISOR_MASK 0x7f /* clock to be used on MDIO */ ++#define BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL 0x2 ++#define BCMA_CORE_PCI_MDIOCTL_PREAM_EN 0x80 /* Enable preamble sequnce */ ++#define BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE 0x100 /* Tranaction complete */ ++#define BCMA_CORE_PCI_MDIO_DATA 0x012c /* Data to the mdio access */ ++#define BCMA_CORE_PCI_MDIODATA_MASK 0x0000ffff /* data 2 bytes */ ++#define BCMA_CORE_PCI_MDIODATA_TA 0x00020000 /* Turnaround */ ++#define BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD 18 /* Regaddr shift (rev < 10) */ ++#define BCMA_CORE_PCI_MDIODATA_REGADDR_MASK_OLD 0x003c0000 /* Regaddr Mask (rev < 10) */ ++#define BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD 22 /* Physmedia devaddr shift (rev < 10) */ ++#define BCMA_CORE_PCI_MDIODATA_DEVADDR_MASK_OLD 0x0fc00000 /* Physmedia devaddr Mask (rev < 10) */ ++#define BCMA_CORE_PCI_MDIODATA_REGADDR_SHF 18 /* Regaddr shift */ ++#define BCMA_CORE_PCI_MDIODATA_REGADDR_MASK 0x007c0000 /* Regaddr Mask */ ++#define BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF 23 /* Physmedia devaddr shift */ ++#define BCMA_CORE_PCI_MDIODATA_DEVADDR_MASK 0x0f800000 /* Physmedia devaddr Mask */ ++#define BCMA_CORE_PCI_MDIODATA_WRITE 0x10000000 /* write Transaction */ ++#define BCMA_CORE_PCI_MDIODATA_READ 0x20000000 /* Read Transaction */ ++#define BCMA_CORE_PCI_MDIODATA_START 0x40000000 /* start of Transaction */ ++#define BCMA_CORE_PCI_MDIODATA_DEV_ADDR 0x0 /* dev address for serdes */ ++#define BCMA_CORE_PCI_MDIODATA_BLK_ADDR 0x1F /* blk address for serdes */ ++#define BCMA_CORE_PCI_MDIODATA_DEV_PLL 0x1d /* SERDES PLL Dev */ ++#define BCMA_CORE_PCI_MDIODATA_DEV_TX 0x1e /* SERDES TX Dev */ ++#define BCMA_CORE_PCI_MDIODATA_DEV_RX 0x1f /* SERDES RX Dev */ ++#define BCMA_CORE_PCI_PCIEIND_ADDR 0x0130 /* indirect access to the internal register */ ++#define BCMA_CORE_PCI_PCIEIND_DATA 0x0134 /* Data to/from the internal regsiter */ ++#define BCMA_CORE_PCI_CLKREQENCTRL 0x0138 /* >= rev 6, Clkreq rdma control */ + #define BCMA_CORE_PCI_PCICFG0 0x0400 /* PCI config space 0 (rev >= 8) */ + #define BCMA_CORE_PCI_PCICFG1 0x0500 /* PCI config space 1 (rev >= 8) */ + #define BCMA_CORE_PCI_PCICFG2 0x0600 /* PCI config space 2 (rev >= 8) */ +@@ -72,6 +101,62 @@ struct pci_dev; + #define BCMA_CORE_PCI_SBTOPCI_RC_READL 0x00000010 /* Memory read line */ + #define BCMA_CORE_PCI_SBTOPCI_RC_READM 0x00000020 /* Memory read multiple */ + ++/* PCIE protocol PHY diagnostic registers */ ++#define BCMA_CORE_PCI_PLP_MODEREG 0x200 /* Mode */ ++#define BCMA_CORE_PCI_PLP_STATUSREG 0x204 /* Status */ ++#define BCMA_CORE_PCI_PLP_POLARITYINV_STAT 0x10 /* Status reg PCIE_PLP_STATUSREG */ ++#define BCMA_CORE_PCI_PLP_LTSSMCTRLREG 0x208 /* LTSSM control */ ++#define BCMA_CORE_PCI_PLP_LTLINKNUMREG 0x20c /* Link Training Link number */ ++#define BCMA_CORE_PCI_PLP_LTLANENUMREG 0x210 /* Link Training Lane number */ ++#define BCMA_CORE_PCI_PLP_LTNFTSREG 0x214 /* Link Training N_FTS */ ++#define BCMA_CORE_PCI_PLP_ATTNREG 0x218 /* Attention */ ++#define BCMA_CORE_PCI_PLP_ATTNMASKREG 0x21C /* Attention Mask */ ++#define BCMA_CORE_PCI_PLP_RXERRCTR 0x220 /* Rx Error */ ++#define BCMA_CORE_PCI_PLP_RXFRMERRCTR 0x224 /* Rx Framing Error */ ++#define BCMA_CORE_PCI_PLP_RXERRTHRESHREG 0x228 /* Rx Error threshold */ ++#define BCMA_CORE_PCI_PLP_TESTCTRLREG 0x22C /* Test Control reg */ ++#define BCMA_CORE_PCI_PLP_SERDESCTRLOVRDREG 0x230 /* SERDES Control Override */ ++#define BCMA_CORE_PCI_PLP_TIMINGOVRDREG 0x234 /* Timing param override */ ++#define BCMA_CORE_PCI_PLP_RXTXSMDIAGREG 0x238 /* RXTX State Machine Diag */ ++#define BCMA_CORE_PCI_PLP_LTSSMDIAGREG 0x23C /* LTSSM State Machine Diag */ ++ ++/* PCIE protocol DLLP diagnostic registers */ ++#define BCMA_CORE_PCI_DLLP_LCREG 0x100 /* Link Control */ ++#define BCMA_CORE_PCI_DLLP_LSREG 0x104 /* Link Status */ ++#define BCMA_CORE_PCI_DLLP_LAREG 0x108 /* Link Attention */ ++#define BCMA_CORE_PCI_DLLP_LSREG_LINKUP (1 << 16) ++#define BCMA_CORE_PCI_DLLP_LAMASKREG 0x10C /* Link Attention Mask */ ++#define BCMA_CORE_PCI_DLLP_NEXTTXSEQNUMREG 0x110 /* Next Tx Seq Num */ ++#define BCMA_CORE_PCI_DLLP_ACKEDTXSEQNUMREG 0x114 /* Acked Tx Seq Num */ ++#define BCMA_CORE_PCI_DLLP_PURGEDTXSEQNUMREG 0x118 /* Purged Tx Seq Num */ ++#define BCMA_CORE_PCI_DLLP_RXSEQNUMREG 0x11C /* Rx Sequence Number */ ++#define BCMA_CORE_PCI_DLLP_LRREG 0x120 /* Link Replay */ ++#define BCMA_CORE_PCI_DLLP_LACKTOREG 0x124 /* Link Ack Timeout */ ++#define BCMA_CORE_PCI_DLLP_PMTHRESHREG 0x128 /* Power Management Threshold */ ++#define BCMA_CORE_PCI_DLLP_RTRYWPREG 0x12C /* Retry buffer write ptr */ ++#define BCMA_CORE_PCI_DLLP_RTRYRPREG 0x130 /* Retry buffer Read ptr */ ++#define BCMA_CORE_PCI_DLLP_RTRYPPREG 0x134 /* Retry buffer Purged ptr */ ++#define BCMA_CORE_PCI_DLLP_RTRRWREG 0x138 /* Retry buffer Read/Write */ ++#define BCMA_CORE_PCI_DLLP_ECTHRESHREG 0x13C /* Error Count Threshold */ ++#define BCMA_CORE_PCI_DLLP_TLPERRCTRREG 0x140 /* TLP Error Counter */ ++#define BCMA_CORE_PCI_DLLP_ERRCTRREG 0x144 /* Error Counter */ ++#define BCMA_CORE_PCI_DLLP_NAKRXCTRREG 0x148 /* NAK Received Counter */ ++#define BCMA_CORE_PCI_DLLP_TESTREG 0x14C /* Test */ ++#define BCMA_CORE_PCI_DLLP_PKTBIST 0x150 /* Packet BIST */ ++#define BCMA_CORE_PCI_DLLP_PCIE11 0x154 /* DLLP PCIE 1.1 reg */ ++ ++/* SERDES RX registers */ ++#define BCMA_CORE_PCI_SERDES_RX_CTRL 1 /* Rx cntrl */ ++#define BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE 0x80 /* rxpolarity_force */ ++#define BCMA_CORE_PCI_SERDES_RX_CTRL_POLARITY 0x40 /* rxpolarity_value */ ++#define BCMA_CORE_PCI_SERDES_RX_TIMER1 2 /* Rx Timer1 */ ++#define BCMA_CORE_PCI_SERDES_RX_CDR 6 /* CDR */ ++#define BCMA_CORE_PCI_SERDES_RX_CDRBW 7 /* CDR BW */ ++ ++/* SERDES PLL registers */ ++#define BCMA_CORE_PCI_SERDES_PLL_CTRL 1 /* PLL control reg */ ++#define BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN 0x4000 /* bit 14 is FREQDET on */ ++ + /* PCIcore specific boardflags */ + #define BCMA_CORE_PCI_BFL_NOPCI 0x00000400 /* Board leaves PCI floating */ + diff --git a/target/linux/brcm47xx/patches-3.2/0038-bcma-export-bcma_pcie_read.patch b/target/linux/brcm47xx/patches-3.2/0038-bcma-export-bcma_pcie_read.patch new file mode 100644 index 000000000..70bb497bf --- /dev/null +++ b/target/linux/brcm47xx/patches-3.2/0038-bcma-export-bcma_pcie_read.patch @@ -0,0 +1,35 @@ +From 01d8709c311858c37e02c96464ea4dc954334210 Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens <hauke@hauke-m.de> +Date: Sat, 14 Jan 2012 20:03:09 +0100 +Subject: [PATCH 25/31] bcma: export bcma_pcie_read() + +This will be needed by the host controller. + +Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> +--- + drivers/bcma/bcma_private.h | 2 ++ + drivers/bcma/driver_pci.c | 2 +- + 2 files changed, 3 insertions(+), 1 deletions(-) + +--- a/drivers/bcma/bcma_private.h ++++ b/drivers/bcma/bcma_private.h +@@ -46,6 +46,8 @@ u32 bcma_pmu_get_clockcpu(struct bcma_dr + int bcma_sflash_init(struct bcma_drv_cc *cc); + #endif /* CONFIG_BCMA_SFLASH */ + ++u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address); ++ + #ifdef CONFIG_BCMA_HOST_PCI + /* host_pci.c */ + extern int __init bcma_host_pci_init(void); +--- a/drivers/bcma/driver_pci.c ++++ b/drivers/bcma/driver_pci.c +@@ -17,7 +17,7 @@ + * R/W ops. + **************************************************/ + +-static u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address) ++u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address) + { + pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_ADDR, address); + pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_ADDR); diff --git a/target/linux/brcm47xx/patches-3.2/0039-bcma-make-some-functions-__devinit.patch b/target/linux/brcm47xx/patches-3.2/0039-bcma-make-some-functions-__devinit.patch new file mode 100644 index 000000000..2534a3a6b --- /dev/null +++ b/target/linux/brcm47xx/patches-3.2/0039-bcma-make-some-functions-__devinit.patch @@ -0,0 +1,111 @@ +From 3cd3138f2ef77e18abc99737c6740f35d61dbbb3 Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens <hauke@hauke-m.de> +Date: Sun, 15 Jan 2012 23:05:05 +0100 +Subject: [PATCH 26/32] bcma: make some functions __devinit + +bcma_core_pci_hostmode_init() has to be in __devinit as it will call a +function in that section and so all functions calling it also have to +be in __devinit. + +Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> +--- + drivers/bcma/bcma_private.h | 4 ++-- + drivers/bcma/driver_pci.c | 6 +++--- + drivers/bcma/driver_pci_host.c | 2 +- + drivers/bcma/host_pci.c | 4 ++-- + drivers/bcma/main.c | 2 +- + include/linux/bcma/bcma_driver_pci.h | 2 +- + 6 files changed, 10 insertions(+), 10 deletions(-) + +--- a/drivers/bcma/bcma_private.h ++++ b/drivers/bcma/bcma_private.h +@@ -13,7 +13,7 @@ + struct bcma_bus; + + /* main.c */ +-int bcma_bus_register(struct bcma_bus *bus); ++int __devinit bcma_bus_register(struct bcma_bus *bus); + void bcma_bus_unregister(struct bcma_bus *bus); + int __init bcma_bus_early_register(struct bcma_bus *bus, + struct bcma_device *core_cc, +@@ -55,7 +55,7 @@ extern void __exit bcma_host_pci_exit(vo + #endif /* CONFIG_BCMA_HOST_PCI */ + + #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE +-void bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc); ++void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc); + #endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */ + + #endif +--- a/drivers/bcma/driver_pci.c ++++ b/drivers/bcma/driver_pci.c +@@ -174,12 +174,12 @@ static void bcma_pcicore_serdes_workarou + * Init. + **************************************************/ + +-static void bcma_core_pci_clientmode_init(struct bcma_drv_pci *pc) ++static void __devinit bcma_core_pci_clientmode_init(struct bcma_drv_pci *pc) + { + bcma_pcicore_serdes_workaround(pc); + } + +-static bool bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc) ++static bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc) + { + struct bcma_bus *bus = pc->core->bus; + u16 chipid_top; +@@ -204,7 +204,7 @@ static bool bcma_core_pci_is_in_hostmode + return true; + } + +-void bcma_core_pci_init(struct bcma_drv_pci *pc) ++void __devinit bcma_core_pci_init(struct bcma_drv_pci *pc) + { + if (pc->setup_done) + return; +--- a/drivers/bcma/driver_pci_host.c ++++ b/drivers/bcma/driver_pci_host.c +@@ -8,7 +8,7 @@ + #include "bcma_private.h" + #include <linux/bcma/bcma.h> + +-void bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc) ++void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc) + { + pr_err("No support for PCI core in hostmode yet\n"); + } +--- a/drivers/bcma/host_pci.c ++++ b/drivers/bcma/host_pci.c +@@ -154,8 +154,8 @@ const struct bcma_host_ops bcma_host_pci + .awrite32 = bcma_host_pci_awrite32, + }; + +-static int bcma_host_pci_probe(struct pci_dev *dev, +- const struct pci_device_id *id) ++static int __devinit bcma_host_pci_probe(struct pci_dev *dev, ++ const struct pci_device_id *id) + { + struct bcma_bus *bus; + int err = -ENOMEM; +--- a/drivers/bcma/main.c ++++ b/drivers/bcma/main.c +@@ -132,7 +132,7 @@ static void bcma_unregister_cores(struct + } + } + +-int bcma_bus_register(struct bcma_bus *bus) ++int __devinit bcma_bus_register(struct bcma_bus *bus) + { + int err; + struct bcma_device *core; +--- a/include/linux/bcma/bcma_driver_pci.h ++++ b/include/linux/bcma/bcma_driver_pci.h +@@ -169,7 +169,7 @@ struct bcma_drv_pci { + #define pcicore_read32(pc, offset) bcma_read32((pc)->core, offset) + #define pcicore_write32(pc, offset, val) bcma_write32((pc)->core, offset, val) + +-extern void bcma_core_pci_init(struct bcma_drv_pci *pc); ++extern void __devinit bcma_core_pci_init(struct bcma_drv_pci *pc); + extern int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc, + struct bcma_device *core, bool enable); + diff --git a/target/linux/brcm47xx/patches-3.2/0040-bcma-add-PCIe-host-controller.patch b/target/linux/brcm47xx/patches-3.2/0040-bcma-add-PCIe-host-controller.patch new file mode 100644 index 000000000..2afd09aee --- /dev/null +++ b/target/linux/brcm47xx/patches-3.2/0040-bcma-add-PCIe-host-controller.patch @@ -0,0 +1,845 @@ +From 47d0e8c2743729b4248585d33b55b6aaeac008d5 Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens <hauke@hauke-m.de> +Date: Sun, 8 Jan 2012 16:53:15 +0100 +Subject: [PATCH 25/34] bcma: add PCIe host controller + +Some SoCs have a PCIe host controller to make it possible to attach +some other devices to it, like an other Wifi card. +This code was tested with an Netgear WNDR3400 (bcm4716 based), but +should work with all bcma based SoCs. + +Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> +--- + arch/mips/pci/pci-bcm47xx.c | 49 +++- + drivers/bcma/bcma_private.h | 1 + + drivers/bcma/driver_pci.c | 38 +-- + drivers/bcma/driver_pci_host.c | 576 +++++++++++++++++++++++++++++++++- + include/linux/bcma/bcma_driver_pci.h | 34 ++ + include/linux/bcma/bcma_regs.h | 27 ++ + 6 files changed, 686 insertions(+), 39 deletions(-) + +--- a/arch/mips/pci/pci-bcm47xx.c ++++ b/arch/mips/pci/pci-bcm47xx.c +@@ -25,6 +25,7 @@ + #include <linux/types.h> + #include <linux/pci.h> + #include <linux/ssb/ssb.h> ++#include <linux/bcma/bcma.h> + #include <bcm47xx.h> + + int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +@@ -32,15 +33,12 @@ int __init pcibios_map_irq(const struct + return 0; + } + +-int pcibios_plat_dev_init(struct pci_dev *dev) +-{ + #ifdef CONFIG_BCM47XX_SSB ++static int bcm47xx_pcibios_plat_dev_init_ssb(struct pci_dev *dev) ++{ + int res; + u8 slot, pin; + +- if (bcm47xx_bus_type != BCM47XX_BUS_TYPE_SSB) +- return 0; +- + res = ssb_pcibios_plat_dev_init(dev); + if (res < 0) { + printk(KERN_ALERT "PCI: Failed to init device %s\n", +@@ -60,6 +58,47 @@ int pcibios_plat_dev_init(struct pci_dev + } + + dev->irq = res; ++ return 0; ++} + #endif ++ ++#ifdef CONFIG_BCM47XX_BCMA ++static int bcm47xx_pcibios_plat_dev_init_bcma(struct pci_dev *dev) ++{ ++ int res; ++ ++ res = bcma_core_pci_plat_dev_init(dev); ++ if (res < 0) { ++ printk(KERN_ALERT "PCI: Failed to init device %s\n", ++ pci_name(dev)); ++ return res; ++ } ++ ++ res = bcma_core_pci_pcibios_map_irq(dev); ++ ++ /* IRQ-0 and IRQ-1 are software interrupts. */ ++ if (res < 2) { ++ printk(KERN_ALERT "PCI: Failed to map IRQ of device %s\n", ++ pci_name(dev)); ++ return res; ++ } ++ ++ dev->irq = res; + return 0; + } ++#endif ++ ++int pcibios_plat_dev_init(struct pci_dev *dev) ++{ ++#ifdef CONFIG_BCM47XX_SSB ++ if (bcm47xx_bus_type == BCM47XX_BUS_TYPE_SSB) ++ return bcm47xx_pcibios_plat_dev_init_ssb(dev); ++ else ++#endif ++#ifdef CONFIG_BCM47XX_BCMA ++ if (bcm47xx_bus_type == BCM47XX_BUS_TYPE_BCMA) ++ return bcm47xx_pcibios_plat_dev_init_bcma(dev); ++ else ++#endif ++ return 0; ++} +--- a/drivers/bcma/bcma_private.h ++++ b/drivers/bcma/bcma_private.h +@@ -55,6 +55,7 @@ extern void __exit bcma_host_pci_exit(vo + #endif /* CONFIG_BCMA_HOST_PCI */ + + #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE ++bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc); + void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc); + #endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */ + +--- a/drivers/bcma/driver_pci.c ++++ b/drivers/bcma/driver_pci.c +@@ -2,7 +2,7 @@ + * Broadcom specific AMBA + * PCI Core + * +- * Copyright 2005, Broadcom Corporation ++ * Copyright 2005, 2011, Broadcom Corporation + * Copyright 2006, 2007, Michael Buesch <m@bues.ch> + * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de> + * +@@ -179,47 +179,19 @@ static void __devinit bcma_core_pci_clie + bcma_pcicore_serdes_workaround(pc); + } + +-static bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc) +-{ +- struct bcma_bus *bus = pc->core->bus; +- u16 chipid_top; +- +- chipid_top = (bus->chipinfo.id & 0xFF00); +- if (chipid_top != 0x4700 && +- chipid_top != 0x5300) +- return false; +- +-#ifdef CONFIG_SSB_DRIVER_PCICORE +- if (bus->sprom.boardflags_lo & SSB_BFL_NOPCI) +- return false; +-#endif /* CONFIG_SSB_DRIVER_PCICORE */ +- +-#if 0 +- /* TODO: on BCMA we use address from EROM instead of magic formula */ +- u32 tmp; +- return !mips_busprobe32(tmp, (bus->mmio + +- (pc->core->core_index * BCMA_CORE_SIZE))); +-#endif +- +- return true; +-} +- + void __devinit bcma_core_pci_init(struct bcma_drv_pci *pc) + { + if (pc->setup_done) + return; + +- if (bcma_core_pci_is_in_hostmode(pc)) { + #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE ++ pc->hostmode = bcma_core_pci_is_in_hostmode(pc); ++ if (pc->hostmode) + bcma_core_pci_hostmode_init(pc); +-#else +- pr_err("Driver compiled without support for hostmode PCI\n"); + #endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */ +- } else { +- bcma_core_pci_clientmode_init(pc); +- } + +- pc->setup_done = true; ++ if (!pc->hostmode) ++ bcma_core_pci_clientmode_init(pc); + } + + int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc, struct bcma_device *core, +--- a/drivers/bcma/driver_pci_host.c ++++ b/drivers/bcma/driver_pci_host.c +@@ -2,13 +2,587 @@ + * Broadcom specific AMBA + * PCI Core in hostmode + * ++ * Copyright 2005 - 2011, Broadcom Corporation ++ * Copyright 2006, 2007, Michael Buesch <m@bues.ch> ++ * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de> ++ * + * Licensed under the GNU/GPL. See COPYING for details. + */ + + #include "bcma_private.h" ++#include <linux/export.h> + #include <linux/bcma/bcma.h> ++#include <asm/paccess.h> ++ ++/* Probe a 32bit value on the bus and catch bus exceptions. ++ * Returns nonzero on a bus exception. ++ * This is MIPS specific */ ++#define mips_busprobe32(val, addr) get_dbe((val), ((u32 *)(addr))) ++ ++/* Assume one-hot slot wiring */ ++#define BCMA_PCI_SLOT_MAX 16 ++#define PCI_CONFIG_SPACE_SIZE 256 ++ ++bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc) ++{ ++ struct bcma_bus *bus = pc->core->bus; ++ u16 chipid_top; ++ u32 tmp; ++ ++ chipid_top = (bus->chipinfo.id & 0xFF00); ++ if (chipid_top != 0x4700 && ++ chipid_top != 0x5300) ++ return false; ++ ++ if (bus->sprom.boardflags_lo & BCMA_CORE_PCI_BFL_NOPCI) { ++ pr_info("This PCI core is disabled and not working\n"); ++ return false; ++ } ++ ++ bcma_core_enable(pc->core, 0); ++ ++ return !mips_busprobe32(tmp, pc->core->io_addr); ++} ++ ++static u32 bcma_pcie_read_config(struct bcma_drv_pci *pc, u32 address) ++{ ++ pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_ADDR, address); ++ pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_ADDR); ++ return pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_DATA); ++} ++ ++static void bcma_pcie_write_config(struct bcma_drv_pci *pc, u32 address, ++ u32 data) ++{ ++ pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_ADDR, address); ++ pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_ADDR); ++ pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_DATA, data); ++} ++ ++static u32 bcma_get_cfgspace_addr(struct bcma_drv_pci *pc, unsigned int dev, ++ unsigned int func, unsigned int off) ++{ ++ u32 addr = 0; ++ ++ /* Issue config commands only when the data link is up (atleast ++ * one external pcie device is present). ++ */ ++ if (dev >= 2 || !(bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_LSREG) ++ & BCMA_CORE_PCI_DLLP_LSREG_LINKUP)) ++ goto out; ++ ++ /* Type 0 transaction */ ++ /* Slide the PCI window to the appropriate slot */ ++ pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI1, BCMA_CORE_PCI_SBTOPCI_CFG0); ++ /* Calculate the address */ ++ addr = pc->host_controller->host_cfg_addr; ++ addr |= (dev << BCMA_CORE_PCI_CFG_SLOT_SHIFT); ++ addr |= (func << BCMA_CORE_PCI_CFG_FUN_SHIFT); ++ addr |= (off & ~3); ++ ++out: ++ return addr; ++} ++ ++static int bcma_extpci_read_config(struct bcma_drv_pci *pc, unsigned int dev, ++ unsigned int func, unsigned int off, ++ void *buf, int len) ++{ ++ int err = -EINVAL; ++ u32 addr, val; ++ void __iomem *mmio = 0; ++ ++ WARN_ON(!pc->hostmode); ++ if (unlikely(len != 1 && len != 2 && len != 4)) ++ goto out; ++ if (dev == 0) { ++ /* we support only two functions on device 0 */ ++ if (func > 1) ++ return -EINVAL; ++ ++ /* accesses to config registers with offsets >= 256 ++ * requires indirect access. ++ */ ++ if (off >= PCI_CONFIG_SPACE_SIZE) { ++ addr = (func << 12); ++ addr |= (off & 0x0FFF); ++ val = bcma_pcie_read_config(pc, addr); ++ } else { ++ addr = BCMA_CORE_PCI_PCICFG0; ++ addr |= (func << 8); ++ addr |= (off & 0xfc); ++ val = pcicore_read32(pc, addr); ++ } ++ } else { ++ addr = bcma_get_cfgspace_addr(pc, dev, func, off); ++ if (unlikely(!addr)) ++ goto out; ++ err = -ENOMEM; ++ mmio = ioremap_nocache(addr, len); ++ if (!mmio) ++ goto out; ++ ++ if (mips_busprobe32(val, mmio)) { ++ val = 0xffffffff; ++ goto unmap; ++ } ++ ++ val = readl(mmio); ++ } ++ val >>= (8 * (off & 3)); ++ ++ switch (len) { ++ case 1: ++ *((u8 *)buf) = (u8)val; ++ break; ++ case 2: ++ *((u16 *)buf) = (u16)val; ++ break; ++ case 4: ++ *((u32 *)buf) = (u32)val; ++ break; ++ } ++ err = 0; ++unmap: ++ if (mmio) ++ iounmap(mmio); ++out: ++ return err; ++} ++ ++static int bcma_extpci_write_config(struct bcma_drv_pci *pc, unsigned int dev, ++ unsigned int func, unsigned int off, ++ const void *buf, int len) ++{ ++ int err = -EINVAL; ++ u32 addr = 0, val = 0; ++ void __iomem *mmio = 0; ++ u16 chipid = pc->core->bus->chipinfo.id; ++ ++ WARN_ON(!pc->hostmode); ++ if (unlikely(len != 1 && len != 2 && len != 4)) ++ goto out; ++ if (dev == 0) { ++ /* accesses to config registers with offsets >= 256 ++ * requires indirect access. ++ */ ++ if (off < PCI_CONFIG_SPACE_SIZE) { ++ addr = pc->core->addr + BCMA_CORE_PCI_PCICFG0; ++ addr |= (func << 8); ++ addr |= (off & 0xfc); ++ mmio = ioremap_nocache(addr, len); ++ if (!mmio) ++ goto out; ++ } ++ } else { ++ addr = bcma_get_cfgspace_addr(pc, dev, func, off); ++ if (unlikely(!addr)) ++ goto out; ++ err = -ENOMEM; ++ mmio = ioremap_nocache(addr, len); ++ if (!mmio) ++ goto out; ++ ++ if (mips_busprobe32(val, mmio)) { ++ val = 0xffffffff; ++ goto unmap; ++ } ++ } ++ ++ switch (len) { ++ case 1: ++ val = readl(mmio); ++ val &= ~(0xFF << (8 * (off & 3))); ++ val |= *((const u8 *)buf) << (8 * (off & 3)); ++ break; ++ case 2: ++ val = readl(mmio); ++ val &= ~(0xFFFF << (8 * (off & 3))); ++ val |= *((const u16 *)buf) << (8 * (off & 3)); ++ break; ++ case 4: ++ val = *((const u32 *)buf); ++ break; ++ } ++ if (dev == 0 && !addr) { ++ /* accesses to config registers with offsets >= 256 ++ * requires indirect access. ++ */ ++ addr = (func << 12); ++ addr |= (off & 0x0FFF); ++ bcma_pcie_write_config(pc, addr, val); ++ } else { ++ writel(val, mmio); ++ ++ if (chipid == 0x4716 || chipid == 0x4748) ++ readl(mmio); ++ } ++ ++ err = 0; ++unmap: ++ if (mmio) ++ iounmap(mmio); ++out: ++ return err; ++} ++ ++static int bcma_core_pci_hostmode_read_config(struct pci_bus *bus, ++ unsigned int devfn, ++ int reg, int size, u32 *val) ++{ ++ unsigned long flags; ++ int err; ++ struct bcma_drv_pci *pc; ++ struct bcma_drv_pci_host *pc_host; ++ ++ pc_host = container_of(bus->ops, struct bcma_drv_pci_host, pci_ops); ++ pc = pc_host->pdev; ++ ++ spin_lock_irqsave(&pc_host->cfgspace_lock, flags); ++ err = bcma_extpci_read_config(pc, PCI_SLOT(devfn), ++ PCI_FUNC(devfn), reg, val, size); ++ spin_unlock_irqrestore(&pc_host->cfgspace_lock, flags); ++ ++ return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL; ++} ++ ++static int bcma_core_pci_hostmode_write_config(struct pci_bus *bus, ++ unsigned int devfn, ++ int reg, int size, u32 val) ++{ ++ unsigned long flags; ++ int err; ++ struct bcma_drv_pci *pc; ++ struct bcma_drv_pci_host *pc_host; ++ ++ pc_host = container_of(bus->ops, struct bcma_drv_pci_host, pci_ops); ++ pc = pc_host->pdev; ++ ++ spin_lock_irqsave(&pc_host->cfgspace_lock, flags); ++ err = bcma_extpci_write_config(pc, PCI_SLOT(devfn), ++ PCI_FUNC(devfn), reg, &val, size); ++ spin_unlock_irqrestore(&pc_host->cfgspace_lock, flags); ++ ++ return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL; ++} ++ ++/* return cap_offset if requested capability exists in the PCI config space */ ++static u8 __devinit bcma_find_pci_capability(struct bcma_drv_pci *pc, ++ unsigned int dev, ++ unsigned int func, u8 req_cap_id, ++ unsigned char *buf, u32 *buflen) ++{ ++ u8 cap_id; ++ u8 cap_ptr = 0; ++ u32 bufsize; ++ u8 byte_val; ++ ++ /* check for Header type 0 */ ++ bcma_extpci_read_config(pc, dev, func, PCI_HEADER_TYPE, &byte_val, ++ sizeof(u8)); ++ if ((byte_val & 0x7f) != PCI_HEADER_TYPE_NORMAL) ++ return cap_ptr; ++ ++ /* check if the capability pointer field exists */ ++ bcma_extpci_read_config(pc, dev, func, PCI_STATUS, &byte_val, ++ sizeof(u8)); ++ if (!(byte_val & PCI_STATUS_CAP_LIST)) ++ return cap_ptr; ++ ++ /* check if the capability pointer is 0x00 */ ++ bcma_extpci_read_config(pc, dev, func, PCI_CAPABILITY_LIST, &cap_ptr, ++ sizeof(u8)); ++ if (cap_ptr == 0x00) ++ return cap_ptr; ++ ++ /* loop thr'u the capability list and see if the requested capabilty ++ * exists */ ++ bcma_extpci_read_config(pc, dev, func, cap_ptr, &cap_id, sizeof(u8)); ++ while (cap_id != req_cap_id) { ++ bcma_extpci_read_config(pc, dev, func, cap_ptr + 1, &cap_ptr, ++ sizeof(u8)); ++ if (cap_ptr == 0x00) ++ return cap_ptr; ++ bcma_extpci_read_config(pc, dev, func, cap_ptr, &cap_id, ++ sizeof(u8)); ++ } ++ ++ /* found the caller requested capability */ ++ if ((buf != NULL) && (buflen != NULL)) { ++ u8 cap_data; ++ ++ bufsize = *buflen; ++ if (!bufsize) ++ return cap_ptr; ++ ++ *buflen = 0; ++ ++ /* copy the cpability data excluding cap ID and next ptr */ ++ cap_data = cap_ptr + 2; ++ if ((bufsize + cap_data) > PCI_CONFIG_SPACE_SIZE) ++ bufsize = PCI_CONFIG_SPACE_SIZE - cap_data; ++ *buflen = bufsize; ++ while (bufsize--) { ++ bcma_extpci_read_config(pc, dev, func, cap_data, buf, ++ sizeof(u8)); ++ cap_data++; ++ buf++; ++ } ++ } ++ ++ return cap_ptr; ++} ++ ++/* If the root port is capable of returning Config Request ++ * Retry Status (CRS) Completion Status to software then ++ * enable the feature. ++ */ ++static void __devinit bcma_core_pci_enable_crs(struct bcma_drv_pci *pc) ++{ ++ u8 cap_ptr, root_ctrl, root_cap, dev; ++ u16 val16; ++ int i; ++ ++ cap_ptr = bcma_find_pci_capability(pc, 0, 0, PCI_CAP_ID_EXP, NULL, ++ NULL); ++ root_cap = cap_ptr + PCI_EXP_RTCAP; ++ bcma_extpci_read_config(pc, 0, 0, root_cap, &val16, sizeof(u16)); ++ if (val16 & BCMA_CORE_PCI_RC_CRS_VISIBILITY) { ++ /* Enable CRS software visibility */ ++ root_ctrl = cap_ptr + PCI_EXP_RTCTL; ++ val16 = PCI_EXP_RTCTL_CRSSVE; ++ bcma_extpci_read_config(pc, 0, 0, root_ctrl, &val16, ++ sizeof(u16)); ++ ++ /* Initiate a configuration request to read the vendor id ++ * field of the device function's config space header after ++ * 100 ms wait time from the end of Reset. If the device is ++ * not done with its internal initialization, it must at ++ * least return a completion TLP, with a completion status ++ * of "Configuration Request Retry Status (CRS)". The root ++ * complex must complete the request to the host by returning ++ * a read-data value of 0001h for the Vendor ID field and ++ * all 1s for any additional bytes included in the request. ++ * Poll using the config reads for max wait time of 1 sec or ++ * until we receive the successful completion status. Repeat ++ * the procedure for all the devices. ++ */ ++ for (dev = 1; dev < BCMA_PCI_SLOT_MAX; dev++) { ++ for (i = 0; i < 100000; i++) { ++ bcma_extpci_read_config(pc, dev, 0, ++ PCI_VENDOR_ID, &val16, ++ sizeof(val16)); ++ if (val16 != 0x1) ++ break; ++ udelay(10); ++ } ++ if (val16 == 0x1) ++ pr_err("PCI: Broken device in slot %d\n", dev); ++ } ++ } ++} + + void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc) + { +- pr_err("No support for PCI core in hostmode yet\n"); ++ struct bcma_bus *bus = pc->core->bus; ++ struct bcma_drv_pci_host *pc_host; ++ u32 tmp; ++ u32 pci_membase_1G; ++ unsigned long io_map_base; ++ ++ pr_info("PCIEcore in host mode found\n"); ++ ++ pc_host = kzalloc(sizeof(*pc_host), GFP_KERNEL); ++ if (!pc_host) { ++ pr_err("can not allocate memory"); ++ return; ++ } ++ ++ pc->host_controller = pc_host; ++ pc_host->pci_controller.io_resource = &pc_host->io_resource; ++ pc_host->pci_controller.mem_resource = &pc_host->mem_resource; ++ pc_host->pci_controller.pci_ops = &pc_host->pci_ops; ++ pc_host->pdev = pc; ++ ++ pci_membase_1G = BCMA_SOC_PCI_DMA; ++ pc_host->host_cfg_addr = BCMA_SOC_PCI_CFG; ++ ++ pc_host->pci_ops.read = bcma_core_pci_hostmode_read_config; ++ pc_host->pci_ops.write = bcma_core_pci_hostmode_write_config; ++ ++ pc_host->mem_resource.name = "BCMA PCIcore external memory", ++ pc_host->mem_resource.start = BCMA_SOC_PCI_DMA; ++ pc_host->mem_resource.end = BCMA_SOC_PCI_DMA + BCMA_SOC_PCI_DMA_SZ - 1; ++ pc_host->mem_resource.flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED; ++ ++ pc_host->io_resource.name = "BCMA PCIcore external I/O", ++ pc_host->io_resource.start = 0x100; ++ pc_host->io_resource.end = 0x7FF; ++ pc_host->io_resource.flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED; ++ ++ /* Reset RC */ ++ udelay(3000); ++ pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST_OE); ++ udelay(1000); ++ pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST | ++ BCMA_CORE_PCI_CTL_RST_OE); ++ ++ /* 64 MB I/O access window. On 4716, use ++ * sbtopcie0 to access the device registers. We ++ * can't use address match 2 (1 GB window) region ++ * as mips can't generate 64-bit address on the ++ * backplane. ++ */ ++ if (bus->chipinfo.id == 0x4716 || bus->chipinfo.id == 0x4748) { ++ pc_host->mem_resource.start = BCMA_SOC_PCI_MEM; ++ pc_host->mem_resource.end = BCMA_SOC_PCI_MEM + ++ BCMA_SOC_PCI_MEM_SZ - 1; ++ pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0, ++ BCMA_CORE_PCI_SBTOPCI_MEM | BCMA_SOC_PCI_MEM); ++ } else if (bus->chipinfo.id == 0x5300) { ++ tmp = BCMA_CORE_PCI_SBTOPCI_MEM; ++ tmp |= BCMA_CORE_PCI_SBTOPCI_PREF; ++ tmp |= BCMA_CORE_PCI_SBTOPCI_BURST; ++ if (pc->core->core_unit == 0) { ++ pc_host->mem_resource.start = BCMA_SOC_PCI_MEM; ++ pc_host->mem_resource.end = BCMA_SOC_PCI_MEM + ++ BCMA_SOC_PCI_MEM_SZ - 1; ++ pci_membase_1G = BCMA_SOC_PCIE_DMA_H32; ++ pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0, ++ tmp | BCMA_SOC_PCI_MEM); ++ } else if (pc->core->core_unit == 1) { ++ pc_host->mem_resource.start = BCMA_SOC_PCI1_MEM; ++ pc_host->mem_resource.end = BCMA_SOC_PCI1_MEM + ++ BCMA_SOC_PCI_MEM_SZ - 1; ++ pci_membase_1G = BCMA_SOC_PCIE1_DMA_H32; ++ pc_host->host_cfg_addr = BCMA_SOC_PCI1_CFG; ++ pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0, ++ tmp | BCMA_SOC_PCI1_MEM); ++ } ++ } else ++ pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0, ++ BCMA_CORE_PCI_SBTOPCI_IO); ++ ++ /* 64 MB configuration access window */ ++ pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI1, BCMA_CORE_PCI_SBTOPCI_CFG0); ++ ++ /* 1 GB memory access window */ ++ pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI2, ++ BCMA_CORE_PCI_SBTOPCI_MEM | pci_membase_1G); ++ ++ ++ /* As per PCI Express Base Spec 1.1 we need to wait for ++ * at least 100 ms from the end of a reset (cold/warm/hot) ++ * before issuing configuration requests to PCI Express ++ * devices. ++ */ ++ udelay(100000); ++ ++ bcma_core_pci_enable_crs(pc); ++ ++ /* Enable PCI bridge BAR0 memory & master access */ ++ tmp = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; ++ bcma_extpci_write_config(pc, 0, 0, PCI_COMMAND, &tmp, sizeof(tmp)); ++ ++ /* Enable PCI interrupts */ ++ pcicore_write32(pc, BCMA_CORE_PCI_IMASK, BCMA_CORE_PCI_IMASK_INTA); ++ ++ /* Ok, ready to run, register it to the system. ++ * The following needs change, if we want to port hostmode ++ * to non-MIPS platform. */ ++ io_map_base = (unsigned long)ioremap_nocache(BCMA_SOC_PCI_MEM, ++ 0x04000000); ++ pc_host->pci_controller.io_map_base = io_map_base; ++ set_io_port_base(pc_host->pci_controller.io_map_base); ++ /* Give some time to the PCI controller to configure itself with the new ++ * values. Not waiting at this point causes crashes of the machine. */ ++ mdelay(10); ++ register_pci_controller(&pc_host->pci_controller); ++ return; ++} ++ ++/* Early PCI fixup for a device on the PCI-core bridge. */ ++static void bcma_core_pci_fixup_pcibridge(struct pci_dev *dev) ++{ ++ if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) { ++ /* This is not a device on the PCI-core bridge. */ ++ return; ++ } ++ if (PCI_SLOT(dev->devfn) != 0) ++ return; ++ ++ pr_info("PCI: Fixing up bridge %s\n", pci_name(dev)); ++ ++ /* Enable PCI bridge bus mastering and memory space */ ++ pci_set_master(dev); ++ if (pcibios_enable_device(dev, ~0) < 0) { ++ pr_err("PCI: BCMA bridge enable failed\n"); ++ return; ++ } ++ ++ /* Enable PCI bridge BAR1 prefetch and burst */ ++ pci_write_config_dword(dev, BCMA_PCI_BAR1_CONTROL, 3); ++} ++DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, bcma_core_pci_fixup_pcibridge); ++ ++/* Early PCI fixup for all PCI-cores to set the correct memory address. */ ++static void bcma_core_pci_fixup_addresses(struct pci_dev *dev) ++{ ++ struct resource *res; ++ int pos; ++ ++ if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) { ++ /* This is not a device on the PCI-core bridge. */ ++ return; ++ } ++ if (PCI_SLOT(dev->devfn) == 0) ++ return; ++ ++ pr_info("PCI: Fixing up addresses %s\n", pci_name(dev)); ++ ++ for (pos = 0; pos < 6; pos++) { ++ res = &dev->resource[pos]; ++ if (res->flags & (IORESOURCE_IO | IORESOURCE_MEM)) ++ pci_assign_resource(dev, pos); ++ } ++} ++DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, bcma_core_pci_fixup_addresses); ++ ++/* This function is called when doing a pci_enable_device(). ++ * We must first check if the device is a device on the PCI-core bridge. */ ++int bcma_core_pci_plat_dev_init(struct pci_dev *dev) ++{ ++ struct bcma_drv_pci_host *pc_host; ++ ++ if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) { ++ /* This is not a device on the PCI-core bridge. */ ++ return -ENODEV; ++ } ++ pc_host = container_of(dev->bus->ops, struct bcma_drv_pci_host, ++ pci_ops); ++ ++ pr_info("PCI: Fixing up device %s\n", pci_name(dev)); ++ ++ /* Fix up interrupt lines */ ++ dev->irq = bcma_core_mips_irq(pc_host->pdev->core) + 2; ++ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); ++ ++ return 0; ++} ++EXPORT_SYMBOL(bcma_core_pci_plat_dev_init); ++ ++/* PCI device IRQ mapping. */ ++int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev) ++{ ++ struct bcma_drv_pci_host *pc_host; ++ ++ if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) { ++ /* This is not a device on the PCI-core bridge. */ ++ return -ENODEV; ++ } ++ ++ pc_host = container_of(dev->bus->ops, struct bcma_drv_pci_host, ++ pci_ops); ++ return bcma_core_mips_irq(pc_host->pdev->core) + 2; + } ++EXPORT_SYMBOL(bcma_core_pci_pcibios_map_irq); +--- a/include/linux/bcma/bcma_driver_pci.h ++++ b/include/linux/bcma/bcma_driver_pci.h +@@ -160,9 +160,40 @@ struct pci_dev; + /* PCIcore specific boardflags */ + #define BCMA_CORE_PCI_BFL_NOPCI 0x00000400 /* Board leaves PCI floating */ + ++/* PCIE Config space accessing MACROS */ ++#define BCMA_CORE_PCI_CFG_BUS_SHIFT 24 /* Bus shift */ ++#define BCMA_CORE_PCI_CFG_SLOT_SHIFT 19 /* Slot/Device shift */ ++#define BCMA_CORE_PCI_CFG_FUN_SHIFT 16 /* Function shift */ ++#define BCMA_CORE_PCI_CFG_OFF_SHIFT 0 /* Register shift */ ++ ++#define BCMA_CORE_PCI_CFG_BUS_MASK 0xff /* Bus mask */ ++#define BCMA_CORE_PCI_CFG_SLOT_MASK 0x1f /* Slot/Device mask */ ++#define BCMA_CORE_PCI_CFG_FUN_MASK 7 /* Function mask */ ++#define BCMA_CORE_PCI_CFG_OFF_MASK 0xfff /* Register mask */ ++ ++/* PCIE Root Capability Register bits (Host mode only) */ ++#define BCMA_CORE_PCI_RC_CRS_VISIBILITY 0x0001 ++ ++struct bcma_drv_pci; ++ ++struct bcma_drv_pci_host { ++ struct bcma_drv_pci *pdev; ++ ++ u32 host_cfg_addr; ++ spinlock_t cfgspace_lock; ++ ++ struct pci_controller pci_controller; ++ struct pci_ops pci_ops; ++ struct resource mem_resource; ++ struct resource io_resource; ++}; ++ + struct bcma_drv_pci { + struct bcma_device *core; + u8 setup_done:1; ++ u8 hostmode:1; ++ ++ struct bcma_drv_pci_host *host_controller; + }; + + /* Register access */ +@@ -173,4 +204,7 @@ extern void __devinit bcma_core_pci_init + extern int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc, + struct bcma_device *core, bool enable); + ++extern int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev); ++extern int bcma_core_pci_plat_dev_init(struct pci_dev *dev); ++ + #endif /* LINUX_BCMA_DRIVER_PCI_H_ */ +--- a/include/linux/bcma/bcma_regs.h ++++ b/include/linux/bcma/bcma_regs.h +@@ -56,4 +56,31 @@ + #define BCMA_PCI_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */ + #define BCMA_PCI_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */ + ++/* SiliconBackplane Address Map. ++ * All regions may not exist on all chips. ++ */ ++#define BCMA_SOC_SDRAM_BASE 0x00000000U /* Physical SDRAM */ ++#define BCMA_SOC_PCI_MEM 0x08000000U /* Host Mode sb2pcitranslation0 (64 MB) */ ++#define BCMA_SOC_PCI_MEM_SZ (64 * 1024 * 1024) ++#define BCMA_SOC_PCI_CFG 0x0c000000U /* Host Mode sb2pcitranslation1 (64 MB) */ ++#define BCMA_SOC_SDRAM_SWAPPED 0x10000000U /* Byteswapped Physical SDRAM */ ++#define BCMA_SOC_SDRAM_R2 0x80000000U /* Region 2 for sdram (512 MB) */ ++ ++ ++#define BCMA_SOC_PCI_DMA 0x40000000U /* Client Mode sb2pcitranslation2 (1 GB) */ ++#define BCMA_SOC_PCI_DMA2 0x80000000U /* Client Mode sb2pcitranslation2 (1 GB) */ ++#define BCMA_SOC_PCI_DMA_SZ 0x40000000U /* Client Mode sb2pcitranslation2 size in bytes */ ++#define BCMA_SOC_PCIE_DMA_L32 0x00000000U /* PCIE Client Mode sb2pcitranslation2 ++ * (2 ZettaBytes), low 32 bits ++ */ ++#define BCMA_SOC_PCIE_DMA_H32 0x80000000U /* PCIE Client Mode sb2pcitranslation2 ++ * (2 ZettaBytes), high 32 bits ++ */ ++ ++#define BCMA_SOC_PCI1_MEM 0x40000000U /* Host Mode sb2pcitranslation0 (64 MB) */ ++#define BCMA_SOC_PCI1_CFG 0x44000000U /* Host Mode sb2pcitranslation1 (64 MB) */ ++#define BCMA_SOC_PCIE1_DMA_H32 0xc0000000U /* PCIE Client Mode sb2pcitranslation2 ++ * (2 ZettaBytes), high 32 bits ++ */ ++ + #endif /* LINUX_BCMA_REGS_H_ */ diff --git a/target/linux/brcm47xx/patches-3.2/0041-bcma-add-bus-num-counter.patch b/target/linux/brcm47xx/patches-3.2/0041-bcma-add-bus-num-counter.patch new file mode 100644 index 000000000..8d49e1ce2 --- /dev/null +++ b/target/linux/brcm47xx/patches-3.2/0041-bcma-add-bus-num-counter.patch @@ -0,0 +1,59 @@ +From eecd733c14952b074d7488934a4f3dc83c9c426b Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens <hauke@hauke-m.de> +Date: Sat, 14 Jan 2012 16:29:51 +0100 +Subject: [PATCH 28/32] bcma: add bus num counter + +If we have two bcma buses on one computer the second will not work +without this patch. Now each bus gets an own number. + +Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> +--- + drivers/bcma/main.c | 12 +++++++++++- + include/linux/bcma/bcma.h | 1 + + 2 files changed, 12 insertions(+), 1 deletions(-) + +--- a/drivers/bcma/main.c ++++ b/drivers/bcma/main.c +@@ -13,6 +13,12 @@ + MODULE_DESCRIPTION("Broadcom's specific AMBA driver"); + MODULE_LICENSE("GPL"); + ++/* contains the number the next bus should get. */ ++static unsigned int bcma_bus_next_num = 0; ++ ++/* bcma_buses_mutex locks the bcma_bus_next_num */ ++static DEFINE_MUTEX(bcma_buses_mutex); ++ + static int bcma_bus_match(struct device *dev, struct device_driver *drv); + static int bcma_device_probe(struct device *dev); + static int bcma_device_remove(struct device *dev); +@@ -93,7 +99,7 @@ static int bcma_register_cores(struct bc + + core->dev.release = bcma_release_core_dev; + core->dev.bus = &bcma_bus_type; +- dev_set_name(&core->dev, "bcma%d:%d", 0/*bus->num*/, dev_id); ++ dev_set_name(&core->dev, "bcma%d:%d", bus->num, dev_id); + + switch (bus->hosttype) { + case BCMA_HOSTTYPE_PCI: +@@ -137,6 +143,10 @@ int __devinit bcma_bus_register(struct b + int err; + struct bcma_device *core; + ++ mutex_lock(&bcma_buses_mutex); ++ bus->num = bcma_bus_next_num++; ++ mutex_unlock(&bcma_buses_mutex); ++ + /* Scan for devices (cores) */ + err = bcma_bus_scan(bus); + if (err) { +--- a/include/linux/bcma/bcma.h ++++ b/include/linux/bcma/bcma.h +@@ -197,6 +197,7 @@ struct bcma_bus { + struct list_head cores; + u8 nr_cores; + u8 init_done:1; ++ u8 num; + + struct bcma_drv_cc drv_cc; + struct bcma_drv_pci drv_pci; diff --git a/target/linux/brcm47xx/patches-3.2/0042-bcma-add-new-PCI-ID.patch b/target/linux/brcm47xx/patches-3.2/0042-bcma-add-new-PCI-ID.patch new file mode 100644 index 000000000..efce69f15 --- /dev/null +++ b/target/linux/brcm47xx/patches-3.2/0042-bcma-add-new-PCI-ID.patch @@ -0,0 +1,24 @@ +From 699c57a18b40ffbe1763915acdc1a3e4fb539d01 Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens <hauke@hauke-m.de> +Date: Fri, 13 Jan 2012 17:42:15 +0100 +Subject: [PATCH 29/32] bcma: add new PCI ID + +This ID was found on the PCIe wireless card on the board of a Netgear +WNDR3400 using a bcm4716. The device with this ID is identified by b43 +as "Broadcom 43224 WLAN". + +Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> +--- + drivers/bcma/host_pci.c | 1 + + 1 files changed, 1 insertions(+), 0 deletions(-) + +--- a/drivers/bcma/host_pci.c ++++ b/drivers/bcma/host_pci.c +@@ -275,6 +275,7 @@ static DEFINE_PCI_DEVICE_TABLE(bcma_pci_ + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4353) }, + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4357) }, + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4727) }, ++ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0xa8d8) }, + { 0, }, + }; + MODULE_DEVICE_TABLE(pci, bcma_pci_bridge_tbl); diff --git a/target/linux/brcm47xx/patches-3.2/0043-bcma-add-extra-sprom-check.patch b/target/linux/brcm47xx/patches-3.2/0043-bcma-add-extra-sprom-check.patch new file mode 100644 index 000000000..0dd196815 --- /dev/null +++ b/target/linux/brcm47xx/patches-3.2/0043-bcma-add-extra-sprom-check.patch @@ -0,0 +1,63 @@ +From 1cd3d0de72e42161fe0df355c5429459265aeef0 Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens <hauke@hauke-m.de> +Date: Sat, 14 Jan 2012 16:11:17 +0100 +Subject: [PATCH 30/32] bcma: add extra sprom check + +This check is needed on the BCM43224 device as it says in the +capabilities it has an sprom but is extra check says it has not. + +Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> +--- + drivers/bcma/sprom.c | 8 ++++++++ + include/linux/bcma/bcma_driver_chipcommon.h | 16 ++++++++++++++++ + 2 files changed, 24 insertions(+), 0 deletions(-) + +--- a/drivers/bcma/sprom.c ++++ b/drivers/bcma/sprom.c +@@ -210,6 +210,7 @@ int bcma_sprom_get(struct bcma_bus *bus) + { + u16 offset; + u16 *sprom; ++ u32 sromctrl; + int err = 0; + + if (!bus->drv_cc.core) +@@ -220,6 +221,13 @@ int bcma_sprom_get(struct bcma_bus *bus) + return -ENOENT; + } + ++ if (bus->drv_cc.core->id.rev >= 32) { ++ sromctrl = bcma_read32(bus->drv_cc.core, BCMA_CC_SROM_CONTROL); ++ if (!(sromctrl & BCMA_CC_SROM_CONTROL_PRESENT)) ++ random_ether_addr(bus->sprom.il0mac); ++ return -ENOENT; ++ } ++ + sprom = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16), + GFP_KERNEL); + if (!sprom) +--- a/include/linux/bcma/bcma_driver_chipcommon.h ++++ b/include/linux/bcma/bcma_driver_chipcommon.h +@@ -239,6 +239,22 @@ + #define BCMA_CC_FLASH_CFG 0x0128 + #define BCMA_CC_FLASH_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */ + #define BCMA_CC_FLASH_WAITCNT 0x012C ++#define BCMA_CC_SROM_CONTROL 0x0190 ++#define BCMA_CC_SROM_CONTROL_START 0x80000000 ++#define BCMA_CC_SROM_CONTROL_BUSY 0x80000000 ++#define BCMA_CC_SROM_CONTROL_OPCODE 0x60000000 ++#define BCMA_CC_SROM_CONTROL_OP_READ 0x00000000 ++#define BCMA_CC_SROM_CONTROL_OP_WRITE 0x20000000 ++#define BCMA_CC_SROM_CONTROL_OP_WRDIS 0x40000000 ++#define BCMA_CC_SROM_CONTROL_OP_WREN 0x60000000 ++#define BCMA_CC_SROM_CONTROL_OTPSEL 0x00000010 ++#define BCMA_CC_SROM_CONTROL_LOCK 0x00000008 ++#define BCMA_CC_SROM_CONTROL_SIZE_MASK 0x00000006 ++#define BCMA_CC_SROM_CONTROL_SIZE_1K 0x00000000 ++#define BCMA_CC_SROM_CONTROL_SIZE_4K 0x00000002 ++#define BCMA_CC_SROM_CONTROL_SIZE_16K 0x00000004 ++#define BCMA_CC_SROM_CONTROL_SIZE_SHIFT 1 ++#define BCMA_CC_SROM_CONTROL_PRESENT 0x00000001 + /* 0x1E0 is defined as shared BCMA_CLKCTLST */ + #define BCMA_CC_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */ + #define BCMA_CC_UART0_DATA 0x0300 diff --git a/target/linux/brcm47xx/patches-3.2/0046-bcma-complete-workaround-for-BCMA43224.patch b/target/linux/brcm47xx/patches-3.2/0046-bcma-complete-workaround-for-BCMA43224.patch new file mode 100644 index 000000000..97e3f9c34 --- /dev/null +++ b/target/linux/brcm47xx/patches-3.2/0046-bcma-complete-workaround-for-BCMA43224.patch @@ -0,0 +1,52 @@ +From efe89df0326b777563d197b8cf1c25209a31ceb0 Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens <hauke@hauke-m.de> +Date: Sat, 21 Jan 2012 18:47:42 +0100 +Subject: [PATCH 32/34] bcma: complete workaround for BCMA43224 + + +Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> +--- + drivers/bcma/driver_chipcommon_pmu.c | 15 +++++++++++---- + include/linux/bcma/bcma_driver_chipcommon.h | 5 +++++ + 2 files changed, 16 insertions(+), 4 deletions(-) + +--- a/drivers/bcma/driver_chipcommon_pmu.c ++++ b/drivers/bcma/driver_chipcommon_pmu.c +@@ -141,12 +141,19 @@ void bcma_pmu_workarounds(struct bcma_dr + /* BCM4331 workaround is SPROM-related, we put it in sprom.c */ + break; + case 43224: ++ case 43421: ++ /* enable 12 mA drive strenth for 43224 and set chipControl register bit 15 */ + if (bus->chipinfo.rev == 0) { +- pr_err("Workarounds for 43224 rev 0 not fully " +- "implemented\n"); +- bcma_chipco_chipctl_maskset(cc, 0, ~0, 0x00F000F0); ++ bcma_cc_maskset32(cc, BCMA_CC_CHIPCTL, ++ BCMA_CCTRL_43224_GPIO_TOGGLE, ++ BCMA_CCTRL_43224_GPIO_TOGGLE); ++ bcma_chipco_chipctl_maskset(cc, 0, ++ BCMA_CCTRL_43224A0_12MA_LED_DRIVE, ++ BCMA_CCTRL_43224A0_12MA_LED_DRIVE); + } else { +- bcma_chipco_chipctl_maskset(cc, 0, ~0, 0xF0); ++ bcma_chipco_chipctl_maskset(cc, 0, ++ BCMA_CCTRL_43224B0_12MA_LED_DRIVE, ++ BCMA_CCTRL_43224B0_12MA_LED_DRIVE); + } + break; + case 43225: +--- a/include/linux/bcma/bcma_driver_chipcommon.h ++++ b/include/linux/bcma/bcma_driver_chipcommon.h +@@ -374,6 +374,11 @@ + #define BCMA_CHIPCTL_4331_BT_SHD0_ON_GPIO4 BIT(16) /* enable bt_shd0 at gpio4 */ + #define BCMA_CHIPCTL_4331_BT_SHD1_ON_GPIO5 BIT(17) /* enable bt_shd1 at gpio5 */ + ++/* 43224 chip-specific ChipControl register bits */ ++#define BCMA_CCTRL_43224_GPIO_TOGGLE 0x8000 /* gpio[3:0] pins as btcoex or s/w gpio */ ++#define BCMA_CCTRL_43224A0_12MA_LED_DRIVE 0x00F000F0 /* 12 mA drive strength */ ++#define BCMA_CCTRL_43224B0_12MA_LED_DRIVE 0xF0 /* 12 mA drive strength for later 43224s */ ++ + #define BCMA_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */ + #define BCMA_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */ + #define BCMA_FLASH1 0x1fc00000 /* MIPS Flash Region 1 */ diff --git a/target/linux/brcm47xx/patches-3.2/601-mips-remove-pci-collision-check.patch b/target/linux/brcm47xx/patches-3.2/601-mips-remove-pci-collision-check.patch deleted file mode 100644 index 7860ca0dd..000000000 --- a/target/linux/brcm47xx/patches-3.2/601-mips-remove-pci-collision-check.patch +++ /dev/null @@ -1,18 +0,0 @@ ---- a/arch/mips/pci/pci.c -+++ b/arch/mips/pci/pci.c -@@ -185,12 +185,10 @@ static int pcibios_enable_resources(stru - if ((idx == PCI_ROM_RESOURCE) && - (!(r->flags & IORESOURCE_ROM_ENABLE))) - continue; -- if (!r->start && r->end) { -- printk(KERN_ERR "PCI: Device %s not available " -- "because of resource collisions\n", -+ if (!r->start && r->end) -+ printk(KERN_WARNING "PCI: Device %s resource" -+ "collisions detected. Ignoring...\n", - pci_name(dev)); -- return -EINVAL; -- } - if (r->flags & IORESOURCE_IO) - cmd |= PCI_COMMAND_IO; - if (r->flags & IORESOURCE_MEM) |